JPH02130917A - Manufacture of semiconductor film - Google Patents
Manufacture of semiconductor filmInfo
- Publication number
- JPH02130917A JPH02130917A JP28542088A JP28542088A JPH02130917A JP H02130917 A JPH02130917 A JP H02130917A JP 28542088 A JP28542088 A JP 28542088A JP 28542088 A JP28542088 A JP 28542088A JP H02130917 A JPH02130917 A JP H02130917A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor
- polycrystalline
- selectively
- epitaxial growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 11
- 238000001459 lithography Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 238000009279 wet oxidation reaction Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 239000010408 film Substances 0.000 description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 208000012868 Overgrowth Diseases 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体膜の製造方法に関するものであ〔従来の
技術〕
従来から用いられてきた半導体膜の製造方法では、St
O□膜を所定の部分に形成し所定の領域の半導体層を露
出した部分にのみ選択的にエピタキシャル成長を行い、
さらにSlO□膜上へ横方向に過剰成長を行う方法が知
られている(J、Appl。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor film. [Prior Art] In the method for manufacturing a semiconductor film that has been used conventionally, St.
An O□ film is formed on a predetermined portion, and epitaxial growth is selectively performed only on the exposed portion of the semiconductor layer in a predetermined region.
Furthermore, a method of performing lateral overgrowth on the SlO□ film is known (J, Appl.
Phys、55(2>15.January 1984
+ p、519. Control oflatera
l epitaxial chemical vapo
r depositionof 5ilicon ov
er 1nsulators)。Phys, 55 (2>15. January 1984
+p, 519. Control
l epitaxial chemical vapo
r depositionof 5ilicon ov
er 1 nsulators).
従来の技術では基板表面に形成した非晶質絶縁膜上へ過
剰成長を行って横方向へ半導体を形成してS OI (
Ses+1conductor On In5ulat
or)の構造を得る場合、不必要な縦方向へも成長が進
行するため薄い成長膜を得ることができない。In conventional technology, SOI (
Ses+1 conductor On In5ulat
When obtaining the structure (or), growth proceeds in unnecessary vertical directions, making it impossible to obtain a thin grown film.
本発明の目的は、この問題を解決した半導体膜の製造方
法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor film that solves this problem.
本発明の半導体膜の製造方法は、
半導体基板上に第1の絶縁膜を形成したのち、前記半導
体基板を露出する第1の開口部を形成し、この第1の開
口部のみに選択的に第1の半導体エピタキシャル成長膜
の成長を行い、第1の絶縁膜と第1の半導体エピタキシ
ャル成長膜上へ多結晶Si膜を堆積し、この多結晶Si
膜上へ第2の絶縁膜を形成し、この第2の絶縁膜に前記
多結晶Si膜が露出するように第2の開口部を形成し、
第1、第2の絶縁膜に挟まれた前記多結晶Si膜を第2
の開口部から選択的にエツチングを行い空洞部を形成し
、この空洞部に選択的に第2の半導体エピタキシャル成
長膜を横方向に成長させることを特徴とする。The method for manufacturing a semiconductor film of the present invention includes forming a first insulating film on a semiconductor substrate, forming a first opening that exposes the semiconductor substrate, and selectively opening only the first opening. A first semiconductor epitaxial growth film is grown, a polycrystalline Si film is deposited on the first insulating film and the first semiconductor epitaxial growth film, and the polycrystalline Si film is deposited on the first insulating film and the first semiconductor epitaxial growth film.
forming a second insulating film on the film, forming a second opening in the second insulating film so that the polycrystalline Si film is exposed;
The polycrystalline Si film sandwiched between the first and second insulating films is
The method is characterized in that a cavity is formed by selectively etching the opening, and a second semiconductor epitaxial growth film is selectively grown laterally in the cavity.
従来の半導体膜を製造する技術では、縦方向に必要以上
に成長し薄い成長膜を得ることができない、これは原料
ガス濃度分布が縦横両方ともほぼ同じ濃度の条件で成長
が行われるためで、結晶の成長速度の面方位依存性が生
じている。この結果、縦と横との成長面を異なる面とし
て選んだ場合でも、各面の成長速度の比が縦横比と同じ
値となって、それ以上大きな縦横比は得られなくなる。With conventional semiconductor film manufacturing technology, it is impossible to obtain a thin film due to excessive growth in the vertical direction. This is because growth is performed under conditions where the raw material gas concentration distribution is approximately the same in both the vertical and horizontal directions. The crystal growth rate depends on the plane orientation. As a result, even if the vertical and horizontal growth surfaces are selected as different surfaces, the ratio of the growth rate of each surface becomes the same value as the aspect ratio, and a larger aspect ratio cannot be obtained.
これに対し本発明では、あらかじめ設定した縦横比を有
する空洞部分を形成することによって、その空洞部分に
のみ選択的にエピタキシャル成長を行うことにより、必
要な縦横比の膜厚の半導体膜の成長を行うことを可能に
している。In contrast, in the present invention, by forming a cavity having a predetermined aspect ratio and performing epitaxial growth selectively only in the cavity, a semiconductor film having a thickness with a required aspect ratio is grown. It makes it possible.
以下、この発明の実施例を模式図を用いて説明する。第
1図は実施例の工程段階を示す断面模式第1図(a)に
示すように、p型シリコン基板12の表面に第1のSi
O□膜14を酸化温度 950℃。Examples of the present invention will be described below using schematic diagrams. FIG. 1 is a schematic cross-sectional diagram showing the process steps of the embodiment. As shown in FIG.
The O□ film 14 is oxidized at a temperature of 950°C.
ウェット酸化によって〜5000人形成する。~5000 formed by wet oxidation.
つぎに第1図(b)に示すように、リソグラフィ技術に
よって第1のSiO□膜14に第1の開口部15を形成
し、p型シリコン基板12を露出させ、第1の開口部1
5にのみ選択的に第1のエピタキシャル成長Si膜13
を、成長温度 850℃+ S I HzCI、流量
300c c/mt n、HCl 流M500cc/m
in、圧力 30Torrで成長させる。Next, as shown in FIG. 1(b), a first opening 15 is formed in the first SiO□ film 14 using lithography technology, exposing the p-type silicon substrate 12, and opening the first opening 15.
The first epitaxially grown Si film 13 is selectively grown only on the
, growth temperature 850°C + SI HzCI, flow rate 300cc/mtn, HCl flow M500cc/m
in, at a pressure of 30 Torr.
つぎに第1図(C)に示すように、多結晶Si膜17を
基板温度 600℃、SiH,流量150cc/min
、圧力 ITorrの条件で〜3000人堆積して、リ
ソグラフィ技術によって必要とする横方向の大きさに多
結晶Si膜17を島状に形成する。Next, as shown in FIG. 1(C), a polycrystalline Si film 17 is deposited at a substrate temperature of 600° C., SiH, and a flow rate of 150 cc/min.
The polycrystalline Si film 17 is deposited under conditions of a pressure of about 3,000 Torr to form an island-like polycrystalline Si film 17 having a required lateral size using lithography technology.
つぎに第1図(d)に示すように、多結晶Si膜17を
含む基板全面に第2のStO,膜19を堆積し、リソグ
ラフィ技術によって第2の5tot膜19に第2の開口
部21を形成し、基板温度 850℃。Next, as shown in FIG. 1(d), a second StO film 19 is deposited on the entire surface of the substrate including the polycrystalline Si film 17, and a second opening 21 is formed in the second 5tot film 19 by lithography. was formed, and the substrate temperature was 850℃.
HCl! 流量500c c /m i n、圧力
30Torrで多結晶Si膜17のみ選択的にガスエツ
チングを行いあらかじめ設定した縦横比の空洞部分23
を形成する。HCl! Flow rate 500cc/min, pressure
Selective gas etching is performed only on the polycrystalline Si film 17 at 30 Torr to form a cavity portion 23 with a preset aspect ratio.
form.
つぎに第1図(e)に示すように、空洞部分23に選択
的に横方向の第2のエピタキシャル成長Si膜25を成
長温度 850℃、SiH,Cj2. 流量300c
c/ml n、HCl 流量500c c /m i
n、圧力 30Torrで成長させる。Next, as shown in FIG. 1(e), a second epitaxially grown Si film 25 is selectively grown laterally in the cavity portion 23 at a growth temperature of 850° C. using SiH, Cj2. Flow rate 300c
c/ml n, HCl flow rate 500c/m i
n, grown at a pressure of 30 Torr.
最後に第1図(f)に示すように、第2のSt0!膜1
9を剥離すると薄くて所望の面積を有するSi膜を形成
することができる。Finally, as shown in FIG. 1(f), the second St0! Membrane 1
By peeling off 9, a thin Si film having a desired area can be formed.
以上の実施例において空洞部を形成する方法として、ガ
スエツチングを利用したが、多結晶膜のみ選択的にエツ
チングすることができるような他の方法(たとえばウェ
ットエツチング等)によっても形成することが可能なこ
とはいうまでもない。Although gas etching was used as a method for forming the cavity in the above embodiments, it is also possible to form it by other methods (such as wet etching) that can selectively etch only the polycrystalline film. Needless to say.
(発明の効果〕
本発明を適用するならば、酸化膜上へ必要な膜厚の単結
晶半導体膜を形成することが可能となる。(Effects of the Invention) By applying the present invention, it becomes possible to form a single crystal semiconductor film with a required thickness on an oxide film.
第1図は本発明の一実施例による半導体膜の作成工程を
示した断面模式図である。
12・・・・p型シリコン基板
13・・・・第1のエピタキシャル成長3i膜14・・
・・第1のSiO□膜
15・・・・第1の開口部
17・・・・多結晶Si膜
19・・・・第2のSiO□膜
21・・・・第2の開口部
23・
・空洞部分
25・
・第2のエピタキシャル成長St膜FIG. 1 is a schematic cross-sectional view showing a process for forming a semiconductor film according to an embodiment of the present invention. 12...p-type silicon substrate 13...first epitaxial growth 3i film 14...
...First SiO□ film 15...First opening 17...Polycrystalline Si film 19...Second SiO□ film 21...Second opening 23.・Cavity portion 25・ ・Second epitaxially grown St film
Claims (1)
記半導体基板を露出する第1の開口部を形成し、この第
1の開口部のみに選択的に第1の半導体エピタキシャル
成長膜の成長を行い、第1の絶縁膜と第1の半導体エピ
タキシャル成長膜上へ多結晶Si膜を堆積し、この多結
晶Si膜上へ第2の絶縁膜を形成し、この第2の絶縁膜
に前記多結晶Si膜が露出するように第2の開口部を形
成し、第1、第2の絶縁膜に挟まれた前記多結晶Si膜
を第2の開口部から選択的にエッチングを行い空洞部を
形成し、この空洞部に選択的に第2の半導体エピタキシ
ャル成長膜を横方向に成長させることを特徴とする半導
体膜の製造方法。(1) After forming a first insulating film on a semiconductor substrate, a first opening exposing the semiconductor substrate is formed, and a first semiconductor epitaxial growth film is selectively formed only in this first opening. A polycrystalline Si film is deposited on the first insulating film and the first semiconductor epitaxially grown film, a second insulating film is formed on the polycrystalline Si film, and the second insulating film is A second opening is formed to expose the polycrystalline Si film, and the polycrystalline Si film sandwiched between the first and second insulating films is selectively etched from the second opening to form a cavity. 1. A method for manufacturing a semiconductor film, comprising forming a second semiconductor epitaxially grown film selectively in the cavity and laterally growing a second semiconductor epitaxial growth film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63285420A JP2527016B2 (en) | 1988-11-11 | 1988-11-11 | Method for manufacturing semiconductor film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63285420A JP2527016B2 (en) | 1988-11-11 | 1988-11-11 | Method for manufacturing semiconductor film |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH02130917A true JPH02130917A (en) | 1990-05-18 |
JP2527016B2 JP2527016B2 (en) | 1996-08-21 |
Family
ID=17691290
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63285420A Expired - Lifetime JP2527016B2 (en) | 1988-11-11 | 1988-11-11 | Method for manufacturing semiconductor film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2527016B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100695144B1 (en) * | 2004-12-01 | 2007-03-14 | 삼성전자주식회사 | Single crystal substrate and fabrication method thereof |
WO2023276107A1 (en) * | 2021-07-01 | 2023-01-05 | 日本電信電話株式会社 | Method for forming semiconductor layer |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6351622A (en) * | 1986-08-20 | 1988-03-04 | Nec Corp | Manufacture of semiconductor film |
JPH0210825A (en) * | 1988-04-05 | 1990-01-16 | Thomson Csf | Manufacture of alternate structure of single crystal semiconductor material layers and insulating material layers |
-
1988
- 1988-11-11 JP JP63285420A patent/JP2527016B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6351622A (en) * | 1986-08-20 | 1988-03-04 | Nec Corp | Manufacture of semiconductor film |
JPH0210825A (en) * | 1988-04-05 | 1990-01-16 | Thomson Csf | Manufacture of alternate structure of single crystal semiconductor material layers and insulating material layers |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100695144B1 (en) * | 2004-12-01 | 2007-03-14 | 삼성전자주식회사 | Single crystal substrate and fabrication method thereof |
WO2023276107A1 (en) * | 2021-07-01 | 2023-01-05 | 日本電信電話株式会社 | Method for forming semiconductor layer |
Also Published As
Publication number | Publication date |
---|---|
JP2527016B2 (en) | 1996-08-21 |
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