JPH01170043A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPH01170043A JPH01170043A JP32714587A JP32714587A JPH01170043A JP H01170043 A JPH01170043 A JP H01170043A JP 32714587 A JP32714587 A JP 32714587A JP 32714587 A JP32714587 A JP 32714587A JP H01170043 A JPH01170043 A JP H01170043A
- Authority
- JP
- Japan
- Prior art keywords
- compound semiconductor
- pattern
- layer
- regular pattern
- dummy patterns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 150000001875 compounds Chemical class 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 26
- 239000013078 crystal Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000001681 protective effect Effects 0.000 claims abstract description 10
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910020175 SiOH Inorganic materials 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、化合物半導体装置の製造方法に係り、特に、
半導体結晶基板上に選択的に半導体層をエピタキシャル
成長するのに好適な方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a compound semiconductor device, and in particular,
The present invention relates to a method suitable for selectively epitaxially growing a semiconductor layer on a semiconductor crystal substrate.
GaAs MESFETのソース、ドレイン領域を選
択成長技術により形成する際、パターンのサイズ、分布
により成長膜厚に不均一性が生じるため、従来技術では
、本パターンの周辺部にダミーパタンを形成し、この問
題を解決していた。When forming the source and drain regions of a GaAs MESFET by selective growth technology, non-uniformity occurs in the thickness of the grown film due to the size and distribution of the pattern, so in the conventional technology, a dummy pattern is formed around the main pattern to solve this problem. was solved.
上記従来技術では、半導体結晶基板上に、本パターンに
よる選択成長層以外に、ダミーパターンによる半導体成
長層が必然的に形成された。このため、半導体集積回路
等をこの結晶基板上に形成する場合に、ダミーパターン
による成長層により多くの制約を生じるなどの問題があ
った。In the above-mentioned prior art, a semiconductor growth layer with a dummy pattern was inevitably formed on the semiconductor crystal substrate in addition to the selective growth layer with the main pattern. For this reason, when a semiconductor integrated circuit or the like is formed on this crystal substrate, there are problems such as more constraints due to the growth layer formed by the dummy pattern.
本発明の目的は、化合物半導体結晶基板上に選択成長す
る場合に、ダミーパターンによる成長層を生じることな
く、且つパターンのサイズ、分布による成長膜厚の不均
一性の無い選択成長層を形成する製造方法を提供するこ
とにある。An object of the present invention is to form a selectively grown layer on a compound semiconductor crystal substrate without producing a grown layer due to a dummy pattern and without non-uniformity in the grown film thickness due to the size and distribution of the pattern. The purpose is to provide a manufacturing method.
上記目的は、まず化合物半導体の表面をSin、。 For the above purpose, first, the surface of the compound semiconductor was coated with Sin.
S 13N41 ws ixなどの保護膜で覆い1選択
成長すべき本パターンを形成し、次に本パターンの周辺
部に基板結晶表面まで到達しない凹形形状、または凸形
状のダミーパターンを形成することにより、達成される
。By forming a main pattern to be selectively grown by covering it with a protective film such as S13N41WSIX, and then forming a concave or convex dummy pattern around the main pattern that does not reach the substrate crystal surface. , achieved.
S i O2v S 1sNne WS ix材の表面
を避けてGaAs表面にのみG a A sが選択的に
エピタキシャル成長する技術は、主にMOCVDと呼ば
れる成長法で得られ易い、この方法を用いて、広い面積
の中に孤立した本パターンに選択的にG a A sを
成長する場合、膜厚が異常に厚くなり。The technique of epitaxially growing GaAs selectively only on the GaAs surface while avoiding the surface of the Si O2v S 1sNne WS ix material is mainly easy to obtain with a growth method called MOCVD. When G a As is selectively grown on the main pattern isolated in the film, the film thickness becomes abnormally thick.
一方、本パターンと同一形状のパターンが、−様に分布
している場合には、成長膜厚は均一になる傾向にある。On the other hand, when patterns having the same shape as the present pattern are distributed in a negative pattern, the grown film thickness tends to be uniform.
これは、結晶成長中に、パターン部以外に堆積しようと
する結晶原子又は分子が、保護膜上を動き回り、GaA
sの表面が露出した部分に集中することによると解釈さ
れている。また孤立パターンの場合、パターンから遠く
はなれた位置には多結晶のクラスターが形成されること
が知られている。従って、パターンの形状1分布に依存
した成長膜厚のばらつきを抑えるためには、周辺部に堆
積するGaAsの原子又は分子が本パターンに集中する
ことがないように、本パターンの周辺部の保護膜上に、
−様に分布した凹部、又は凸部を形成すれば可能である
。また、本パターン周辺の凹形ダミーパターンが基板結
晶表面まで達しないようにすれば、ダミーパターンによ
る不〔実施例〕
ラトランジスタのコレクタ電極部取り出しに適用した実
施例1を第1図に示した平面図、および第1図中a−a
’部分の断面図である第2図により説明する。This is because during crystal growth, crystal atoms or molecules that try to deposit in areas other than the pattern area move around on the protective film, causing GaA
It is interpreted that this is due to concentration in the exposed part of the surface of s. Furthermore, in the case of an isolated pattern, it is known that polycrystalline clusters are formed at positions far away from the pattern. Therefore, in order to suppress variations in the thickness of the grown film depending on the distribution of the shape of the pattern, it is necessary to protect the periphery of the pattern so that the GaAs atoms or molecules deposited in the periphery do not concentrate on the pattern. on the membrane,
This is possible by forming concave portions or convex portions distributed in a −-like manner. In addition, if the concave dummy pattern around the main pattern is prevented from reaching the substrate crystal surface, the dummy pattern can be used to prevent the concave dummy pattern from reaching the substrate crystal surface. Plan view and a-a in Figure 1
This will be explained with reference to FIG. 2, which is a sectional view of the section '.
まず半絶縁性GaAs基板20上にコレクタ層となるn
”GaAs層21およびn型GaAs層22、ベース層
となるp”型GaAs層23.エミッタ層となるn型A
lGaAs層24.最後にオーミックコンタクトを取り
やすくするためのキャップ層としてn+型G a A
s M 25を順次MBE法によりエピタキシャル成長
する。ここで、例えばn′″型GaAs層21はSiを
5X10”cm−3ドープし、厚さ5000人、n型G
aAs層22はSiを5 X 101′1am−”ドー
プし、厚さ3000人、p3型GaAs層23はBeを
2×1019cm−3ドープし、厚さ1000人、n型
AlGaAs層24はA1組成が0.3でSiを5X
I O”cm−3ドープし、厚さ1000人、n゛型G
aAs層25はSiを5 X 1018cm−3ドープ
し、厚さ1000人とする。First, a collector layer is formed on a semi-insulating GaAs substrate 20.
"GaAs layer 21, n-type GaAs layer 22, p"-type GaAs layer 23 serving as a base layer. n-type A that becomes the emitter layer
lGaAs layer 24. Finally, an n+ type Ga A is used as a cap layer to make it easier to make ohmic contact.
s M 25 is sequentially epitaxially grown by the MBE method. Here, for example, the n''' type GaAs layer 21 is doped with Si 5X10'' cm-3, has a thickness of 5000 mm, and has an n type G
The aAs layer 22 is doped with Si to 5 x 101'1 am-" and has a thickness of 3000 nm. The p3 type GaAs layer 23 is doped with Be to 2 x 1019 cm-3 and has a thickness of 1000 nm. The n-type AlGaAs layer 24 has an A1 composition. is 0.3 and Si is 5X
I O”cm-3 doped, 1000mm thick, n-type G
The aAs layer 25 is doped with 5×10 18 cm −3 of Si and has a thickness of 1000 nm.
次に全面をホトレジスト工程および反応性イオンエツチ
ングにより、コレクタ領域(本パターン部11とその周
辺部13)にコレクタ層22まで達する、深さ約800
0人穴あけを行う。次いで全面ニS i O2膜26
をCVD法により約8000人堆積する。次にホトレジ
工程及びドライ、ウェットエジチングにより、本パター
ン部11のみn0型G a A s層21の表面を露出
し周辺部13及び他の部分はS i 02膜を残す。Next, the entire surface is subjected to a photoresist process and reactive ion etching to a depth of about 800 mm to reach the collector layer 22 in the collector region (main pattern section 11 and its peripheral section 13).
Perform 0-person drilling. Next, the entire surface is covered with a SiO2 film 26.
Approximately 8,000 people are deposited using the CVD method. Next, by a photoresist process and dry/wet etching, the surface of the n0 type GaAs layer 21 is exposed only in the main pattern part 11, and the Si02 film is left in the peripheral part 13 and other parts.
次に、同様のホトレジ工程およびドライ及びウェットエ
ツチング工程を用いてダミーパターン部12に、GaA
s結晶表面が露出しないように、S i 02膜26に
深さ約5000人の凹地ダミーパターン12を形成する
。ここで、本パターン11の平面寸法は、例えば5μm
×10μm、ダミーパターン部12も同様とし、パター
ン間の距離は5μm以上100μm以下とし、第1図に
示すように一様に分布させた。Next, GaA
A concave dummy pattern 12 with a depth of about 5000 people is formed in the SiO2 film 26 so that the surface of the S crystal is not exposed. Here, the planar dimension of the main pattern 11 is, for example, 5 μm.
x 10 μm, and the same was applied to the dummy pattern portion 12, and the distance between the patterns was 5 μm or more and 100 μm or less, and uniformly distributed as shown in FIG.
次に、MOCVD法により、n″GaAs層27を選層
内7成長する。ここで、例えばn”GaAs層27はS
iを5×101f101f1ドープ、厚さ8000人と
し、キャップ層25と、選択成長層27の表面等しくな
るようにした。このとき、ダミーパターン12上には、
第2図に示すように多結晶G a A sのクラスタ2
8が堆積した。Next, an n'' GaAs layer 27 is selectively grown by the MOCVD method. Here, for example, the n'' GaAs layer 27 is S
i was 5×101f101f1 doped, the thickness was 8000, and the surfaces of the cap layer 25 and the selective growth layer 27 were made to be equal. At this time, on the dummy pattern 12,
As shown in Fig. 2, cluster 2 of polycrystalline Ga As
8 was deposited.
次いで、S i OH膜26をエツチングすると同時に
多結晶G a A s 28を除去した後、通常のプロ
セス技術を用いて、エミッタ、ベース、コレクタ電極を
形成し、ヘテロ接合バイポーラトランジスタ構造を作製
した。なお、5iOz膜26は必ずしも全て除去する必
要はない。Next, after etching the SiOH film 26 and removing the polycrystalline GaAs 28 at the same time, the emitter, base, and collector electrodes were formed using a normal process technique to fabricate a heterojunction bipolar transistor structure. Note that the 5iOz film 26 does not necessarily need to be completely removed.
以上により、コレクタ領域にのみn°型G a A s
層を選択的に成長でき、他の部分に不要な成長層が形成
されないような状態を実現することができ。As a result of the above, n° type Ga A s exists only in the collector region.
It is possible to selectively grow layers and achieve a state in which unnecessary growth layers are not formed in other parts.
プレーナー構造のHBTを作製することができた。We were able to fabricate an HBT with a planar structure.
(実施例2)
GaAs−AIGaAsヘテロ接合バイポーラトランジ
スタに本発明を適用した実施例2を第3図に示した平面
図、および第3図b−b’部分の断面図である第4図に
より説明する。(Example 2) Example 2 in which the present invention is applied to a GaAs-AIGaAs heterojunction bipolar transistor will be explained with reference to the plan view shown in FIG. 3 and FIG. 4 which is a cross-sectional view taken along line bb' in FIG. do.
実施例1と同様に、半絶縁性G a A s基板40上
にヘテロ接合バイポーラトランジスタを形成する結晶を
MBE法により成長し、n”GaAs層41まで達する
穴を開け、穴の周辺部33にS i 02からなるも絶
縁層の側壁46を形成する。As in Example 1, a crystal forming a heterojunction bipolar transistor is grown on a semi-insulating GaAs substrate 40 by the MBE method, a hole reaching up to the n'' GaAs layer 41 is formed, and a hole is formed in the peripheral area 33 of the hole. A side wall 46 of an insulating layer made of S i 02 is formed.
また同時に結晶表面にS i O,からなる保護膜46
を形成するe S z 02はCVD法により約1μm
厚とした。At the same time, a protective film 46 made of SiO is formed on the crystal surface.
The e S z 02 formed is approximately 1 μm by CVD method.
Made thick.
次にホトレジスト工程およびドライエツチング工程を用
いて、本パターン31周辺の保護膜上にダミーパターン
32を形成する。ダミーパターンの高さは約6000人
とした。Next, a dummy pattern 32 is formed on the protective film around the main pattern 31 using a photoresist process and a dry etching process. The height of the dummy pattern was approximately 6,000 people.
次にMOCVD法によりn”GaAs層47を成長する
と1本パターン部31にのみ選択的に、結晶成長が進行
する。一方、保護膜46上には結晶は成長せず、GaA
s、Ga又はAsの分子によるクラスタ48が堆積する
が、ダミーパターン32により、本パターン部への移動
は抑制される。Next, when the n'' GaAs layer 47 is grown by the MOCVD method, crystal growth progresses selectively only in one pattern portion 31. On the other hand, no crystal grows on the protective film 46, and the GaAs
Clusters 48 of s, Ga, or As molecules are deposited, but the dummy pattern 32 suppresses their movement to the main pattern portion.
したがって再成長n′″G a A s層、47の膜厚
は、パターンの形状2分布に依存することなく、均一な
膜厚を得ることができた。Therefore, it was possible to obtain a uniform thickness of the regrown n'''GaAs layer 47 without depending on the pattern shape distribution.
この後は、実施例1で述べたように、通常のプロセス技
術を用いてプレーナー構造のへテロ接合バイポーラトラ
ンジスタを作製した。Thereafter, as described in Example 1, a planar structure heterojunction bipolar transistor was manufactured using a normal process technique.
本発明によけば、化合物半導体結晶基板上に選択的成長
するi合に、パターンの寸法、分布による成長膜厚の不
均一性を抑制することができるので、任意の寸法1分布
、形状のパターンに均一な膜厚の結晶を選択的に成長す
ることが可能となる。According to the present invention, when selectively growing on a compound semiconductor crystal substrate, it is possible to suppress non-uniformity in the grown film thickness due to pattern dimensions and distribution. It becomes possible to selectively grow crystals with a uniform thickness in a pattern.
また、エミッタとコレクタの位置が逆転したコレクタト
ップ型のへテロ接合バイポーラトラジスタにおいて、エ
ミッタを選択再成長する場合にも本発明が有効であるこ
とは言うまでもない。It goes without saying that the present invention is also effective when selectively regrowing the emitter in a collector top type heterojunction bipolar transistor in which the positions of the emitter and collector are reversed.
第、1図は本発明の実施例1の平面図、第2図は、第1
図のa−a’部分の断面図、第3図は本発明の実施例2
の平面図、第4図は第3図のb−b ’部分の断面図で
ある。
10.3O−GaAs結晶ウェハー、11.31・・・
本パターン(コレクタ領域)、12.32・・・ダミー
パターン、13.33・・・S i 02による絶縁領
域、20.40−・・半絶縁性G a A a基板、2
1゜41−n”GaAs層(コレクタ)、22,42”
・n型G a A s層(コレクタ)、23.43・・
・p′″型GaAs層(ベース) 、24.44−=n
型AlGaAs層(エミッタ)、25.45−n”型G
a A s層(キャップ)、26.46−8i02層
、27.47・・・選択成長n゛型GaAs層、28・
・・ダミーパターン上に堆積したGaAsクラスタ、4
8・・・保護膜上に堆積したGaAsクラスタ。
−し
ノ27ご一ノJターン 21 グミー/Jターン」
=−4竺4シ蕾ノa
42回
JOGaJls7エムー −l ハθ、Jメ′!J
3圓
第4rfJ1 is a plan view of Embodiment 1 of the present invention, and FIG. 2 is a plan view of Embodiment 1 of the present invention.
Embodiment 2 of the present invention, FIG. 3 is a sectional view taken along the line a-a'
FIG. 4 is a sectional view taken along line bb' in FIG. 3. 10.3O-GaAs crystal wafer, 11.31...
Main pattern (collector region), 12.32... Dummy pattern, 13.33... Insulating region by S i 02, 20.40-... Semi-insulating G a A a substrate, 2
1゜41-n"GaAs layer (collector), 22,42"
・N-type GaAs layer (collector), 23.43...
・p''' type GaAs layer (base), 24.44-=n
Type AlGaAs layer (emitter), 25.45-n” type G
a As layer (cap), 26.46-8i02 layer, 27.47...selectively grown n'-type GaAs layer, 28.
...GaAs cluster deposited on dummy pattern, 4
8...GaAs cluster deposited on the protective film. -Shino 27 Goichino J Turn 21 Gummy/J Turn”
=-4 纺4し达ノa 42nd JOGaJls7Emu -l Haθ, Jme'! J
3rd circle 4th rfJ
Claims (1)
どからなる保護膜で覆われた半導体基板結晶を用いて、
本パターンの周辺にダミーパターンを形成し、本パター
ン部のみに選択的に化合物半導体結晶をエピタキシャル
成長する工程を有する化合物半導体装置の製造方法にお
いて、上記ダミーパターンは上記保護膜に結晶表面まで
到達しない凹部もしくは凸部を形成したものであること
を特徴とする化合物半導体装置の製造方法。 2、上記化合物半導体結晶はGaAsであり、上記エピ
タキシャル成長法はMOCVD法である特許請求の範囲
第1項記載の化合物半導体装置の製造方法。 3、上記本パターンと上記ダミーパターンの最短距離は
100μm以下である特許請求の範囲第1項記載の化合
物半導体装置の製造方法。[Claims] 1. Using a semiconductor substrate crystal whose surface is covered with a protective film made of SiO_2, Si_3N_4, WSix, etc.,
In a method for manufacturing a compound semiconductor device, which includes a step of forming a dummy pattern around the main pattern and selectively epitaxially growing a compound semiconductor crystal only in the main pattern portion, the dummy pattern is a recessed portion of the protective film that does not reach the crystal surface. Alternatively, a method for manufacturing a compound semiconductor device characterized in that a convex portion is formed. 2. The method for manufacturing a compound semiconductor device according to claim 1, wherein the compound semiconductor crystal is GaAs, and the epitaxial growth method is MOCVD. 3. The method for manufacturing a compound semiconductor device according to claim 1, wherein the shortest distance between the main pattern and the dummy pattern is 100 μm or less.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62327145A JP2585665B2 (en) | 1987-12-25 | 1987-12-25 | Method for manufacturing compound semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62327145A JP2585665B2 (en) | 1987-12-25 | 1987-12-25 | Method for manufacturing compound semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01170043A true JPH01170043A (en) | 1989-07-05 |
JP2585665B2 JP2585665B2 (en) | 1997-02-26 |
Family
ID=18195815
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62327145A Expired - Fee Related JP2585665B2 (en) | 1987-12-25 | 1987-12-25 | Method for manufacturing compound semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2585665B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01228186A (en) * | 1988-03-09 | 1989-09-12 | Sumitomo Electric Ind Ltd | Semiconductor selective growth method |
JPH06260509A (en) * | 1993-03-03 | 1994-09-16 | Nec Corp | Method of manufacturing semiconductor device |
JP2008085215A (en) * | 2006-09-28 | 2008-04-10 | Oki Electric Ind Co Ltd | Method for manufacturing semiconductor device |
-
1987
- 1987-12-25 JP JP62327145A patent/JP2585665B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01228186A (en) * | 1988-03-09 | 1989-09-12 | Sumitomo Electric Ind Ltd | Semiconductor selective growth method |
JPH06260509A (en) * | 1993-03-03 | 1994-09-16 | Nec Corp | Method of manufacturing semiconductor device |
JP2008085215A (en) * | 2006-09-28 | 2008-04-10 | Oki Electric Ind Co Ltd | Method for manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP2585665B2 (en) | 1997-02-26 |
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