JPH033935B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention provides enhancement/depletion (E/D ) The present invention relates to an improvement in a method for manufacturing a semiconductor device having the above structure.

Prior Art and Problems In general, this type of field effect transistor includes an undoped GaAs channel layer formed on a semi-insulating GaAs substrate and an n-type AlGaAs electron supply layer formed thereon. and its threshold voltage V _th is the n-type voltage that exists between the undoped GaAs channel layer and the gate electrode junction surface.
It is determined by the thickness of the semiconductor layer including the AlGaAs electron supply layer.

Apart from this, it can be said that semiconductor devices with an E/D configuration are indispensable in modern logic circuits. Of course, in this E/D configuration semiconductor device, a field effect transistor having an E-mode threshold voltage V _th and a D-mode threshold voltage V _th
A field-effect transistor having the same characteristics must be formed on the same substrate.

Therefore, when trying to obtain a semiconductor device with an E/D configuration using a field effect transistor that uses a 2DEG layer to speed up the speed, it is necessary to make contact between the short gate electrode and the semiconductor layer due to the relationship of the threshold voltage. It is necessary to fabricate two types of field effect transistors with different depths on the same substrate.

When manufacturing such a semiconductor device, the conventional technology that was initially implemented used a selective dry etching method using a CCl ₂ F ₂ containing gas as an etchant when processing the enhancement type transistor portion. Although the controllability and uniformity of the threshold voltage are good, when processing the depletion type transistor part, a wet etching method with no selectivity is applied, so the controllability and uniformity are not good either. It was hot.

In order to eliminate such drawbacks, the following technology has been provided.

FIG. 10 is a cross-sectional side view of essential parts of this type of semiconductor device.

In the figure, 1 is a semi-insulating GaAs substrate, 2 is an undoped GaAs channel layer, and 3 is an n-type AlGaAs substrate.
layer electron supply layer, 4 is n-type GaAs layer, 5 is n-type
AlGaAs layer, 6 is n-type GaAs contact layer, 7 is E/D insulation groove, 8, 9, 10, 11 are ohmic contact electrodes, 12 and 13 are shot contact gate electrodes, 14 is 2DEG layer,
E indicates an enhancement type transistor portion, and D indicates a depletion type transistor portion.

When manufacturing this semiconductor device, the biggest problem is, as mentioned above, that the shot gate electrodes 12 and 13 are placed on the n-type AlGaAs layer 5, and
Switch contact gate electrode 13 to n-type
In order to make contact with the AlGaAs electron supply layer 3, recesses are formed.

The steps for manufacturing the semiconductor device using the conventional technique are as follows.

First, enhancement type transistor part E
Concavity formation is performed. To do this, first pattern the gate part, perform wet etching until the n-type AlGaAs layer 5 is removed from the surface of the n-type GaAs contact layer 6, and then use the same photoresist film to form a depletion type transistor. Patterning of the gate portion is performed, and selective dry etching is performed on the enhancement type transistor portion E and the depletion type transistor portion D. The etching is performed on the n-type AlGaAs electron supply layer in the enhancement type transistor portion E. 3, and also stops at the n-type AlGaAs layer 5 in the depletion type transistor portion D.

However, the existence of shortcomings in this technology was also recognized.

That is, as mentioned above, the wet etching method is applied to remove the n-type AlGaAs layer 5.
The underlying n-type GaAs layer 4 has a thickness of
Since it is about 100 [Å], for example, the diameter is about 5 [cm]
It is quite difficult to stop the wet etching at the surface of the n-type GaAs layer 4 over the entire surface of a (2 inch) wafer, especially when the gate electrode length becomes about 1 [μm]. The etching solution is not well circulated and the etching speed changes, so that it is not easy to control the etching. To explain this more specifically, as mentioned above, the thickness of the n-type GaAs layer 4 is extremely thin, about 100 [Å], and the thickness of the object to be etched is, for example, about 400 [Å]. n-type
GaAs contact layer 6 and thickness is, for example, 30 [Å]
approximately 5 n-type AlGaAs layers, totaling approximately 430
The allowable over-etching for n-type GaAs layer 4 is only 100 [Å] for etching of about [Å].
Etching may occur, and mass production of this type of semiconductor device is in jeopardy.

In all of the above-described techniques, the formation of the recess and the formation of the gate electrode are simultaneously performed for the enhancement type transistor portion E and the depletion type transistor portion D, but these are performed separately for each to solve the above-mentioned drawbacks. Attempts have also been made to resolve this issue.

However, this method has drawbacks such as complicating the process and making it difficult to connect the gate electrodes.

Purpose of the Invention The present invention provides an E/D configuration consisting of a field effect transistor that is accelerated using 2DEG, and in which the threshold voltage of the enhancement type transistor part and the threshold voltage of the depletion type transistor part are accurately controlled. In addition, when manufacturing the semiconductor device, it is possible to manufacture a gate portion in a simple process, and also to form an enhancement type transistor portion and a depletion type transistor portion simultaneously and with high precision. It can be so.

Structure of the Invention In the method for manufacturing a semiconductor device according to the present invention, an undoped first semiconductor layer serving as a channel layer, a second semiconductor layer serving as a carrier supply layer, and a depletion layer are provided on a substrate. A third semiconductor layer that serves as a threshold voltage control layer of a type (hereinafter referred to as D type) transistor portion, a fourth semiconductor layer that serves as a second etching stop layer, and a fifth semiconductor layer that serves as a second contact layer. a sixth semiconductor layer serving as a first etching stop layer, and a seventh semiconductor layer serving as a first contact layer; At least the seventh region of the region including the gate
and a step of removing the sixth semiconductor layer, a step of forming a mask film having an opening corresponding to the gate of the D-type transistor portion and an opening corresponding to the gate of the E-type transistor portion, and etching rate of the etching stop layer. By using a selective dry etching method, which has an extremely high etching speed for the contact layer, the fourth semiconductor layer is etched in the E-type transistor part and the sixth semiconductor layer in the D-type transistor part through the opening. exposing the semiconductor layers, and etching the etching stop layer at a higher etching rate than the contact layer through the opening, and in the E-type transistor portion, etching the third semiconductor layer, D
In the type transistor portion, a step of exposing the fifth semiconductor layer, and a selective dry etching method in which the etching rate of the contact layer and the threshold voltage control layer is much higher than the etching rate of the etching stop layer and the carrier supply layer. Depending on
exposing the second semiconductor layer in the E-type transistor portion and the fourth semiconductor layer in the D-type transistor portion through the opening; and adopts a configuration including a step of forming a gate electrode on the second semiconductor layer and, in the D-type transistor portion, on the fourth semiconductor layer.

As can be seen from this configuration, when manufacturing a semiconductor device with an E/D configuration, it is possible to form the gate portions of both E/D mode transistors simultaneously and with high precision using a single mask process.
The threshold voltages of each of the enhancement and depletion transistor sections are precisely controlled.

Embodiment of the Invention FIGS. 1 to 8 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining an embodiment of the present invention, and the following description will be made with reference to these figures. do.

See Figure 2 (a) Molecular beam epitaxial growth (molecular
beam epitaxy (MBE) method or MOCVD
(metal organic vapor deposition)
By appropriately selecting and employing a technique such as the above method, an undoped GaAs layer 22 (first semiconductor layer) that will become a channel layer and an n-type AlGaAs layer that will become an electron supply layer are formed on a semi-insulating GaAs substrate 21. 23
(second semiconductor layer), an n-type GaAs layer 24 (third semiconductor layer) which becomes a transistor control layer in the depletion type transistor portion, and an n-type AlGaAs layer 25 which serves as a second etching stop layer.
(fourth semiconductor layer), an n-type GaAs layer 26 (fifth semiconductor layer) which is a layer capable of ohmic contact, and an n-type GaAs layer 26 which is a first etching stop layer.
AlGaAs layer 27 (sixth semiconductor layer), n-type GaAs layer 2 which is a layer capable of ohmic contact
8 (seventh semiconductor layer).

The data for each semiconductor layer in this case is as follows.

(1) N-type AlGaAs layer 23 which is the second semiconductor layer
Thickness: 300 [Å] Donna concentration: 2×10 ¹⁸ [cm ^-3 ] (2) Thickness of n-type GaAs layer 24, which is the third semiconductor layer: 100 [Å] Donna concentration: 2×10 ¹⁸ [cm ^-3 ] (3) N-type AlGaAs layer 25 which is the fourth semiconductor layer
Thickness: 30 [Å] Donna concentration: 2×10 ¹⁸ [cm ^-3 ] (4) Thickness of n-type GaAs layer 26, which is the fifth semiconductor layer: 400 [Å] Donna concentration: 2×10 ¹⁸ [cm ^-3 ] (5) N-type AlGaAs layer 27 which is the sixth semiconductor layer
Thickness: 30 [Å] Donna concentration: 2×10 ¹⁸ [cm ^-3 ] (6) Thickness of n-type GaAs layer 28, which is the seventh semiconductor layer: 100 [Å] Donna concentration: 2×10 ¹⁸ [cm ^-3 ] See Figure 3 (b) For example, by applying a wet etching method using a hydrofluoric acid etching solution, the enhancement type transistor part E and the depletion type transistor part D can be insulated and separated. Perform mesa etching to still,
In this step, insulation isolation between elements may be performed by applying an ion implantation method.

Refer to FIG. 4(c) For example, by applying the wet etching method using a hydrofluoric acid-based etching solution in the same manner as in step (b), the n-type GaAs layer 28 in the enhancement type transistor portion E can be removed. and n
The type AlGaAs layer 27 is etched. This forms a recess 28A.

Even if the part removed by this etching is only a part as shown in the figure, or
It may be all of the GaAs layer 28 and the n-type AlGaAs layer 27.

See Figure 5 (d) Chemical vapor deposition
By applying the deposition (CVD) method,
The thickness of the silicon dioxide (SiO ₂ ) film 29 is, for example,
Formed to about 3000 [Å].

(e) For example, by applying a wet etching method using a hydrofluoric acid etching solution, the silicon dioxide film 29 is patterned using a photoresist film (not shown) as a mask to form electrode contact windows. Form.

(f) The photoresist film formed when patterning the silicon dioxide film 29 is left as is, and an electrode metal film made of Au.Ge/Au is formed by applying a vapor deposition method.

(g) By dissolving and removing the photoresist film, patterning is performed by lift-off of the electrode metal film, and then alloying is performed to form an ohmic contact electrode 3.
0, 31, 32, 33 are formed.

Refer to FIG. 6 (h) Form a photoresist film 34 and form openings 34E and 34D for creating recesses for forming gate electrodes in the enhancement type transistor portion E and depletion type transistor portion D, respectively. do.

(i) Etching the silicon dioxide film 29 using the photoresist film 34 as a mask by applying a wet etching method using a hydrofluoric acid-based etching solution as the etchant;
Openings 29E and 29D are formed.

(j) By applying a selective dry etching method using a gas containing CCl ₂ F ₂ as an etchant,
Using the photoresist film 34 as a mask, the enhancement type transistor portion E has an n-type
In the depletion type transistor portion D of the GaAs layer 26, the n-type GaAs layer 28 is etched to form recesses 35E and 35D. In this case, the n-type AlGaAs layer 25 is formed in the enhancement type transistor portion E, and the n-type AlGaAs layer 25 is formed in the depletion type transistor portion D.
Needless to say, the AlGaAs layer 27 serves as an etching stopper.

According to the etching technology currently being put into practical use by the inventors, GaAs is approximately 200 times smaller than AlGaAs.
Etching can be done at twice the speed, so
The etching described above can be considered to automatically stop at the surfaces of the n-type AlGaAs electron supply layer 25 and the n-type AlGaAs layer 27, and its controllability is extremely high.

Refer to FIG. 7(k) By applying a wet etching method using a hydrofluoric acid etching solution as an etchant, the n-type AlGaAs layer 25 is etched in the enhancement type transistor portion E and the depletion type transistor portion D is etched. n-type
The AlGaAs layer 27 is etched and the recess 35 is etched.
E and 35D are deepened and GaAs layers 24 and 26
expose the surface of

In this case, etching is performed by etching the n-type AlGaAs layer 2.
5 and n-type AlGaAs layer 27 as described above.
Since it is extremely thin and only has a thickness of [Å], its controllability is good, and even if the underlying layer is thin, the etching will not penetrate through it. Note that as the etching technique applied here, a dry etching method can also be applied.

See Figure 8 (l) By applying a selective dry etching method using a gas containing CCl ₂ F ₂ as an etchant,
In the enhancement type transistor part E, n
The n-type GaAs layer 24 and the n-type GaAs layer 26 in the depletion transistor portion D are etched to further deepen the recesses 35E and 35D. Furthermore, for this etching, n-type
Needless to say, the surface of the AlGaAs layer 23 or the n-type AlGaAs layer 25 serves as a stopper.

Refer to FIG. 1(m) With the photoresist film 34 used as a mask for forming the recesses 35E and 35D left intact, an aluminum (Al) film is deposited to a thickness of e.g. by applying, for example, a vapor deposition method. 3000
Form to about [Å].

(n) The photoresist film 34 used as the mask is dissolved and removed.

As a result, the aluminum film is selectively removed by the so-called lift-off method, and the shot contact gate electrodes 36 and 37 are removed.
is formed.

According to the embodiments described herein, the threshold voltage V _th
It will be understood that a semiconductor device with an E/D configuration in which the E/D structure is accurately controlled can be easily obtained. Furthermore, the n-type
Regarding the GaAs layer 24, n-type AGaAs layer 25, n-type GaAs layer 26, n-type AlGaAs layer 27, n-type GaAs layer 28, etc., their conductivity types and dopant concentrations are determined as required for the cap layer in this type of semiconductor device. They are selected as appropriate within the scope of their role.

FIG. 9 is a cross-sectional side view of a main part of a semiconductor device for explaining another embodiment of the present invention, and the same parts as those explained with reference to FIGS. 1 to 8 are indicated by the same symbols. be.

This semiconductor device is manufactured using the steps of the embodiment described above.
In the step corresponding to (c), the n-type GaAs layer 28 and the n-type
This is an example in which the AlGaAs layer 27 is removed, and even if this is done, the subsequent steps and the performance of the completed semiconductor device are the same as in the previous embodiment.

Effects of the Invention In the method of manufacturing a semiconductor device according to the present invention, an undoped first semiconductor layer serving as a channel layer, a second semiconductor layer serving as a carrier supply layer, and a depletion layer are provided on a substrate. A third semiconductor layer that serves as a threshold voltage control layer of a type (hereinafter referred to as D type) transistor portion, a fourth semiconductor layer that serves as a second etching stop layer, and a fourth semiconductor layer that serves as a second etching stop layer. A semiconductor layer, a fifth semiconductor layer that becomes a second contact layer, a sixth semiconductor layer that becomes a first etching stop layer, and a seventh semiconductor layer that becomes a first contact layer are grown in order. a step of removing the seventh and sixth semiconductor layers in the region including at least the gate in the enhancement type (hereinafter referred to as E type) transistor portion; and removing an opening corresponding to the gate of the D type transistor portion. E
By forming a mask film having an opening corresponding to the gate of the type transistor part and using a selective dry etching method in which the etching rate of the contact layer is much higher than the etching rate of the etching stop layer, E is etched through the opening. A step of exposing the fourth semiconductor layer in the D-type transistor portion and a sixth semiconductor layer in the D-type transistor portion, and etching the etching stop layer through the opening at a rate lower than that of the contact layer. Etching is performed at a high etching rate, and in the E-type transistor portion, the third semiconductor layer is etched.
In the D-type transistor portion, the step of exposing the fifth semiconductor layer, and selective dry etching in which the etching rate of the contact layer and the threshold voltage control layer is much higher than the etching rate of the etching stop layer and the carrier supply layer. exposing the second semiconductor layer in the E-type transistor portion and the fourth semiconductor layer in the D-type transistor portion through the opening by a method; The structure includes a step of forming a gate electrode on the second semiconductor layer in some portions and on the fourth semiconductor layer in the D-type transistor portion.

As can be seen from this configuration, due to the formation and selective removal of the sixth and seventh semiconductor layers, gate electrode formation in both E/D mode transistors can be performed in one step. This kind of E/D
It is possible to shorten the manufacturing process for a semiconductor device having the above structure. In addition, the formation of the recess in the gate electrode area basically does not require wet etching and can be completed with selective dry etching, allowing for precise control of the thickness of the active layer under the gate electrode. Therefore, it is possible to suppress variations in threshold voltage in semiconductor devices to a small level over the entire wafer surface. Furthermore, in the gate electrode forming portion of the E-mode transistor, first, even the fifth semiconductor layer (n-type GaAs contact layer 5) is etched to form the fourth semiconductor layer (n-type GaAs contact layer 5).
The AlGaAs layer 25) is exposed, and then the fourth semiconductor layer (n-type AlGaAs layer 25) is wet-etched to form the third semiconductor layer (n-type GaAs layer 24).
As mentioned above, the process of exposing the third semiconductor layer (n-type
The GaAs layer 24) is of n-type as described in FIG.
Although it is over-etched in the same way as the GaAs layer 4, in the present invention, the fourth semiconductor layer (n-type
The AlGaAs layer 25) is very thin (approximately 30 Å)
Therefore, the etching can be performed with high precision, and the third semiconductor layer (the third semiconductor layer (n-type AlGaAs layer 25) can be etched to allow over-etching when etching the thin fourth semiconductor layer (n-type AlGaAs layer 25). The n-type GaAs layer 24) is sufficiently thick (approximately 100 Å) compared to the extremely thin fourth semiconductor layer (n-type AlGaAs layer 25) that is the object of etching, and therefore, the overetching does not depend on the overetching. There is no risk that everything will be lost, and this will have a great effect on moving the manufacturing of this type of semiconductor device out of the laboratory stage and into commercialization.

[Brief explanation of the drawing]

1 to 8 are cutaway side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIG. 9 is a side view of a semiconductor device manufactured in another embodiment of the present invention. FIG. 10 shows a cutaway side view of a main part of a semiconductor device, and FIG. 10 shows a cutaway side view of a main part of a semiconductor device manufactured by a conventional technique. In the figure, 21 is a semi-insulating GaAs substrate, 22
is an undoped GaAs channel layer (first semiconductor layer), 23 is an n-type AlGaAs electron supply layer (second semiconductor layer), 24 is an n-type GaAs layer (third semiconductor layer), 25 is n-type AlGaAs layer (fourth semiconductor layer),
26 is an n-type GaAs layer (fifth semiconductor layer), 27 is an n-type AlGaAs layer (sixth semiconductor layer), 28 is n-type
GaAs layer (seventh semiconductor layer), 29 is a silicon dioxide film, 29E and 29D are openings, 30, 31,
32, 33 are Ohmic contact electrodes, 34
34E and 34D are openings, 35E and 35D are recesses, and 36 and 37 are shot contacts and gate electrodes, respectively.

Claims (1)

[Claims] 1. On a substrate, an undoped first semiconductor layer serving as a channel layer, a second semiconductor layer serving as a carrier supply layer, and a depletion type (hereinafter referred to as D type) transistor portion. a third semiconductor layer serving as a threshold voltage control layer; a fourth semiconductor layer serving as a second etching stop layer; a fifth semiconductor layer serving as a second contact layer; and a fifth semiconductor layer serving as a first etching stop layer. a step of sequentially growing a sixth semiconductor layer and a seventh semiconductor layer to become a first contact layer; and a step of removing the sixth semiconductor layer; a step of forming a mask film having an opening corresponding to the gate of the D-type transistor portion and an opening corresponding to the gate of the E-type transistor portion; and etching rate of the etching stop layer. By using a selective dry etching method, which has an extremely high etching rate of the contact layer,
A step of exposing a fourth semiconductor layer in the E-type transistor portion and a sixth semiconductor layer in the D-type transistor portion, and through the opening, an etching stop rate lower than the etching rate of the contact layer. etching the layer at a high etching rate to expose the third semiconductor layer in the E-type transistor portion and the fifth semiconductor layer in the D-type transistor portion; and an etching stop layer. By using a selective dry etching method in which the etching rate of the contact layer and the threshold voltage control layer is much higher than the etching rate of the carrier supply layer, the second semiconductor layer is etched through the opening in the E-type transistor portion. ,D
a step of exposing the fourth semiconductor layer in the E-type transistor portion, and exposing the fourth semiconductor layer in the D-type transistor portion; 1. A method for manufacturing a semiconductor device, comprising: forming a gate electrode on the layer.