JP2615714B2 - Heterojunction field effect transistor - Google Patents
Heterojunction field effect transistorInfo
- Publication number
- JP2615714B2 JP2615714B2 JP62311580A JP31158087A JP2615714B2 JP 2615714 B2 JP2615714 B2 JP 2615714B2 JP 62311580 A JP62311580 A JP 62311580A JP 31158087 A JP31158087 A JP 31158087A JP 2615714 B2 JP2615714 B2 JP 2615714B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- semiconductor
- effect transistor
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 7
- 230000005641 tunneling Effects 0.000 claims description 4
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 16
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 14
- 230000004888 barrier function Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔概要〕 本発明はヘテロ接合電界効果トランジスタの中、特に
２次元電子ガス供給層とキャップ層の間にグレーデッド
層を設けた構造の素子に関し、 ゲート電極部のリセス構造形成工程でエッチング停止
点が不定であることに起因して、Vthが変動することの
解消を目的とし、 グレーデッド層とキャップ層の間に、キャップ層とは
被エッチング特性が異なる材料の薄層を介在させて構成
する。DETAILED DESCRIPTION OF THE INVENTION [Overview] The present invention relates to a heterojunction field-effect transistor, particularly to an element having a structure in which a graded layer is provided between a two-dimensional electron gas supply layer and a cap layer. In order to eliminate the variation of Vth due to the indeterminate etching stop point in the structure forming process, a thin material made of a material having different etching characteristics from the cap layer is placed between the graded layer and the cap layer. It is configured with layers interposed.
〔産業上の利用分野〕 本発明はヘテロ接合電界効果トランジスタ（FET）に
関わり、特に２次元電子ガス供給層とキャップ層の間に
グレーデッド層を設けた構造のヘテロ接合FETに関わ
る。The present invention relates to a heterojunction field effect transistor (FET), and more particularly to a heterojunction FET having a structure in which a graded layer is provided between a two-dimensional electron gas supply layer and a cap layer.
ヘテロ接合FETは高電子移動度トランジスタと呼ばれ
ることもあり、超高速の論理素子として注目されてい
る。該素子の基本的な構造は第３図に断面模式図が示さ
れるようなものであって、GaAs基板１の上にチャネル層
である真性GaAs層２、２次元電子ガス給層であるｎ型Al
GaAs層３、オーミックコンタクト形成のためのキャップ
層であるｎ型GaAs層６が順次積層され、リセス構造のAl
ゲート電極７、AuGe/AuのS/D電極８が設けられている。Heterojunction FETs, sometimes called high electron mobility transistors, have attracted attention as ultra-high-speed logic devices. The basic structure of the element is as shown in a schematic sectional view in FIG. 3, and an intrinsic GaAs layer 2 serving as a channel layer on an GaAs substrate 1 and an n-type serving as a two-dimensional electron gas supply layer. Al
A GaAs layer 3 and an n-type GaAs layer 6 serving as a cap layer for forming an ohmic contact are sequentially laminated, and a recessed Al layer is formed.
A gate electrode 7 and an AuGe / Au S / D electrode 8 are provided.
S/D電極８は、熱処理によって合金化された部分が図
示の如くチャネル層にまで到達しているが、キャリヤで
ある電子がチャネルに進入する経路には、合金化領域か
ら直接チャネルに入るものと、キャップ層／電子供給層
を経由してチャネルに入るものとがある。The S / D electrode 8 has a portion alloyed by the heat treatment reaching the channel layer as shown in the figure, but a path through which electrons serving as carriers enter the channel is a material directly entering the channel from the alloyed region. And those entering the channel via the cap layer / electron supply layer.
後者のキャップ層／電子供給層を経由する経路につい
て見ると、そのエネルギ帯構造は第４図に示されるよう
なものであり、電子がｎ−GaAsの領域（６）からｎ−Al
GaAsの領域（３）に進入するには高い障壁を越えなけれ
ばならない。このことはソースのコンタクト抵抗が高く
なることを意味しており、素子特性の向上を阻害する一
因となっている。Looking at the latter path via the cap layer / electron supply layer, the energy band structure is as shown in FIG. 4, and the electrons move from the n-GaAs region (6) to the n-Al
To enter the GaAs region (3), one must cross a high barrier. This means that the contact resistance of the source is increased, which is a factor that hinders the improvement of the device characteristics.
この問題を解決する方策として、電子供給層とキャッ
プ層の間にグレーデッド層を設けることが考えられた。
これは第５図に断面模式図が示される構造を持つもの
で、ｎ型のAlGaAs層４は電子供給層であるｎ−AlGaAs層
３に隣接する側では層３と同一組成であり、上方に行く
に従ってAl量を減じ、キャップ層６につながる部分では
Al量が０のGaAs組成となっている。As a measure to solve this problem, it has been considered to provide a graded layer between the electron supply layer and the cap layer.
This has a structure shown in a schematic sectional view in FIG. 5. The n-type AlGaAs layer 4 has the same composition as the layer 3 on the side adjacent to the n-AlGaAs layer 3 which is an electron supply layer. As the amount goes down, the amount of Al is reduced.
The GaAs composition has an Al amount of 0.
該グレーデッド層を設けた構造では、エネルギ帯構造
は第６図に示されるようなものとなり、ｎ−GaAs領域
（６）とｎ−AlGaAs領域（３）の間には電子の進入を妨
げる障壁は存在せず、従ってコンタクト抵抗も低くな
り、素子特性も向上する。In the structure provided with the graded layer, the energy band structure is as shown in FIG. 6, and a barrier between the n-GaAs region (6) and the n-AlGaAs region (3) for preventing the entry of electrons. Does not exist, the contact resistance is reduced, and the device characteristics are improved.
このように、グレーデッド層を介在させることによっ
て、キャップ層と電子供給層間に生ずる障壁の問題は解
決されるのであるが、該構造では製造工程上の新たな問
題が発生する。As described above, the problem of the barrier generated between the cap layer and the electron supply layer can be solved by interposing the graded layer. However, the structure causes a new problem in the manufacturing process.
即ちこの種のFETでは、ゲート電極のリセス構造を得
るため、ドライエッチングでキャップ層を選択的に除去
する工程が非常に有効であり、CCl2F2をエッチングガス
とする処理が行われるが、第３図の構造の素子を形成す
る場合には、GaAsとAlGaAsの被エッチング速度に200倍
程度の差が存在するため、キャップ層のエッチングが終
わったところでエッチングは事実上停止し、電子供給層
の厚さは当初の堆積層の厚さで定まるのに対し、第５図
の素子では、キャップ層から電子供給層にかけて組成が
連続的に変化しており、エッチング停止位置が不明確で
あり、電子供給層の厚さを一定とすることが困難であ
る。That is, in this type of FET, in order to obtain a recess structure of the gate electrode, a process of selectively removing the cap layer by dry etching is very effective, and a process using CCl 2 F 2 as an etching gas is performed. When an element having the structure shown in FIG. 3 is formed, there is a difference of about 200 times between the etching rates of GaAs and AlGaAs. 5 is determined by the initial thickness of the deposited layer, whereas in the device of FIG. 5, the composition continuously changes from the cap layer to the electron supply layer, and the etching stop position is unclear. It is difficult to make the thickness of the electron supply layer constant.
素子の閾値電圧（Vth）は電子供給層の厚さによって
定まるので、該層の厚さが制御できないということは、
素子を設計通りに形成できないことであり、重大な障害
である。Since the threshold voltage (Vth) of the device is determined by the thickness of the electron supply layer, the fact that the thickness of the layer cannot be controlled means that
The inability to form the device as designed is a serious obstacle.
本発明の目的は、グレーデッド層を持つ素子の形成に
於いて、ドライエッチングが所定の位置で事実上停止す
るような素子構造を提供することであり、それによって
Vthの安定した素子を得ることである。It is an object of the present invention to provide a device structure in which dry etching effectively stops at a predetermined position in the formation of a device having a graded layer, whereby
The goal is to obtain a device with a stable Vth.
上記目的を達成するため、本発明のヘテロ接合FETで
は 前記第２の半導体層と前記第３の半導体層の間に、前
記第２の半導体層と前記第３の半導体層の間に、前記第
２の半導体よりも被エッチング速度が小である材料より
成る第４の半導体層が設けられており、該第４の半導体
層は電子のトンネル確率が素子特性を阻害しない程度の
厚さを備えたものとなっている。In order to achieve the above object, in the heterojunction FET of the present invention, the second semiconductor layer is provided between the second semiconductor layer and the third semiconductor layer, and the second semiconductor layer is provided between the third semiconductor layer. A fourth semiconductor layer made of a material whose etching rate is lower than that of the second semiconductor; and the fourth semiconductor layer has such a thickness that the tunneling probability of electrons does not impair device characteristics. It has become something.
被エッチング特性が異なる材料としてAlGaAsを選んだ
場合、CCl2F2をエッチングガスとするドライエッチング
では、AlGaAs層は10Å程度でもエッチングストッパとし
て機能する。更に、該層の厚さが100Å程度以下であれ
ば、電子のトンネル確率は十分に高く、コンタクト抵抗
は低く抑えられる。When AlGaAs is selected as a material having different etching characteristics, in dry etching using CCl 2 F 2 as an etching gas, the AlGaAs layer functions as an etching stopper even at about 10 °. Further, when the thickness of the layer is about 100 ° or less, the tunneling probability of electrons is sufficiently high, and the contact resistance is suppressed low.
第１図は本発明実施例の素子の構造を示す断面模式図
である。第３図或いは第５図と同じ符号で表されるもの
は同じ材料或いは同じ機能要素であり、第５図の構造と
の相違点はｎ型AlGaAsであるストッパ層５が、グレーデ
ッド層４とキャップ層６の間に設けられているところで
ある。FIG. 1 is a schematic sectional view showing the structure of an element according to an embodiment of the present invention. 3 or 5 are the same materials or the same functional elements. The difference from the structure of FIG. 5 is that the stopper layer 5 made of n-type AlGaAs is It is provided between the cap layers 6.
現実のヘテロ接合FETに於ける各構成層の厚さの一例
をあげると、チャネル層であるｉ−GaAs層２は3000Å、
２次元電子供給層であるｎ−AlGaAs層３は200Å、グレ
ーデッド層であるｎ−AlGaAs層４は200Å、キャップ層
であるｎ−GaAs層６は600Åであって、リセス構造のAl
ゲート電極７、AuGe/AuのS/D電極８が設けられている。To give an example of the thickness of each constituent layer in an actual heterojunction FET, the i-GaAs layer 2 which is a channel layer has a thickness of 3000.
The n-AlGaAs layer 3 as a two-dimensional electron supply layer has a thickness of 200 °, the n-AlGaAs layer 4 as a graded layer has a thickness of 200 °, and the n-GaAs layer 6 as a cap layer has a thickness of 600 °.
A gate electrode 7 and an AuGe / Au S / D electrode 8 are provided.
エッチングストッパであるｎ−AlGaAs層４の厚さは、
既述せる如く、10〜100Åの範囲でよいが、トンネル確
率を十分に大とするためには50Å以下であることが望ま
しい、第１図の素子ではゲート電極下のｎ−AlGaAs層４
は除去されているが、HF系のウェットエッチングによれ
ばAlGaAs層だけを除去することが可能である。また、ゲ
ート電極下に薄いAlGaAs層が残存しても、ヘテロ接合FE
Tとして機能することは変わらない。The thickness of the n-AlGaAs layer 4 serving as an etching stopper is
As described above, the angle may be in the range of 10 to 100 [deg.], But is desirably 50 [deg.] Or less in order to sufficiently increase the tunnel probability. In the device shown in FIG.
Has been removed, but only HF-based wet etching can remove only the AlGaAs layer. Even if a thin AlGaAs layer remains under the gate electrode, the heterojunction FE
It still functions as a T.
該実施例の素子のエネルギ帯構造は第２図に示される
ようになる。即ち、概略は第６図と同じであるが、キャ
ップ層領域（６）とグレーデッド層領域（４）の間に、
極めて薄いｎ−AlGaAs層領域（５）が存在する点が異な
っている。なお、該層の不純物濃度は2.0×1018cm-3で
ある。The energy band structure of the device of this embodiment is as shown in FIG. That is, although the outline is the same as that of FIG. 6, between the cap layer region (6) and the graded layer region (4),
The difference is that an extremely thin n-AlGaAs layer region (5) exists. Note that the impurity concentration of the layer is 2.0 × 10 18 cm −3 .
このような領域が存在しても、該領域の厚さが極めて
小であるため、電子はトンネリングによって簡単に通過
し、ソース電極のコンタクト抵抗は殆ど高められること
がないのに対し、製造工程ではエッチングストッパとし
て機能するので、素子の電子供給層の厚さは、MBEなど
によるエピタキシャル成長層の厚さと正確に一致するこ
とになる。Even if such a region exists, since the thickness of the region is extremely small, electrons easily pass by tunneling, and the contact resistance of the source electrode is hardly increased. Since the element functions as an etching stopper, the thickness of the electron supply layer of the device exactly matches the thickness of the epitaxial growth layer formed by MBE or the like.
以上説明したように本発明の素子では、その製造工程
においてエッチングストッパが有効に機能するので、Vt
hのばらつきが狭い範囲に抑えられる。また、素子特性
は従来の素子と殆ど同じである。As described above, in the device of the present invention, since the etching stopper functions effectively in the manufacturing process, Vt
The variation in h can be suppressed to a narrow range. The element characteristics are almost the same as those of the conventional element.
【図面の簡単な説明】 第１図は本発明のFETの構造を示す断面模式図、 第２図は本発明のFETのエネルギ帯構造を示す図、 第３図は公知のFETの構造を示す断面模式図、 第４図は公知のFETのエネルギ帯構造を示す図、 第５図は改良された公知FETの構造を示す断面模式図、 第６図は改良された公知FETのエネルギ帯構造を示す図 であって、 図において １はGaAs基板、 ２はｉ−GaAs、 ３はｎ−AlGaAs、 ４はグレーデッドｎ−AlGaAs、 ５はｎ−AlGaAs、 ６はｎ−GaAs、 ７はゲート電極、 ８はS/D電極 である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing the structure of the FET of the present invention, FIG. 2 is a view showing the energy band structure of the FET of the present invention, and FIG. FIG. 4 is a schematic view showing an energy band structure of a known FET, FIG. 5 is a schematic sectional view showing an improved structure of a known FET, and FIG. 6 is a diagram showing an energy band structure of an improved known FET. In the figure, 1 is a GaAs substrate, 2 is i-GaAs, 3 is n-AlGaAs, 4 is graded n-AlGaAs, 5 is n-AlGaAs, 6 is n-GaAs, 7 is a gate electrode, 8 is an S / D electrode.
Claims (1)
元電子ガス供給層であり電子親和力が前記チャネル層半
導体よりも小である第１のｎ型半導体層と、オーミック
コンタクト形成領域に形成され、電子親和力が前記第１
のｎ型半導体より大である第２のｎ型半導体層が積層さ
れた構造を有するヘテロ接合電界効果トランジスタに於
いて、 前記第１の半導体層と第２の半導体層の間に、組成が前
記第１の半導体の組成から前記第２の半導体の組成に連
続的に変化する第３のｎ型半導体層が設けられ、更に 前記第２の半導体層と前記第３の半導体層の間に、前記
第２の半導体よりも電子親和力が小で且つ被エッチング
速度が小である材料より成る第４の半導体層が設けられ
ており、 該第４の半導体層は電子のトンネル確率が素子特性を阻
害しない程度の厚さを備えたものであることを特徴とす
るヘテロ接合電界効果トランジスタ。1. A first n-type semiconductor layer, which is a two-dimensional electron gas supply layer and has an electron affinity smaller than that of the channel layer semiconductor, on an intrinsic semiconductor layer which is a channel layer, and is formed in an ohmic contact formation region. And the electron affinity is the first
In a heterojunction field effect transistor having a structure in which a second n-type semiconductor layer which is larger than the n-type semiconductor is stacked, the composition between the first semiconductor layer and the second semiconductor layer is A third n-type semiconductor layer which continuously changes from the composition of the first semiconductor to the composition of the second semiconductor is provided; and the third n-type semiconductor layer is provided between the second semiconductor layer and the third semiconductor layer. A fourth semiconductor layer made of a material having a smaller electron affinity and a lower etching rate than the second semiconductor is provided, and the fourth semiconductor layer does not impair the device characteristics due to the tunneling probability of electrons. A heterojunction field-effect transistor having a thickness of the order of magnitude.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62311580A JP2615714B2 (en) | 1987-12-09 | 1987-12-09 | Heterojunction field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62311580A JP2615714B2 (en) | 1987-12-09 | 1987-12-09 | Heterojunction field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01152674A JPH01152674A (en) | 1989-06-15 |
| JP2615714B2 true JP2615714B2 (en) | 1997-06-04 |
Family
ID=18018948
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62311580A Expired - Lifetime JP2615714B2 (en) | 1987-12-09 | 1987-12-09 | Heterojunction field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2615714B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100231704B1 (en) * | 1996-11-18 | 1999-11-15 | 정선종 | A substrate structure for e-mesfet and d-mesfet and its fabrication method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6124265A (en) * | 1984-07-13 | 1986-02-01 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS60231368A (en) * | 1984-05-01 | 1985-11-16 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH0789585B2 (en) * | 1984-12-28 | 1995-09-27 | 日本電気株式会社 | Semiconductor device |
| JPS62202564A (en) * | 1986-03-03 | 1987-09-07 | Agency Of Ind Science & Technol | Hetero-junction field effect transistor |
-
1987
- 1987-12-09 JP JP62311580A patent/JP2615714B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01152674A (en) | 1989-06-15 |
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