JPS6124265A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simultaneously form the gate of both E/D transistors by one mask process precisely and to enable accurately controlling the threshold voltage of each enhancement type transistor and depletion type transistor by such a method as a specific process in the manufacture of the gate. CONSTITUTION:The first and the second semiconductor layers 22, 23 for a channel layer and a carrier supply layer, the third and the fourth semiconductor layers 24, 25 for the threshold voltage control layer and the etching stop layer of a depletion type transistor (D) and the fifth semiconductor layer 26 which enables ohmic contact are grown on a substrate 21. Then, an insulation film 27 is formed on all the surface, the insulation film 27 of a region where an enhancement type transistor (E) is to be formed is selectively removed and a depression which reaches to the fourth semiconductor layer 25 at (E) region for forming a gate electrode is formed. Then, the extension of the above-mentioned depression at (E) region reaching to the surface of the second semiconductor layer 23 and the formation of the depression for forming the gate electrode reaching to the surface of the fourth semiconductor layer 25 at (D) region are simultaneously carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention provides enhancement/depression ( enhance
element/depleti.

The present invention relates to an improvement in a method for manufacturing a semiconductor device having a configuration of n:E/I)).

[Conventional technology]

In one ship, in this type of field effect transistor,
Untopped G formed on a semi-insulating GaAS substrate
a As channel layer and rl type Δ formed thereon
the n-type A7! comprising a βGaAs electron supply layer, the dark voltage V of which is present between the undoped GaAs channel layer and the gate electrode junction surface; Ga As
It is determined by the thickness of the semiconductor layer including the electron supply layer.

Apart from this, in current logic circuits, E/
It can be said that a D-configuration semiconductor device is indispensable. Of course, in the semiconductor device Mq of this E/D configuration, a field effect transistor having a dark-mode threshold voltage Vth and a field-effect transistor having a D-mode dark voltage vth are on the same substrate. It must be formed and must be punched.

Therefore, when attempting to obtain a semiconductor device with an E/D configuration using a high-speed field effect transistor using a 20EG layer, the Schottky gate electrode and the semiconductor layer are in contact because of the dark voltage relationship. It is necessary to fabricate two types of field effect transistors with different depths on the same substrate.

When manufacturing such a semiconductor device, the conventional technology that was initially implemented used a selective dry etching method using CCl2F2-containing gas as an etchant when processing the enhancement type transistor part.
The controllability and uniformity of the dark voltage is good, but when processing the depression type transistor part, the wet etching method with no selectivity is applied, so the controllability and uniformity are not good either. was there.

In order to eliminate such drawbacks, the following technology has been provided.

FIG. 15 is a cross-sectional side view of essential parts of this type of semiconductor device.

In the figure, l is a semi-insulating GaAs substrate, 2 is an undoped GaAs channel layer, and 3 is an n-type AfiGaA
s electron supply layer, 4 is an n-type GaAs layer, and 5 is an n-type Ad! G
aAs layer, 6 is n-type GaAs contact layer, 7 is E
/D insulation groove, 8, 9, 10, 11 are ohmic contact electrodes, 12 and 13 are Schottky contact gate electrodes, 14 is a 2DEG layer, E is an enhancement type transistor part, and D is a depletion type transistor part. are shown respectively.

When manufacturing this half λJ body device, the biggest problem is, as mentioned above, that the Schottky gate electrodes 12 and 1
3 as n-type Aj! GaAs layer 5 and Schottky
In order to bring the contact gate electrodes 13 into contact with the n-type AβGaAs electron supply layer 3, recesses are formed.

The steps for manufacturing the semiconductor device using the conventional technique are as follows.

First, a recess is formed for the enhancement type transistor portion E. To do this, first, the gate portion is patterned, and the n-type GaAs contact layer 6 is
Wet etching is performed until the type A jl Ga aAs layer 5 is removed. Next, the same photoresist film is used to pattern the gate part in the depression type transistor part, and the enhancement type transistor, part E, and depression type transistor are patterned. Selective dry etching is performed on the enhancement type transistor portion E. It stops at the GaAs electron supply layer 3, and in the depletion type transistor part, n
It stops at the type AJGaAs layer 5.

However, the existence of shortcomings in this technology was also recognized.

Therefore, as mentioned above, n-type A7! A wet etching method is applied to remove the GaAs layer 5, but the underlying n-type GaAs layer 4 has a thickness of 1110 C.]
For example, the diameter is approximately 5 (cm) (2
It is quite difficult to stop the etching on the surface of the n-type GaAs layer 4 over the entire surface of the wafer, especially when the gate electrode length is 1 [μm].
] When the etching solution reaches a certain level, the circulation of the etching solution is not carried out well, and the etching speed changes. Therefore, it is not easy to control the etching.

In all of the above-described techniques, the formation of the recess and the formation of the gate electrode are performed simultaneously on one enhancement type transistor portion and one depletion type transistor portion, but these are performed separately for each portion to eliminate the above-mentioned drawbacks. Attempts have also been made to resolve this issue.

However, doing it this way may complicate the process or
There is a drawback that it becomes difficult to connect the gate electrodes.

[Problem that the invention seeks to solve]

The present invention consists of a field effect transistor which is made faster by using 2DEG, and has an E/D configuration in which the dark value voltage of the enhancement type transistor part and the dark value voltage of the depletion type transistor part are accurately controlled. To provide an improved semiconductor device, and in manufacturing the semiconductor device, a gate portion can be manufactured in a simple process, and an enhancement type transistor portion and a depletion type transistor portion can be formed simultaneously and with high precision. Do it like this.

Means for Solving Problem C] In the method for manufacturing a semiconductor device according to the present invention, first and second layers, which become a channel layer and a carrier supply layer, are formed on a substrate.
, the third and fourth semiconductor layers which serve as the threshold voltage control layer and process stop layer of the depletion type transistor portion, and the fifth semiconductor layer which is a layer capable of ohmic contact. grow sequentially, then
An insulating film is formed on the entire surface, and then an enhancement type l
- selectively removing the insulating film in the region where the transistor portion is to be formed, then forming a recess for forming the gate electrode that reaches the fourth semiconductor layer in the enhancement type transistor portion; In the enhancement type transistor part, the recess for forming the gate electrode extends to reach the surface of the second semiconductor layer, and in the depletion type transistor part, the gate electrode is formed from the insulating film to the surface of the fourth semiconductor layer. The formation of the recesses for each purpose is carried out at the same time.

[Effect]

As can be seen from the content of +14, when manufacturing a semiconductor device with an E/D configuration, F,
/r) It is possible to form the gate portions of both mode transistors at the same time with high precision, and the dark voltage of each of the enhancement type 1-type transistor portion and the depletion type transistor portion can be accurately controlled.

Embodiment of the Invention FIGS. 1 to 8 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures. do.

See Figure 2 (a) Molecular beam epitaxial growth (molecular beam epitaxial growth)
Ar beam epitaxy (MBE) method or MOCVD (metal organic c
chemical vapor deposit
By appropriately selecting and employing a technique such as on) method, an undoped GaAs layer 22 (first semiconductor layer) that becomes a channel layer and an n-type layer that becomes an electron supply layer are formed on a semi-insulating GaAs substrate 21. AllGaAs layer 23 (second semiconductor layer)
, an n-type GaAs layer 24 (third semiconductor layer) serving as a dark voltage control layer in the depletion type transistor portion, and an n-type AβGaAS layer 25 serving as an etching stop layer.
(fourth semiconductor layer) and an n-type GaAs layer 26 (fifth semiconductor layer), which are layers capable of ohmic contact, are grown.

The data for each semiconductor layer in this case is as follows.

(1) N-type A#GaAs layer 2 which is the second semiconductor layer
Regarding 3, the thickness: 300 (people) Toner concentration: 2X1018 (Cm bow) (2) The third semiconductor layer, n-type GaAs layer 2□4 Thickness: 100 (people) 1" Boo? Agricultural degree: 2 X 1 0 I8
(cm-3) (3) N-type A which is the fourth semiconductor layer
Thickness of IGaA's layer 25: 30 [person] Isu concentration: 2 X l O" [cm-3] (4)
Thickness of the n-type GaAs layer 26, which is the fifth semiconductor layer: 400 (people) Toner concentration: 72 x 101 B (am-'') See Figure 3 (L+l) By applying the etching method, mesa etching is performed to insulate and separate the enhancement type transistor part E and the depletion type transistor part.In addition, in this process, the ion implantation method is applied. Depending on the method, insulation and isolation between elements may be performed.

See Figure 4 (C) Chemical vapor deposition
.

A silicon dioxide (SiOz) film 27 is formed to a thickness of, for example, about 300 mm (1 person) by applying the ur deposition (CVD) method.

(By applying the dl C, V D method, a silicon nitride (St3N4) film 28 is formed to a thickness of, for example, about 1000 [layers].

+8) For example, by applying a dry etching method using CF4 as an etchant, photo-etching can be achieved.
The silicon nitride film 28 is patterned using a resist film (not shown) as a mask, and an opening 28A is formed in the enhancement type transistor portion E to expose a portion of the silicon dioxide film 27.

For example, by applying a wet etching method using a hydrofluoric acid-based etching solution, the silicon dioxide film 27 can be patterned using a photoresist film (not shown) as a mask. to form an electrode contact window.

fgl By leaving the photoresist film formed when patterning the silicon dioxide film 27 as it is and applying the vapor deposition method, Au-Ge/A
An electrode metal film made of u is formed.

fhl By dissolving and removing the photoresist film, patterning is performed by lift-off of the electrode metal film, and then alloying is performed to form an ohmic contact electrode of 29°30.31. form 32.

Refer to FIG. 6. A photoresist film 33 is formed, and openings 33E and 33D are formed to form recesses for forming gate electrodes in the enhancement type transistor portion E and depletion type transistor portion, respectively.

See Figure 7 (j) By applying a wet etching method using a hydrofluoric acid-based etching solution as the etchant,
The silicon dioxide film 27 is etched using the photoresist film 33 as a mask to form an opening 27E.

(kl By applying a selective dry etching method using gas containing CC12F 2 as an etchant, using the photoresist film 33 as a mask, the n-type GaAs layer 26 is etched in the enhancement type transistor portion E, and the recess 34E is etched. form.

In this case, it goes without saying that the n-type AAGaAs layer 25 serves as an etching stopper in the enhancement type transistor portion E, and the silicon nitride film 28 serves as an etching stopper in the diversion type transistor portion.

According to the enching technology currently put into practical use by the present inventors, G'a A s becomes Aj! Approximately 200 compared to GaAs
Since the etching speed can be doubled, the etching can be considered to automatically stop at the surface of the n-type 71/GaAs electron supply layer 25, and its controllability is extremely high.

Refer to Figure 8 (11 By applying a wet etching method using a hydrofluoric acid-based etching solution as an etchant, the enhancement type transistor part R can be etched by ■1 type A1.G.
The silicon nitride film 28 and the silicon dioxide film 26 of the aAs layer 25 and the deep solution type transistor portion are etched, the recess 34B is extended and the opening 27D is formed, and the GaAs layer 24 and the silicon dioxide film 26 are etched. 26 surface is exposed.

In this case, the etching is performed using n-type A (lGaAs layer 25, as mentioned above, which is only 30 mm thick and extremely thin, so its controllability is good, and even if the underlying layer is thin, the etching will penetrate through.) Note that a dry etching method can also be applied as the etching technique applied here.

By applying a selective dry etching method using a gas containing hlccm22F2 as an etchant, the n-type GaAs layer 24 is removed in the enhancement type transistor portion E.
Also, in the depletion type transistor part, 5J1326 was etched on the n-type Ga, and the recess 34 was etched.
E is extended and a recess 34D is formed. Furthermore, for this etching, n-type Aj! GaAs layer 23 or n-type Al
Needless to say, the surface of the 2GaAs layer 25 serves as a stopper.

See FIG. 1 (nl) With the photoresist film 33 used as a mask for forming the recesses 34E and 34D left as is, aluminum (
AN) A film is formed to a thickness of, for example, about 3000 [people].

(θ) Photoresist film 33 used as the mask
Dissolve and remove.

As a result, the aluminum film is selectively removed by the so-called lift-off method, and the aluminum film is removed selectively by the so-called lift-off method.
Gate electrodes 35 and 36 are formed.

It will be understood that according to the embodiments described here, it is easy to obtain a semiconductor device with an E/D configuration in which the dark value voltage vth is accurately controlled. Note that the n-type GaAs layer 24, the n-type A
The conductivity type and dopant concentration of the 12GaAs layer 25, the n-type GaAs layer 2fi, etc. are appropriately selected within a range that serves as a cap layer in this type of semiconductor device.

FIGS. 9 to 14 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining other embodiments of the present invention, and the following description will be made with reference to these figures. In each figure, the same parts as those described with respect to FIGS. 1 to 8 are indicated by the same symbols. Furthermore, in this embodiment, the steps up to the formation of the silicon dioxide film 27 are the same as those in the embodiments explained with reference to FIGS. 1 to 8, so the explanation will be omitted and the next step will be explained.

(See Figure 9 fa) By applying a wet etching method using a hydrofluoric acid-based etching solution as an etchant, a photoresist film (not shown) is used as a mask to remove carbon dioxide in the area of the enhancement type transistor. Etching is performed to reduce the thickness of the silicon film 27 to about 1000 cm.

Refer to FIG. 10 (b) The photoresist film used in the step fal is removed, a new photoresist film mask (not shown) is formed, and a hydrofluoric acid-based etching solution is used as an etchant. By applying the wet etching method used previously, the silicon dioxide film 27 is patterned to form electrode contact windows.

fcl By leaving the photoresist film formed when patterning the silicon dioxide film 27 as it is and applying the vapor deposition method, A u-Ge
An electrode metal film consisting of /Au is formed.

(d+ By dissolving and removing the fumetresist film, patterning is performed by lift-off of the electrode metal film, and each time alloying is performed, the ohmic contact electrode is 29°30.31. form 32.

Refer to FIG. 11. A resist film 33 is formed, and openings 331:1. and 33D
form.

See Figure 12 (fl) By applying a wet etching method using a hydrofluoric acid-based etching solution as the etchant,
The silicon dioxide film 27 is etched using the photoresist film 33 as a mask to form openings 27B and recesses 27D.
′ is formed.

That is, this etching creates an opening 27. in the silicon dioxide film 27 in the enhancement type transistor portion E. E
It is carried out only for the time it takes to form.

(gl By applying a selective dry etching method using gas containing CC7t2F2 as an etchant, using the photoresist film 33 as a mask, the n-type QaAs 26 at the enhancement type transistor portion is etched to form the recess 34E. Form.

In this case, the n-type AnGaAs layer 25 serves as an etching stopper in the enhancement type transistor portion E, and the silicon dioxide film 27 serves as an etching stopper in the depletion type transistor portion.

See Figure 13 (hl) By applying a wet etching method using a hydrofluoric acid-based etching solution as an etchant,
In the enhancement type transistor part E, n-type Ajl
The GaAs layer 25 and the silicon dioxide film 27 in the depression type transistor area are etched to extend the recess 34E and form the opening 27D.
The surfaces of the As layers 24 and 26 are exposed. Incidentally, as the etching technique in this case, a dry etching method can be applied.

(By applying a selective dry etching method using a gas containing ilccβzFz as an etchant, the r1 type GaAs layer 2 is removed in the enhancement type transistor portion E.
4, the n-type GaAs layer 26 is etched in the depression A transistor area, and the recess 34E is etched.
is extended and a recess 34D is formed. Furthermore, for this etching, n-type Aj! GaAs layer 23 or n-type Aj
! The surface of the GaAs layer 25 serves as a stopper.

Refer to FIG. 14 01 With the photoresist film 33 used as a mask for forming the recesses 34E and 34D left as is,
By applying a vapor deposition method, an aluminum film is formed to a thickness of about 3000 mm.

(k) Photoresist (-
The film 33 is dissolved and removed.

As a result, the aluminum film is selectively removed by a so-called lift-off method, and Schottky contact gate electrodes 35 and 36 are formed.

The performance of the semiconductor device obtained according to this embodiment is completely the same as that manufactured according to the previous embodiment.

Effects of the Invention In the method for manufacturing a semiconductor device according to the present invention, first and second semiconductor layers, which become a channel layer and a carrier supply layer, and a threshold voltage control layer and a second semiconductor layer of a depletion type 1-transistor portion are formed on a substrate. The third and fourth semiconductor layers, which serve as etching stop layers, and the fifth semiconductor layer, which enables ohmic contact, are grown in the above order, and then,
forming an insulating film over the entire surface, selectively removing the insulating film in a region where an enhancement type transistor portion is to be formed, and then forming a gate electrode that reaches the fourth semiconductor layer in the enhancement type transistor portion; After that, in the enhancement type transistor part, the recess for forming the gate electrode is extended until it reaches the surface of the second semiconductor layer, and in the depletion type transistor part, the recess is extended from the insulating film to the second semiconductor layer surface. Formation of recesses for forming gate electrodes reaching the surface of the semiconductor layer No. 4 is performed simultaneously.

As can be seen from this configuration, due to the selective removal of the insulating film, both the E/D mode transistors and the CJ
Forming the gate electrode is a one-time process, and this type of IE
/I) It is possible to shorten the manufacturing process in a semiconductor device having the configuration. In addition, wet etching is basically not used to form the recess in the gate electrode part.
Since the process can be completed with selective dry etching, the thickness of the active layer under the gate electrode can be controlled with high precision, making it possible to suppress variations in threshold voltage in semiconductor devices over the entire wafer surface. .

[Brief explanation of the drawing]

1 to 8 are cross-sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIGS. 9 to 14 are other embodiments of the present invention. FIG. 15 shows a cutaway side view of a main part of a semiconductor device at key points in the process for explaining the process, and FIG. 15 shows a cutaway side view of a main part of a semiconductor device manufactured by a conventional technique. In the figure, 21 is a semi-insulating GaAs substrate, 22 is an undoped GaAs channel N (first semiconductor layer), and 23 is a semi-insulating GaAs substrate.
is an n-type ANGaAs electron supply layer (second semiconductor layer), 2
4 is an n-type GaAs layer (third semiconductor layer), 25 is an n-type A layer
11 GaAs layer (fourth semiconductor layer), 26 n-type GaA
s layer (fifth semiconductor layer), 27 is a silicon dioxide film, 2
8 is a silicon nitride film, 29.30, 31.32 are ohmic contact electrodes, 33 is a photoresist film, 3
3E and 33D are openings, 34B and 34D are recesses, 35
and 36 indicate Schottky contact gate electrodes, respectively. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 1 Figure 2 Figure 3 Figure 5 Figure 7 Figure 9 Figure 11 Figure 13 Figure 15

Claims (1)

[Claims] First and second semiconductor layers serving as a channel layer and carrier supply layer, and a third semiconductor layer serving as a threshold voltage control layer and an etching stop layer for a depletion type transistor portion are formed on the substrate.
A fourth semiconductor layer and a fifth semiconductor layer, which is a layer capable of ohmic contact, are grown in the above-mentioned order, an insulating film is formed on the entire surface, and then an insulating film is formed on the area where the enhancement type transistor portion is to be formed. The insulating film in the enhancement type transistor portion is selectively removed, and then a recess for forming a gate electrode is formed that reaches the fourth semiconductor layer in the enhancement type transistor portion, and then the gate electrode is formed in the enhancement type transistor portion. simultaneously forming a recess for forming a gate electrode extending from the insulating film to the surface of the fourth semiconductor layer in the depression type transistor portion; 1. A method of manufacturing a semiconductor device, comprising the steps of: