JPH04125938A - Field effect semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize high speed operation by forming a Schottky contact part between a gate electrode and an active layer, in a line and space type, and reducing the capacitance of the area corresponding with the line part. CONSTITUTION:A first resist film is spread on the whole region of an N-type GaAs active layer 2 between a source electrode 4 and a drain electrode 5. Said film is selectively exposed and developed, thereby forming a negative resist film 6 in the effective gate width in the direction perpendicular to the direction connecting the source electrode 4 and the drain electrode 5. Said film 6 constitutes a line and space type wherein the widths of a line and a space are about 0.1mum. A second positive resist film is spread on the whole surface containing the film 6, and selectively exposed and developed, thereby forming a positive resist film 7 having an aperture of a gate pattern intersecting the lines of the negative resist film 6. By using said film 7 as a mask, a recess etching part 8 is formed. Further, on the whole surface, Schottky electrode material is evaporated, and a residual resist layer is eliminated. The space part of a gate electrode 10 formed by lift-off comes into Schottky contact with the N-type GaAs active layer 2, and the line part keeps a specified interval from the active layer 2.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a field effect semiconductor device, particularly a Schottky gate type field effect semiconductor device having a characteristic gate electrode structure, and a method for manufacturing the same, which reduces gate capacitance, enables high-speed operation, The purpose of the present invention is to provide a field effect semiconductor device having low noise characteristics, and to provide a manufacturing method suitable for the same. In a field effect semiconductor device comprising a source electrode and a drain electrode formed to face each other, and a gate electrode formed in Schottky contact on an active layer between the source electrode and the drain electrode, the active layer of the gate electrode The Schottky-contacting portion is configured to have a line-and-space shape or a dot-and-space shape at least in a portion within the effective gate width.

In addition, a process of forming an active layer on a semi-insulating substrate, a process of forming a source electrode and a drain electrode facing each other on this active layer, and a process of forming a small (both A part of the effective gate width has line and space or dot and space patterns longer than the gate length.
A step of forming a first resist film in a space shape, and a step of forming a second resist film having an opening that intersects with the line or dot on the line and space shape or dot and space shape first resist film. The method is configured to include a step of forming a resist film, a step of depositing a gate electrode material through the opening, and a step of removing a second resist film and the second resist film.

[Industrial application field]

The present invention relates to a field effect semiconductor device, and particularly to a Schottky gate field effect semiconductor device having a characteristic structure of a gate electrode, and a method for manufacturing the same.

[Prior Art] Prior to explaining the present invention, a method for manufacturing an example of a conventional Schottky gate field effect transistor and its structure will be explained.

FIG. 2 is a manufacturing process diagram of an example of a conventional Schottky gate field effect transistor.

In this figure, 21 is a CraAs semi-insulating substrate, 22
23 is an n-type GaAs active layer, 23 is an isolation region, 24 is a source electrode, 25 is a drain electrode, and 26 is a Schottky gate electrode.

The main manufacturing process of this Schottky gate field effect transistor is as follows.

First step (see FIG. 2(a)) An n-type GaAs layer is epitaxially grown on a GaAs semi-insulating substrate 21 to form an n-type GaAs active layer 22.

Next, ions are implanted in a frame shape surrounding the device region to form an n-type GaAs active layer 22 and a GaAs semi-insulating substrate 21.
A defect layer is formed to form an inter-element isolation region 23.

Second step (see FIG. 2(b)) On the n-type GaAs active layer 22, a source electrode 24 and a drain electrode 25, which are in resistance contact with this active layer, are formed facing each other.

Third step (see FIG. 2(c)) A part of the n-type CaAs active layer 22 between the source electrode 24 and the drain electrode 25 is recess-etched to form a recess, and in this recess, the n-type GaAs A gate electrode 26 is formed in Schottky contact with the active layer 22.

Through the above manufacturing process, a source in resistance contact with the n-type GaAs active layer 22 is placed in the device region surrounded by the device isolation region 23 of the n-type GaAs active layer 22 formed on the GaAs semi-insulating substrate 21. A Schottky gate field effect transistor having a structure having an electrode 24, a drain electrode 25, and a Schottky gate electrode 26 whose entire surface is in contact with the n-type CaAs active layer 22 is formed.

[Problem to be solved by the invention] Factors that enable field-effect semiconductor devices such as field-effect transistors to operate at high speed include shortening gate length, reducing series resistance, reducing parasitic capacitance, and reducing gate resistance. , a chain of improvement in carrier mobility is considered, and attempts are being made to improve each factor.

Among these, attempts have been made in recent years to improve high-speed operation by shortening the gate length.
m, and it is difficult to recommend further miniaturization.

In addition, regarding attempts to reduce gate capacitance, gate capacitance is inevitably determined depending on gate length, gate width, and carrier concentration, but there are restrictions on shortening gate length as described above, and gate width is There are limits to making the diameter narrower or lowering the carrier concentration, depending on the desired characteristics.

Therefore, it is difficult to further reduce the gate capacitance using the conventional gate structure, and it is necessary to develop a new gate structure.

In view of this situation, it is an object of the present invention to provide a field-effect semiconductor device that employs a novel gate structure to reduce gate capacitance, is capable of high-speed operation, and has low noise characteristics, and also provides a field-effect semiconductor device that can be manufactured appropriately. The purpose is to provide a method.

[Means to solve the problem]

A semi-insulating substrate according to the present invention, an active layer formed thereon, a source electrode and a drain electrode formed facing each other on the active layer, and an active layer between the source electrode and the drain electrode. In a field effect semiconductor device comprising a gate electrode formed on a layer in Schottky contact, the portion of the gate electrode that makes Schottky contact with the active layer has a line-and-space shape or a line-and-space shape at least in a part of the effective gate width. A dot-and-space configuration was adopted.

Further, the method for manufacturing a field effect semiconductor device according to the present invention includes a step of forming an active layer on a semi-insulating substrate;
A step of forming a source electrode and a drain electrode facing each other on the active layer, and forming a line with a length equal to or longer than the gate length in at least a part of the effective gate width in the region immediately below the gate electrode. a step of forming a first resist film in an and-space shape or a dot-and-space shape;
A step of forming a second resist film having openings that intersect with the lines or dots on the line-and-space or dot-and-space first resist film, and introducing the gate electrode material through the openings. The second resist film and the second resist film were removed.

[Function] As mentioned above, the Schottky contact portion between the gate electrode and the active layer is made into a line-and-space shape or a dot-and-space shape, and the area of the actual contact portion is made smaller than that of the conventional method. By significantly reducing the gate-source capacitance by 10-50% compared to when the entire surface of the gate is in contact with the active layer, the gate-source capacitance can be reduced to 10-50%.
% can be reduced.

In this way, by reducing the gate-source capacitance, it is possible to speed up the operation of this type of semiconductor device, and also reduce the noise caused by channel noise being fed back to the gate via the gate capacitance. can be reduced.

[Example] Hereinafter, a method for manufacturing a field effect semiconductor device according to the present invention will be explained based on the drawings.

FIG. 1 is a process diagram of a method of manufacturing an embodiment of a field effect semiconductor device of the present invention.

In this figure, 1 is a GaAs semi-insulating substrate, 2 is an n-type GaAs active layer, 3 is an element isolation region, 4 is a source electrode, 5 is a drain electrode, 6 is a line-and-space negative resist film, 7 is a positive resist film having a gate pattern opening, 8 is a recess etching portion, 9 is a gate electrode material, and 1° is a gate electrode.

A method of manufacturing an embodiment of the field effect semiconductor device of the present invention will be explained with reference to this process diagram.

First step (see FIG. 1(a)) An n-type GaAs active layer 2 is formed on a GaAs semi-insulating substrate 1 by epitaxial growth, and oxygen ions are implanted into a frame-shaped region surrounding the element region. Then, element isolation regions 3 are formed.

For this inter-element isolation region, conventionally known techniques such as air separation by mesa etching can be used as appropriate.

Second step (see FIG. 1(b)) AuC is placed on both ends of the n-type GaAs active layer 2 surrounded by the element isolation region 3 in resistance contact with this active layer.

A source electrode 4 and a drain electrode 5 of the e/A u are formed to face each other.

Third step (see FIG. 1(c)) A first resist film, for example, a negative [
・Apply a shift film (SAL601-ER7R7 film 1) to the entire surface, selectively expose it to light, develop it, and adjust the line length to the gate length in the direction connecting the source electrode 4 and the train electrode 5 ( A line and a line with a length of 6) or more, which will be formed later in the sixth step, are formed within at least the effective gate width in the direction perpendicular to the direction connecting the so-sumi electrode 4 and the drain electrode 5. A line-and-space negative resist film 6 of about 0.1 μm each is formed.

Fourth step (see FIG. 1(d)) A second resist film is applied to the entire surface including the line-and-space negative resist film 6 formed in the third step.
For example, positive resist film (ZC'MR100 Nippon Zeon)
This is selectively exposed and developed to form a positive resist film 7 having gate pattern openings that intersect with the lines of the negative resist film 6.

As shown in the A-A' cross-sectional view and the B-B' cross-sectional view, 1, where the negative resist film 6 is present, the opening stops at the surface, and where the negative resist film 6 is not present, the opening is n. It reaches the surface of the GaAs type active layer.

Fifth step (see FIG. 1(e)) Using this body resist l-Ml, 7 as a mask, the surface of the n-type GaAs active layer 2 within the opening is etched.
, forming a recess etched portion 8.

By this recess etching, the thickness of the channel layer is set to the optimum value, and thick n-type Ga
A, S The electrical resistance of the active layer 2 is kept low (to reduce the series resistance).

Sixth step (see Figure 1(f)) In a high vacuum that does not contain an oxidizing atmosphere, the positive resist film 7 is
Al, which is Schottky gate electrode material 9, is vapor-deposited over the entire surface including the opening.

As seen in the A-A" cross-sectional view and the B-B' cross-sectional view, where the negative resist film 6 exists, the Schottky gate electrode material 9 stops at the surface, and where the negative resist film 6 does not exist, the Schottky gate electrode material 9 becomes n-type. The surface of the GaAs active layer 2 is in contact with the etched portion 8 .

Seventh step (see FIG. 1(g)) The remaining negative resist film 6 and positive resist film 7 are removed.

At this time, the gate electrode material 9 formed on the second resist film 7 is lifted off, and since the line portion of the negative resist film 6 has a narrow length of about 0.5 μm, the gate electrode material 9 on both sides thereof is Elutes from the opening.

The gate electrode 10 formed by this lift-off is
It has a structure in which Schottky contact is made with the n-type GaAs active layer 2 in the space part of the line-and-space pattern, and a distance is maintained between the line part and the active layer 2. The volume is reduced by the corresponding area of bone.

Examples of materials that can be used in the above embodiments are as follows.

Negative resist 5AL601-ER7 Developer: Organic alkaline developer such as THMA (tetrahydramethylammonium) Positive resist ZCMR100 0EBR-1000 Developer: Methyl isobutyl ketone developer Lift-off solvent Stripping solution 502 Tokyo Ohka In the above examples Although the gate electrode has been described as having a line-and-space pattern, a similar effect can be obtained even if the gate electrode has a dot-and-space pattern in which the length of the line is shortened.

Further, in the above embodiment, a case where a line-and-space pattern is formed over the entire effective gate width is illustrated, but a line-and-space pattern is formed in a part of the effective gate width. Even if a space is formed, the effect is commensurate with the area of the space.

Furthermore, after the negative resist film has been developed, it has a stable property that it does not dissolve in the positive resist film applied thereon or in its developer, so in the above example,
Although a negative resist was used as the first resist film 6 and a positive resist was used as the second resist film 7, the resist film and developer may be selected as appropriate depending on the characteristics of the material and the process.

Furthermore, the above embodiment is an example in which the present invention is applied to a field effect transistor, but when applied to a HEMT, which is a field effect transistor that utilizes high-mobility electrons accumulated at a heterojunction interface, it becomes even more It is possible to realize faster operation.

〔Effect of the invention〕

In the field effect semiconductor device according to the present invention, when comparing a field effect transistor with a gate length of about 0.25 μm, the gate-source capacitance can be reduced by about 10 to 50%, so the cutoff frequency (rt) can be reduced by about 10 to 50%.
This is a 50% improvement and enables faster operation.

Furthermore, since the capacitance between the gate and source is reduced, channel noise fed back to the gate via this capacitance can be reduced, so that noise characteristics can be improved.

In addition, after forming the gate electrode material 9 using the first resist film and the second adhesive and -cyst film, unnecessary gate electrode material is removed all at once by lift-off, reducing the number of manufacturing steps. can do.

Then, when a negative resist film is used as the first resist film and a positive resist film is used as the second resist film, when applying the second resist film after developing the first resist film, and , when developing this, the first
Regis Ii melts and 1. Deterioration of the resist pattern can be prevented.

[Brief explanation of drawings]

FIG. 1 is a manufacturing process diagram of an embodiment of a field effect semiconductor device of the present invention, and FIG. 2 is a manufacturing process diagram of an example of a conventional Schottky gate field effect transistor. 1---CaAs semi-insulating substrate, 2-n-type GaAs
active layer, 3-element isolation region, 4-source electrode, 5-
Drain electrode, 6- line and space negative resist film, 7- positive resist film with gate pattern opening, 8- recess etching, 9 gate electrode material, 1
0-Gate Electrode Patent Applicant Fujitsu Limited Patent Attorney Shoji Aitani

Claims (3)

[Claims] (1) A semi-insulating substrate, an active layer formed thereon, a source electrode and a drain electrode formed facing each other on the active layer, and an active layer between the source electrode and the drain electrode. In a field effect semiconductor device comprising a gate electrode formed in Schottky contact thereon, the portion of the gate electrode that makes Schottky contact with the active layer has a line-and-space shape or a dot-like shape at least in a part of the effective gate width. A field effect semiconductor device characterized by being formed in an and space shape. (2) a step of forming an active layer on a semi-insulating substrate; a step of forming a source electrode and a drain electrode facing each other on the active layer;
forming a first resist film in a line-and-space shape or dot-and-space shape with a length equal to or longer than the gate length in at least a part of the effective gate width; dot and
A step of forming a second resist film having an opening that intersects with the line or dot on the space-shaped first resist film, a step of depositing a gate electrode material through this opening, and a step of depositing the gate electrode material on the first resist film and the first resist film. 2. A method for manufacturing a field effect semiconductor device, comprising the steps of: 2. removing a resist film. (3) In the method for manufacturing a field effect semiconductor device according to claim 2, the first resist film is a negative resist film,
A method for manufacturing a field effect semiconductor device, characterized in that the second resist film is a positive resist film.