JP2841633B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a plurality of semiconductor devices such as heterojunction type field effect transistors (hereinafter referred to as FETs) operating at two or more different threshold voltages. The present invention relates to a method for manufacturing a semiconductor device provided.

[Problems to be solved by conventional technology and invention]

FIG. 3 is a view for explaining a conventional manufacturing method of this kind, and shows a cross-sectional view of an inverter constituted by a heterojunction FET. Non-doped GaAs on semi-insulating GaAs substrate 1
A layer 2, an n-type AlGaAs layer 3 having a smaller electron affinity and containing a donor impurity, and an n-type GaAs layer 4 are provided. Next, a part of the n-type GaAs layer 4 and a part of the n-type AlGaAs layer 3 are selectively removed to provide a gate electrode 5. Thereafter, the source electrode and the drain electrode 6 are formed on the n-type GaAs layer 4.
Is formed, and the wiring 8 is further formed via the insulating film 7.

Incidentally, the gate threshold voltage of a heterojunction FET is generally determined by the impurity concentration in the n-type AlGaAs layer immediately below the gate electrode and the thickness of this layer. Therefore, in the illustrated inverter, in order to form an enhancement mode (hereinafter referred to as E mode) FET element and a depletion mode (referred to as D mode) FET element constituting the same on the same substrate, Depending on whether the E-mode or D-mode FET element is to be formed, the AlGaAs
The thickness of the layer 3 was changed. In other words, by changing the thickness of the active layer made of AlGaAs, FET elements having different threshold voltages can be formed on the same substrate. However, recess (groove) etching must be repeated twice independently in the gate electrode forming step. And the process was complicated. Further, there are wet etching and dry etching as etching methods, and it is difficult to accurately control the recess etching as described above having different etching depths with good reproducibility by using either method.

In addition, JP-A-60-116178 discloses a technique for forming E-mode and D-mode FET elements having different threshold voltages on the same substrate. Briefly, E mode and D mode
An AlGaAs layer is provided by the thickness difference of the n-type AlGaAs layer in the mode,
In a step before recess etching, a region where a gate electrode is to be formed of an E-mode FET element is selectively removed, and the gate electrode forming step is performed simultaneously for the E-mode and D-mode FET elements. However, according to this technique, the number of steps for selectively removing a region where a gate electrode is to be formed of an E-mode FET element is increased, so that the steps are complicated.

Furthermore, by providing an etch stop layer, a manufacturing technology that realizes an E-mode high electron mobility transistor (hereinafter referred to as HEMT) and a D-mode HEMT on the same substrate (Solid State Device Conference (1984)) Proceedings, p359-p3
62) is also known. Briefly referring to FIG. 4, a non-doped GaAs layer 12 and a Si
The doped AlGaAs layer 13 and the upper layers 14, 15, 16 are grown by molecular beam epitaxy (hereinafter referred to as MBE). The upper layer is composed of the GaAs layers 14 and 16 and the above-described etch stop layer 15 embedded between them. Next, the upper layer
Gate electrodes 20 are provided by selectively removing portions of the 14, 15, 16 and the AlGaAs layer 13. Thereafter, a source electrode and a drain electrode 21 are formed on the GaAs layer 16, and a wiring 19 is formed via insulating films 17 and 18 of SiO ₂ .

However, this technique also has a problem that the time required for crystal growth becomes longer or a step of exposing one of the regions in a step prior to the step of forming a gate electrode is required, which complicates the process.

In view of the above circumstances, an object of the present invention is to provide a manufacturing method capable of easily obtaining a semiconductor device including a plurality of semiconductor elements having two or more types of threshold voltages with a high yield.

[Means for Solving the Problems] In order to achieve the above object, in a method for manufacturing a semiconductor device having a plurality of semiconductor elements operating at two or more different threshold voltages according to the present invention, two or more areas are provided. Forming a mask pattern partially covering the substrate so that the substrate surface is exposed in the plurality of regions on the substrate surface; and Crystal growing simultaneously semiconductor layers having different carrier densities according to the area of the exposed region; and forming the plurality of semiconductor elements operating at different threshold voltages on the substrate from the semiconductor layers having different carrier densities. And is characterized by including.

[Action]

In a semiconductor layer crystal growth step, a semiconductor layer formed on an exposed surface that is not covered by the mask pattern has a different carrier density due to a difference in the area of the exposed surface. By forming a predetermined electrode or the like on two or more kinds of semiconductor layers having different carrier densities, two or more kinds of semiconductor elements having different threshold voltages can be formed on the same substrate. That is, according to the manufacturing method of the present application, only a single crystal growth step is required to provide a difference in the threshold voltage for operating each semiconductor element.

〔Example〕

First, the principle of the present invention will be briefly described. In the present invention, in order to manufacture a plurality of semiconductor elements (for example, FETs) which operate at two or more threshold voltages, the thickness of a semiconductor layer to be an active layer is controlled instead of the thickness of the semiconductor layer. Such impurity control utilizes the characteristics of crystal growth. That is, the fact that the carrier density (impurity concentration) of the semiconductor layer containing impurities differs depending on the area of the exposed surface of the substrate is utilized.

FIG. 2 is a diagram for explaining the characteristics of the selective growth.
The vertical axis indicates the carrier density (cm ^-3 ) obtained by Hall measurement.
And the horizontal axis is a raw material arsine (AsH ₃ ) for the group V element As.
And the supply molar ratio of the group III element Ga to the raw material trimethylgallium (TMG), that is, the V / III ratio. Here, the carrier density plotted by a white square where the supply molar ratio of disilane (Si ₂ H ₆ ), which is a dopant of Si, and trimethylgallium (TMG), which is a raw material of Ga, a group III element, is constant, Si-doped GaAs (Si-GaAs) is grown on a 100 μm-wide exposed GaAs substrate by metal organic chemical vapor deposition (OMVP).
Call it E. ) When selectively grown. The carrier densities plotted by white circles are those obtained by bulk growth on a GaAs substrate by a similar growth method. For example, under the condition of V / III = 200, Si-GaAs selectively grown has a carrier density of 2.8 × 10 ¹⁸ cm ^-3 , while bulk-grown Si-GaAs has a carrier density of 1.6 × 10 ¹⁸ cm ^-3 . Was shown. Therefore, in this case, the selectively grown Si-GaAs is about 1.
Has 75 times the carrier density. This is presumably because the exposed surface of the semiconductor layer on which the semiconductor layer grows is smaller in the case of selective growth than in the case of bulk growth, so that the supply of raw materials per unit area is increased. Therefore, if the exposed surface area for selective growth is greatly changed on the same substrate,
Semiconductor layers having significantly different carrier densities can be obtained. By utilizing this difference, it is possible to obtain active layers having different carrier densities, so that FETs having different gate threshold voltages can be obtained.
Can be manufactured on the same substrate.

FIG. 1 illustrates a method of manufacturing a plurality of semiconductor elements having two kinds of threshold voltages on the same substrate by using such selective growth characteristics.

The entire surface of the semiconductor substrate 31 serving as a substrate is covered with an insulating film 32 (for example, SiN or SiO ₂ ), and a desired pattern having an opening in a region including two or more types of areas is formed with a photoresist, and the RIE The exposed insulating film 32 is selectively etched. Thereby, a mask pattern corresponding to the pattern of the photoresist can be obtained. FIG. 1A is a plan view showing the mask pattern, that is, the insulating layer 32 that has not been etched, by hatching. FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A. The exposed surface 31a where the semiconductor substrate 31 is exposed, which is surrounded by the mask pattern, that is, the insulating film 32, is a region where a semiconductor element having a higher carrier density active region (D mode FET in this embodiment) is to be formed. The exposed surface 31b, which is not surrounded by the insulating film 32, is a region where a semiconductor element (E-mode FET in this embodiment) having an active region with a lower carrier density is to be formed.

Next, as shown in FIG. 1C, non-doped GaAs layers 33a and 33b and Si-doped AlGaAs layers 34a and 34 are formed on the semiconductor substrate 31.
b, and semiconductor layers such as Si-doped GaAs layers 35a and 35b
The crystals are sequentially grown by the method. As described above with respect to the selective growth, the AlGaAs semiconductor layer 34a formed on the exposed surface 31a surrounded by the insulating film 32 has a higher carrier density. On the other hand, the AlGaAs semiconductor layer 34b formed on the exposed surface 31b not surrounded by the insulating film 32 has a lower carrier density.

Next, element isolation is performed by mesa etching or proton implantation to form an ohmic electrode 36 (FIG. 1 (d)).

Subsequently, the Si-doped GaAs layers 35a and 35b and the Si-doped AlGa
After selectively removing a part of the As layers 34a and 34b, a gate electrode 37 is formed (FIG. 1E).

Thereafter, the entire surface is covered with an insulating film (for example, SiN _x or SiO ₂ ) 38, a wiring pattern is formed, and a metal wiring 39 is formed to complete the process (FIG. 1 (f)).

As described above, according to the manufacturing method of the present embodiment,
Semiconductor layers having different carrier densities can be formed by a single crystal growth. In addition, a mask for performing anisotropic etching does not require high-frequency fine processing, and thus a pre-process before crystal growth is simple. Further, the electrodes for operating this semiconductor layer as an active layer can be formed on these semiconductor layers at the same time.
FETs with simple and different gate threshold voltages with good yield
Is obtained. Therefore, it is effective to apply the embodiment to a semiconductor device including an inverter circuit or the like.

In the above embodiment, the exposed surface 3 where the D-mode FET is to be formed
Although the shape of 1a is a square, the exposed surface can have any shape. Further, the exposed surface does not necessarily have to be surrounded by the insulating film. For example,
A D-mode FET may be formed by selectively growing a semiconductor layer on a band-shaped portion sandwiched between absolute liquid films.

In the above description, FETs with two types of gate threshold voltages
Has been described, but if three or more types of areas are selectively grown, it is possible to produce FETs having three or more types of gate threshold voltages.

In the above description, the manufacture of a semiconductor device including a heterojunction FET has been described. However, the present invention is not limited to this, and can be applied to the manufacture of a semiconductor device including DMT, MESFET, and the like. . Further, the present invention is applicable to a method of manufacturing a semiconductor device such as an inverter including a plurality of devices using a n-type semiconductor active layer crystal-grown on a substrate made of a semiconductor, such as an inverter, and the like.
Further, the present invention can be applied to a semiconductor device including a circuit in which this is integrated. The n-type impurity is not limited to Si, but may be Se, Te, S, or the like.

In addition, the crystal growth method of semiconductor layers having different carrier densities on different exposed surfaces is limited to OMVPE as long as selective growth is utilized.
It is not limited to law. For example, a CBE (chemical beam epitaxy) method or the like may be used.

〔The invention's effect〕

As described above, according to the manufacturing method of the present invention, semiconductor layers having different carrier densities can be easily formed by a single crystal growth. Therefore, active layers having different threshold voltages can be simultaneously formed on the same substrate surface. For this reason, a semiconductor device including semiconductor elements operating at different threshold voltages can be manufactured simply and with high yield.

[Brief description of the drawings]

FIG. 1 is a view showing an embodiment of a method of manufacturing a semiconductor device according to the present invention, FIG. 2 is a view showing that the carrier density varies depending on the area of selective growth, and FIG. FIG. 4 is a diagram showing a junction type FET, and FIG. 4 is a diagram showing a HEMT manufactured by another conventional technique. 31 ... Semiconductor substrate, 31a ... Exposed surface with small area, 31b ...
... exposed surface with large area, 32 ... mask pattern, 34a ...
... a semiconductor layer formed in a small area, 34b ... a semiconductor layer formed in a wide area, 37 ... a gate electrode.

Claims (1)

(57) [Claims] In a method of manufacturing a semiconductor device having a plurality of semiconductor elements operating at two or more different threshold voltages, the substrate is partially exposed so that the substrate surface is exposed in a plurality of regions having at least two types of areas. Forming a mask pattern that covers the substrate on the surface of the substrate, and simultaneously supplying semiconductor materials having different carrier densities according to the area of the exposed region by supplying a raw material containing impurities on the exposed substrate surface. A method of manufacturing a semiconductor device, comprising: a step of growing crystals; and a step of forming, on the semiconductor substrate, the plurality of semiconductor elements operating at different threshold voltages from the semiconductor layers having different carrier densities.