WO2023272786A1 - 一种半导体器件的制作方法以及半导体器件 - Google Patents

一种半导体器件的制作方法以及半导体器件 Download PDF

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Publication number
WO2023272786A1
WO2023272786A1 PCT/CN2021/106494 CN2021106494W WO2023272786A1 WO 2023272786 A1 WO2023272786 A1 WO 2023272786A1 CN 2021106494 W CN2021106494 W CN 2021106494W WO 2023272786 A1 WO2023272786 A1 WO 2023272786A1
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conductive layer
substrate
layer
semiconductor device
opening
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PCT/CN2021/106494
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English (en)
French (fr)
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刘杰
应战
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长鑫存储技术有限公司
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Priority to US17/454,877 priority Critical patent/US20230005817A1/en
Publication of WO2023272786A1 publication Critical patent/WO2023272786A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Definitions

  • the present disclosure relates to but not limited to a manufacturing method of a semiconductor device and the semiconductor device.
  • TSV Through Silicon Vias
  • the silicon material and the copper material need to be ground at the same time.
  • the silicon material is brittle and prone to cracks.
  • the copper material is easy to diffuse in the semiconductor silicon wafer, and the phenomenon of copper pollution on the surface of the silicon layer or cracks is easy to occur, resulting in low yield.
  • the present disclosure provides a manufacturing method of a semiconductor device and a semiconductor device.
  • a method for manufacturing a semiconductor device including: providing a substrate having a groove, the groove extending from a first surface of the substrate along a thickness direction of the substrate; A first auxiliary layer and a first conductive layer are sequentially formed in the trench, the first conductive layer covers the first auxiliary layer; the substrate is thinned on the second surface of the substrate until exposed The first auxiliary layer, wherein the first surface and the second surface are oppositely disposed; the first auxiliary layer is removed to form a first opening; and a second dielectric layer is formed on the second surface of the substrate ; patterning the second dielectric layer, forming a second opening in the second dielectric layer, the second opening exposing the first opening; depositing a second initial conductive layer, filling the second initial conductive layer the first opening and the second opening.
  • the technical solution of the second aspect of the present disclosure provides a semiconductor device, including: a substrate, the substrate has a first surface and a second surface, the first surface and the second surface are arranged opposite to each other; at least one through hole, Penetrating through the substrate along the thickness direction of the substrate; the first conductive layer and the second conductive layer are filled in the through hole and filled with the through hole, and the first conductive layer and the second conductive layer in the same through hole The second conductive layer is connected; the top surface of the first conductive layer is flush with the first surface of the base.
  • FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment
  • FIG. 3 is a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment
  • FIG. 4 is a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment
  • FIG. 5 is a flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment
  • FIG. 6 is a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment
  • FIGS. 7 to 25 are schematic diagrams of structures involved in each step of processing a semiconductor device in a semiconductor device manufacturing method
  • Fig. 26 is a schematic structural diagram of a semiconductor device according to an exemplary embodiment
  • Fig. 27 is a schematic structural diagram of a semiconductor device according to an exemplary embodiment
  • Fig. 28 is a schematic structural diagram of a semiconductor device according to an exemplary embodiment.
  • TSV Through Silicon Vias
  • the silicon material and the copper material need to be ground at the same time.
  • the silicon material is brittle and prone to cracks.
  • the copper material is easy to diffuse in the semiconductor silicon wafer, and the phenomenon of copper pollution on the surface of the silicon layer or cracks is easy to occur, resulting in low yield.
  • the present disclosure provides a method for manufacturing a semiconductor device, which can increase the yield of the semiconductor device while reducing processing steps.
  • the method for manufacturing a semiconductor device includes:
  • S101 Provide a substrate having a groove, the groove extending from the first surface of the substrate along the thickness direction of the substrate;
  • S103 Thinning the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are opposite to each other;
  • S106 patterning the second dielectric layer, forming a second opening in the second dielectric layer, the second opening exposing the first opening;
  • S107 Depositing a second initial conductive layer, where the second initial conductive layer fills the first opening and the second opening.
  • the groove 13 on the substrate 10 is a non-penetrating groove formed on the first surface 14 of the substrate 10, that is, the bottom surface of the groove 13 is connected to the second surface 15 of the substrate 10. a certain distance between them.
  • the groove 13 extends from the first surface 14 of the substrate 10 along the thickness direction of the substrate 10, so that the bottom surface of the groove 13 is close to the second surface 15 of the substrate 10, and the first surface 14 and the second surface 15 are opposite to each other.
  • the number of grooves 13 on the substrate 10 is not specifically limited, and may be one, two or more. Taking a plane parallel to the substrate 10 as a cross-section, the cross-sectional shape of the trench 13 includes but not limited to a circle, a rectangle, and a rhombus.
  • Various active devices eg, transistors, diodes, etc.
  • various electrical interconnection structures may also be formed between the active devices.
  • a first auxiliary layer 20 is first deposited in the trench 13, so that the first auxiliary layer 20 covers the bottom surface of the trench 13, and the first auxiliary layer 20 has a certain thickness.
  • a first conductive layer 30 is deposited on the first auxiliary layer 20 so that the first conductive layer 30 covers the first auxiliary layer 20 . That is, the first auxiliary layer 20 is located at the bottom of the trench 13 , and the first auxiliary layer 20 is located on a side close to the second surface 15 relative to the first conductive layer 30 .
  • the material of the first conductive layer 30 can be selected from a material with good conductivity, such as silver, copper, aluminum and the like.
  • the first auxiliary layer 20 and the first conductive layer 30 can be directly connected to the side wall surface of the trench 13, that is, between the first auxiliary layer 20 and the side wall surface of the trench 13 and between the first conductive layer 30 and the trench 13. No other structures are arranged between the side wall surfaces of the groove 13 .
  • a barrier layer can be provided between the first auxiliary layer 20 and the side wall surface of the trench 13 and between the first conductive layer 30 and the side wall surface of the trench 13, such as a barrier layer can be provided. other structures.
  • a method of grinding the second surface 15 of the substrate 10 may be used to thin the substrate 10 until the first auxiliary layer 20 is exposed. Then the top surface of the first auxiliary layer 20 is flush with the second surface 15 , and the surface of the first conductive layer 30 is flush with the first surface 14 .
  • the groove 13 forms openings on the first surface 14 and the second surface 15, so that the groove 13 forms a through hole penetrating through the first surface 14 and the second surface 15 of the substrate 10.
  • the material of the substrate 10 close to the second surface 15 and part of the first auxiliary layer 20 are ground away at the same time, so as to avoid grinding to the first conductive layer 30 .
  • the material of the first auxiliary layer 20 adopts non-metallic materials (such as silicon dioxide or silicon nitride, etc.), on the one hand, there is no metal material contamination of the second surface of the substrate 10; on the other hand, the ductility of the non-metallic materials Weaker than metal materials, the ductility of the first auxiliary layer 20 is closer to the material of the substrate 10.
  • the material of the substrate 10 and part of the first auxiliary layer 20 are ground off at the same time, the deformation of the first auxiliary layer 20 in the radial direction is very small, so that The first auxiliary layer 20 exerts less pressure on the substrate 10 in the radial direction, which reduces the probability of cracks on the second surface 15 of the substrate 10 , thereby improving the yield of TSV manufacturing.
  • the material of the first auxiliary layer 20 includes but not limited to non-metallic materials such as silicon dioxide or silicon nitride.
  • the material of the first auxiliary layer 20 in this embodiment can also be a metal material with low ductility, which can reduce the possibility of metal contamination of the second surface 15 or cracks on the second surface 15. probability.
  • the first auxiliary layer 20 may be removed by an etching process, so that a first opening 131 is formed at one end of the trench 13 facing the second surface 15, exposing the The inner first conductive layer 30.
  • the etching process may adopt wet etching, dry etching, deep reactive ion etching, laser etching and the like.
  • step 105 step 106 and S107, as shown in FIG. 16, FIG. 18 and FIG. 19, and refer to FIG. 15.
  • a second dielectric layer 16 is formed on the second surface 15 of the substrate 10, wherein the material of the second dielectric layer 16 can be silicon dioxide, and the second dielectric layer 16 combines the second surface 15 of the substrate 10 with the The first opening 131 is covered.
  • the second dielectric layer 16 is patterned such that a second opening 161 capable of exposing the first opening 131 is formed on the second dielectric layer 16 .
  • the second initial conductive layer 40 is finally deposited so that the second initial conductive layer 40 fills the first opening 131 and the second opening 161, and the first conductive layer 30 and the second initial conductive layer 40 are connected as a whole, so that Through-silicon vias for conducting electricity are formed on the substrate 10 , so that multiple semiconductor devices (such as chips) can be stacked in a vertical plane direction to save space.
  • the material of the second initial conductive layer 40 includes but not limited to silver, copper, aluminum, and the materials of the second initial conductive layer 40 and the first conductive layer 30 may be the same or different.
  • the material of the second initial conductive layer 40 is preferably a material with good conductivity, such as silver, copper, aluminum, etc.
  • the purpose of forming the second dielectric layer 16 on the second surface 15 is to deposit the second initial conductive layer 40 process, the second initial conductive layer 40 is formed on the surface of the second dielectric layer 16 and in the first opening 131 and the second opening 161 , so as to prevent metal material from contaminating the second surface 15 of the substrate 10 and cracks on the second surface 15 .
  • a method for fabricating a semiconductor device includes:
  • S201 Provide a substrate having a groove, the groove extending from the first surface of the substrate along the thickness direction of the substrate;
  • S203 Thinning the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are opposite to each other;
  • S207 Depositing a second initial conductive layer, where the second initial conductive layer fills the first opening and the second opening;
  • step S208 of this embodiment as shown in FIG. 20, referring to FIG. 18 and FIG.
  • the inner second initial conductive layer 40 is used as the second conductive layer 41 , so that the surface of the second conductive layer 41 is flush with the second surface 15 .
  • the first conductive layer 30 and the second conductive layer 41 form a connected whole, and the first conductive layer 30 and the second conductive layer 41 are all made of materials with good conductivity, such as silver, copper, aluminum, etc., so that The first conductive layer 30 and the second conductive layer 41 form the conductive through-silicon via structure of the semiconductor device.
  • the first conductive layer 30 and the second conductive layer 41 are stacked as a plurality of semiconductor devices in the vertical plane direction, every two adjacent semiconductor devices The electrical connection structure between devices.
  • the top surface of the second conductive layer 41 formed in this embodiment is flush with the second surface 15, and the devices connected to the second conductive layer 41 can be directly arranged on the substrate 10 and connected to the second conductive layer 41.
  • a method for fabricating a semiconductor device includes:
  • S301 Provide a substrate with grooves, the grooves extending from the first surface of the substrate along the thickness direction of the substrate;
  • S303 Thinning the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are opposite to each other;
  • S307 Depositing a second initial conductive layer, where the second initial conductive layer fills the first opening and the second opening;
  • S308 Remove the second dielectric layer, retain the second initial conductive layer located in the second opening, and use the second initial conductive layer as the second conductive layer.
  • step S301 to step S307 are the same as the steps in the above embodiment, and will not be repeated here.
  • step S308 as shown in FIG. 25, referring to FIG. 24, the second dielectric layer 16 is removed, and the second initial conductive layer 40 located in the second opening 161 remains, and the second initial conductive layer 40 is used as the second conductive layer 41, Protruding from the second surface 15 of the second conductive layer 41 forms a protruding structure.
  • the first conductive layer 30 and the second conductive layer 41 form a connected whole, and the first conductive layer 30 and the second conductive layer 41 all adopt materials with good conductivity, such as silver, copper, aluminum, etc., so that the first conductive layer
  • the layer 30 and the second conductive layer 41 form the conductive through-silicon via structure of the semiconductor device.
  • the first conductive layer 30 and the second conductive layer 41 realize that when multiple semiconductor devices are stacked in the vertical plane direction, there is a gap between each adjacent two semiconductor devices. electrical connection, wherein the second conductive layer 41 forms a raised structure on the second surface 15 to facilitate the electrical connection between two adjacent semiconductor devices.
  • the material of the first conductive layer 30 and the material of the second conductive layer 41 may be the same or different.
  • the coefficient of thermal expansion of the second conductive layer 41 is smaller than that of the first conductive layer 30, so as to reduce the stress on the substrate 10 under heat treatment.
  • the second conductive layer 41 is a protruding structure protruding from the second surface 15, the projection of the second conductive layer 41 on the substrate 10 covers the first conductive layer 30, and the second conductive layer 41 is formed on the substrate 10.
  • the projected profile on is larger than the projected profile of the first conductive layer 30 .
  • a method for fabricating a semiconductor device includes:
  • S401 Provide a substrate having a groove, the groove extending from the first surface of the substrate along the thickness direction of the substrate;
  • S402 sequentially forming a first auxiliary layer and a first conductive layer in the trench, the first conductive layer covering the first auxiliary layer;
  • S403 Thinning the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are opposite to each other;
  • S406 Patterning the second dielectric layer, forming a second opening in the second dielectric layer, the second opening exposing the first opening;
  • S409 Depositing a second initial conductive layer, where the second initial conductive layer fills the first opening and the second opening;
  • S410 Remove the second dielectric layer, retain the second initial conductive layer located in the second opening, and use the second initial conductive layer as the second conductive layer.
  • steps S401 to S406, and S409 and S410 are the same as those in the above embodiment, and will not be repeated here.
  • steps S407 and S408, as shown in FIG. 22 and FIG. 23 referring to FIG. 25 , the second dielectric layer 52 and the second barrier layer 62 are deposited in the second opening 161 by a deposition process. At least covering the inner wall of the second opening 161 and a partial area of the second surface 15 inside the second opening 161 .
  • the second barrier layer 62 is deposited and formed by a deposition process, and the second barrier layer 62 covers the second dielectric layer 52, thereby isolating the second conductive layer 41 from the substrate 10, so as to prevent the second conductive layer from being damaged during the operation of the semiconductor device.
  • annealing is performed on the second conductive layer 41 to eliminate stress in the second conductive layer 41 .
  • a method for fabricating a semiconductor device includes:
  • S501 Provide a substrate having a groove, the groove extending from the first surface of the substrate along the thickness direction of the substrate;
  • S505 Thinning the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are opposite to each other;
  • S508 Patterning the second dielectric layer, forming a second opening in the second dielectric layer, the second opening exposing the first opening;
  • S509 Depositing a second initial conductive layer, where the second initial conductive layer fills the first opening and the second opening.
  • steps S501, and steps S504 to S509 are implemented in the same manner as in the foregoing embodiments, and will not be repeated here.
  • steps S502 and S503 as shown in FIG. 10 and FIG. 11 , a first dielectric layer 51 and a first barrier layer 61 are formed on the sidewall of the trench 13 through a deposition process, and the first dielectric layer 51 covers the trench 13 The inner wall and the first barrier layer 61 cover the first dielectric layer 51, so that the first conductive layer 30, the first auxiliary layer 20 and the inner wall of the trench 13 are isolated by the first dielectric layer 51 and the first barrier layer 61 open.
  • the material of the first dielectric layer 51 is silicon nitride
  • the material of the first barrier layer 61 is titanium nitride.
  • the first conductive layer 30 and the first auxiliary layer 20 in this embodiment are not directly connected to the inner sidewall of the trench 13 , but between the above two and the sidewall of the trench 13
  • the first dielectric layer 51 and the first barrier layer 61 are provided, and the sidewalls of the first conductive layer 30 and the first auxiliary layer 20 are in contact with the first barrier layer 61 .
  • the first dielectric layer 51 plays an insulating role, preventing the first conductive layer 30, the second conductive layer 41 from contacting the substrate 10.
  • the first barrier layer 61 can provide a buffer barrier for the substrate 10 during grinding, reducing the probability of cracks in the silicon layer and preventing copper from polluting the surface or cracks of the adjacent silicon layer. Further improve the yield rate of TSV production.
  • a method for fabricating a semiconductor device includes:
  • S602 forming a first dielectric layer on the surface of the substrate to form a base
  • S603 patterning the first dielectric layer, forming a groove in the substrate, the groove passing through the first dielectric layer, and the exposed surface of the first dielectric layer being the first surface;
  • S604 Provide a substrate having a groove, the groove extending from the first surface of the substrate along the thickness direction of the substrate;
  • S606 Thinning the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are opposite to each other;
  • S609 patterning the second dielectric layer, forming a second opening in the second dielectric layer, the second opening exposing the first opening;
  • S610 Deposit a second initial conductive layer, where the second initial conductive layer fills the first opening and the second opening.
  • Steps S604 to S5610 are implemented in the same manner as in the foregoing embodiments, and details are not repeated here.
  • steps S601, S602 and S603 first provide a substrate 11, the material of the substrate 11 can be silicon, and form a first dielectric layer 12 on the surface of the substrate 11 , the substrate 11 and the first dielectric layer 12 are the base 10 .
  • the first dielectric layer 12 is patterned, and a trench 13 is formed in the substrate 10 through an etching process.
  • the surface of the first dielectric layer 12 away from the substrate 11 is the first surface 14
  • the surface of the substrate 11 away from the first dielectric layer 12 is the second surface 15 .
  • a mask layer 17 is first formed on the first dielectric layer 12, a geometric pattern is formed on the mask layer 17 by exposure and development, and then the etching process The pattern on the mask layer 17 is transferred to the substrate 10 to form the trench 13 .
  • the materials of the first dielectric layer 12 and the second dielectric layer 16 are different.
  • the material of the first auxiliary layer 20 is silicon dioxide or silicon nitride or a metal with low ductility, and the material of the substrate 10 is silicon, so the etching of the first auxiliary layer 20
  • the etching rate is higher than the etching rate of the substrate 10, so that in step S104, when the first auxiliary layer 20 is removed by an etching process, the etching rate of the first auxiliary layer 20 is faster than the etching rate of the substrate 10, so as to ensure the removal of the first auxiliary layer 20. layer 20, the amount of etching to the substrate 10 should be minimized.
  • the first auxiliary layer 20 has a high selectivity ratio to the substrate 10, that is, the etching rate of the first auxiliary layer 20 is higher than the etching rate of the substrate 10, for example, the ratio of the etching rate of the first auxiliary layer 20 to the etching rate of the substrate 10 for 100 or 80 etc.
  • High selection ratio refers to how much faster the etching rate of one material is compared with another material under the same etching conditions. It is defined as the etching rate of the etched material compared with the etching rate of another material. rate ratio.
  • a high selectivity ratio means that only the desired layer of material is removed.
  • a highly selective etch process does not etch the underlying material (stopping at the proper depth) and the protective photoresist is not etched.
  • the ductility of the material of the first auxiliary layer 20 is smaller than the ductility of the material of the first conductive layer 30 .
  • the material of the first auxiliary layer 20 is silicon dioxide or silicon nitride or a metal material with low ductility.
  • the first auxiliary layer 20 is made of a metal with less ductility than the first conductive layer 30, it will also reduce the metal contained in the first auxiliary layer 20 from entering the surface of the silicon layer to a certain extent. or chance of contamination in crevices.
  • the first auxiliary layer and the first conductive layer are sequentially deposited in the groove, and in the process of thinning the substrate through a grinding process so that the groove forms a through hole penetrating through both sides of the substrate, the substrate’s
  • the second surface and the first auxiliary layer in the trench are ground simultaneously without grinding to the first conductive layer, so the metal (such as copper) in the first conductive layer will not contaminate the second surface or cracks of the substrate.
  • the material of the first auxiliary layer is made of silicon dioxide or silicon nitride, which has ductility close to that of silicon, so that the probability of cracks on the second surface of the substrate is reduced, and there is no metal contamination of the second surface of the substrate and cracks. , can further improve the yield of TSV production.
  • the semiconductor device includes a substrate 10 having a first surface 14 and a second surface 15.
  • the first surface 14 and the second surface 15 are oppositely arranged.
  • At least one through hole 18 is disposed on the base 10 , penetrating through the base 10 along the thickness direction of the base 10 .
  • the semiconductor device also includes a first conductive layer 30 and a second conductive layer 41, both of which are filled in the through hole 18 and are full of the through hole 18, and the first conductive layer 30 and the second conductive layer 41 in the same through hole 18 are connected, wherein , the top surface of the first conductive layer 30 is flush with the first surface 14 of the substrate 10 , and the top surface of the second conductive layer 41 is flush with the second surface 15 of the substrate 10 .
  • the first conductive layer 30 and the second conductive layer 41 form the TSV structure of the semiconductor device, realizing interconnection with the shortest distance between chips and the smallest pitch, so as to achieve better electrical performance.
  • the semiconductor device further includes a dielectric layer 50 covering the inner wall of the through hole 18 , and a barrier layer 60 covering the inner wall of the through hole 18 and the dielectric layer 50 .
  • the first conductive layer 30 and the second conductive layer 41 are located inside the barrier layer 60, and the dielectric layer 50 and the barrier layer 60 connect the first The conductive layer 30 and the second conductive layer 41 are isolated from the substrate 10 , so as to prevent the charges in the first conductive layer 30 and the second conductive layer 41 from interfering with active devices on the substrate 10 .
  • the second conductive layer 41 includes a first portion 411 and a second portion 412 , and the top surface of the first portion 411 is flush with the second surface 15 of the substrate 10 .
  • the second part 412 is located on the second surface 15, and the surface of the second part 412 connected to the first part 411 covers part of the second surface 15, so that the second part 412 of the second conductive layer 41 protrudes from the second surface 15 of the substrate 10
  • a protruding structure is formed for electrical connection between different semiconductor devices.
  • the first part 411 and the second part 412 are connected as a whole.
  • the method for manufacturing a semiconductor device and the semiconductor device provided by the embodiments of the present disclosure can effectively prevent the material of the first auxiliary layer from contaminating the surface or gaps of the substrate during the process of thinning the substrate, thereby improving the yield.
  • using the method for manufacturing a semiconductor device in the present disclosure to process a semiconductor device can reduce processing steps and improve processing efficiency.

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Abstract

本公开提供了一种半导体器件制作方法以及半导体器件。其中，半导体器件制作方法包括：提供具有沟槽的基底，沟槽由基底的第一表面沿基底的厚度方向延伸；在沟槽内依次形成第一辅助层和第一导电层，第一导电层覆盖第一辅助层；在基底的第二表面对基底进行减薄，至暴露第一辅助层；去除第一辅助层，形成第一开口；在基底的第二表面上形成第二介质层；图形化第二介质层，在第二介质层形成第二开口，第二开口暴露第一开口；沉积第二初始导电层，第二初始导电层填充第一开口和第二开口。

Description

一种半导体器件的制作方法以及半导体器件
本公开要求在2021年07月01日提交中国专利局、申请号为202110750950.6、发明名称为“一种半导体器件的制作方法以及半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种半导体器件的制作方法以及半导体器件。
背景技术
硅通孔(Through Silicon Vias，TSV)技术可以实现芯片与芯片间距离最短、间距最小的互连，以达到更好的电学性能。
但是相关技术中，制作TSV的过程中，通常要研磨至露出铜层。在这一过程中，需要同时对硅材质与铜材质研磨，硅的材质较脆，容易产生裂缝。而在高温和加电场的情况下，铜材料容易在半导体硅片中扩散，容易出现铜污染硅层表面或裂缝的现象，导致成品率低。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种半导体器件的制作方法以及一种半导体器件。
根据本公开的第一方面技术方案，提出了一种半导体器件的制作方法，包括：提供具有沟槽的基底，所述沟槽由所述基底的第一表面沿所述基底的厚度方向延伸；在所述沟槽内依次形成第一辅助层和第一导电层，所述第一导电层覆盖所述第一辅助层；在所述基底的第二表面对所述基底进行减薄，至暴露所述第一辅助层，其中，所述第一表面和所述第二表面相对设置；去除所述第一辅助层，形成第一开口；在所述基底的第二表面上形成第二介质层；图形化所述第二介质层，在所述第二介质层形成第二开口，所述第二开 口暴露所述第一开口；沉积第二初始导电层，所述第二初始导电层填充所述第一开口和所述第二开口。
本公开的第二方面技术方案提供了一种半导体器件，包括：基底，所述基底具有第一表面和第二表面，所述第一表面和所述第二表面相对设置；至少一个通孔，沿所述基底的厚度方向贯穿所述基底；第一导电层和第二导电层，填充于所述通孔内且充满所述通孔，同一所述通孔中的所述第一导电层和所述第二导电层相连；所述第一导电层的顶面与所述基底的第一表面平齐。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本申请的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为根据一示例性实施例示出的半导体器件制作方法的流程图；
图2为根据一示例性实施例示出的半导体器件制作方法的流程图；
图3为根据一示例性实施例示出的半导体器件制作方法的流程图；
图4为根据一示例性实施例示出的半导体器件制作方法的流程图；
图5为根据一示例性实施例示出的半导体器件制作方法的流程图；
图6为根据一示例性实施例示出的半导体器件制作方法的流程图；
图7至图25为半导体器件制作方法加工半导体器件各个步骤涉及到的结构的示意图；
图26为根据一示例性实施例示出的半导体器件的结构示意图；
图27为根据一示例性实施例示出的半导体器件的结构示意图；
图28为根据一示例性实施例示出的半导体器件的结构示意图。
具体实施方式
在下文中，仅简单地描述了某些示例性实施例。正如本领域技术人员可以认识到的那样，在不脱离本公开的精神或范围的情况下，可通过各种不同方式修改所描述的实施例。因此，附图和描述被认为本质上是示例性的而非限制性的。
目前，硅通孔(Through Silicon Vias，TSV)技术可以实现芯片与芯片间距离最短、间距最小的互连，以达到更好的电学性能。
但是相关技术中，制作TSV的过程中，通常要研磨至露出铜层。在这一过程中，需要同时对硅材质与铜材质研磨，硅的材质较脆，容易产生裂缝。而在高温和加电场的情况下，铜材料容易在半导体硅片中扩散，容易出现铜污染硅层表面或裂缝的现象，导致成品率低。
鉴于此，本公开提供了一种半导体器件的制作方法，在减少加工步骤的同时，还能够提高半导体器件的成品率。
参考图1所示，本公开实施例提供的半导体器件的制作方法，包括：
S101：提供具有沟槽的基底，沟槽由基底的第一表面沿基底的厚度方向延伸；
S102：在沟槽内依次形成第一辅助层和第一导电层，第一导电层覆盖第一辅助层；
S103：在基底的第二表面对基底进行减薄，至暴露第一辅助层，其中，第一表面和第二表面相对设置；
S104：去除第一辅助层，形成第一开口；
S105：在基底的第二表面上形成第二介质层；
S106：图形化第二介质层，在第二介质层形成第二开口，第二开口暴露第一开口；
S107：沉积第二初始导电层，第二初始导电层填充第一开口和第二开口。
在步骤101中，如图9所示，基底10上的沟槽13为在基底10的第一表面14上形成的非贯通的凹槽，即沟槽13的底面与基底10的第二表面15之间相距一定距离。沟槽13由基底10的第一表面14沿基底10的厚度方向延伸，使沟槽13的底面靠近基底10的第二表面15，第一表面14和第二表面 15相对设置。
其中，基底10上的沟槽13个数不做具体限定，可以是一个、两个或多个。以平行于基底10的平面作为横截面，沟槽13的横截面形状包括但不限于圆形、矩形、菱形。
在基底10的第一表面14可以设置有多种有源器件(例如，晶体管、二极管等)，在有源器件之间还可以形成有各种电互连结构。
在步骤102中，如图12和图13所示，在沟槽13内首先沉积第一辅助层20，使第一辅助层20覆盖沟槽13的底面，并且第一辅助层20具有一定的厚度。然后，在第一辅助层20的上方沉积第一导电层30，使第一导电层30覆盖第一辅助层20。即，第一辅助层20位于沟槽13的底部，第一辅助层20相对于第一导电层30位于靠近第二表面15的一侧。其中，第一导电层30的材质可以选择导电性良好的材质，例如银、铜、铝等。
本实施例中，第一辅助层20第一导电层30可以直接与沟槽13的侧壁面接触连接，即第一辅助层20与沟槽13的侧壁面之间以及第一导电层30与沟槽13的侧壁面之间不设置其他结构。当然，可以理解的是，在其他实施例中，第一辅助层20与沟槽13的侧壁面之间以及第一导电层30与沟槽13的侧壁面之间可以设置比如阻挡层之类的其他结构。
本实施例中，当基底10上具有两个或两个以上的沟槽13时，不同的沟槽13的深度可能存在差异，但是，任意一个沟槽13内的第一导电层30与第一辅助层20的接触面与基底10的第一表面14之间的距离小于其他任何一个沟槽13的深度，以避免在执行步骤S103，即在基底10的第二表面15对基底10进行减薄时，研磨到第一导电层30。
在步骤103中，如图14所示，可以采用对基底10的第二表面15进行研磨的方法，以使基底10减薄，直至暴露第一辅助层20。则第一辅助层20的顶面与第二表面15平齐，第一导电层30的表面与第一表面14平齐。沟槽13在第一表面14和第二表面15均形成开口，使沟槽13形成贯穿基底10的第一表面14和第二表面15的通孔，在对基底10进行减薄的研磨过程中，靠近第二表面15的基底10材料和部分第一辅助层20同时被研磨掉，而避免研磨到第一导电层30。当第一辅助层20的材料采用非金属材料(例如二氧化硅或氮化硅等)，一方面，不存在金属材料污染基底10第二表面的情况；另 一方面，非金属材料的延展性弱于金属材料，第一辅助层20的延展性更加接近基底10材料，基底10材料和部分第一辅助层20同时被研磨掉时，第一辅助层20在径向方向的形变很小，使第一辅助层20在径向方向上对基底10产生的挤压较小，减小基底10的第二表面15产生裂缝的概率，从而提高TSV制作的成品率。为尽量避免金属等物质污染第二表面15以及第二表面15上的裂缝，第一辅助层20的材料包括但不限于二氧化硅或氮化硅等非金属材料。
另外，本实施例中的第一辅助层20的材料除了可以为非金属材料之外，还可以为延展性小的金属材料，可以降低金属污染第二表面15或第二表面15上的裂缝的概率。
在步骤104中，参照图12、图14和图15，可以通过蚀刻工艺去除第一辅助层20，使得在沟槽13朝向第二表面15的一端形成第一开口131，暴露出处于沟槽13内的第一导电层30。
其中，蚀刻工艺可以采用湿法蚀刻、干法蚀刻、深反应离子蚀刻、激光蚀刻等。
在步骤105、步骤106和S107中，如图16、图18和图19所示，并参照图15。请参见图16，在基底10的第二表面15上形成第二介质层16，其中，第二介质层16的材料可以是二氧化硅，第二介质层16将基底10的第二表面15和第一开口131覆盖。参见图18，图形化第二介质层16，使得第二介质层16上形成能够暴露第一开口131的第二开口161。参照图19，最后沉积第二初始导电层40，使第二初始导电层40填充第一开口131和第二开口161，并且第一导电层30与第二初始导电层40连接为一个整体，以在基底10上形成用于导电的硅通孔，从而能够实现多个半导体器件(例如芯片)在垂直平面方向堆叠，节省空间。其中，第二初始导电层40的材料包括但不限于银、铜、铝，第二初始导电层40与第一导电层30的材料可以相同也可以不同。
如图17所示，在图形化第二介质层16时，先在第二介质层16上形成掩膜层17，利用曝光和显影在掩膜层17上刻画几何图形结构，然后通过刻蚀工艺将光掩模层17上的图形转移到所在第二介质层16上，从而形成第二开口161。其中，第二初始导电层40的材料优选为导电性良好的材质，例如 银、铜、铝等，在第二表面15上形成第二介质层16的目的在于，在沉积第二初始导电层40的过程，第二初始导电层40形成在第二介质层16的表面以及第一开口131和第二开口161内，避免金属材料污染基底10的第二表面15以及第二表面15上的裂缝。
参考图2所示，在一个示例性实施例中，提供了一种半导体器件的制作方法。该半导体器件的制作方法包括：
S201：提供具有沟槽的基底，沟槽由基底的第一表面沿基底的厚度方向延伸；
S202：在沟槽内依次形成第一辅助层和第一导电层，第一导电层覆盖第一辅助层；
S203：在基底的第二表面对基底进行减薄，至暴露第一辅助层，其中，第一表面和第二表面相对设置；
S204：去除第一辅助层，形成第一开口；
S205：在基底的第二表面上形成第二介质层；
S206：图形化第二介质层，在第二介质层形成第二开口，第二开口暴露第一开口；
S207：沉积第二初始导电层，第二初始导电层填充第一开口和第二开口；
S208：去除第二介质层和位于第二开口中的第二初始导电层，保留位于第一开口内的第二初始导电层作为第二导电层。
在本实施例中，步骤S201至步骤S207的实现方式与上述实施例相同，在此不再赘述。本实施例的步骤S208中，如图20所示，参照图18和图19所示，去除第二介质层16和位于第二开口161中的第二初始导电层40，保留位于第一开口131内的第二初始导电层40作为第二导电层41，使第二导电层41的表面与第二表面15平齐。此时，第一导电层30和第二导电层41形成连接的整体，且第一导电层30和第二导电层41均采用具有良好导电性的材料，例如银、铜、铝等，从而使第一导电层30、第二导电层41组成半导体器件的导电硅通孔结构，第一导电层30、第二导电层41作为多个半导体器件在垂直平面方向堆叠时每相邻的两个半导体器件之间的电连接结构。
本实施例中形成的第二导电层41的顶面与第二表面15平齐，与第二导 电层41相连接的器件可以直接设置在基底10上并与第二导电层41接触连接。
参考图3所示，在一个示例性实施例中，提供了一种半导体器件的制作方法。该半导体器件的制作方法包括：
S301：提供具有沟槽的基底，沟槽由基底的第一表面沿基底的厚度方向延伸；
S302：在沟槽内依次形成第一辅助层和第一导电层，第一导电层覆盖第一辅助层；
S303：在基底的第二表面对基底进行减薄，至暴露第一辅助层，其中，第一表面和第二表面相对设置；
S304：去除第一辅助层，形成第一开口；
S305：在基底的第二表面上形成第二介质层；
S306：图形化第二介质层，在第二介质层形成第二开口，第二开口暴露第一开口；
S307：沉积第二初始导电层，第二初始导电层填充第一开口和第二开口；
S308：去除第二介质层，保留位于第二开口中的第二初始导电层，第二初始导电层作为第二导电层。
在本实施例中，步骤S301至步骤S307的实现方式与上述实施例中的步骤相同，在此，不再赘述。在步骤S308中，如图25所示，参照图24，去除第二介质层16，保留位于第二开口161中的第二初始导电层40，第二初始导电层40作为第二导电层41，使第二导电层41的凸出于第二表面15形成凸起结构。第一导电层30和第二导电层41形成连接的整体，且第一导电层30和第二导电层41均采用具有良好导电性的材料，例如银、铜、铝等，从而使第一导电层30、第二导电层41组成半导体器件的导电硅通孔结构，第一导电层30、第二导电层41实现多个半导体器件在垂直平面方向堆叠时每相邻的两个半导体器件之间的电连接，其中，第二导电层41在第二表面15上形成的凸起结构以便于相邻的两个半导体器件之间形成电连接。
本实施例中，第一导电层30的材料与第二导电层41的材料可以相同，也可以不同。在其他可能的实施例中，第二导电层41的热膨胀系数小于第 一导电层30的热膨胀系数，以在热处理情况下，降低基底10承受的应力。
本实施例中，第二导电层41为凸出于第二表面15的凸起结构，第二导电层41在基底10上的投影覆盖第一导电层30，且第二导电层41在基底10上的投影轮廓大于第一导电层30的投影轮廓。
在一个示例性实施例中，参照图4所示，提供了一种半导体器件的制作方法。本实施例中的半导体器件的制作方法，包括：
S401：提供具有沟槽的基底，沟槽由基底的第一表面沿基底的厚度方向延伸；
S402：在沟槽内依次形成第一辅助层和第一导电层，第一导电层覆盖第一辅助层；
S403：在基底的第二表面对基底进行减薄，至暴露第一辅助层，其中，第一表面和第二表面相对设置；
S404：去除第一辅助层，形成第一开口；
S405：在基底的第二表面上形成第二介质层；
S406：图形化第二介质层，在第二介质层形成第二开口，第二开口暴露第一开口；
S407：形成第二介电层，第二介电层至少覆盖第二开口的内壁和位于第二开口内的第二表面；
S408：形成第二阻挡层，第二阻挡层覆盖第二介电层；
S409：沉积第二初始导电层，第二初始导电层填充第一开口和第二开口；
S410：去除第二介质层，保留位于第二开口中的第二初始导电层，第二初始导电层作为第二导电层。
在该实施例中，步骤S401至S406，以及S409和S410与上述实施例中的实现方式相同，在此，不再赘述。在步骤S407和S408中，如图22和图23所示，参考图25，在第二开口161的内中通过沉积工艺沉积第二介电层52和第二阻挡层62第二介电层52至少覆盖第二开口161的内壁和位于第二开口161内的第二表面15的部分区域。再通过沉积工艺沉积形成第二阻挡层62，第二阻挡层62覆盖第二介电层52，从而将第二导电层41和基底10隔离开，避免在半导体器件的运行时，第二导电层41中的电荷对基底10的影 响。
本实施例中，在形成第二导电层41后，若第二导电层41的材料为铜，则对第二导电层41进行退火处理，以消除第二导电层41内的应力。
在一个示例性实施例中，参照图5所示，提供了一种半导体器件的制作方法。本实施例中的半导体器件的制作方法包括：
S501：提供具有沟槽的基底，沟槽由基底的第一表面沿基底的厚度方向延伸；
S502：形成第一介电层，第一介电层覆盖沟槽的内壁；
S503：形成第一阻挡层，第一阻挡层覆盖第一介电层；
S504：在沟槽内依次形成第一辅助层和第一导电层，第一导电层覆盖第一辅助层；
S505：在基底的第二表面对基底进行减薄，至暴露第一辅助层，其中，第一表面和第二表面相对设置；
S506：去除第一辅助层，形成第一开口；
S507：在基底的第二表面上形成第二介质层；
S508：图形化第二介质层，在第二介质层形成第二开口，第二开口暴露第一开口；
S509：沉积第二初始导电层，第二初始导电层填充第一开口和第二开口。
在本实施例中，步骤S501，以及S504至S509与上述实施例中的实现方式相同，在此，不再赘述。在步骤S502和S503中，如图10和图11所示，在沟槽13的侧壁通过沉积工艺形成第一介电层51和第一阻挡层61，第一介电层51覆盖沟槽13的内壁、第一阻挡层61覆盖第一介电层51，使得在第一导电层30、第一辅助层20与沟槽13内壁之间通过第一介电层51和第一阻挡层61隔离开。其中，第一介电层51的材料为氮化硅，第一阻挡层61的材料为氮化钛。
另外，参照图12、图13所示，本实施例中的第一导电层30和第一辅助层20不与沟槽13的内侧壁直接连接，上述两者与沟槽13的侧壁之间设置上第一介电层51和第一阻挡层61，第一导电层30和第一辅助层20的侧壁与第一阻挡层61接触连接。
本实施例中通过设置第一介电层51和第一阻挡层61，一方面，第一介电层51起到绝缘作用，防止第一导电层30、第二导电层41与基底10上的有源器件之间产生干扰；另一方面，第一阻挡层61可以为基底10提供研磨时的缓冲屏障，减小硅层产生裂缝的几率，并防止铜污染到旁边硅层表面或裂缝中，进一步提高TSV制作的成品率。
参考图6所示，在一个示例性实施例中，提供了一种半导体器件的制作方法。该半导体器件的制作方法包括：
S601：提供衬底；
S602：在衬底的表面形成第一介质层，形成基底；
S603：图形化第一介质层，在基底中形成沟槽，沟槽贯穿第一介质层，第一介质层暴露的表面为第一表面；
S604：提供具有沟槽的基底，沟槽由基底的第一表面沿基底的厚度方向延伸；
S605：在沟槽内依次形成第一辅助层和第一导电层，第一导电层覆盖第一辅助层；
S606：在基底的第二表面对基底进行减薄，至暴露第一辅助层，其中，第一表面和第二表面相对设置；
S607：去除第一辅助层，形成第一开口；
S608：在基底的第二表面上形成第二介质层；
S609：图形化第二介质层，在第二介质层形成第二开口，第二开口暴露第一开口；
S610：沉积第二初始导电层，第二初始导电层填充第一开口和第二开口。
步骤S604至S5610与上述实施例中的实现方式相同，在此，不再赘述。如图7和图8所示，并参照图9，在步骤S601、S602和S603中，首先提供衬底11，衬底11的材质可以为硅，在衬底11的表面形成第一介质层12，衬底11与第一介质层12即为基底10。图形化第一介质层12，通过蚀刻工艺在基底10中形成沟槽13。其中，第一介质层12的远离衬底11一侧的表面为第一表面14，衬底11的远离第一介质层12一侧的表面为第二表面15。
如图8所示，在图形化第一介质层12时，先在第一介质层12上形成掩 膜层17，利用曝光和显影在掩膜层17上形成几何图形图案，然后通过刻蚀工艺将掩膜层17上的图形转移到所在基底10上，从而形成沟槽13。其中，第一介质层12与第二介质层16的材料不同。
本实施例中，同一刻蚀条件下，因此，第一辅助层20的材料是二氧化硅或氮化硅或延展性小的金属，基底10的材料是硅，所以第一辅助层20的刻蚀速率高于基底10的刻蚀速率，以便在步骤S104中，通过蚀刻工艺去除第一辅助层20时，第一辅助层20的蚀刻速率比基底10的蚀刻速率快，以确保去除第一辅助层20时，尽量减少对基底10的蚀刻量。
第一辅助层20与基底10具有高选择比，即第一辅助层20的刻蚀速率高于基底10的刻蚀速率，例如，第一辅助层20的蚀刻速率与基底10的蚀刻速率之比为100或80等。
高选择比：选择比指的是在同一刻蚀条件下一种材料与另一种材料相比刻蚀速率快多少，它定义为被刻蚀材料的刻蚀速率与另一种材料的刻蚀速率的比。高选择比意味着只刻除想要刻去的那一层材料。一个高选择比的刻蚀工艺不刻蚀下面一层材料(刻蚀到恰当的深度时停止)并且保护的光刻胶也未被刻蚀。
另外，本实施例中，第一辅助层20的材料的延展性小于第一导电层30的材料的延展性。例如，第一辅助层20的材料为二氧化硅或氮化硅或延展性小的金属材料，此时，在进行步骤S103时，靠近第二表面15的基底10材料和部分第一辅助层20同时被研磨掉，由于第一辅助层20的材料为二氧化硅或氮化硅等延展性与硅接近的材料，基底10第二表面15出现裂缝的概率减小，也不存在金属污染基底10的第二表面15以及裂缝的情况，若第一辅助层20采用延展性小与第一导电层30的金属，也一定程度上减小了第一辅助层20中含有的金属进入到硅层表面或裂缝中造成污染的几率。
本公开提出的半导体器件的制作方法，通过在沟槽内依次沉积第一辅助层和第一导电层，在通过研磨工艺减薄基底使沟槽形成贯穿基底两面的通孔的过程中，基底的第二表面和沟槽内的第一辅助层同时被研磨，并不会研磨到第一导电层，因此，第一导电层中的金属(例如铜)不会污染基底的第二表面或裂缝，同时，第一辅助层的材料采用二氧化硅或氮化硅等延展性与硅接近的材料，基底第二表面出现裂缝的概率减小，也不存在金属污染基底的 第二表面以及裂缝的情况，可以进一步提高TSV制作的成品率。
本公开的第二方面技术方案提供了一种半导体器件，根据一个示例性实施例，如图26和图27，参照图28，半导体器件包括基底10，基底10具有第一表面14和第二表面15，第一表面14和第二表面15相对设置。在基底10上设置至少一个通孔18，沿基底10的厚度方向贯穿基底10。半导体器件还包括第一导电层30和第二导电层41，两者填充于通孔18内且充满通孔18，同一通孔18中的第一导电层30和第二导电层41相连，其中，第一导电层30的顶面与基底10的第一表面14平齐，第二导电层41的顶面与基底10的第二表面15平齐。本实施例中，第一导电层30和第二导电层41组成半导体器件的TSV结构，实现芯片与芯片间距离最短、间距最小的互连，以达到更好的电学性能。
在一个示例性实施例中，参照图26、图28所示，半导体器件还包括覆盖通孔18的内壁的介电层50，通孔18以及覆盖介电层50的内壁的阻挡层60。当通孔18的横截面呈圆形时，沿通孔18的径向方向，第一导电层30和第二导电层41位于阻挡层60的内侧，介电层50和阻挡层60将第一导电层30和第二导电层41与基底10隔离开，避免第一导电层30、第二导电层41中的电荷对基底10上的有源器件造成干扰。
本实施例中，如图25所示，第二导电层41包括第一部分411和第二部分412，第一部分411的顶面与基底10的第二表面15平齐。第二部分412位于第二表面15上，第二部分412的与第一部分411相连的表面覆盖部分第二表面15，使第二导电层41的第二部分412凸出基底10的第二表面15形成凸起结构，用于不同半导体器件之间的电连接。其中，第一部分411和第二部分412连为一体。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的一种半导体器件的制作方法以及半导体器件，可以有效避免对基底进行减薄过程中，第一辅助层的材料污染基底的表面或缝隙，提高成品率。同时，使用本公开中的半导体器件制作方法对半导体器件进行加工，可以减少加工步骤，提高加工效率。

Claims (16)

  1. 一种半导体器件的制作方法，所述制作方法包括：
    提供具有沟槽的基底，所述沟槽由所述基底的第一表面沿所述基底的厚度方向延伸；
    在所述沟槽内依次形成第一辅助层和第一导电层，所述第一导电层覆盖所述第一辅助层；
    在所述基底的第二表面对所述基底进行减薄，至暴露所述第一辅助层，其中，所述第一表面和所述第二表面相对设置；
    去除所述第一辅助层，形成第一开口；
    在所述基底的第二表面上形成第二介质层；
    图形化所述第二介质层，在所述第二介质层形成第二开口，所述第二开口暴露所述第一开口；
    沉积第二初始导电层，所述第二初始导电层填充所述第一开口和所述第二开口。
  2. 根据权利要求1所述的半导体器件的制作方法，在沉积所述第二初始导电层之后，所述制作方法还包括：
    去除所述第二介质层和位于所述第二开口中的第二初始导电层，保留位于所述第一开口内的所述第二初始导电层作为第二导电层。
  3. 根据权利要求1所述的半导体器件的制作方法，在沉积所述第二初始导电层之后，所述制作方法还包括：
    去除所述第二介质层，保留位于所述第二开口中的所述第二初始导电层，所述第二初始导电层作为第二导电层。
  4. 根据权利要求3所述的半导体器件的制作方法，其中，
    所述第二导电层的热膨胀系数小于所述第一导电层的热膨胀系数。
  5. 根据权利要求3所述的半导体器件的制作方法，其中，所述第一导电层的材料与所述第二导电层的材料相同或不同。
  6. 根据权利要求3所述的半导体器件的制作方法，所述第二开口在所述基底上的投影轮廓的宽度大于所述第一开口在所述基底上的投影轮廓的宽度，沉积第二初始导电层之前，所述制作方法还包括：
    形成第二介电层，所述第二介电层至少覆盖所述第二开口的内壁和位于所述第二开口内的所述第二表面；
    形成第二阻挡层，所述第二阻挡层覆盖所述第二介电层。
  7. 根据权利要求2至6中任一项所述的半导体器件的制作方法，在形成所述第二导电层后，所述制作方法还包括：
    对所述第二导电层进行退火处理。
  8. 根据权利要求1所述的半导体器件的制作方法，在所述沟槽内依次形成第一辅助层和第一导电层之前，所述制作方法还包括：
    形成第一介电层，所述第一介电层覆盖所述沟槽的内壁；
    形成第一阻挡层，所述第一阻挡层覆盖所述第一介电层。
  9. 根据权利要求1所述的半导体器件的制作方法，所述提供具有沟槽的基底之前，所述制作方法还包括：
    提供衬底；
    在所述衬底的表面形成第一介质层，形成所述基底；
    图形化所述第一介质层，在所述基底中形成所述沟槽，所述沟槽贯穿所述第一介质层，所述第一介质层暴露的表面为所述第一表面。
  10. 根据权利要求1所述的半导体器件的制作方法，其中，
    同一刻蚀条件下，所述第一辅助层的刻蚀速率高于所述基底的刻蚀速率。
  11. 根据权利要求1所述的半导体器件的制作方法，其中，
    所述第一辅助层的材料的延展性小于所述第一导电层的材料的延展性。
  12. 一种半导体器件，所述半导体器件包括：
    基底，所述基底具有第一表面和第二表面，所述第一表面和所述第二表面相对设置；
    至少一个通孔，沿所述基底的厚度方向贯穿所述基底；
    第一导电层和第二导电层，填充于所述通孔内且充满所述通孔，同一所述通孔中的所述第一导电层和所述第二导电层相连；
    所述第一导电层的顶面与所述基底的第一表面平齐。
  13. 根据权利要求12所述的半导体器件，所述半导体器件还包括：
    介电层，覆盖所述通孔的内壁；
    阻挡层，覆盖所述介电层的内壁；
    沿所述通孔的径向方向，所述第一导电层和所述第二导电层位于所述阻挡层的内侧。
  14. 根据权利要求12所述的半导体器件，其中，所述第二导电层的顶面与所述基底的第二表面平齐。
  15. 根据权利要求12所述的半导体器件，其中，所述第二导电层包括第一部分和第二部分，所述第一部分的顶面与所述基底的第二表面平齐；
    所述第二部分位于所述第二表面上，所述第二部分的与所述第一部分相连的表面覆盖部分所述第二表面。
  16. 根据权利要求15所述的半导体器件，其中，所述第一部分和所述第二部分连为一体。
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