WO2023245817A9 - 半导体结构及其制造方法、存储芯片、电子设备 - Google Patents

半导体结构及其制造方法、存储芯片、电子设备 Download PDF

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Publication number
WO2023245817A9
WO2023245817A9 PCT/CN2022/109526 CN2022109526W WO2023245817A9 WO 2023245817 A9 WO2023245817 A9 WO 2023245817A9 CN 2022109526 W CN2022109526 W CN 2022109526W WO 2023245817 A9 WO2023245817 A9 WO 2023245817A9
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Prior art keywords
parallel signal
signal lines
lead
semiconductor structure
lead posts
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PCT/CN2022/109526
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English (en)
French (fr)
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WO2023245817A1 (zh
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王弘
李晓杰
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长鑫存储技术有限公司
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Priority to KR1020227040289A priority Critical patent/KR20240001017A/ko
Priority to EP22835546.7A priority patent/EP4328968A4/en
Priority to US18/154,930 priority patent/US20230413515A1/en
Publication of WO2023245817A1 publication Critical patent/WO2023245817A1/zh
Publication of WO2023245817A9 publication Critical patent/WO2023245817A9/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Definitions

  • Embodiments of the present disclosure belong to the field of semiconductors, and specifically relate to semiconductor structures and manufacturing methods, memory chips, and electronic devices.
  • the semiconductor structure includes a plurality of memory cells, which need to be connected to peripheral circuits to perform memory functions.
  • the volume of the memory unit has reached the scaling limit; due to process factors, it is difficult to increase the number of stacked layers of the memory unit.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, a memory chip, and an electronic device, which are at least conducive to improving the integration level of the semiconductor structure.
  • an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure includes: a substrate having a stacked structure on the substrate, the stacked structure including a plurality of memory cells arranged in a first direction
  • the memory unit group includes a plurality of memory cells arranged in multiple layers in a second direction;
  • the stacked structure also includes a plurality of parallel signal lines arranged in the second direction, and each of the parallel signal lines is connected to a layer of the memory unit; a plurality of lead posts arranged in the first direction, the plurality of lead posts and the plurality of parallel signal lines are arranged along a third direction, and the lead posts and the parallel signal lines line connection.
  • another aspect of the present disclosure further provides a semiconductor structure, wherein the semiconductor structure includes: a substrate having a stacked structure on the substrate, the stacked structure including a plurality of arrays arranged in a first direction.
  • a memory unit group the memory unit group includes multiple layers of memory cells arranged in a second direction; the stacked structure also includes a plurality of parallel signal lines arranged in the second direction, each of the parallel signal lines Connect a layer of the memory cells; a plurality of lead posts arranged in the first direction and extending along the second direction, the orthographic projection of the plurality of lead posts on the substrate surface is at least the same as the orthographic projection of the parallel signal line on the substrate surface. Partially overlap, and the lead posts are connected to the parallel signal lines.
  • another aspect of the embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, wherein the manufacturing method includes: providing a substrate; forming a stacked structure on the substrate, the stacked structure including a first A plurality of memory unit groups arranged in a second direction, the memory unit group includes multiple layers of a plurality of memory cells arranged in a second direction; the stacked structure also includes a plurality of parallel signal lines arranged in the second direction, each of the Parallel signal lines connect one layer of the memory cells; a plurality of lead posts arranged in a first direction are formed, the plurality of lead posts and the plurality of parallel signal lines are arranged along a third direction, and the lead posts are arranged with The parallel signal lines are connected.
  • the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, wherein the manufacturing method includes: providing a substrate; forming a stacked structure on the substrate, the stacked structure including a first A plurality of memory unit groups arranged in a second direction, the memory unit group includes multiple layers of a plurality of memory cells arranged in a second direction; the stacked structure also includes a plurality of parallel signal lines arranged in the second direction, each of the Parallel signal lines connect one layer of the memory cells; a plurality of lead posts arranged in the first direction and extending in the second direction are formed.
  • the orthographic projection of the plurality of lead posts on the substrate surface is consistent with the parallel signal lines on the substrate surface.
  • the orthographic projections at least partially overlap, and the lead posts are connected to the parallel signal lines.
  • embodiments of the present disclosure also provide a memory chip.
  • the memory chip includes the semiconductor structure as described above.
  • embodiments of the present disclosure further provide an electronic device, and the electronic device includes the memory chip as mentioned above.
  • the stacked structure includes a plurality of parallel signal lines arranged in the second direction, each of the parallel signal lines is connected to a layer of memory cells in the stacked structure, and the plurality of lead posts are connected to the plurality of parallel signal lines.
  • the signal lines are arranged along the third direction, and the lead posts are connected to parallel signal lines. That is, in the third direction, the lead posts are directly connected to the parallel signal lines, which is beneficial to reducing the number of steps or no longer providing separate step areas, thereby improving the integration of the semiconductor structure.
  • the plurality of lead posts extend along the second direction, and the orthographic projections of the plurality of lead posts on the substrate surface at least partially overlap with the orthographic projections of the parallel signal lines on the substrate surface. That is, the lead posts and the parallel signal lines are directly connected in a cross-arrangement manner. Therefore, it is beneficial to reduce the number of steps or no longer provide separate step areas, thereby improving the integration level of the semiconductor structure.
  • Figure 1 shows a top view of a semiconductor structure
  • Figure 2 shows a partial enlarged view of Figure 1
  • Figure 3 shows a cross-sectional view of Figure 2 in the A-A1 direction
  • 11 to 13 and 24 respectively show different partial cross-sectional schematic diagrams of a semiconductor structure provided by an embodiment of the present disclosure
  • Figures 14-23 and 25-28 respectively show different top schematic views of the semiconductor structure provided by an embodiment of the present disclosure
  • 29-30 respectively show three-dimensional views of two semiconductor structures provided by another embodiment of the present disclosure.
  • Figures 31, 32, 34, and 36 respectively show different cross-sectional schematic diagrams of a semiconductor structure provided by another embodiment of the present disclosure
  • Figure 33 shows a partial enlarged view of Figure 32
  • Figure 35 shows a partial enlarged view of Figure 34
  • Figure 37 shows a partial enlarged view of Figure 36
  • 45-56 show structural schematic diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided by yet another embodiment of the present disclosure
  • 57-60 show schematic structural diagrams corresponding to each step in a method for manufacturing a semiconductor structure provided by yet another embodiment of the present disclosure.
  • Figure 1 is a top view of a semiconductor structure
  • Figure 2 is an enlarged view of the steps in the dotted circle in Figure 1
  • Figure 3 is a cross-sectional view of Figure 2 in the A-A1 direction.
  • the semiconductor structure includes a memory cell region 100 and a step region 200 .
  • the memory cell area 100 has multiple layers of memory cells. There are multiple steps in the step area 200, and each step is arranged in one-to-one correspondence with each layer of memory cells.
  • a connection layer (not shown in the figure) can be provided in the step, and a lead post 300 can be set on the step.
  • the lead post 300 is electrically connected to the memory unit through the connection layer in the step, thereby drawing out the memory unit to facilitate the connection between the memory unit and the peripheral circuit. connect.
  • the connection layer below each step only functions as a support and electrical connection, resulting in a waste of space on the bottom floor. Therefore, the integration level of semiconductor structures needs to be further improved.
  • Embodiments of the present disclosure provide a semiconductor structure.
  • a plurality of lead posts and a plurality of parallel signal lines are arranged along a third direction, and the lead posts are connected to the parallel signal lines; or, the plurality of lead posts are arranged along a third direction.
  • the orthographic projections of the plurality of lead posts on the substrate surface at least partially overlap with the orthographic projections of the parallel signal lines on the substrate surface. That is, the lead posts and the parallel signal lines are directly connected by being arranged side by side or crossed. Therefore, there is no need to connect the lead posts with the parallel signal lines through the connection layer in the step area, thereby improving the space utilization in the semiconductor structure and thereby improving the semiconductor structure.
  • Structural integration is arranged in two directions, the orthographic projections of the plurality of lead posts on the substrate surface at least partially overlap with the orthographic projections of the parallel signal lines on the substrate surface. That is, the lead posts and the parallel signal lines are directly connected by being arranged side by side or crossed. Therefore, there is no
  • an embodiment of the present disclosure provides a semiconductor structure.
  • the semiconductor structure includes: a substrate (not shown in the figure) with a stacked structure on the substrate.
  • the stacked structure includes multiple layers arranged in a first direction X.
  • the memory cell group TC0 includes multiple layers of multiple memory cells TC arranged in the second direction Z.
  • the stacked structure also includes a plurality of parallel signal lines 3 arranged in the second direction Z. Each parallel signal line 3 Connect a layer of memory cells TC; multiple lead posts 5 arranged in the first direction X, multiple lead posts 5 and multiple parallel signal lines arranged along the third direction Y, and the lead posts 5 are connected to the parallel signal lines 3 .
  • the edge of the orthographic projection of the lead post 5 on the substrate surface is in contact with the edge of the orthogonal projection of the parallel signal line 3 on the substrate surface.
  • at least part of the sidewalls of the lead posts 5 are directly connected to the sidewalls of the parallel signal lines 3 without being indirectly connected through the connection layer in the step area, thereby reducing the number of connection layers and steps, which is beneficial to improving the semiconductor structure. degree of integration.
  • FIGS. 6 to 10 are partial side views. In order to be more intuitive, the structures used to isolate and support the lead posts 5 in the semiconductor structure are not shown in FIGS. 6 to 9 .
  • Figure 10 shows a structure for isolating and supporting lead posts 5.
  • each parallel signal line 3 is connected to at least one lead post 5 . That is, each parallel signal line 3 can be directly connected to the lead post 5 and thereby be led out by the lead post 5 . Therefore, the step region can no longer be provided separately, which can greatly improve the space utilization of the semiconductor structure and facilitate the simplification of the production process.
  • multiple parallel signal lines 3 are connected to multiple lead posts 5 in one-to-one correspondence. That is, each parallel signal line 3 is connected to one lead post 5, which is beneficial to reducing the number of connection locations between the parallel signal lines 3 and the lead posts 5, and the production process is simpler.
  • a parallel signal line 3 can also be connected to multiple lead posts 5 , thereby increasing the contact area between the parallel signal line 3 and the lead posts 5 and reducing contact resistance.
  • the lead posts 5 extend in the second direction Z. That is, the plurality of lead posts 5 are parallel to each other, and the extension direction of the lead posts 5 is the same as the direction in which the memory cells TC are stacked. In this way, it is helpful to simplify the production process and improve the uniformity of the semiconductor structure.
  • the stacking direction of the memory cells TC is the second direction Z, and the second direction Z is perpendicular to the substrate surface.
  • the lead posts 5 will be arranged adjacent to the multi-layer parallel signal lines 3, but based on the lead posts 5 It can be seen from the lead-out function that each lead post 5 is only connected to one parallel signal line 3 and will not be connected to two parallel signal lines 3 at the same time, otherwise signal confusion will occur.
  • the parallel signal lines 3 connected to the lead posts 5 are called parallel signal lines 3 of the corresponding layer.
  • the lead posts 5 are insulated from the parallel signal lines 3 other than the parallel signal lines 3 of the corresponding layer.
  • the lead post 5 is divided into a stacked contact portion 51 and an extension portion 52.
  • the contact portion 51 is provided in the same layer as the parallel signal line 3 of the corresponding layer, and the two are connected to each other.
  • the extension portion 52 is arranged adjacent to the parallel signal line 3 above the corresponding layer, but is insulated from each other.
  • the stacked structure may further include a dielectric layer 6 .
  • the dielectric layer 6 is at least located on the sidewall of the lead post 5 facing the parallel signal line 3 above the corresponding layer, and the lower surface of the dielectric layer 6 is higher than the parallel signal line 3 connected to the lead post 5 .
  • the dielectric layer 6 is used to isolate the lead posts 5 from the parallel signal lines 3 outside the corresponding layer to avoid incorrect electrical connections.
  • the dielectric layer 6 may surround the side walls of the extension portion 52 of the lead post 5 .
  • the material of the dielectric layer 6 may be a low dielectric constant material such as silicon nitride or silicon oxide.
  • the lead posts 5 connected to different parallel signal lines 3 have different lengths in the second direction Z, and the bottoms of the lead posts 5 are connected to the parallel signal lines 3 .
  • the lead post 5 connected to the parallel signal line 3 on the top layer has the smallest length in the second direction Z
  • the lead post 5 connected to the parallel signal line 3 on the bottom layer has the shortest length in the second direction Z.
  • the length of the lead posts 5 can also be the same, but the lead posts 5 are only connected to the parallel signal lines 3 of the corresponding layer, and are insulated from the parallel signal lines 3 above and below the corresponding layer.
  • the bottom surface of the lead post 5 can be flush with the bottom surface of the parallel signal line 3 of the corresponding layer; or, the bottom surface of the lead post 5 can be slightly lower. on the bottom surface of the parallel signal line 3 of the corresponding layer. In other embodiments, the bottom surface of the lead post 5 can also be higher than the bottom surface of the parallel signal line 3 of the corresponding layer, but needs to be lower than the top surface of the parallel signal line 3 of the corresponding layer.
  • adjacent lead posts 5 and the like are arranged at equal intervals in the first direction X. That is, the spacing between adjacent lead posts 5 is balanced, thereby improving the uniformity of the semiconductor structure.
  • the lead posts 5 may be arranged sequentially according to their length in the second direction Z.
  • the lengths of the lead posts 5 may not increase or decrease in sequence, but alternate lengths, thereby avoiding large parasitic capacitances between lead posts 5 with larger lengths.
  • the spacing between adjacent lead posts 5 is proportional to the facing area. It should be noted that the facing area of adjacent lead posts 5 is proportional to the size of the parasitic capacitance. Therefore, if the facing area of adjacent lead posts 5 is larger, the distance between them can be increased accordingly to reduce the parasitic capacitance.
  • the stacked structure further includes multiple etching stopper layers 13 arranged in the second direction Z; each etching stopper layer 13 is connected to the bottom surface of at least one lead post 5 .
  • the method of forming the lead pillar 5 may include: using an etching process to form a through hole 8 on one side of the parallel signal line 3 (refer to FIG. 53 ), and depositing conductive material in the through hole 8 to form the lead pillar 5 . Therefore, the position of the through hole 8 determines the position of the lead post 5.
  • the etching barrier layer 13 can play a role in stopping etching, thereby realizing a self-alignment function to avoid the problem of over-etching or insufficient etching in the through hole 8 . That is to say, the etching barrier layer 13 and the isolation layer 14 are alternately arranged in the second direction Z.
  • the etching barrier layer 13 is directly opposite to the gap between two adjacent layers of parallel signal lines 3, and the isolation layer 14 is directly opposite to the parallel signal line 3. 3 are arranged on the same layer, and the isolation layer 14 and the etching barrier layer 13 are relatively large compared with the selective etching.
  • the material of the isolation layer 14 may be silicon oxide
  • the material of the etching barrier layer 13 may be silicon nitride.
  • the etching barrier layer 13 can also play an isolation role.
  • only the isolation layer 14 may be provided on one side of the parallel signal line 3 without the etching barrier layer 13 .
  • the depth of the through hole 8 is controlled by the etching time. In this way, only one etchant can be used, thereby simplifying the manufacturing process.
  • the memory cell TC includes a channel region 22 and a source-drain doping region 21 arranged in the third direction Y.
  • the source-drain doping region 21 is located on both sides of the channel region 22. . That is, the memory cell TC includes at least the transistor T.
  • the memory unit TC may also include a capacitor C, and the transistor T and the capacitor C are arranged in the third direction Y.
  • the storage unit TC includes a transistor T and a capacitor C.
  • the storage unit TC may only include a transistor T.
  • the storage unit TC is composed of six transistors T. For example, there is no transistor T.
  • the memory unit TC is composed of a double gate transistor T.
  • the stacked structure further includes vertical signal lines 4 extending along the second direction Z and connected to the multi-layer memory cells TC of the same memory cell group TC0 .
  • One of the parallel signal line 3 and the vertical signal line 4 is a bit line BL, and the other is a word line WL.
  • the bit line BL is connected to the source and drain doped regions 21
  • the word line WL is connected to the channel region 22 .
  • the source-drain doped region 21 connected to the bit line BL is called the first source-drain doped region 211, and the source-drain doped region 21 spaced apart from the bit line BL is called the second source-drain doped region 212.
  • bit line BL bit line BL
  • word line WL word line
  • the parallel signal line 3 is the bit line BL
  • the parallel signal line 3 and the lead post 5 mainly have the following positional relationships:
  • Example 1 referring to Figures 14 to 18, the lead post 5 and the memory cell TC are respectively located on opposite sides of the parallel signal line 3 arranged in the third direction Y, that is, the lead post 5 is located on the side of the parallel signal line 3 away from the memory cell TC. . In this way, the arrangement position and size of the lead posts 5 can be set more flexibly.
  • the lead post 5 is directly opposite to the memory cell group TC0 in the third direction Y. In this way, it is helpful to improve the uniformity of position arrangement.
  • the lead posts 5 and the memory cell groups TC0 are staggered in the first direction
  • the lead posts 5 are disposed opposite to the memory cell group TC0 and the space between the adjacent memory cell groups TC0 at the same time.
  • some of the lead posts 5 are directly opposite to the space between adjacent memory cell groups TC0 , and some of the lead posts are directly opposite to the memory cell group TC0 .
  • the gap between adjacent lead pillars 5 may be arranged opposite to at least one memory cell group TC0 .
  • the spacing between adjacent lead posts 5 may be the same.
  • the spacing between adjacent lead posts 5 can also be adjusted according to different facing areas, thereby balancing the parasitic capacitances between different lead posts 5 .
  • the width of the lead pillar 5 in the first direction In other embodiments, referring to FIG. 18 , the width of the lead post 5 in the first direction , thereby reducing contact resistance.
  • the width of the lead pillar 5 in the first direction X may also be greater than or equal to the pitch of the adjacent memory cell group TCO. In this way, it is beneficial to increase the contact area between the lead post 5 and the parallel signal line 3 of the corresponding layer, thereby reducing the contact resistance.
  • the width of the lead post 5 in the first direction X is greater than the width of the lead post 5 in the third direction Y.
  • the length of the parallel signal line 3 in the first direction X is very long. Therefore, the lead post 5 has sufficient accommodation space in the first direction X.
  • a certain width difference can be set for the lead post 5 in the first direction X and the third direction Y.
  • Example 2 referring to Figures 19 and 20, the lead post 5 and the memory cell TC are located on the same side of the parallel signal line 3. That is, the lead posts 5 may be located between adjacent memory cell groups TCO. In this way, it is conducive to making full use of the spatial position within the stacked structure, thereby improving space utilization.
  • At least two memory cell groups TC0 can be spaced between adjacent lead posts 5 .
  • the number of memory cell groups TC0 at intervals between adjacent lead posts 5 may be the same.
  • the number of memory cell groups TC0 spaced between adjacent lead posts 5 can also be adjusted according to different facing areas, thereby balancing the parasitic capacitances between different lead posts 5 .
  • the width of the lead post 5 in the third direction Y is greater than the width of the lead post 5 in the first direction X. In this way, the distance between adjacent memory cell groups TC0 can be reduced, thereby reducing the area occupied by the stacked structure on the substrate surface; the cross-sectional area of the lead post 5 can also be increased, thereby reducing the contact resistance of the lead post 5 . In other embodiments, the width of the lead post 5 in the third direction Y may also be equal to the width of the lead post 5 in the first direction X.
  • Example 1 and Example 2 can also be combined with each other, that is, part of the lead posts 5 is located on one side of the parallel signal line 3 , and another part of the lead posts 5 is located on the other side of the parallel signal line 3 .
  • the number of storage cells in each layer of the memory cell group TCO is one.
  • the number of memory cells TC in each layer of the memory cell group TC0 is two, and the two memory cells TC are respectively located on the parallel signal line 3 in the third direction Y arrangement. Opposite sides. As the number of memory cells TC in the memory cell group TC0 increases, the storage capacity of the semiconductor structure is correspondingly enhanced.
  • part of the lead posts 5 may be located between adjacent memory cell groups TCO of one stacked structure, and part of the lead posts 5 may be located between adjacent memory cell groups TCO of another stacked structure. That is, the plurality of lead posts 5 are located on different sides of the parallel signal line 3 . For example, adjacent lead posts 5 are located on different sides of the parallel signal lines 3 . In other words, two adjacent lead posts 5 are staggered from each other in the first direction X, thereby reducing parasitic capacitance.
  • all the lead posts 5 are located on the same side of the parallel signal line 3 , which is beneficial to improving the uniformity of the arrangement of the lead posts 5 and simplifying the semiconductor manufacturing process.
  • one lead post 5 may only be used to lead out a stacked structure of parallel signal lines 3 .
  • one lead post 5 can also be shared by two stacked structures.
  • Figure 23 is a top view
  • Figure 24 is a cross-sectional view of Figure 23 in the third direction Y.
  • the parallel signal lines 3 of two adjacent stacked structures are arranged facing each other, and the lead posts 5 are located adjacent to each other.
  • the parallel signal lines 3 in the stacked structure and the parallel signal lines 3 in the same layer of the adjacent stacked structure are electrically connected through at least one lead post 5 . Since the lead posts 5 can be shared by two stacked structures, the number of lead posts 5 can be reduced, which is beneficial to reducing the volume of the semiconductor structure.
  • the memory cells TC corresponding to the parallel signal lines 3 are still controlled by different word lines WL. Therefore, the memory cells TC of the two stacked structures are still controlled by different word lines WL. Can be controlled independently.
  • the parallel signal line 3 is the word line WL
  • the parallel signal line 3 and the lead post mainly have the following positional relationships:
  • the word line WL may cover the entire channel region 22 , or the word line WL may be connected to the top surface and/or the bottom surface of the channel region 22 . If the word line WL covers the entire channel region 22, the area of the sidewalls of the word line WL is larger. Since the sidewalls of the word line WL are connected to the sidewalls of the lead posts 5, a larger sidewall area of the word line WL is conducive to increasing the contact area between the word line WL and the lead posts 5, thereby reducing contact resistance. If the word lines WL are located on the top and bottom surfaces of the channel area 22, in order to increase the contact area, the lead posts 5 can be connected to the word lines WL located on the top and bottom surfaces of the channel area 22 at the same time.
  • all the lead posts 5 are located on the same side of the parallel signal line 3 , which is beneficial to improving the uniformity of the arrangement of the lead posts 5 and simplifying the semiconductor manufacturing process.
  • all lead posts 5 are located on the side of the parallel signal line 3 close to the first source and drain doping region 211; with reference to Figures 26-27, all lead posts 5 are located on the side of the parallel signal line 3 close to the second source and drain region. one side of the doped region 212 .
  • At least two memory cell groups TC0 may be spaced between adjacent lead posts 5 .
  • the same number of memory cell groups TC0 can be provided between adjacent lead pillars 5 .
  • the number of memory cell groups TC0 spaced between adjacent lead posts 5 can also be adjusted according to different facing areas, thereby balancing the parasitic capacitances between different lead posts 5 .
  • part of the lead posts 5 may be located on one side of the parallel signal line 3 , and part of the lead posts 5 may be located on the other side of the parallel signal line 3 .
  • adjacent lead posts 5 are located on different sides of the parallel signal lines 3 , that is, the lead posts 5 can be staggered in the first direction X, thereby reducing parasitic capacitance.
  • a plurality of lead posts 5 and a plurality of parallel signal lines are arranged along the third direction Y, and the lead posts 5 are connected to the parallel signal lines 3 . That is, the edges of the orthographic projections of the lead posts 5 and the parallel signal lines 3 on the substrate surface are in contact. Since the lead posts 5 are directly connected to the parallel signal lines 3, the number of connection layers and steps can be reduced, thereby improving the integration of the semiconductor structure.
  • FIGS. 29 to 44 another embodiment of the present disclosure provides a semiconductor structure.
  • This semiconductor structure is substantially the same as the semiconductor structure in the previous embodiment.
  • the main difference is that the plurality of lead posts 5 of this semiconductor structure are on the substrate.
  • the orthographic projection of the surface overlaps at least partially with the orthographic projection of the parallel signal line 3 on the substrate surface.
  • the semiconductor structure includes: a substrate (not shown in the figure) with a stacked structure on the substrate.
  • the stacked structure includes a plurality of memory cell groups TCO arranged in the first direction X.
  • the memory unit group TCO includes multiple layers arranged in the second direction Z.
  • the lead posts 5 at least use the spatial position of part of the parallel signal lines 3 to directly connect to the parallel signal lines 3 in a cross-arrangement manner. Therefore, it is beneficial to reduce the number of steps or no longer separately provide step areas, thereby improving the semiconductor structure. degree of integration.
  • the lead posts 5 are located on the top surfaces of the parallel signal lines 3 of the corresponding layers, and the bottom surfaces of the lead posts 5 are connected to the top surfaces of the parallel signal lines 3 of the corresponding layers.
  • the bottom of the lead post 5 can also be embedded inside the parallel signal line 3 of the corresponding layer; or, the bottom of the lead post 5 can also penetrate the parallel signal line 3 of the corresponding layer, that is, the side wall of the lead post 5 It can also be connected to the parallel signal line 3 of the corresponding layer.
  • At least one lead post 5 penetrates at least one parallel signal line 3, that is, at least one lead post 5 among the plurality of lead posts 5 is parallel to the non-top layer.
  • Signal line 3 is connected.
  • the lead posts 5 connected to the parallel signal lines 3 on the non-top layer in addition to using the spatial position of the parallel signal lines 3 on the corresponding layer, they also need to occupy the spatial position of the parallel signal lines 3 above the corresponding layer. Therefore, the lead post 5 will penetrate the parallel signal line 3 located above the corresponding layer.
  • the lead posts 5 do not need to penetrate the parallel signal lines 3 outside the corresponding layer.
  • lead posts 5 penetrate the parallel signal lines 3 located above the corresponding layer 5, they do not completely cut off the parallel signal lines 3 located above the corresponding layer.
  • the parallel signal lines 3 include contact areas 31 and exposed areas 32 arranged in the third direction Y; the lead posts 5 are connected to the contact areas 31 and expose the exposed areas 32; the third direction Y is vertical in the second direction Z and parallel to the substrate surface. That is to say, the lead posts 5 are connected to the contact areas 31 of the parallel signal lines 3 on the corresponding layer, penetrate the contact areas 31 of the parallel signal lines 3 above the corresponding layer, and expose all the exposed areas 32 of the parallel signal lines 3 . Although the parallel signal line 3 above the corresponding layer is penetrated, the exposed area 32 is still retained, so the parallel signal line 3 will not be completely cut off, and the parallel signal line 3 can still be connected to the memory cell TC on the same layer.
  • FIG. 33 shows a partial enlarged view of the parallel signal lines 3 and lead posts 5 of the corresponding layers in FIG. 32 .
  • the exposed areas 32 are located on opposite sides of the contact area 31 .
  • the orthographic projection of the pillar 5 on the substrate surface coincides with the orthographic projection of the contact area 31 on the substrate surface. That is to say, the contact area 31 is located in the middle of the parallel signal line 3, the lead post 5 is connected to the center of the parallel signal line 3 of the corresponding layer, and penetrates the center of the parallel signal line 3 located above the corresponding layer.
  • the parallel signal line The exposed area 32 of 3 is not cut off, and the parallel signal line 3 can still be connected to the memory cell TC on the same layer.
  • FIG. 35 shows a partial enlarged view of the parallel signal lines 3 and lead posts 5 of the corresponding layers in FIG. 34
  • FIG. 37 shows a parallel view of the corresponding layers in FIG. 36
  • Figure 38 is a schematic top view of the semiconductor structure shown in Figure 36.
  • the parallel signal line 3 has opposite sides arranged in the third direction Y, the exposed area 32 is located on one side of the opposite sides, and the contact area 31 is located on the other side of the opposite sides. That is, the lead post 5 is connected to one side of the parallel signal line 3 of the corresponding layer, and exposes the other side of the parallel signal line 3.
  • the lead post 5 penetrates one side of the parallel signal line 3 above the corresponding layer, and the parallel signal line 3 above the corresponding layer. The other side of line 3 is not penetrated.
  • the orthographic projection of the lead post 5 on the substrate surface coincides with the orthographic projection of the exposed area 32 on the substrate surface, that is, in the direction parallel to the substrate, the lead post 5 utilizes parallel signals.
  • the spatial position of the line 3 does not exceed the parallel signal line 3, which is conducive to improving the compactness of the lead post 5 and the parallel signal line 3 to improve space utilization.
  • the lead post 5 is disposed protrudingly relative to the contact area 31 . That is, the lead post 5 is protrudingly disposed relative to one side of the parallel signal line 3 . That is to say, only part of the bottom surface of the lead post 5 is in contact with the contact area 31 .
  • the protruding arrangement can reduce the area of the parallel signal lines 3 above the corresponding layer that the lead posts 5 penetrate, thereby reducing the resistance of the parallel signal lines 3 above the corresponding layers; at the same time, it can also ensure that the lead posts 5 have a larger cross-sectional area. Thereby, the resistance of the lead post 5 is reduced.
  • the parallel signal lines 3 may be in a long strip shape, that is, the orthographic projection of the parallel signal lines 3 on the substrate surface is a rectangle.
  • the parallel signal line 3 may also include a connected main body part and a protruding part.
  • the main part may be in the shape of a strip, and the protruding part may be in the shape of a square or a zigzag. That is, the protruding part is in The length in the first direction X is smaller than the length of the main body portion in the first direction X.
  • the main body part and the protruding part may be arranged in the third direction Y.
  • the main part is connected to the memory cell resistor TC0, and the protruding part is connected to the lead post 5.
  • the bottom surface of the lead post 5 can be connected to the top surface of the protruding portion of the corresponding layer. In this way, the lead post 5 does not need to penetrate the main body above the corresponding layer, thereby helping to reduce the resistance of the parallel signal line 3 above the corresponding layer. .
  • the memory cell TC includes a channel region 22 and a source-drain doped region 21 arranged in the third direction Y.
  • the source-drain doped region 21 is located on both sides of the channel region 22 . That is, the memory cell TC includes at least the transistor T.
  • the memory unit TC may also include a capacitor C, and the transistor T and the capacitor C are arranged in the third direction Y.
  • the source-drain doping region 21 may include a first source-drain doping region 211 and a second source-drain doping region 212.
  • the first source-drain doping region 211 may be connected to the bit line BL, and the second source-drain doping region 212 may be located at The channel region 22 is on a side away from the first source-drain doping region 211 .
  • the stacked structure also includes vertical signal lines 4 extending along the second direction Z and connected to the multi-layer memory cells TC of the same memory cell group TC0.
  • One of the parallel signal line 3 and the vertical signal line 4 is a bit line BL, and the other is a word line WL.
  • the bit line BL is connected to the source and drain doped regions 21
  • the word line WL is connected to the channel region 22 .
  • bit line BL bit line BL
  • word line WL word line
  • the parallel signal line 3 is the bit line BL
  • the parallel signal line 3 and the lead post 5 mainly have the following positional relationships:
  • Example 1 referring to Figures 38 and 39, the lead post 5 is directly opposite to the memory cell group TC0 in the third direction Y. In this way, it is helpful to improve the uniformity of position arrangement.
  • Example 2 referring to FIG. 40 , the lead posts 5 and the memory cells TC are arranged staggeredly in the first direction X. That is, the lead post 5 may be directly opposite to the space between adjacent memory cell groups TC0.
  • Example 3 referring to FIG. 41 , the lead posts 5 are disposed relative to the space between the memory cell group TC0 and the adjacent memory cell group TC0 at the same time.
  • the exposed area 32 can be located on the side close to the memory cell TC.
  • the contact area 31 may be located on a side away from the memory cell TC; or, the exposed areas 32 may be located on opposite sides of the contact area 31 .
  • the number of memory cells TC in each layer of the memory cell group TC0 is two, and the two memory cells TC are respectively located on opposite sides of the parallel signal line 3 arranged in the third direction Y. At this time, one lead post 5 leads to more memory cells TC through the parallel signal line 3, which is beneficial to improving the integration of the semiconductor structure.
  • the parallel signal line 3 is the word line WL
  • the parallel signal line 3 and the lead post 5 mainly have the following positional relationships:
  • Example 1 referring to FIG. 43, the lead pillar 5 is located between adjacent memory cell groups TC0, that is, the lead pillar 5 and the channel region 22 are staggered from each other, thereby preventing the lead pillar 5 from cutting off the memory cells TC located above the corresponding layer, thereby reducing The number of failed memory cells TC.
  • Example 2 referring to FIG. 44 , the orthographic projection of the lead post 5 on the substrate surface overlaps with the orthographic projection of the channel region 22 on the substrate surface. That is, the lead post 5 can use the position of the channel region 22 to lead out the parallel signal line 3, which is beneficial to reducing the spacing between adjacent memory cell groups TC0, thereby improving the compactness of the memory cell group TC0, thereby improving the quality of the semiconductor structure. Failure Rate.
  • the edges of orthographic projections of the lead posts 5 and the parallel signal lines 3 on the substrate surface overlap. That is, the lead posts 5 can be directly connected to the parallel signal lines 3 by utilizing the space of the parallel signal lines 3 themselves, thereby reducing the number of connection layers and steps, thereby improving the integration of the semiconductor structure.
  • FIGS. 45 to 56 yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. It should be noted that, in order to facilitate description and clearly illustrate the steps of the method for manufacturing a semiconductor structure, FIGS. 45 to 56 are is a schematic diagram of the partial structure of a semiconductor structure. A method for manufacturing a semiconductor structure provided by an embodiment of the present application will be described in detail below with reference to the accompanying drawings.
  • a substrate is provided; a stacked structure is formed on the substrate, the stacked structure includes a plurality of memory cell groups TC0 arranged in the first direction It includes a plurality of parallel signal lines 3 arranged in the second direction Z, and each parallel signal line 3 is connected to a layer of memory cells TC.
  • the memory cell TC may include a transistor T and a capacitor C.
  • the step of forming the transistor T may include: forming multiple active layers arranged at intervals, each active layer including a plurality of active structures; and performing a doping process on the active structures to form the source and drain doping regions 21 , channel region 22; a gate dielectric layer 6 is formed on the surface of the channel region 22.
  • the memory cell TC includes a channel region 22 and a source-drain doping region 21 arranged in the third direction Y.
  • the source-drain doping region 21 is located on both sides of the channel region 22; the third direction Y is parallel to the substrate surface. .
  • the steps of forming the capacitor C may include: forming a capacitor support layer and a capacitor hole located in the capacitor support layer; forming a lower electrode on the inner wall of the capacitor hole, forming a capacitor dielectric layer 6 on the surface of the lower electrode, and forming a capacitor dielectric layer 6 on the surface of the capacitor dielectric layer 6. upper electrode.
  • the lower electrode, capacitive dielectric layer 6 and upper electrode form the capacitor C.
  • the plurality of parallel signal lines 3 include the first to Nth parallel signal lines arranged sequentially in the second direction Z, where N is a positive integer greater than 1.
  • the 1st parallel signal line is on the top layer, and the Nth parallel signal line is on the bottom layer.
  • a through hole 8 is formed.
  • the through hole 8 includes a first through hole through an Nth through hole.
  • the first through hole exposes the side wall of the first parallel signal line; the Nth through hole exposes the first parallel signal. line to the side wall of the Nth parallel signal line.
  • an isolation structure is formed on the side wall of the parallel signal line 3.
  • the isolation structure may include alternating etching barrier layers 13 and isolation layers 14 .
  • the isolation layer 14 is arranged on the same layer as the parallel signal lines 3 , and the etching barrier layer 13 is arranged directly opposite the insulating layer 12 (refer to FIG. 10 ) between adjacent parallel signal lines 3 .
  • the isolation structure may only include the isolation layer 14 , and the isolation layer 14 covers the parallel signal lines 3 and the sidewalls of the insulation layer 12 .
  • a mask layer 71 is formed.
  • the mask layer 71 has N openings 72 ; N is a positive integer greater than 1; the openings 72 are located on one side of the parallel signal line 3 .
  • the mask layer 71 may be a photoresist layer, and the photoresist layer is photoetched to form the opening 72 .
  • the mask layer 71 may also be a stacked hard mask layer 71 and a photoresist layer. After the photoresist layer is photoetched, the hard mask layer 71 is etched to form the opening 72 .
  • the isolation layer 14 on the top layer is etched along the opening 72 until the etching barrier layer 13 on the top layer is exposed, thereby forming a plurality of first sub-vias 811, and the first sub-vias 811 expose the first parallel signal.
  • one of the first sub-through holes 811 serves as the first through hole 81 .
  • a sacrificial layer 73 filling the first sub-via hole 811 is formed.
  • a low dielectric constant material such as silicon oxide is deposited in the first sub-via hole 811 as the sacrificial layer 73 .
  • the mask layer 71 is patterned so that the mask layer 71 has N-1 openings 72 .
  • the photoresist layer can be spin-coated again, and photolithography can be performed on the photoresist layer to form the opening 72 .
  • the sacrificial layer 73 and the second isolation layer 14 are etched along the opening 72 , thereby forming the N-1 second sub-via hole 821 , in which one of the second sub-via holes 821 serves as the second sub-via hole 821 . 2 through holes 82.
  • the steps of forming the sacrificial layer 73 , patterning the mask layer 71 and etching are repeated until the sidewalls of the Nth parallel signal line 3 are exposed, that is, the top surface of the Nth etching barrier layer is exposed.
  • the through hole 8 can be formed, and the through hole 8 includes the first through Nth through hole 8 to the Nth through hole 8 .
  • a first through hole 81 , a second through hole 82 , a third through hole 83 , a fourth through hole 84 and a fifth through hole 85 may be formed. It should be noted that in the first direction . In other embodiments, in the first direction Or decreasing, but alternating between deep and shallow, thereby avoiding excessive parasitic capacitance between lead posts 5 with a large depth in the subsequently formed lead posts 5 .
  • the steps of forming the through hole 8 are similar to the aforementioned steps.
  • the main difference is that the insulating layer 12 between the adjacent memory cell groups TC0 is etched to form the through hole. 8.
  • steps related to forming the mask layer 71 and forming the sacrificial layer 73 please refer to the foregoing detailed description.
  • first to Nth contact portions are respectively formed at the bottoms of the first to Nth through holes 81 to Nth through holes, and the first to Nth contact portions are respectively connected with the first to Nth parallel signals.
  • the parallel signal lines 3 are arranged on the same layer, and the contact portion 51 covers the side walls of the parallel signal lines 3 of the corresponding layer.
  • the dielectric layer 6 is formed on the side wall of the through hole 8 .
  • an initial dielectric layer is formed on the sidewalls of the through hole 8 and the surface of the contact portion 51 through a chemical vapor deposition process; the initial dielectric layer on the surface of the contact portion 51 is removed, and the initial dielectric layer on the sidewall of the through hole 8 serves as the dielectric layer 6.
  • an extension portion 52 filling the through hole 8 is formed, and the contact portion 51 and the extension portion 52 constitute the lead post 5 .
  • metal such as copper, aluminum, titanium or tungsten is deposited in the through hole 8 to serve as the lead post 5 .
  • the above method of forming the lead post 5 is only an illustrative description and is not limited thereto.
  • the method of forming the lead post 5 can be adjusted according to the specific structure of the lead post 5 .
  • FIGS. 57-60 yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the manufacturing method of this semiconductor structure is substantially the same as the manufacturing method of the aforementioned semiconductor structure.
  • FIGS. 57 to 60 are partial structural schematic diagrams of the semiconductor structure. The manufacturing method of the semiconductor structure will be described in detail below with reference to the accompanying drawings.
  • the stacked structure includes a plurality of memory cell groups TC0 arranged in the first direction It includes a plurality of parallel signal lines 3 arranged in the second direction Z, and each parallel signal line 3 is connected to a layer of memory cells TC.
  • the plurality of parallel signal lines 3 include the first to Nth parallel signal lines arranged sequentially in the second direction Z, where N is a positive integer greater than 1.
  • the 1st parallel signal line is on the top layer, and the Nth parallel signal line is on the bottom layer.
  • a through hole 8 is formed.
  • the through hole 8 includes a first through hole 81 to an Nth through hole.
  • the top surface of the first through hole 81 exposes the first parallel signal line; the Nth through hole penetrates the first through hole.
  • the steps for forming the through hole 8 are substantially the same as those in the previous embodiment.
  • the main difference is that the through hole 8 penetrates the parallel signal line 3 , so the parallel signal line 3 needs to be etched.
  • the lead post 5 uses the position of the memory cell group TC0, the channel area 22 and the insulating layer 12 between the upper and lower memory cells TC need to be etched when forming the through hole 8; if the lead post 5 uses the adjacent memory cell TC At the position between the cell groups TC0, when forming the through hole 8, it is also necessary to etch the insulating layer 12 between the adjacent memory cells TC.
  • steps related to forming the mask layer 71 and forming the sacrificial layer 73 please refer to the detailed descriptions in the foregoing embodiments.
  • a dielectric layer 6 is formed on the sidewall of the through hole 8 .
  • an initial dielectric layer is formed on the inner wall of the through hole 8 , and the initial dielectric layer located on the bottom wall of the through hole 8 is removed to expose the parallel signal line 3 of the corresponding layer.
  • the initial dielectric layer located on the side wall of the through hole 8 serves as the dielectric layer 6 .
  • the lead posts 5 filling the through holes 8 are formed, and the bottom surfaces of the lead posts 5 are electrically connected to the parallel signal lines 3 .
  • the parallel signal lines 3 are etched to form the through holes 8 , and the dielectric layer 6 and the lead posts 5 filling the through holes 8 are formed.
  • the lead posts 5 can use the spatial position of the parallel signal lines 3 to directly achieve electrical connection with the parallel signal lines 3, thereby reducing the number of steps or not forming a separate step area, which is beneficial to improving the integration of the semiconductor structure.
  • Embodiments of the present disclosure also provide a memory chip, including the semiconductor structure provided in the foregoing embodiments.
  • Memory chips are memory components used to store programs and various data information.
  • the memory chip may be a random access memory chip or a read-only memory chip.
  • the random access memory chip may include a dynamic random access memory or a static random access memory. Due to the high integration level of the aforementioned semiconductor structure, it is conducive to miniaturization of memory chips.
  • An embodiment of the present disclosure also provides an electronic device, including the memory chip provided in the foregoing embodiment.
  • the electronic device may be a television, a computer, a mobile phone, a tablet, or other devices.
  • the electronic device may include a circuit board and a packaging structure.
  • the memory chip may be soldered to the circuit board and protected by the packaging structure.
  • the electronic device may also include a power supply for providing operating voltage to the memory chip.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构及其制造方法、存储芯片、电子设备，半导体结构包括：基底，所述基底上具有堆叠结构，所述堆叠结构包括在第一方向排列的多个存储单元组，所述存储单元组包括多层在第二方向排列的多个存储单元；所述堆叠结构还包括在所述第二方向排列的多条平行信号线，每条所述平行信号线连接一层所述存储单元；在所述第一方向排列的多个引线柱，所述多个引线柱与所述多条平行信号线沿第三方向排布，且所述引线柱与所述平行信号线连接。本公开实施例至少可以提高半导体结构的集成度。

Description

半导体结构及其制造方法、存储芯片、电子设备
交叉引用
本申请引用于2022年6月21日递交的名称为“半导体结构及其制造方法、存储芯片、电子设备”的第202210709274.2号中国专利申请，其通过引用被全部并入本申请。
技术领域
本公开实施例属于半导体领域，具体涉及半导体结构及其制造方法、存储芯片、电子设备。
背景技术
半导体结构包括多个存储单元，存储单元需要与外围电路连接以执行存储功能。半导体结构的集成度越高，则其可容纳的存储单元的数目越多，半导体结构的性能也更为优异。然而，目前半导体结构内的空间浪费较多；此外，受制于物理特性的因素，存储单元的体积已达到缩放极限；受制于工艺因素，存储单元的堆叠层数也难以提高。
因此，亟需一种新架构的半导体结构，以提高半导体结构的集成度。
发明内容
本公开实施例提供一种半导体结构及其制造方法、存储芯片、电子设备，至少有利于提高半导体结构的集成度。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，其中，半导体结构包括：基底，所述基底上具有堆叠结构，所述堆叠结构包括在第一方向排列的多个存储单元组，所述存储单元组包括多层在第二方向排列的多个存储单元；所述堆叠结构还包括在所述第二方向排列的多条平行信号线，每条所述平行信号线连接一层所述存储单元；在所述第一方向排列的多个引线柱，所述多个引线柱与所述多条平行信号线沿第三方向排布，且所述引线柱与所述平行信号线连接。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构，其中，半导体结构包括：基底，所述基底上具有堆叠结构，所述堆叠结构包括在第一方向排列的多个存储单元组，所述存储单元组包括多层在第二方向排列的多个存储单元；所述堆叠结构还包括在所述第二方向排列的多条平行信号线，每条所述平行信号线连接一层所述存储单元；在所述第一方向排列且沿第二方向延伸的多个引线柱，所述多个引线柱在基底表面的正投影与平行信号线在基底表面的正投影至少部分重叠，且所述引线柱与所述平行信号线连接。
根据本公开一些实施例，本公开实施例又一方面还提供一种半导体结构的制造方法，其中，制造方法包括：提供基底；在所述基底上形成堆叠结构，所述堆叠结构包括在第一方向排列的多个存储单元组，所述存储单元组包括多层在第二方向排列的多个存储单元；所述堆叠结构还包括在第二方向排列的多条平行信号线，每条所述平行信号线连接一层所述存储单元；形成在第一方向排列的多个引线柱，所述多个引线柱与所述多条平行信号线沿第三方向排布，且所述引线柱与所述平行信号线连接。
根据本公开一些实施例，本公开实施例再一方面还提供一种半导体结构的制造方法，其中，制造方法包括：提供基底；在所述基底上形成堆叠结构，所述堆叠结构包括在第一方向排列的多个存储单元组，所述存储单元组包括多层在第二方向排列的多个存储单元；所述堆叠结构还包括在第二方向排列的多条平行信号线，每条所述平行信号线连接一层所述存储单元；形成在所述第一方向排列且沿第二方向延伸的多个引线柱，所述多个引线柱在基底表面的正投影与平行信号线在基底表面的正投影至少部分重叠，且所述引线柱与所述平行信号线连接。
根据本公开一些实施例，本公开实施例还提供一种存储芯片，存储芯片包括如前所述的半导体结构。
根据本公开一些实施例，本公开实施例还提供一种电子设备，电子设备包括如前所述的存储芯片。
本公开实施例提供的技术方案至少具有以下优点：
在本公开一些实施例中，堆叠结构包括在所述第二方向排列的多条平行信号线，每条所述平行信号线连接堆叠结构内的一层存储单元，多个引线柱与多条平行信号线沿第三方向排布，且引线柱与平行信号线连接。即在第三方向上，引线柱直接与平行信号线相连，从而有利于减少台阶个数或者不再单独设置台阶区，进而提高半导体结构的集成度。
在本公开另一些实施例中，多个引线柱沿第二方向延伸，且多个引线柱在基底表面的正投影与平行信号线在基底表面的正投影至少部分重叠。即，引线柱与平行信号线通过交叉设置的方式直接相连，因此，从而有利于减少台阶个数或者不再单独设置台阶区，进而提高半导体结构的集成度。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了一种半导体结构的俯视图；
图2示出了图1的局部放大图；
图3示出了图2在A-A1方向上的剖面图；
图4-图5分别示出了本公开一实施例提供的两种半导体结构的立体图；
图6-图10分别示出了本公开一实施例提供的半导体结构的不同局部侧视示意图；
图11-图13、图24分别示出了本公开一实施例提供的半导体结构的不同局部剖面示意图；
图14-图23、图25-图28分别示出了本公开一实施例提供的半导体结构的不同俯视示意图；
图29-图30分别示出了本公开另一实施例提供的两种半导体结构的立体图；
图31、图32、图34、图36分别示出了本公开另一实施例提供的半导体结构的不同剖面示意图；
图33示出了图32的局部放大图；
图35示出了图34的局部放大图；
图37示出了图36的局部放大图；
图38-图44分别示出了本公开另一实施例提供的半导体结构的不同俯视示意图；
图45-图56示出了本公开又一实施例提供的半导体结构的制造方法中各步骤对应的结构示意图；
图57-图60示出了本公开再一实施例提供的半导体结构的制造方法中各步骤对应的结构示意图。
具体实施方式
图1为一种半导体结构的俯视图，图2为图1中虚线圈内台阶的放大图，图3为图2在A-A1方向上的剖面图。参考图1-图3，半导体结构包括存储单元区100和台阶区200。存储单元区100内具有多层存储单元。台阶区200内具有多个台阶，每个台阶与每层存储单元一一对应设置。台阶内可以设置连接层(图中未示出)，台阶上可设置引线柱300，引线柱300通过台阶内的连接层与存储单元电连接，从而将存储单元引出，以便于存储单元与外围电路连接。然而，随着存储单元堆叠层数的增加，台阶区200所占用的面积会越来越大。比如，若共有64层存储单元，相应地，则需要64个台阶，越底层的台阶的面积会越大。若最顶层的台阶的面积为0.25μm 2，则最底层的台阶的面积为64*0.25＝16μm 2。参考图3，每个台阶以下的连接层仅仅起到支撑和电连接的作用，从而造成底层空间的浪费。因此，半导体结构的集成度有待进一步提高。
本公开实施例提供一种半导体结构，在此半导体结构中，多个引线柱与多条平行信号线沿第三方向排布，且引线柱与平行信号线连接；或者，多个引线柱沿第二方向延伸，且多个引线柱在基底表面的正投影与平行信号线在基底表面的正投影至少部分重叠。即，引线柱与平行信号线通过并排设置或交叉设置的方式直接相连，因此，无需通过台阶区的连接层将引线柱与平行信号线连接，从而提高半导体结构内的空间利用率，进而提高半导体结构的集成度。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
如图4-图28所示，本公开一实施例提供一种半导体结构，半导体结构包括：基底(图中未示出)，基底上具有堆叠结构，堆叠结构包括在第一方向X排列的多个存储单元组TC0，存储单元组TC0包括多层在第二方向Z排列的多个存储单元TC；堆叠结构还包括在第二方向Z排列的多条平行信号线3，每条平行信号线3连接一层存储单元TC；在第一方向X排列的多个引线柱5，多个引线柱5与多条平行信号线沿第三方向Y排布，且引线柱5与平行信号线3连接。
即，引线柱5在基底表面上的正投影的边缘与平行信号线3在基底表面上的正投影的边缘相接。换言之，引线柱5的至少部分侧壁与平行信号线3的侧壁直接相连，而无需通过台阶区的连接层间接地相连，从而可以减少连接层和台阶的个数，进而有利于提高半导体结构的集成度。
以下将结合附图对半导体结构进行详细说明。
首先需要说明的是，图6-图10为局部侧视示意图，为了更加直观，图6-图9中未将其示出半导体结构内用于隔离和支撑引线柱5的结构示出。图10示出了用于隔离和支撑引线柱5的结构。
在一些实施例中，参考图6-图10，每条平行信号线3至少与一个引线柱5连接。即每条平行信号线3都可以直接与引线柱5连接，从而被引线柱5引出。因此，可以不再单独设置台阶区，从而能够较大程度地提高半导体结构的空间利用率，且有利于简化生产工艺。
示例地，参考图6-图8，多条平行信号线3与多个引线柱5一一对应连接。即，每条平行信号线3均与一个引线柱5连接，从而有利于减少平行信号线3与引线柱5的连接位置，生产工艺更简单。在另一些实施例中，参考图9，一条平行信号线3也可以与多个引线柱5连接，从而可以增大平行信号线3与引线柱5的接触面积，降低接触电阻。
在一些实施例中，参考图4-图13，引线柱5在第二方向Z延伸。即，多个引线柱5相互平行，且引线柱5的延伸方向与存储单元TC的堆叠的方向相同。如此，有利于简化生产工艺，并提高半导体结构的均一性。示例地，存储单元TC的堆叠的方向为第二方向Z，第二方向Z垂直于基底表面。
参考图4-图11，需要说明的是，对于与非顶层的平行信号线3相连的引线柱5，此引线柱5会与多层的平行信号线3相邻设置，但是基于引线柱5的引出功能可知，每个引线柱5只连接一个平行信号线3，而不会同时连接两条平行信号线3，否则会发生信号的错乱。为便于理解，将与引线柱5相连的平行信号线3称之为对应层的平行信号线3。引线柱5与对应层的平行信号线3以外的平行信号线3绝缘设置。此外，将引线柱5划分为层叠设置的接触部51和延伸部52，接触部51与对应层的平行信号线3同层设置，且二者相互连接。延伸部52与对应层上方的平行信号线3相邻设置，但相互绝缘。
相应地，参考图5-图13，堆叠结构还可以包括介质层6。介质层6至少位于引线柱5朝向对应层上方的平行信号线3的侧壁，且介质层6的下表面高于与引线柱5相连的平行信号线3。即。介质层6用于将引线柱5与对应层以外的平行信号线3相隔离，以避免发生错误的电连接。具体地，介质层6可以环绕引线柱5的延伸部52的侧壁。介质层6的材料可以为氮化硅或氧化硅等低介电常数材料。
在一些实施例中，参考图4-图10，与不同平行信号线3连接的引线柱5在第二方向Z上的长度不同，且引线柱5的底部与平行信号线3相连。示例地，与顶层的平行信号线3连接的引线柱5在第二方向Z上的长度最小，与底层的平行信号线3连接的引线柱5在第二方向Z上的长度最短，如此，有利于节省材料，进而降低生产成本，还有利于简化生产工艺。在另一些实施例中，引线柱5的长度也可以相同，但引线柱5只与对应层的平行信号线3连接，而与对应层上方及下方的平行信号线3绝缘设置。
为增大引线柱5与平行信号线3的接触面积，以减小接触电阻，引线柱5的底面可以与对应层的平行信号线3的底面齐平；或者，引线柱5的底面可以略低于对应层的平行信号线3的底面。在另一些实施例中，引线柱5的底面也可以高于对应层的平行信号线3的底面，但需要低于对应层的平行信号线3的顶面。
在一些实施例中，参考图6-图7，相邻引线柱5等在第一方向X上等间距排布。即配平相邻引线柱5之间的间距，从而提高半导体结构的均一性。
参考图6，引线柱5可以按照在第二方向Z上的长度大小依次排布。在另一些实施例中，参考图7，引线柱5的长度也可以不依次递增或递减，而是长短交替，从而避免长度较大的引线柱5之间产生较大的寄生电容。
在另一些实施例中，参考图8，相邻引线柱5的间距与正对面积成正比。需要说明的是，相邻引线柱5的正对面积与寄生电容的大小呈正比关系。因此，若相邻引线柱5的正对面积越大，则可相应增加二者的间距从而降低寄生电容。
在一些实施例中，参考图10-图12，堆叠结构还包括在第二方向Z排列的多层刻蚀阻挡层13；每层刻蚀阻挡层13与至少一个引线柱5的底面相接。具体地，形成引线柱5的方法可以包括：采用刻蚀工艺在平行信号线3的一侧形成通孔8(参考图53)，在通孔8中沉积导电材料以形成引线柱5。因此，通孔8的位置决定了引 线柱5的位置。刻蚀阻挡层13能够起到停止刻蚀的作用，从而实现自对准的功能，以避免通孔8发生过刻蚀或刻蚀程度不足的问题。也就是说，刻蚀阻挡层13与隔离层14在第二方向Z上交替设置，刻蚀阻挡层13与相邻两层平行信号线3之间的间隙正对，隔离层14与平行信号线3同层设置，且隔离层14与刻蚀阻挡层13与选择刻蚀比较大。示例地，隔离层14的材料可以为氧化硅，刻蚀阻挡层13的材料可以为氮化硅。此外，刻蚀阻挡层13也可以起到隔离的作用。
在另一些实施例中，参考图13，也可以在平行信号线3的一侧只设置隔离层14，而不设置刻蚀阻挡层13。相应地，在形成通孔8的过程中，通过刻蚀时间来控制通孔8的深度。如此，可以只采用一种刻蚀剂，从而有利于简化制造工艺。
参考图4-图5，图11-图28，存储单元TC包括在第三方向Y排列的沟道区22和源漏掺杂区21，源漏掺杂区21位于沟道区22的两侧。即，存储单元TC至少包括晶体管T。在另一些实施例中，存储单元TC还可以包括电容C，晶体管T和电容C在第三方向Y上排列。示例地，在动态随机存取存储器(Dynamic Random Access Memory，DRAM)中，存储单元TC包括一个晶体管T和一个电容C。在另一些实施例中，存储单元TC也可以只包括晶体管T，比如，在静态随机存取存储器(Static Random-Access Memory，SRAM)中，其存储单元TC由六个晶体管T构成，又比如无电容C双栅量子阱单晶体管TDRAM(Capacitorless Double Gate Quantum Well Single Transistor DRAM，1T DRAM)中，其存储单元TC由一个双栅晶体管T构成。
参考图4-图5，堆叠结构还包括垂直信号线4，垂直信号线4沿第二方向Z延伸，并与同一存储单元组TC0的多层存储单元TC连接。平行信号线3和垂直信号线4中的一者为位线BL，另一者为字线WL。位线BL与源漏掺杂区21相连，字线WL与沟道区22相连。与位线BL相连的源漏掺杂区21称之为第一源漏掺杂区211，与位线BL间隔设置的源漏掺杂区21称之为第二源漏掺杂区212。
以下将分为位线BL和字线WL两种情况，对平行信号线3与引线柱5的位置关系进行详细说明。
在平行信号线3为位线BL时，平行信号线3与引线柱5主要具有如下几种位置关系：
示例一，参考图14-图18，引线柱5和存储单元TC分别位于平行信号线3在第三方向Y排列的相对两侧，即引线柱5位于平行信号线3远离存储单元TC的一侧。如此，可以更加灵活地设置引线柱5的排列位置和尺寸大小。
具体地，参考图14，在一些实施例中，引线柱5与存储单元组TC0在第三方向Y上正对。如此，有利于提高位置排布的均一性。在另一些实施例中，参考图15，引线柱5与存储单元组TC0在第一方向X上交错排列，即引线柱5可以与相邻存储单元组TC0之间的空间正对。在另一些实施例中，参考图16，引线柱5同时与存储单元组TC0以及相邻存储单元组TC0之间的空间相对设置。在另一些实施例中，参考图17，部分引线柱5与相邻存储单元组TC0之间的空间正对，部分引线柱与存储单元组TC0正对。
继续参考图14-图17，为降低相邻引线柱5之间的寄生电容，相邻引线柱5之间的间隙可以与至少一个存储单元组TC0相对设置。此外，参考图14-图16，为增加半导体结构的均一性，相邻引线柱5之间的间距可以相同。此外，参考图17，还可以根据不同正对面积，调整相邻引线柱5之间的间距，从而平衡不同引线柱5之间的寄生电容。
在一些实施例中，参考图14-图17，引线柱5在第一方向X上的宽度等于存储单元组TC0的宽度，如此，有利于统一不同结构的特征尺寸，以简化生产工艺。在另一些实施例中，参考图18，引线柱5在第一方向X上的宽度大于存储单元组 TC0的宽度，如此，有利于增大引线柱5与对应层的平行信号线3的接触面积，从而降低接触电阻。
另外，引线柱5的在第一方向X上的宽度还可以大于或等于相邻存储单元组TC0的间距。如此，有利于增大引线柱5与对应层的平行信号线3的接触面积，从而降低接触电阻。
另外，参考图18，引线柱5在第一方向X上的宽度大于引线柱5在第三方向Y上的宽度。需要说明的是，平行信号线3在第一方向X上的长度很长，因此，引线柱5在第一方向X上具有充足的容纳空间。为了在增加引线柱5的横截面积的同时，提高半导体空间的利用率，可以对引线柱5在第一方向X上和第三方向Y上设置一定的宽度差。
示例二，参考图19-图20，引线柱5和存储单元TC位于平行信号线3的同一侧。即，引线柱5可以位于相邻存储单元组TC0之间。如此，有利于充分利用堆叠结构内的空间位置，从而提高空间利用率。
继续参考图19-图20，为降低相邻引线柱5之间的寄生电容，相邻引线柱5之间至少可以间隔两个存储单元组TC0。此外，参考图19，为增加半导体结构的均一性，相邻引线柱5之间的间隔的存储单元组TC0的数量可以相同。此外，参考图20，还可以根据不同正对面积，调整相邻引线柱5间隔的存储单元组TC0的数量，从而平衡不同引线柱5之间的寄生电容。
在一些实施例中，参考图19-图20，引线柱5在第三方向Y上的宽度大于引线柱5在第一方向X上的宽度。如此，既能够降低相邻存储单元组TC0的间距，从而降低堆叠结构在基底表面所占据的面积大小；还能够增大引线柱5的横截面积，从而降低引线柱5的接触电阻。在另一些实施例中，引线柱5在第三方向Y上的宽度也可以等于引线柱5在第一方向X上的宽度。
需要说明的是，示例一和示例二还可以相互结合，即部分引线柱5位于平行信号线3的一侧，另一部分引线柱5位于平行信号线3的另一侧。
在一些实施例中，参考图14-图20，存储单元组TC0的每层的储存单元数量为一个。在另一个实施例中，参考图21-图22，存储单元组TC0的每层存储单元TC的数量为两个，且两个存储单元TC分别位于平行信号线3在第三方向Y排列上的相对两侧。由于存储单元组TC0的存储单元TC的数量增加，半导体结构的存储容量也相应增强。
在一些实施例中，参考图21，部分引线柱5可以位于一堆叠结构的相邻存储单元组TC0之间，部分引线柱5可以位于另一堆叠结构的相邻存储单元组TC0之间。即，多个引线柱5位于平行信号线3的不同两侧。举例而言，相邻引线柱5位于平行信号线3的不同侧。换言之，相邻两个引线柱5在第一方向X上相互错开，从而可以减小寄生电容。
在另一些实施例中，参考图22，所有引线柱5位于平行信号线3的同一侧，从而有利于提高引线柱5的排列方式的均一性，以简化半导体的制造工艺。
值得注意的是，在一些实施例中，一个引线柱5可以只用于引出一个堆叠结构的平行信号线3。在另一些实施例中，一个引线柱5还可以被两个堆叠结构所共用。具体地，参考图23-图24，图23为俯视图，图24为图23在第三方向Y上的剖面图，相邻两个堆叠结构的平行信号线3相向设置，引线柱5位于相邻堆叠结构的平行信号线3之间，且相邻堆叠结构的同一层的平行信号线3至少通过一个引线柱5电连接。由于引线柱5可以被两个堆叠结构共用，因此，可以减少引线柱5的数量，从而有利于缩小半导体结构的体积。
需要说明的是，虽然两个堆叠结构的平行信号线3相电连接，但是平行信号 线3所对应的存储单元TC仍然受到不同字线WL的控制，因此，两个堆叠结构的存储单元TC依然可以独立控制。
在平行信号线3为字线WL时，平行信号线3与引线柱主要具有如下几种位置关系：
首先，需要说明的是，字线WL与沟道区22存在多种位置关系。比如，字线WL可以包覆整个沟道区22，或者，字线WL可以与沟道区22的顶面和/或底面相连。若字线WL包覆整个沟道区22，则字线WL侧壁的面积更大。由于字线WL的侧壁与引线柱5的侧壁相连，因此，更大的字线WL侧壁面积有利于增大字线WL与引线柱5的接触面积，从而降低接触电阻。若字线WL位于沟道区22的顶面和底面，为增加接触面积，引线柱5可以同时与位于沟道区22顶面和底面的字线WL相连。
在一些实施例中，参考图25-图27，所有引线柱5位于平行信号线3的同一侧，从而有利于提高引线柱5的排列方式的均一性，以简化半导体的制造工艺。示例地，参考图25，所有引线柱5位于平行信号线3靠近第一源漏掺杂区211的一侧；参考图26-图27，所有引线柱5位于平行信号线3靠近第二源漏掺杂区212的一侧。
参考图25-图27，为降低寄生电容，相邻引线柱5之间可以至少间隔有两个存储单元组TC0。此外，参考图25和图26，为提高半导体结构的均一性，可使得相邻引线柱5之间具有相同数目的存储单元组TC0。或者，参考图27，还可以根据不同正对面积，调整相邻引线柱5间隔的存储单元组TC0的数量，从而平衡不同引线柱5之间的寄生电容。
在另一些实施例中，参考图28，部分引线柱5可以位于平行信号线3的一侧，部分引线柱5可以位于平行信号线3的另一侧。示例地，相邻引线柱5位于平行信号线3的不同侧，即，引线柱5可以在第一方向X上交错排列，从而降低寄生电容。
综上所述，在本公开一实施例中，多个引线柱5与多条平行信号线沿第三方向Y排布，且引线柱5与平行信号线3连接。即，引线柱5和平行信号线3在基底表面上的正投影的边缘相接。由于引线柱5与平行信号线3直接相连，因而可以减少连接层和台阶的数量，从而提高半导体结构的集成度。
如图29-图44所示，本公开另一实施例提供一种半导体结构，此半导体结构与前述实施例中的半导体结构大致相同，主要区别在于：此半导体结构的多个引线柱5在基底表面的正投影与平行信号线3在基底表面的正投影至少部分重叠。此半导体结构与前述实施例提供的半导体结构相同或相似的部分请参考前述实施例中的详细说明，在此不再赘述。
半导体结构包括：基底(图中未示出)，基底上具有堆叠结构，堆叠结构包括在第一方向X排列的多个存储单元组TC0，存储单元组TC0包括多层在第二方向Z排列的多个存储单元TC；堆叠结构还包括在第二方向Z排列的多条平行信号线3，每条平行信号线3连接一层存储单元TC；在第一方向X排列且沿第二方向Z延伸的多个引线柱5，多个引线柱5在基底表面的正投影与平行信号线3在基底表面的正投影至少部分重叠，且引线柱5与平行信号线3连接。
即，引线柱5至少利用部分平行信号线3的空间位置，与平行信号线3通过交叉设置的方式直接相连，因此，从而有利于减少台阶个数或者不再单独设置台阶区，进而提高半导体结构的集成度。
以下将结合附图对此半导体结构进行详细说明。
参考图29-图37，引线柱5位于对应层的平行信号线3的顶面上，且引线柱5的底面与对应层的平行信号线3的顶面相连。在另一些实施例中，引线柱5的底 部还可以嵌入对应层的平行信号线3的内部；或者，引线柱5的底部还可以贯穿对应层的平行信号线3，即引线柱5的侧壁也可以与对应层的平行信号线3相连。
参考图29-图30以及图32、图34和图36，至少一个引线柱5贯穿至少一个平行信号线3，也就是说，多个引线柱5中的至少一个引线柱5与非顶层的平行信号线3相连。需要说明的是，对于与非顶层的平行信号线3相连的引线柱5，除了需要利用对应层的平行信号线3的空间位置外，还需要占用对应层上方的平行信号线3的空间位置。因此，引线柱5会贯穿位于对应层上方的平行信号线3。参考图31，对于与顶层的平行信号线3相连的引线柱5，此引线柱5无需贯穿对应层以外的平行信号线3。
需要说明的是，引线柱5虽然贯穿位于对应层5上方的平行信号线3，但并未将对应层上方的平行信号线3完全截断。
具体地，参考图29-图44，平行信号线3包括在第三方向Y排列的接触区31和暴露区32；引线柱5与接触区31相连，并露出暴露区32；第三方向Y垂直于第二方向Z且平行于基底表面。也就是说，引线柱5与对应层的平行信号线3的接触区31相连，并贯穿位于对应层上方的平行信号线3的接触区31，且露出所有平行信号线3的暴露区32。对应层上方的平行信号线3虽然被贯穿，但是由于暴露区32仍被保留，因此，平行信号线3不会被完全截断，平行信号线3仍然能够与同一层的存储单元TC相连。
在一些实施例中，参考图32-图33，图33示出了图32中对应层的平行信号线3和引线柱5的局部放大图，暴露区32位于接触区31的相对两侧，引线柱5在基底表面的正投影与接触区31在基底表面的正投影重合。也就是说是说，接触区31位于平行信号线3的中间位置，引线柱5与对应层的平行信号线3的中心相连，并贯穿位于对应层上方的平行信号线3的中心，平行信号线3的暴露区32未被截断，平行信号线3仍然能够与同一层的存储单元TC相连。
在另一些实施例中，参考图34-图38，图35示出了图34中对应层的平行信号线3和引线柱5的局部放大图，图37示出了图36中对应层的平行信号线3和引线柱5的局部放大图，图38为图36所示的半导体结构的俯视示意图。平行信号线3具有在第三方向Y排列的相对两侧，暴露区32位于相对两侧中的一侧，接触区31位于相对两侧中的另一侧。即引线柱5与对应层的平行信号线3的一侧相连，并露出平行信号线3的另一侧，引线柱5贯穿对应层上方的平行信号线3的一侧，对应层上方的平行信号线3的另一侧未被贯穿。
在一个例子中，参考图34-图35，引线柱5在基底表面的正投影与暴露区32在基底表面的正投影重合，即在平行于基底的方向上，引线柱5利用的是平行信号线3的空间位置，而不会超出平行信号线3，从而有利于提高引线柱5与平行信号线3的紧凑程度，以提高空间利用率。
在另一个例子中，参考图36-图38，引线柱5相对于接触区31呈凸出设置。即，引线柱5相对于平行信号线3的一侧呈凸出设置。也就是说，引线柱5仅部分底面与接触区31接触相连。凸出设置可以降低引线柱5贯穿的对应层上方的平行信号线3的面积，从而降低对应层上方的平行信号线3的电阻；同时，还可以保证引线柱5具有较大的横截面积，从而降低引线柱5的电阻。
需要说明的是，在一些实施例中，平行信号线3可以为长条状，即平行信号线3在基底表面的正投影为矩形。在另一些实施例中，平行信号线3还可以包括相连的主体部和凸出部，主体部为长条状，凸出部可以为方块状或锯齿状等形状，即，凸出部在第一方向X上的长度小于主体部在第一方向X上的长度。主体部和凸出部可以在第三方向Y上排列。主体部与存储单元阻TC0相连，凸出部与引线柱5相 连。示例地，引线柱5的底面可以与对应层的凸出部的顶面相连，如此，引线柱5可以无需贯穿对应层上方的主体部，从而有利于降低对应层上方的平行信号线3的电阻。
参考图29-图30，存储单元TC包括在第三方向Y排列的沟道区22和源漏掺杂区21，源漏掺杂区21位于沟道区22的两侧。即，存储单元TC至少包括晶体管T。在另一些实施例中，存储单元TC还可以包括电容C，晶体管T和电容C在第三方向Y上排列。源漏掺杂区21可以包括第一源漏掺杂区211和第二源漏掺杂区212，第一源漏掺杂区211可以位线BL相连，第二源漏掺杂区212可以位于沟道区22远离第一源漏掺杂区211的一侧。
堆叠结构还包括垂直信号线4，垂直信号线4沿第二方向Z延伸，并与同一存储单元组TC0的多层存储单元TC连接。平行信号线3和垂直信号线4中的一者为位线BL，另一者为字线WL，位线BL与源漏掺杂区21相连，字线WL与沟道区22相连。
以下将分为位线BL和字线WL两种情况，对平行信号线3与引线柱5的位置关系进行详细说明。
在平行信号线3为位线BL时，平行信号线3与引线柱5主要具有如下几种位置关系：
示例一，参考图38-图39，引线柱5与存储单元组TC0在第三方向Y上正对。如此，有利于提高位置排布的均一性。
示例二，参考图40，引线柱5与存储单元TC在第一方向X上交错设置排列。即引线柱5可以与相邻存储单元组TC0之间的空间正对。
示例三，参考图41，引线柱5同时与存储单元组TC0以及相邻存储单元组TC0之间的空间相对设置。
需要说明的是，在平行信号线3为位线BL时，为了避免引线柱5切断对应层上方的平行信号线3与存储单元TC的连接关系，暴露区32可以位于靠近存储单元TC的一侧，接触区31可以位于远离存储单元TC的一侧；或者，暴露区32可以位于接触区31的相对两侧。
在一些实施例中，参考图42，存储单元组TC0的每层存储单元TC的数量为两个，且两个存储单元TC分别位于平行信号线3的在第三方向Y排列的相对两侧。此时，一条引线柱5通过平行信号线3引出的更多的存储单元TC，从而有利于提高半导体结构的集成度。
在平行信号线3为字线WL时，平行信号线3与引线柱5主要具有如下几种位置关系：
示例一，参考图43，引线柱5位于相邻存储单元组TC0之间，即引线柱5与沟道区22相互错开，从而可以避免引线柱5截断位于对应层上方的存储单元TC，从而减少失效的存储单元TC的数量。
示例二，参考图44，引线柱5在基底表面上的正投影与沟道区22在基底表面的正投影具有重叠。即，引线柱5可以利用沟道区22的位置引出平行信号线3，从而有利于减小相邻存储单元组TC0之间的间距，以提高存储单元组TC0的紧凑程度，进而提高半导体结构的失效率。
综上所述，在本公开另一实施例中，引线柱5和平行信号线3在基底表面上的正投影的边缘具有重叠。即，引线柱5可以利用平行信号线3本身的空间位于与平行信号线3直接相连，因而可以减少连接层和台阶的数量，从而提高半导体结构的集成度。
如图45-图56所示，本公开再一实施例提供一种半导体结构的制造方法，需 要说明的是，为了便于描述以及清晰地示意出半导体结构制作方法的步骤，图45至图56均为半导体结构的局部结构示意图。以下将结合附图对本申请一实施例提供的半导体结构的制造方法进行详细说明。
提供基底；在基底上形成堆叠结构，堆叠结构包括在第一方向X排列的多个存储单元组TC0，存储单元组TC0包括多层在第二方向Z排列的多个存储单元TC；堆叠结构还包括在第二方向Z排列的多条平行信号线3，每条平行信号线3连接一层存储单元TC。
示例地，存储单元TC可以包括晶体管T和电容C。具体地，形成晶体管T的步骤可以包括：形成多层间隔设置的有源层，每一有源层包括多个有源结构；对有源结构进行掺杂处理，以形成源漏掺杂区21、沟道区22；在沟道区22的表面形成栅介质层6。也就是说，存储单元TC包括在第三方向Y排列的沟道区22和源漏掺杂区21，源漏掺杂区21位于沟道区22的两侧；第三方向Y与基底表面平行。此外，还需要在相邻层的晶体管T之间形成绝缘层12，以隔离相邻晶体管T。形成电容C的步骤可以包括：形成电容支撑层，以及位于电容支撑层内的电容孔；在电容孔的内壁形成下电极，在下电极的表面形成电容介质层6，在电容介质层6的表面形成上电极。下电极、电容介质层6和上电极构成电容C。
形成在第一方向X排列的多个引线柱5，多个引线柱5与多条平行信号线沿第三方向Y排布，且引线柱5与平行信号线3连接。
以下将对引线柱5的形成方法进行详细说明。
首先需要说明的是，多条平行信号线3包括在第二方向Z上依次排布的第1平行信号线至第N平行信号线，N为大于1的正整数。第1平行信号线位于顶层，第N平行信号线位于底层。
参考图45-图56，形成通孔8，通孔8包括第1通孔至第N通孔，第1通孔的露出第1平行信号线的侧壁；第N通孔露出第1平行信号线至第N平行信号线的侧壁。
以下将以平行信号线3为位线BL为例，对形成通孔8的步骤进行详细说明。
参考图45-图46，在平行信号线3的侧壁形成隔离结构。在一些实施例中，隔离结构可以包括交替设置的刻蚀阻挡层13和隔离层14。隔离层14与平行信号线3同层设置，刻蚀阻挡层13与相邻平行信号线3之间的绝缘层12(参考图10)正对设置。在另一些实施例中，隔离结构可以只包括隔离层14，且隔离层14覆盖平行信号线3和绝缘层12的侧壁。
继续参考图45-图46，形成掩膜层71，掩膜层71具有N个开口72；N为大于1的正整数；开口72位于平行信号线3的一侧。示例的，掩膜层71可以为光刻胶层，对光刻胶层进行光刻，以形成开口72。或者，掩膜层71还可以为层叠设置的硬掩膜层71和光刻胶层，对光刻胶层光刻后，再刻蚀硬掩膜层71，以形成开口72。
参考图47-图48，沿开口72刻蚀顶层的隔离层14，直至露出顶层的刻蚀阻挡层13，从而形成多个第1子通孔811，第1子通孔811露出第1平行信号线的侧壁，其中一个第1子通孔811作为第1通孔81。
参考图49-图50，形成填充第1子通孔811的牺牲层73。示例地，在第1子通孔811中沉积氧化硅等低介电常数材料以作为牺牲层73。
继续参考图49-图50，图案化掩膜层71，以使掩膜层71具有N-1个开口72。具体地，可以再次旋涂光刻胶层，并对光刻胶层进行光刻，以形成开口72。
参考图51-图52，沿着开口72刻蚀牺牲层73和第二层的隔离层14，从而形成了第N-1个第2子通孔821，其中一个第2子通孔821作为第2通孔82。
参考图53-图54，重复形成牺牲层73、图案化掩膜层71以及刻蚀的步骤， 直至露出第N平行信号线3的侧壁，即露出第N层刻蚀阻挡层的顶面。
至此，基于图49-图54，可以形成通孔8，通孔8包括第1通孔8至第N通孔8。示例地，参考图53-图54，可以形成第1通孔81、第2通孔82、第3通孔83、第4通孔84和第5通孔85。在需要说明的是，在第一方向X上，依次排布的第1通孔81、第2通孔82、第3通孔83、第4通孔84和第5通孔85的深度依次递增。在其他实施例中，在第一方向X上，依次排布的第1通孔81、第2通孔82、第3通孔83、第4通孔84和第5通孔85的深度可不递增或递减，而是深浅交替，从而避免后续形成的引线柱5中，深度大的引线柱5之间的寄生电容过大。
需要说明的是，在平行信号线3为字线WL时，形成通孔8的步骤与前述步骤相似，主要区别在于，刻蚀位于相邻存储单元组TC0之间的绝缘层12以形成通孔8。其他有关形成掩膜层71和形成牺牲层73等步骤可参考前述详细说明。
参考图55-图56，在第1通孔81至第N通孔的底部分别形成第1接触部至第N接触部，第1接触部至第N接触部分别与第1平行信号至第N平行信号线3同层设置，且接触部51覆盖对应层的平行信号线3的侧壁。
继续参考图55-图56，形成接触部51后，在通孔8的侧壁形成介质层6。示例地，通过化学气相沉积工艺在通孔8的侧壁和接触部51的表面形成初始介质层；去除位于接触部51表面的初始介质层，位于通孔8侧壁的初始介质层作为介质层6。
继续参考图55-图56，形成填充通孔8的延伸部52，接触部51与延伸部52构成引线柱5。示例地，在通孔8中沉积铜、铝、钛或钨等金属以作为引线柱5。
需要说明的是，上述形成引线柱5的方法仅为示例性说明，而不限于此，可以根据引线柱5的具体结构对引线柱5的方法进行调整。
如图57-图60所示，本公开又一实施例提供一种半导体结构的制造方法。此半导体结构的制造方法与前述半导体结构的制造方法大致相同，相同或相似的部分请参考前述实施例的详细说明。为了便于描述以及清晰地示意出半导体结构制作方法的步骤，图57至图60均为半导体结构的局部结构示意图。以下将结合附图对半导体结构的制造方法进行详细说明。
提供基底；在基底上形成堆叠结构，堆叠结构包括在第一方向X排列的多个存储单元组TC0，存储单元组TC0包括多层在第二方向Z排列的多个存储单元TC；堆叠结构还包括在第二方向Z排列的多条平行信号线3，每条平行信号线3连接一层存储单元TC。
有关堆叠结构的形成方法可参考前述实施例的详细说明。
参考图57-图60，形成在第一方向X排列且沿第二方向Z延伸的多个引线柱5，多个引线柱5在基底表面的正投影与平行信号线3在基底表面的正投影至少部分重叠，且引线柱5与平行信号线3连接。
以下将对引线柱5的制造方法进行详细说明。
首先需要说明的是，多条平行信号线3包括在第二方向Z上依次排布的第1平行信号线至第N平行信号线，N为大于1的正整数。第1平行信号线位于顶层，第N平行信号线位于底层。
参考图57-图58，形成通孔8，通孔8包括第1通孔81至第N通孔，第1通孔81的露出第1平行信号线的顶面；第N通孔贯穿第1平行信号线至第N-1平行信号线，且露出第N平行信号线的顶面。
形成通孔8的步骤与前述实施例大致相同，主要区别在于，通孔8贯穿平行信号线3，因此，需刻蚀平行信号线3。此外，若引线柱5利用存储单元组TC0的位置，则形成通孔8时还需刻蚀沟道区22以及位于上下层存储单元TC之间的绝缘 层12；若引线柱5利用相邻存储单元组TC0之间的位置，则形成通孔8时还需刻蚀相邻存储单元TC之间的绝缘层12。其他有关形成掩膜层71和形成牺牲层73的步骤可参考前述实施例中的详细说明。
参考图59-图60，在通孔8的侧壁形成介质层6。具体地，在通孔8的内壁形成初始介质层，去除位于通孔8底壁的初始介质层，以露出对应层的平行信号线3，位于通孔8侧壁的初始介质层作为介质层6。形成填充通孔8的引线柱5，引线柱5的底面与平行信号线3电连接。
综上，在本公开实施例中，刻蚀平行信号线3以形成通孔8，形成填充通孔8的介质层6和引线柱5。如此，引线柱5可以利用平行信号线3的空间位置，直接与平行信号线3实现电连接，从而可以减少台阶数目或者不形成单独的台阶区，进而有利于提高半导体结构的集成度。
本公开实施例还提供一种存储芯片，包括前述实施例提供的半导体结构。
存储芯片是用来存储程序和各种数据信息的记忆部件。示例地，存储芯片可以为随机存取存储芯片或只读存储芯片，举例而言，随机存取存储芯片可以包括动态随机存取存储器或静态随机存储器。由于前述半导体结构的集成度较高，从而有利于实现存储芯片的微型化。
本公开实施例还提供一种电子设备，包括前述实施例提供的存储芯片。
示例地，电子设备可以为电视、电脑、手机或平板等设备。电子设备可以包括电路板和封装结构，存储芯片可焊接于电路板上，并受到封装结构的保护。此外，电子设备还可以包括电源，用于向存储芯片提供工作电压。
在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型，故但凡依本公开的权利要求和说明书所做的变化或修饰，皆应属于本公开专利涵盖的范围之内。

Claims (36)

  1. 一种半导体结构，包括：基底，所述基底上具有堆叠结构，所述堆叠结构包括在第一方向排列的多个存储单元组，所述存储单元组包括多层在第二方向排列的多个存储单元；
    所述堆叠结构还包括在所述第二方向排列的多条平行信号线，每条所述平行信号线连接一层所述存储单元；
    在所述第一方向排列的多个引线柱，所述多个引线柱与所述多条平行信号线沿第三方向排布，且所述引线柱与所述平行信号线连接。
  2. 根据权利要求1所述的半导体结构，其中，
    每条所述平行信号线至少与一个所述引线柱连接。
  3. 根据权利要求2所述的半导体结构，其中，
    多条所述平行信号线与多个所述引线柱一一对应连接。
  4. 根据权利要求1所述的半导体结构，其中，
    所述引线柱在所述第二方向延伸。
  5. 根据权利要求1所述的半导体结构，其中，与不同所述平行信号线连接的所述引线柱在所述第二方向上的长度不同，且所述引线柱的底部与所述平行信号线相连。
  6. 根据权利要求1所述的半导体结构，其中，相邻所述引线柱等在所述第一方向上等间距排布；或者，
    相邻所述引线柱的间距与正对面积成正比。
  7. 根据权利要求1所述的半导体结构，其中，所述堆叠结构还包括：
    在所述第二方向排列的多层刻蚀阻挡层；每层刻蚀阻挡层与至少一个所述引线柱的底面相接。
  8. 根据权利要求1所述的半导体结构，其中，所述堆叠结构还包括：介质层，至少位于所述引线柱朝向所述平行信号线的侧壁，且所述介质层的下表面高于与所述引线柱相连的所述平行信号线。
  9. 根据权利要求1所述的半导体结构，其中，所述存储单元包括在所述第三方向排列的沟道区和源漏掺杂区，所述源漏掺杂区位于所述沟道区的两侧。
  10. 根据权利要求9所述的半导体结构，其中，所述平行信号线为位线，所述位线与所述源漏掺杂区相连。
  11. 根据权利要求10所述的半导体结构，其中，所述引线柱和所述存储单元分别位于所述平行信号线在所述第三方向排列的相对两侧。
  12. 根据权利要求11所述的半导体结构，其中，所述引线柱在所述第一方向上的宽度大于或等于存储单元组的宽度；和/或，
    所述引线柱的在所述第一方向上的宽度大于或等于相邻所述存储单元组的间距；和/或，
    所述引线柱在所述第一方向上的宽度大于所述引线柱在所述第三方向上的宽度。
  13. 根据权利要求11所述的半导体结构，其中，所述引线柱与所述存储单元组在所述第三方向上正对；或者，
    所述引线柱与所述存储单元组在所述第一方向上交错排列。
  14. 根据权利要求10所述的半导体结构，其中，所述引线柱和所述存储单元位于所述平行信号线的同一侧。
  15. 根据权利要求14所述的半导体结构，其中，所述引线柱在所述第三方向上的宽度大于所述引线柱在所述第一方向上的宽度。
  16. 根据权利要求10所述的半导体结构，其中，相邻两个堆叠结构的所述平行信号线相向设置，所述引线柱位于相邻所述堆叠结构的所述平行信号线之间，且相邻所述堆叠结构的同一层的所述平行信号线至少通过一个所述引线柱电连接。
  17. 根据权利要求10所述的半导体结构，其中，所述存储单元组的每层所述存储单元的数量为两个，且两个所述存储单元分别位于所述平行信号线在所述第三方向排列的相对两侧。
  18. 根据权利要求17所述的半导体结构，其中，相邻所述引线柱位于所述平行信号线的不同侧；或者，
    所有所述引线柱位于所述平行信号线的同一侧。
  19. 根据权利要求9所述的半导体结构，其中，所述平行信号线为字线，所述字线与所述沟道区相连。
  20. 根据权利要求19所述的半导体结构，其中，相邻所述引线柱位于所述平行信号线的不同侧；或者，
    所有所述引线柱位于所述平行信号线的同一侧。
  21. 一种半导体结构，包括：基底，所述基底上具有堆叠结构，所述堆叠结构包括在第一方向排列的多个存储单元组，所述存储单元组包括多层在第二方向排列的多个存储单元；
    所述堆叠结构还包括在所述第二方向排列的多条平行信号线，每条所述平行信号线连接一层所述存储单元；
    在所述第一方向排列且沿第二方向延伸的多个引线柱，所述多个引线柱在基底表面的正投影与平行信号线在基底表面的正投影至少部分重叠，且所述引线柱与所述平行信号线连接。
  22. 根据权利要求21所述的半导体结构，其中，
    至少一个所述引线柱贯穿至少一个所述平行信号线。
  23. 根据权利要求21所述的半导体结构，其中，
    所述平行信号线包括在第三方向排列的接触区和暴露区；所述引线柱与所述接触区相连；所述第三方向垂直于所述第二方向且平行于所述基底表面。
  24. 根据权利要求23所述的半导体结构，其中，
    所述平行信号线具有在所述第三方向排列的相对两侧，所述暴露区位于所述相对两侧中的一侧，所述接触区位于所述相对两侧中的另一侧，所述引线柱相对于所述接触区凸出设置。
  25. 根据权利要求21所述的半导体结构，其中，所述存储单元包括在第三方向排列的沟道区和源漏掺杂区，所述源漏掺杂区位于所述沟道区的两侧。
  26. 根据权利要求25所述的半导体结构，其中，所述平行信号线为位线，且所述位线与所述源漏掺杂区相连。
  27. 根据权利要求26所述的半导体结构，其中，
    所述引线柱与所述存储单元组在所述第三方向上正对；或者，
    所述引线柱与所述存储单元在所述第一方向上交错排列。
  28. 根据权利要求25所述的半导体结构，其中，所述平行信号线为字线，且所述字线与所述沟道区相连。
  29. 根据权利要求28所述的半导体结构，其中，
    所述引线柱位于相邻所述存储单元组之间；或者，
    所述引线柱在所述基底表面的正投影与所述沟道区在所述基底表面的正投影具有重叠。
  30. 根据权利要求21所述的半导体结构，其中，所述平行信号线具有在第三方 向排列的相对两侧；所述存储单元组的每层所述存储单元的数量为两个，且两个所述存储单元分别位于所述平行信号线的在所述第三方向排列的相对两侧。
  31. 一种半导体结构的制造方法，包括：
    提供基底；
    在所述基底上形成堆叠结构，所述堆叠结构包括在第一方向排列的多个存储单元组，所述存储单元组包括多层在第二方向排列的多个存储单元；所述堆叠结构还包括在第二方向排列的多条平行信号线，每条所述平行信号线连接一层所述存储单元；
    形成在第一方向排列的多个引线柱，所述多个引线柱与所述多条平行信号线沿第三方向排布，且所述引线柱与所述平行信号线连接。
  32. 根据权利要求31所述的半导体结构的制造方法，其中，多条所述平行信号线包括在所述第二方向上依次排布的第1平行信号线至第N平行信号线，N为大于1的正整数；
    所述制造方法包括：
    形成第1通孔至第N通孔，所述第1通孔的露出所述第1平行信号线的侧壁；所述第N通孔露出所述第1平行信号线至第N平行信号线的侧壁；
    在所述第1通孔至第N通孔的底部分别形成第1接触部至第N接触部，所述第1接触部至所述第N接触部分别覆盖所述第1平行信号至所述第N平行信号线的侧壁；
    形成所述接触部后，在所述通孔的侧壁形成介质层；
    形成填充所述通孔的延伸部，所述接触部与所述延伸部构成所述引线柱。
  33. 一种半导体结构的制造方法，包括：
    提供基底；
    在所述基底上形成堆叠结构，所述堆叠结构包括在第一方向排列的多个存储单元组，所述存储单元组包括多层在第二方向排列的多个存储单元；所述堆叠结构还包括在第二方向排列的多条平行信号线，每条所述平行信号线连接一层所述存储单元；
    形成在所述第一方向排列且沿第二方向延伸的多个引线柱，所述多个引线柱在基底表面的正投影与平行信号线在基底表面的正投影至少部分重叠，且所述引线柱与所述平行信号线连接。
  34. 根据权利要求33所述的半导体结构的制造方法，其中，多条所述平行信号线包括在所述第二方向上依次排布的第1平行信号线至第N平行信号线，N为大于1的正整数；
    所述制造方法包括：
    形成第1通孔至第N通孔，所述第1通孔的露出所述第1平行信号线的顶面；所述第N通孔贯穿所述第1平行信号线至第N-1平行信号线，且露出所述第N平行信号线的顶面；
    在所述通孔的侧壁形成介质层；
    形成填充所述通孔的所述引线柱。
  35. 一种存储芯片，包括如权利要求1-20及权利要求21-30中任一项所述的半导体结构。
  36. 一种电子设备，包括权利要求35所述的存储芯片。
PCT/CN2022/109526 2022-06-21 2022-08-01 半导体结构及其制造方法、存储芯片、电子设备 WO2023245817A1 (zh)

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