WO2023151133A1 - 存储单元结构、存储阵列结构、半导体结构及其制备方法 - Google Patents

存储单元结构、存储阵列结构、半导体结构及其制备方法 Download PDF

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WO2023151133A1
WO2023151133A1 PCT/CN2022/077731 CN2022077731W WO2023151133A1 WO 2023151133 A1 WO2023151133 A1 WO 2023151133A1 CN 2022077731 W CN2022077731 W CN 2022077731W WO 2023151133 A1 WO2023151133 A1 WO 2023151133A1
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layer
dielectric layer
word line
line structure
covers
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PCT/CN2022/077731
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English (en)
French (fr)
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邵光速
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长鑫存储技术有限公司
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Priority to US17/824,905 priority Critical patent/US20230262964A1/en
Publication of WO2023151133A1 publication Critical patent/WO2023151133A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, in particular to a memory cell structure, a memory array structure, a semiconductor structure and a preparation method thereof.
  • Non-planar structure of the device has been difficult to meet the requirements of circuit design, so non-planar structure of the device came into being.
  • Devices with non-planar structures include silicon on insulator (SOI, Silicon On Insulator), double gate, multi-gate, nanowire field effect transistor and three-dimensional DRAM structure.
  • the traditional three-dimensional DRAM manufacturing process can stack multi-layer DRAMs, the height of a single layer is relatively large, resulting in a low DRAM density.
  • a memory cell structure a memory array structure, a semiconductor structure and a manufacturing method thereof are provided.
  • the first aspect of the present application provides a memory cell structure, including: a substrate, an active region, a word line structure, an insulating dielectric layer, and a capacitor structure, wherein the substrate has a bit line structure; the active region Located on the bit line structure, in a direction perpendicular to the substrate, the active region includes a first connection end, a second connection end away from the first connection end, and a trench between the first connection end and the second connection end In the channel area, the first connection end is electrically connected to the bit line structure; the word line structure covers the sidewall of the channel area in a direction perpendicular to the substrate; the insulating medium layer covers the word line structure and the first connection end and the second connection The outer side of the end; the capacitance structure covers the outer side of the insulating medium layer, and covers the top surface of the insulating medium layer and the top surface of the second connection end, and the capacitance structure is electrically connected to the second connection end.
  • the word line structure includes a word line dielectric layer and a word line conductive layer located outside the word line dielectric layer.
  • the insulating medium layer includes a connecting terminal dielectric layer and a word line structure insulating layer, the connecting terminal dielectric layer covers the first connecting terminal and the second connecting terminal, and the word line structure insulating layer covers the word line structure.
  • the capacitor structure includes an upper electrode, a lower electrode and a capacitor dielectric layer; the lower electrode covers the outer side of the insulating dielectric layer, and covers the top surface of the insulating dielectric layer and the top surface of the second connection end, the lower electrode and the second The connecting ends are electrically connected; the capacitor medium layer covers the surface of the lower electrode; the upper electrode covers the surface of the capacitor medium layer.
  • the active region includes an InGaZnO layer.
  • the second aspect of the present application discloses a memory array structure, including: a plurality of memory cell structures in any of the foregoing embodiments, the memory cell structures are arranged in an array of multiple rows and multiple columns; The bit line structures of the memory cell structures in the row are electrically connected to each other; the word line structures of the memory cell structures in the same column are electrically connected to each other; the capacitor structure of each memory cell structure includes upper electrodes, capacitors, The dielectric layer and the lower electrode, the upper electrodes of each capacitor structure are connected to each other, the capacitor dielectric layers of each capacitor structure are connected to each other, and the lower electrodes of each capacitor structure are separated by the capacitor dielectric layer.
  • an active area dielectric layer is included between the storage unit structures in the same column, and the active areas of the storage unit structures in the same column are separated by the active area dielectric layer.
  • the third aspect of the present application discloses a semiconductor structure, which includes multiple layers of the storage array structure in any of the above-mentioned embodiments, each layer of storage array structures is stacked up and down, and there is an interlayer between adjacent storage array structures. Isolation layer; wherein, the word line structure, the bit line structure and the capacitance structure between the storage array structures of each layer are independent of each other.
  • the fourth aspect of the present application discloses a method for fabricating a memory array structure, including: providing a substrate; forming a plurality of bit line structures extending along the first direction in the substrate; forming spacers on the substrate
  • the active area is arranged on the bit line structure, and in the direction perpendicular to the substrate, the active area includes a first connection end, a second connection end far away from the first connection end, and a second connection end located at the first connection end.
  • the channel region between the terminal and the second connection terminal, the first connection terminal is electrically connected to the bit line structure; between the active regions extending along the second direction, the active region isolating adjacent active regions in the second direction is formed Dielectric layer in the active area; an insulating dielectric layer is formed outside the exposed first connection end and second connection end of the active area, and a word line structure is formed outside the channel area exposed in the active area; a capacitance structure is formed, and the capacitance structure covers The outer side of the insulating medium layer covers the top surface of the insulating medium layer and the top surface of the second connection end, and the capacitor structure is electrically connected to the second connection end.
  • forming active regions arranged at intervals on the substrate includes: forming an active region material layer on the upper surface of the substrate; forming several active region material layers along the first direction in the active region material layer.
  • the active area dielectric layer is extended and arranged at intervals, and the active area dielectric layer is located between adjacent bit line structures; several isolation trenches extending along the second direction and arranged at intervals are formed in the active area material layer , the isolation trench cuts the active area material layer and the active area dielectric layer along the second direction; wherein, the isolation trench exposes part of the upper surface of the bit line structure; the active area material layer between adjacent isolation trenches form the active region.
  • an insulating dielectric layer is formed outside the exposed first connection end and the second connection end of the active region, and a word line structure is formed outside the channel region exposed in the active region, including: A connection terminal dielectric layer is formed on opposite sides, and the connection terminal dielectric layer covers the first connection terminal, the second connection terminal and the sidewall of the channel region; a word line structure is formed in the middle of the connection terminal dielectric layer, and the word line structure covers the channel The side wall of the region; the word line structure insulating layer is formed to cover the outer side of the word line structure, and the word line structure insulating layer and the connection terminal dielectric layer together form an insulating dielectric layer.
  • the word line structure is formed in the middle of the connection terminal dielectric layer, and the word line structure covers the sidewall of the channel region, including: forming a sacrificial layer, and the sacrificial layer fills the isolation trench; removing part of the connection terminal dielectric layer , to expose the second connection end of the active region and the channel region; form a word line dielectric layer to at least cover the sidewall of the channel region, the thickness of the word line dielectric layer is less than the thickness of the connection end dielectric layer; on the word line A word line conductive layer is formed outside the dielectric layer, and the top of the word line conductive layer is lower than the top of the active area; a connection terminal dielectric layer is formed on the top of the word line conductive layer to cover the side wall of the second connection terminal.
  • the method further includes: forming an insulating layer of the bit line structure at the bottom of the isolation trench to cover the exposed part of the upper surface of the bit line structure.
  • forming the capacitor structure includes: forming a lower electrode material layer, the lower electrode material layer covers the upper surface of the insulating layer of the bit line structure, the top surface of the second connection terminal, and the outer side and the top surface of the insulating medium layer; Disconnecting the material layer of the lower electrode along the first direction and the second direction to obtain a plurality of lower electrodes arranged in arrays, the lower electrodes correspond to the active regions one by one; forming a capacitive dielectric layer to cover the surface of the obtained structure; forming an upper electrode , the upper electrode covers the surface of the capacitor dielectric layer and fills up the isolation trench.
  • the fifth aspect of the present application discloses a method for preparing a semiconductor structure, including: using the method in any of the above embodiments to prepare multiple memory array structures; stacking memory array structures sequentially from bottom to top to obtain a semiconductor structure with A semiconductor structure of a multilayer memory array structure.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the above-mentioned memory cell structure has a ring channel capacitor structure, and the capacitor structure covers the outside of the active region and the word line structure, which reduces the occupied area and height of the memory cell structure, increases the size of the memory cell structure, and reduces the cost of the manufacturing process. difficulty. Since the height of a single memory cell structure is reduced, the density of the memory structure can be increased when the above memory cell structure is used to prepare a multi-layer memory structure.
  • the active area is made of indium gallium zinc oxide layer. Compared with traditional active area materials, indium gallium zinc oxide can drive a large amount of current, write faster, and when they are turned off, the leakage current is lower, which makes the bit last longer.
  • the above-mentioned memory array structure includes the memory cell structures in the above-mentioned embodiments. With the help of the ring channel capacitance structure, the layer height of the memory array structure is lower. When stacking a multi-layer memory array structure, the number of stacked layers can be increased. , to increase the density of the memory cell structure.
  • the above-mentioned semiconductor structure has a multi-layer memory array structure, and the height of the single-layer memory array structure is reduced by using the ring channel capacitor structure, which can increase the number of stacked layers, thereby increasing the storage density.
  • the preparation method of the above memory array structure can surround the capacitor structure outside the active region and the word line structure, which reduces the occupied area and height of a single memory cell structure and increases the storage density; in addition, the size of the memory array structure can also be increased , to reduce the difficulty of the process.
  • FIG. 1 is a schematic cross-sectional structure diagram of a memory cell structure in an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structure diagram of a memory array structure in an embodiment of the present application.
  • FIG. 3 is a schematic cross-sectional structure diagram of a semiconductor structure in an embodiment of the present application.
  • FIG. 4 is a flowchart of a method for preparing a memory array structure in an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a three-dimensional structure of a substrate in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a three-dimensional structure after bit line trenches are formed in an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a three-dimensional structure after forming a bit line structure in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a three-dimensional structure after forming an active region material layer in an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a three-dimensional structure after forming a dielectric layer in an active region in an embodiment of the present application.
  • Figure 10a is a schematic diagram of a three-dimensional structure after forming an isolation trench in an embodiment of the present application
  • Figure 10b is a schematic diagram of a cross-sectional structure along the direction AA' in Figure 10a
  • Figure 10c is a schematic diagram of a cross-sectional structure along the direction BB' in Figure 10a.
  • FIG. 11 is a schematic diagram of a cross-sectional structure after forming a dielectric layer at a connection end in an embodiment of the present application.
  • FIG. 12-FIG. 16 are schematic diagrams of the process of forming the word line structure in the dielectric layer at the connection end in an embodiment of the present application.
  • FIG. 17 is a schematic diagram of a cross-sectional structure after forming an insulating layer of a word line structure in an embodiment of the present application.
  • FIG. 18 is a schematic cross-sectional structure diagram after forming a word line structure insulating layer and a bit line structure insulating layer in an embodiment of the present application.
  • FIG. 19 is a schematic diagram of a cross-sectional structure after forming a bottom electrode material layer in an embodiment of the present application.
  • FIG. 20 is a schematic diagram of a cross-sectional structure after forming a mask layer in an embodiment of the present application.
  • FIG. 21 is a top view of a patterned photoresist layer in an embodiment of the present application.
  • FIG. 22 is a schematic diagram of a cross-sectional structure after etching a lower electrode in an embodiment of the present application.
  • FIG. 23 is a schematic diagram of a cross-sectional structure after forming a capacitive dielectric layer in an embodiment of the present application.
  • FIG. 24 is a schematic diagram of a cross-sectional structure after forming an upper electrode in an embodiment of the present application.
  • connection or “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integrated Connection; it can be a direct connection, or an indirect connection through an intermediary, or an internal connection between two components.
  • connection or “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integrated Connection; it can be a direct connection, or an indirect connection through an intermediary, or an internal connection between two components.
  • an embodiment of the present application discloses a memory cell structure, including: a substrate 10 with a bit line structure 63 therein; an active region 20 located at the bit line structure 63 In the direction perpendicular to the substrate 10, the active region 20 includes a first connection terminal 21, a second connection terminal 22 away from the first connection terminal 21, and a Between the channel region 23, the first connection end 21 is electrically connected to the bit line structure 63; the word line structure 30, in the direction perpendicular to the substrate 10, the word line structure 30 covers the sidewall of the channel region 23; the insulation Dielectric layer 40, the insulating dielectric layer 40 covers the outer side of the word line structure 30 and the first connection end 21 and the second connection end 22; Capacitor structure 50, the capacitance structure 50 covers the outer side of the insulating dielectric layer 40, and covers the outer side of the insulating dielectric layer 40 The top surface is electrically connected to the top surface of the second connection end 22 , and the capacitor structure 50 is electrically connected to the second connection end 22
  • the substrate 10 may include a base 11 and a base dielectric layer 12 on the surface of the base 11 , wherein the base 11 may include but not limited to a silicon base, a silicon carbide base or other bases.
  • the base dielectric layer 12 may include but not limited to a silicon oxide layer.
  • the bit line structure 63 is located in the base dielectric layer 12 .
  • the active region 20 is located above the bit line structure 63 , is in contact with the upper surface of the bit line structure 63 , and extends perpendicular to the direction of the substrate 10 .
  • the active region 20 includes a first connection end 21, a second connection end 22 away from the first connection end 21, and a channel region 23 between the first connection end 21 and the second connection end 22, the first connection end 21 It is electrically connected to the bit line structure 63 .
  • the active region 20 may include, but is not limited to, Indium Gallium Zinc Oxide (IGZO), which can drive a large amount of current and write faster than conventional active region materials, and when they are turned off , the leakage current is lower, which makes the bit duration longer.
  • IGZO Indium Gallium Zinc Oxide
  • the word line structure 30 covers the sidewall of the channel region 23 in a direction perpendicular to the substrate 10 .
  • the word line structure 30 may include a word line dielectric layer 31 and a word line conductive layer 32 located outside the word line dielectric layer 31 .
  • the word line dielectric layer 31 may be a gate oxide layer, such as a silicon oxide layer.
  • the word line dielectric layer 31 may only cover the outside of the channel region 23 , or may cover the outside of the channel region 23 and the second connection end 22 .
  • the word line conductive layer 32 may be a metal layer (such as metal copper), located outside the word line dielectric layer 31 and corresponding to the position of the channel region 23 .
  • the insulating dielectric layer 40 covers the outer sides of the word line structure 30 and the first connecting end 21 and the second connecting end 22 .
  • the insulating dielectric layer 40 may include a connecting terminal dielectric layer 41 and a word line structure insulating layer 42 .
  • the connection end dielectric layer 41 covers the outside of the first connection end 21 and the second connection end 22 .
  • the word line structure insulating layer 42 covers at least the outer side of the word line conductive layer 32 .
  • the insulating layer 42 of the word line structure may also cover the outer side of the dielectric layer 41 at the connection end.
  • the connection terminal dielectric layer 41 may be a silicon nitride layer
  • the word line structure insulating layer 42 may be a silicon oxide layer.
  • the capacitor structure 50 covers the outer side of the insulating medium layer 40 and covers the top surface of the insulating medium layer 40 and the top surface of the second connecting terminal 22 , and the capacitor structure 50 is electrically connected to the second connecting terminal 22 .
  • a bit line structure insulating layer 61 is further included between the capacitor structure 50 and the substrate 10 to separate the capacitor structure 50 from the bit line structure 63 .
  • the capacitive structure 50 includes an upper electrode 53, a lower electrode 51, and a capacitive dielectric layer 52; wherein, the lower electrode 51 covers the outer side of the insulating dielectric layer 40, and covers the top surface of the insulating dielectric layer 40 and the second capacitive dielectric layer.
  • the lower electrode 51 covers the outer side of the insulating dielectric layer 40, and covers the top surface of the insulating dielectric layer 40 and the second capacitive dielectric layer.
  • the lower electrode 51 is electrically connected to the second connection end 22 ;
  • the capacitor medium layer 52 covers the surface of the lower electrode 51 ;
  • the upper electrode 53 covers the surface of the capacitor medium layer 52 .
  • the above storage unit structure may be a DRAM storage unit structure.
  • the above-mentioned memory cell structure has a ring channel capacitor structure, and the capacitor structure covers the outside of the active region and the word line structure, which reduces the occupied area and height of the memory cell structure, increases the size of the memory cell structure, and reduces the cost of the manufacturing process. difficulty. Since the height of a single memory cell structure is reduced, the density of the memory structure can be increased when the above memory cell structure is used to prepare a multi-layer memory structure.
  • an embodiment of the present application also discloses a storage array structure, including: a plurality of storage unit structures in any of the above-mentioned embodiments, and the storage unit structures are arranged in an array of multiple rows and multiple columns; wherein , the bit line structures 63 of the memory cell structures in the same row are electrically connected to each other; the word line structures 30 of the memory cell structures in the same column are electrically connected to each other; The upper electrode 53, the capacitor dielectric layer 52 and the lower electrode 51 are arranged, the upper electrodes 53 of each capacitor structure 50 are connected to each other, the capacitor dielectric layers 52 of each capacitor structure 50 are connected to each other, and the lower electrodes 51 of each capacitor structure 50 are connected by a capacitor The dielectric layer 52 separates them.
  • bit line structures 63 of the memory cell structures in the same row are electrically connected to each other and extend along a first direction, which is the row direction of the memory array structure.
  • the memory array structure further includes a bit line structure insulating layer 61 located on the upper surface of the bit line structure 63 to separate the capacitor structure 50 from the bit line structure 63 .
  • the word line structures 30 of the memory cell structures in the same column are electrically connected to each other and extend along a second direction, the second direction being the column direction of the memory array structure.
  • an active area dielectric layer (not shown in the figure) is included between each memory cell structure in the same column, and the active area 20 of each memory cell structure in the same column is separated by the active area dielectric layer.
  • the dielectric layer in the active area and the active area 20 are alternately arranged in the second direction.
  • the capacitor structure 50 in each memory cell structure includes an upper electrode 53, a capacitor dielectric layer 52, and a lower electrode 51 stacked in sequence from top to bottom, wherein the upper electrodes 53 of each capacitor structure 50 are connected to each other, and the capacitance of each capacitor structure 50
  • the dielectric layers 52 are connected to each other, and the lower electrodes 51 of each capacitive structure 50 are separated by the capacitive dielectric layer 52 , thereby forming mutually independent memory cell structures.
  • the above-mentioned memory array structure includes a plurality of memory cell structures arranged in an array. With the help of the ring channel capacitor structure, the layer height of the memory array structure is lower. When stacking a multi-layer memory array structure, the number of stacked layers can be increased. Increase the density of the memory cell structure.
  • An embodiment of the present application also discloses a semiconductor structure, comprising multiple layers of the storage array structure in any of the above-mentioned embodiments, each layer of storage array structures is stacked up and down, and an isolation layer is provided between adjacent storage array structures; Wherein, the word line structure 30, the bit line structure 63 and the capacitor structure 50 among the storage array structures of each layer are independent of each other.
  • FIG. 3 shows a semiconductor structure with a two-layer memory array structure.
  • the base dielectric layer 12 of each storage array structure includes bit line structures 63 arranged in parallel at intervals, and the arrangements and connections of the bit line structures 63, word line structures 30, and capacitor structures 50 can refer to the foregoing embodiments, and are not described herein. Let me repeat. For example, the number of layers of the storage array structure can be increased according to requirements.
  • the above-mentioned semiconductor structure has a multi-layer memory array structure, and the ring channel capacitor structure is used to reduce the height of the single-layer memory array structure, and the number of stacked layers can be larger, thereby increasing the memory density.
  • an embodiment of the present application provides a method for preparing a memory array structure, including:
  • S30 Form active regions arranged at intervals on the substrate, the active regions are located on the bit line structure, and in a direction perpendicular to the substrate, the active regions include a first A connection end, a second connection end away from the first connection end, and a channel region between the first connection end and the second connection end, the first connection end is electrically connected to the bit line structure connecting; forming an active region dielectric layer that isolates adjacent active regions in the second direction between the active regions extending along the second direction;
  • S40 Form an insulating dielectric layer outside the first connection end and the second connection end exposed in the active region, and form a word line structure outside the channel region exposed in the active region;
  • S50 forming a capacitor structure, the capacitor structure covers the outer side of the insulating medium layer, and covers the top surface of the insulating medium layer and the top surface of the second connection end, and the capacitor structure is electrically connected to the second connection end.
  • the capacitor structure can be covered outside the active region and the word line structure, reducing the occupied area and height of a single memory cell structure, and increasing the storage density; in addition, the memory array structure can also be increased size, reducing the difficulty of the process.
  • the provided substrate 10 may include a base 11 and a base dielectric layer 12 on the surface of the base 11 , as shown in FIG. 5 .
  • the substrate 11 may include but not limited to a silicon substrate 11 , a silicon carbide substrate 11 or other substrates 11 .
  • the base dielectric layer 12 may include but not limited to a silicon oxide layer.
  • step S20 referring to step S20 in FIG. 4 and FIGS. 6 to 7 , a plurality of bit line structures 63 extending along the first direction are formed in the substrate 10 .
  • the base dielectric layer 12 may be etched first to form bit line trenches 62 extending along the first direction in the base dielectric layer 12 , and the bit line trenches 62 are arranged in parallel and at intervals.
  • the process for forming the bit line trench 62 may be a dry etching process or a wet etching process.
  • bit line trench 62 After the bit line trench 62 is formed, a metal layer is deposited in the bit line trench 62 to form the bit line structure 63 .
  • the top surface of the bit line structure 63 is flush with the top surface of the substrate 10 , as shown in FIG. 7 .
  • the material forming the metal layer may include but not limited to metal copper.
  • step S30 referring to step S30 in FIG. 4 and FIG. 8 to FIG. 17, the step of forming active regions 20 arranged at intervals on the substrate 10 includes:
  • an indium gallium zinc oxide layer can be deposited on the surface of the substrate 10 as the active region material layer 24.
  • indium gallium zinc oxide can drive a large amount of current, and the writing speed is faster , and when they are off, the leakage current is lower, which makes the bit last longer.
  • the active region material layer 24 may be formed in several shallow trench isolation structures arranged in parallel and at intervals, and then a silicon oxide layer is filled in the shallow trench isolation structures to form the active region dielectric Layer 25.
  • the active region dielectric layer 25 is located between adjacent bit line structures 63 .
  • the width of the dielectric layer 25 in the active region is equal to the width of the space between the bit line structures 63 .
  • Fig. 10b is a schematic cross-sectional view of the structure shown in Fig. 10a along the direction AA' (first direction)
  • Fig. 10c is a schematic cross-sectional view of the structure shown in Fig. 10a along the direction BB' (second direction).
  • an etching process may be used to form several isolation trenches 26 arranged at intervals in the active region material layer 24 along the second direction, and the isolation trenches 26 cut the active region material layer 24 and the active region material layer 24 along the second direction.
  • the dielectric layer 25 in the source region is shown in FIG. 10a.
  • Part of the upper surface of the bit line structure 63 is exposed by the isolation trench 26, as shown in FIG. 10b.
  • the active region material layer 24 between adjacent isolation trenches 26 forms the active region 20, and the active region 20 and the active region dielectric layer 25 are alternately arranged in the second direction, as shown in FIG. 10c.
  • the active region 20 includes a first connection end 21 , a second connection end 22 away from the first connection end 21 , and a channel region 23 between the first connection end 21 and the second connection end 22 .
  • step S40 referring to step S40 in FIG. 4 and FIG. 11 to FIG. 17, the step of forming an insulating dielectric layer and a word line structure may include:
  • connection terminal dielectric layer 41 Form a connection terminal dielectric layer 41 on opposite sides of the active region 20 , and the connection terminal dielectric layer 41 covers the sidewalls of the first connection terminal 21 , the second connection terminal 22 and the channel region 23 , as shown in FIG. 11 .
  • a silicon nitride layer can be deposited on the sidewall of the active region 20 to form the connection terminal dielectric layer 41 .
  • the top of the connection terminal dielectric layer 41 is flush with the top of the active region 20 to completely cover the sidewalls of the first connection terminal 21 , the second connection terminal 22 and the channel region 23 of the active region 20 .
  • the process of depositing the silicon nitride layer may include an atomic layer deposition process, a plasma deposition process, a chemical vapor deposition process or a physical vapor deposition process.
  • S42 Form a word line structure 30 in the middle of the connection end dielectric layer 41 , and the word line structure 30 covers the sidewall of the channel region 23 .
  • the steps of forming the word line structure 30 include:
  • S421 Form a sacrificial layer 27, and the sacrificial layer 27 fills up the isolation trench 26, as shown in FIG. 12 .
  • a silicon oxide layer may be filled in the isolation trench 26 as the sacrificial layer 27 , and the top of the silicon oxide layer is flush with the top of the active region 20 .
  • S422 Remove part of the connection terminal dielectric layer 41 to expose the second connection terminal 22 and the channel region 23 of the active region 20, as shown in FIG. 13 .
  • connection terminal dielectric layer 41 can be etched with a gas having a higher etching selectivity to the silicon nitride layer to remove part of the connection terminal dielectric layer 41 to obtain the structure shown in FIG. 13 , and the active region 20 The second connection terminal 22 and the channel region 23 are exposed.
  • S423 Form a word line dielectric layer 31 to at least cover the sidewall of the channel region 23 , the thickness of the word line dielectric layer 31 is smaller than the thickness of the connection end dielectric layer 41 , as shown in FIG. 14 .
  • an atomic layer deposition (ALD) process may be used to deposit a silicon oxide layer on the sidewall of the channel region 23 to obtain the word line dielectric layer 31 .
  • ALD atomic layer deposition
  • the thickness of the word line dielectric layer 31 is smaller than the thickness of the connection terminal dielectric layer 41 .
  • the word line dielectric layer 31 may also cover the sidewalls of the second connection end 22 and the channel region 23 at the same time, and the top of the word line dielectric layer 31 is flush with the top of the active region 20 .
  • metal or other conductive materials can be deposited between the word line dielectric layer 31 and the sacrificial layer 27 to form the word line conductive layer 32 .
  • the word line conductive layer 32 may be a copper layer.
  • the bottom of the word line conductive layer 32 is in contact with the connection terminal dielectric layer 41 , and the top of the word line conductive layer 32 is lower than the top of the active region 20 .
  • the word line conductive layer 32 and the word line dielectric layer 31 together form the word line structure 30 .
  • connection terminal dielectric layer 41 Form a connection terminal dielectric layer 41 on the top of the word line conductive layer 32 to cover the sidewall of the second connection terminal 22, as shown in FIG. 16 .
  • connection terminal dielectric layer 41 is deposited on the top of the word line conductive layer 32 to form a connection terminal dielectric layer 41 flush with the top of the active region 20, and the newly formed connection terminal dielectric layer 41 covers the second portion of the active region 20.
  • Connection terminal 22 is deposited on the top of the word line conductive layer 32 to form a connection terminal dielectric layer 41 flush with the top of the active region 20, and the newly formed connection terminal dielectric layer 41 covers the second portion of the active region 20.
  • Connection terminal 22 is deposited on the top of the word line conductive layer 32 to form a connection terminal dielectric layer 41 flush with the top of the active region 20, and the newly formed connection terminal dielectric layer 41 covers the second portion of the active region 20.
  • the sacrificial layer 27 may be removed first, and then an oxide layer is deposited on the outer sidewalls of the connection terminal dielectric layer 41 and the word line conductive layer 32 by atomic layer deposition (ALD) to form the word line structure insulating layer 42 .
  • ALD atomic layer deposition
  • the height of the insulating layer 42 of the word line structure is equal to the height of the active region 20 .
  • the word line structure insulating layer 42 and the connection terminal dielectric layer 41 together form the insulating dielectric layer 40 .
  • the word line structure insulating layer 42 after forming the word line structure insulating layer 42, it further includes: forming a bit line structure insulating layer 61 at the bottom of the isolation trench 26 to cover the exposed part of the upper surface of the bit line structure 63, as shown in FIG. 18 Show.
  • an oxide layer may be deposited on the bottom of the isolation trench 26 to cover the exposed upper surface of the bit line structure 63 to form the bit line structure insulating layer 61 .
  • step S50 please refer to step S50 in FIG. 4 and FIG. 19 to FIG. 24, the steps of forming the capacitor structure 50 include:
  • the bottom electrode material layer 511 may include but not limited to a tungsten layer, titanium nitride or other conductive layers.
  • S52 Cut the lower electrode material layer 511 along the first direction and the second direction respectively to obtain a plurality of lower electrodes 51 arranged in an array, and the lower electrodes 51 correspond to the active regions 20 one by one.
  • the step of forming the lower electrode 51 includes:
  • S521 Form a mask layer 54, and the mask layer 54 fills up the isolation trench 26, as shown in FIG. 20 .
  • the mask layer 54 may be a silicon oxide layer or a silicon oxynitride layer.
  • the mask layer 54 can be formed by atomic layer deposition, plasma deposition, chemical vapor deposition or physical vapor deposition.
  • the top of the mask layer 54 is flush with the top of the bottom electrode material layer 511 .
  • S522 Form a patterned photoresist layer 55 on the upper surface of the mask layer 54 , and etch the lower electrode material layer 511 based on the patterned photoresist layer 55 .
  • the patterned photoresist layer 55 can be used to define the positions in the lower electrode material layer 511 that need to be disconnected.
  • the top view of the patterned photoresist layer 55 is shown in FIG. 21 , and the lower electrode material layer 511 is etched based on the patterned photoresist layer 55 to remove the lower electrode material layer 511 exposed by the patterned photoresist layer 55 .
  • Seen from the first direction remove part of the lower electrode material layer 511 at the bottom of the isolation trench 26; Refer to FIG. 10a) for the position of the dielectric layer 25 in the region, so as to form several lower electrodes 51 arranged in an array, as shown in FIG. 22 .
  • the mask layer 54 can be completely removed first, and then the capacitive dielectric layer 52 is deposited on the upper surface of the obtained structure.
  • the material forming the upper electrode 53 may be the same as that of the lower electrode material layer 511 , for example, both are tungsten layer, titanium nitride layer or other conductive layers.
  • the present application also discloses a method for preparing a semiconductor structure, including: using the method in any of the foregoing embodiments to prepare multiple storage array structures; stacking the storage array structures sequentially from bottom to top to obtain a semiconductor with a multi-layer storage array structure structure.
  • an isolation layer is also provided between two adjacent storage array structures.
  • the word line structure 30, the bit line structure 63 and the capacitor structure 50 among the memory array structures of each layer are independent of each other.
  • the layer height of the single-layer memory array structure can be reduced, and the number of stacked layers can be increased, thereby increasing the memory density.

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Abstract

一种存储单元结构、存储阵列结构、半导体结构及其制备方法。存储单元结构包括：衬底、有源区、字线结构、绝缘介质层和电容结构，衬底中具有位线结构；有源区位于位线结构上，在沿垂直于衬底的方向上，包括第一连接端、远离第一连接端的第二连接端、以及位于第一连接端和第二连接端之间的沟道区，第一连接端与位线结构电连接；字线结构在垂直于衬底的方向上，覆盖沟道区的侧壁；绝缘介质层覆盖字线结构以及第一连接端和第二连接端的外侧；电容结构覆盖绝缘介质层的外侧，且覆盖绝缘介质层的顶面和第二连接端的顶面，电容结构和第二连接端电连接。上述存储单元结构利用环沟道电容结构，降低了结构高度，可以增大存储密度。

Description

存储单元结构、存储阵列结构、半导体结构及其制备方法
相关申请的交叉引用
本申请要求于2022年02月14日提交中国专利局、申请号为2022101336207的中国专利的优先权，所述专利申请的全部内容通过引用结合在本申请中。
技术领域
本公开涉及半导体制造领域，特别是涉及一种存储单元结构、存储阵列结构、半导体结构及其制备方法。
背景技术
随着集成电路行业的不断发展，传统的平面结构的器件已经难以满足电路设计的要求，因此非平面结构的器件应运而生。非平面结构的器件包括绝缘体上硅(SOI，Silicon On Insulator)、双栅、多栅、纳米线场效应管以及三维DRAM结构。
然而，传统的三维DRAM制备工艺虽然可以堆叠多层DRAM，但是单层层高较大，使得DRAM密度较低。
发明内容
根据本申请的各种实施例，提供一种存储单元结构、存储阵列结构、半导体结构及其制备方法。
根据一些实施例，本申请第一方面提供一种存储单元结构，包括：衬底、有源区、字线结构、绝缘介质层和电容结构，其中，衬底中具有位线结构；有源区位于位线结构上，在沿垂直于衬底的方向上，有源区包括第一连接端、远离第一连接端的第二连接端、以及位于第一连接端和第二连接端之间的沟道区，第一连接端与位线结构电连接；字线结构在垂直于衬底的方向上，覆盖沟道区的侧壁；绝缘介质层覆盖字线结构以及第一连接端和第二连接端的外侧；电容结构覆盖绝缘介质层的外侧，且覆盖绝缘介质层的顶面和第二连接端的顶面，电容结构和第二连接端电连接。
在其中一个实施例中，字线结构包括字线介质层和位于字线介质层外侧的字线导电层。
在其中一个实施例中，绝缘介质层包括连接端介质层和字线结构绝缘层，连接端介质层覆盖第一连接端和第二连接端，字线结构绝缘层覆盖字线结构。
在其中一个实施例中，电容结构包括上电极、下电极和电容介质层；下电极覆盖绝缘介质层的外 侧，且覆盖绝缘介质层的顶面和第二连接端的顶面，下电极与第二连接端电连接；电容介质层覆盖下电极的表面；上电极覆盖电容介质层的表面。
在其中一个实施例中，有源区包括氧化铟镓锌层。
根据一些实施例，本申请第二方面公开了一种存储阵列结构，包括：多个前述任一实施例中的存储单元结构，存储单元结构呈多行多列的阵列排布；其中，位于同一行的各存储单元结构的位线结构彼此电连接；位于同一列的各存储单元结构的字线结构彼此电连接；各存储单元结构的电容结构包括从上至下依次叠置的上电极、电容介质层和下电极，各电容结构的上电极相互连接，各电容结构的电容介质层相互连接，各电容结构的下电极之间由电容介质层隔开。
在其中一个实施例中，位于同一列的各存储单元结构之间包括有源区介质层，同一列中各存储单元结构的有源区由有源区介质层分隔开。
根据一些实施例，本申请第三方面公开了一种半导体结构，包括多层前述任一实施例中的存储阵列结构，各层存储阵列结构上下叠置，且相邻存储阵列结构之间设置有隔离层；其中，各层存储阵列结构之间的字线结构、位线结构和电容结构相互独立。
根据一些实施例，本申请第四方面公开了一种存储阵列结构的制备方法，包括：提供衬底；在衬底中形成多条沿第一方向延伸的位线结构；在衬底上形成间隔排布的有源区，有源区位于位线结构上，且在垂直于衬底的方向上，有源区包括第一连接端、远离第一连接端的第二连接端、以及位于第一连接端和第二连接端之间的沟道区，第一连接端与位线结构电连接；在沿第二方向延伸的有源区之间形成在第二方向上隔离相邻的有源区的有源区介质层；在有源区暴露的第一连接端和第二连接端的外侧形成绝缘介质层，在有源区暴露的沟道区的外侧形成字线结构；形成电容结构，电容结构覆盖绝缘介质层的外侧，且覆盖绝缘介质层的顶面和第二连接端的顶面，电容结构和第二连接端电连接。
在其中一个实施例中，在衬底的上形成间隔排布的有源区，包括：于衬底的上表面形成有源区材料层；于有源区材料层中形成若干个沿第一方向延伸且间隔排布的有源区介质层，有源区介质层位于相邻的位线结构之间；于有源区材料层中形成若干个沿第二方向延伸且间隔排布的隔离沟槽，隔离沟槽沿第二方向切割开有源区材料层和有源区介质层；其中，隔离沟槽暴露出位线结构的部分上表面；相邻隔离沟槽之间的有源区材料层形成有源区。
在其中一个实施例中，在有源区暴露的第一连接端和第二连接端的外侧形成绝缘介质层，在有源区暴露的沟道区的外侧形成字线结构，包括：于有源区相对的两侧形成连接端介质层，连接端介质层覆盖第一连接端、第二连接端和沟道区的侧壁；于连接端介质层的中部形成字线结构，字线结构覆盖沟道区的侧壁；形成字线结构绝缘层，以覆盖字线结构的外侧，字线结构绝缘层和连接端介质层共同组成绝缘介质层。
在其中一个实施例中，于连接端介质层的中部形成字线结构，字线结构覆盖沟道区的侧壁，包括：形成牺牲层，牺牲层填满隔离沟槽；去除部分连接端介质层，以暴露出有源区的第二连接端和沟道区；形成字线介质层，以至少覆盖沟道区的侧壁，字线介质层的厚度小于连接端介质层的厚度；于字线介质层的外侧形成字线导电层，字线导电层的顶部低于有源区的顶部；于字线导电层的顶部形成连接端介质层，以覆盖第二连接端的侧壁。
在其中一个实施例中，形成字线结构绝缘层之后，还包括：于隔离沟槽的底部形成位线结构绝缘层，以覆盖位线结构暴露出的部分上表面。
在其中一个实施例中，形成电容结构，包括：形成下电极材料层，下电极材料层覆盖位线结构绝缘层的上表面、第二连接端的顶面以及绝缘介质层的外侧和顶面；分别沿第一方向和第二方向断开下电极材料层，以得到若干阵列排布的下电极，下电极与有源区一一对应；形成电容介质层，以覆盖所得结构的表面；形成上电极，上电极覆盖电容介质层的表面，且填满隔离沟槽。
根据一些实施例，本申请第五方面公开了一种半导体结构的制备方法，包括：采用上述任一实施例中的方法制备多个存储阵列结构；从下至上依次堆叠存储阵列结构，以得到具有多层存储阵列结构的半导体结构。
本公开实施例可以/至少具有以下优点：
上述存储单元结构具有环沟道电容结构，电容结构覆盖于有源区和字线结构外侧，减少了存储单元结构的占用面积和高度，并且增大了存储单元结构的尺寸，降低了制备工艺的难度。由于单个存储单元结构的高度有所降低，利用上述存储单元结构制备多层存储结构时，可以增大存储结构的密度。
采用氧化铟镓锌层制作有源区，氧化铟镓锌相比于传统的有源区材料，可以驱动大量电流，写入速度更快，并且当它们关闭时，漏电流更低，这使得比特持续时间更长。
上述存储阵列结构，包括多个前述实施例中的存储单元结构，借助于环沟道电容结构，存储阵列结构的层高更低，在进行多层存储阵列结构的堆叠时，可以增加堆叠层数，提高存储单元结构的密度。
上述半导体结构，具有多层存储阵列结构，利用环沟道电容结构降低了单层存储阵列结构的高度，可以增大堆叠层数，从而增大存储密度。
上述存储阵列结构的制备方法，可以将电容结构环绕于有源区和字线结构外侧，减少了单个存储单元结构的占用面积和高度，增加存储密度；此外，还可以增大存储阵列结构的尺寸，降低工艺难度。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为本申请一实施例中一种存储单元结构的截面结构示意图。
图2为本申请一实施例中一种存储阵列结构的截面结构示意图。
图3为本申请一实施例中一种半导体结构的截面结构示意图。
图4为本申请一实施例中一种制备存储阵列结构的方法流程框图。
图5为本申请一实施例中衬底的三维结构示意图。
图6为本申请一实施例中形成位线沟槽后的三维结构示意图。
图7为本申请一实施例中形成位线结构后的三维结构示意图。
图8为本申请一实施例中形成有源区材料层后的三维结构示意图。
图9为本申请一实施例中形成有源区介质层后的三维结构示意图。
图10a为本申请一实施例中形成隔离沟槽后的三维结构示意图；图10b为沿图10a中AA’方向的截面结构示意图；图10c为沿图10a中BB’方向的截面结构示意图。
图11为本申请一实施例中形成连接端介质层后的截面结构示意图。
图12-图16为本申请一实施例中于连接端介质层中形成字线结构的过程示意图。
图17为本申请一实施例中形成字线结构绝缘层后的截面结构示意图。
图18为本申请一实施例中形成字线结构绝缘层和位线结构绝缘层后的截面结构示意图。
图19为本申请一实施例中形成下电极材料层后的截面结构示意图。
图20为本申请一实施例中形成掩膜层后的截面结构示意图。
图21为本申请一实施例中图案化光阻层的俯视图。
图22为本申请一实施例中刻蚀下电极后的截面结构示意图。
图23为本申请一实施例中形成电容介质层后的截面结构示意图。
图24为本申请一实施例中形成上电极后的截面结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理 解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在描述位置关系时，除非另有规定，否则当一个元件例如层基板被指为在另一膜层“上”时，其能直接在其他膜层上或亦可存在中间膜层。进一步说，当层被指为在另一层“下”时，其可直接在下方，亦可存在一个或多个中间层。亦可以理解的是，当层被指为在两层“之间”时，其可为两层之间的唯一层，或亦可存在一个或多个中间层。本申请所称“上”、“下”是相对于触觉反馈模组在应用过程中与使用者靠近的程度而言，相对靠近使用者的一侧为“上”，相对远离使用者的一侧为“下”。
在使用本文中描述的“包括”、“具有”、和“包含”的情况下，除非使用了明确的限定用语，例如“仅”、“由……组成”等，否则还可以添加另一部件。除非相反地提及，否则单数形式的术语可以包括复数形式，并不能理解为其数量为一。
在本申请的描述中，需要说明的是，除非另有明确规定和限定，术语“相连”或“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接连接，亦可以是通过中间媒介间接连接，可以是两个部件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，在本申请的描述中，除非另有说明，“多个”、“相互”、“叠合”、“层叠”和“若干”的含义是两个或两个以上。
如图1所示，本申请的一个实施例公开了一种存储单元结构，包括：衬底10，衬底10中具有位线结构63；有源区20，有源区20位于位线结构63上，在沿垂直于衬底10的方向上，有源区20包括第一连接端21、远离第一连接端21的第二连接端22、以及位于第一连接端21和第二连接端22之间的沟道区23，第一连接端21与位线结构63电连接；字线结构30，在垂直于衬底10的方向上，字线结构30覆盖沟道区23的侧壁；绝缘介质层40，绝缘介质层40覆盖字线结构30以及第一连接端21和第二连接端22的外侧；电容结构50，电容结构50覆盖绝缘介质层40的外侧，且覆盖绝缘介质层40的顶面和第二连接端22的顶面，电容结构50和第二连接端22电连接。
示例地，衬底10可以包括基底11及位于基底11表面的基底介质层12，其中，基底11可以包括但不限于硅基底、碳化硅基底或其他基底。基底介质层12可以包括但不限于氧化硅层。位线结构63位于基底介质层12中。
有源区20位于位线结构63上方，与位线结构63的上表面相接触，且垂直于衬底10的方向延伸。有源区20包括第一连接端21、远离第一连接端21的第二连接端22、以及位于第一连接端21和第二连接端22之间的沟道区23，第一连接端21与位线结构63电连接。示例地，有源区20可以包括但不限于氧化铟镓锌层(IGZO)，氧化铟镓锌相比于传统的有源区材料，可以驱动大量电流，写入速度更快， 并且当它们关闭时，漏电流更低，这使得比特持续时间更长。
字线结构30在垂直于衬底10的方向上，覆盖沟道区23的侧壁。示例地，字线结构30可以包括字线介质层31和位于字线介质层31外侧的字线导电层32。其中，字线介质层31可以为栅氧化层，例如氧化硅层。可选地，字线介质层31还可以仅覆盖于沟道区23的外侧，也可以覆盖于沟道区23和第二连接端22的外侧。字线导电层32可以是金属层(例如金属铜)，位于字线介质层31的外侧，且与沟道区23的位置相对应。
绝缘介质层40覆盖字线结构30以及第一连接端21和第二连接端22的外侧。示例地，绝缘介质层40可以包括连接端介质层41和字线结构绝缘层42。示例地，连接端介质层41覆盖于第一连接端21和第二连接端22的外侧。字线结构绝缘层42至少覆盖字线导电层32的外侧。可选地，如图1所示，字线结构绝缘层42还可以覆盖连接端介质层41的外侧。作为示例，连接端介质层41可以为氮化硅层，字线结构绝缘层42可以为氧化硅层。
电容结构50覆盖绝缘介质层40的外侧，且覆盖绝缘介质层40的顶面和第二连接端22的顶面，电容结构50和第二连接端22电连接。如图1所示，电容结构50与衬底10之间还包括位线结构绝缘层61，以将电容结构50和位线结构63间隔开。通过向字线导电层32施加高电平，可以在沟道区23中形成电流，使得电容结构50与位线结构63通过有源区20电连接，从而可以从电容结构50中读取数据，或者向电容结构50中写入数据。
示例地，如图1所示，电容结构50包括上电极53、下电极51和电容介质层52；其中，下电极51覆盖绝缘介质层40的外侧，且覆盖绝缘介质层40的顶面和第二连接端22的顶面，下电极51与第二连接端22电连接；电容介质层52覆盖下电极51的表面；上电极53覆盖电容介质层52的表面。
示例地，上述存储单元结构可以为DRAM存储单元结构。
上述存储单元结构具有环沟道电容结构，电容结构覆盖于有源区和字线结构外侧，减少了存储单元结构的占用面积和高度，并且增大了存储单元结构的尺寸，降低了制备工艺的难度。由于单个存储单元结构的高度有所降低，利用上述存储单元结构制备多层存储结构时，可以增大存储结构的密度。
如图2所示，本申请的一个实施例还公开了一种存储阵列结构，包括：多个上述任一实施例中的存储单元结构，存储单元结构呈多行多列的阵列排布；其中，位于同一行的各存储单元结构的位线结构63彼此电连接；位于同一列的各存储单元结构的字线结构30彼此电连接；各存储单元结构的电容结构50包括从上至下依次叠置的上电极53、电容介质层52和下电极51，各电容结构50的上电极53相互连接，各电容结构50的电容介质层52相互连接，各电容结构50的下电极51之间由电容介质层52隔开。
位于同一行的各存储单元结构的位线结构63彼此电连接，沿第一方向延伸，第一方向为存储阵列 结构的行方向。示例地，如图2所示，存储阵列结构还包括位线结构绝缘层61，位于位线结构63的上表面，将电容结构50与位线结构63隔开。
位于同一列的各存储单元结构的字线结构30彼此电连接，沿第二方向延伸，第二方向为存储阵列结构的列方向。示例地，位于同一列的各存储单元结构之间还包括有源区介质层(图中未示出)，同一列中各存储单元结构的有源区20由有源区介质层分隔开。有源区介质层和有源区20在第二方向上交替排列。
各存储单元结构中的电容结构50包括从上至下依次叠置的上电极53、电容介质层52和下电极51，其中，各电容结构50的上电极53相互连接，各电容结构50的电容介质层52相互连接，各电容结构50的下电极51之间由电容介质层52隔开，从而形成相互独立的存储单元结构。
上述存储阵列结构，包括多个阵列排布的存储单元结构，借助于环沟道电容结构，存储阵列结构的层高更低，在进行多层存储阵列结构的堆叠时，可以增加堆叠层数，提高存储单元结构的密度。
本申请的一个实施例还公开了一种半导体结构，包括多层上述任一实施例中的存储阵列结构，各层存储阵列结构上下叠置，且相邻存储阵列结构之间设置有隔离层；其中，各层存储阵列结构之间的字线结构30、位线结构63和电容结构50相互独立。
示例地，图3展示了一种具有两层存储阵列结构的半导体结构。各层存储阵列结构的基底介质层12中包括平行间隔排布的位线结构63，位线结构63、字线结构30和电容结构50的排布和连接方式可以参考前述实施例，在此不再赘述。示例地，存储阵列结构的层数可以根据需求增加。
上述半导体结构，具有多层存储阵列结构，利用环沟道电容结构降低了单层存储阵列结构的高度，堆叠层数可以更大，从而增加了存储密度。
如图4所示，本申请的一个实施例提供了一种存储阵列结构的制备方法，包括：
S10：提供衬底；
S20：在所述衬底中形成多条沿第一方向延伸的位线结构；
S30：在所述衬底上形成间隔排布的有源区，所述有源区位于所述位线结构上，且在垂直于所述衬底的方向上，所述有源区包括第一连接端、远离所述第一连接端的第二连接端、以及位于所述第一连接端和所述第二连接端之间的沟道区，所述第一连接端与所述位线结构电连接；在沿第二方向延伸的所述有源区之间形成在所述第二方向上隔离相邻的所述有源区的有源区介质层；
S40：在所述有源区暴露的所述第一连接端和所述第二连接端的外侧形成绝缘介质层，在所述有源区暴露的所述沟道区的外侧形成字线结构；
S50：形成电容结构，电容结构覆盖绝缘介质层的外侧，且覆盖绝缘介质层的顶面和第二连接端的顶面，电容结构和第二连接端电连接。
利用上述存储阵列结构的制备方法，可以将电容结构覆盖于有源区和字线结构外侧，减少了单个存储单元结构的占用面积和高度，增加存储密度；此外，还可以增大存储阵列结构的尺寸，降低工艺难度。
示例地，在步骤S10中，请参阅图4中的S10步骤及图5，提供的衬底10可以包括基底11及位于基底11表面的基底介质层12，如图5所示。其中，基底11可以包括但不限于硅基底11、碳化硅基底11或其他基底11。基底介质层12可以包括但不限于氧化硅层。
在步骤S20中，请参阅图4中的S20步骤及图6至图7，于衬底10中形成多条沿第一方向延伸的位线结构63。
示例地，如图6所示，可以先对基底介质层12进行刻蚀，于基底介质层12中形成沿第一方向延伸的位线沟槽62，各位线沟槽62平行间隔排布。形成位线沟槽62的工艺可以为干法刻蚀工艺或湿法刻蚀工艺。
形成位线沟槽62之后，于位线沟槽62中沉积金属层，形成位线结构63。可选地，位线结构63的顶面与衬底10的顶面相齐平，如图7所示。其中，形成金属层的材料可以包括但不限于金属铜。
在步骤S30中，请参阅图4中的S30步骤及图8至图17，于衬底10上形成间隔排布的有源区20的步骤包括：
S31：于衬底10的上表面形成有源区材料层24，如图8所示。
示例地，可以于衬底10表面沉积氧化铟镓锌层(IGZO)作为有源区材料层24，氧化铟镓锌相比于传统的有源区材料，可以驱动大量电流，写入速度更快，并且当它们关闭时，漏电流更低，这使得比特持续时间更长。
S32：于有源区材料层24中形成若干个沿第一方向延伸且间隔排布的有源区介质层25，有源区介质层25位于相邻的位线结构63之间，如图9所示。
示例地，可以先沿第一方向在有源区材料层24中形成若干个平行间隔排布的浅沟槽隔离结构，然后在浅沟槽隔离结构中填充氧化硅层，以形成有源区介质层25。其中，有源区介质层25位于相邻的位线结构63之间。可选地，有源区介质层25的宽度与位线结构63之间的间隔宽度相等。
S33：于有源区材料层24中形成若干个沿第二方向延伸且间隔排布的隔离沟槽26，隔离沟槽26沿第二方向切割开有源区材料层24和有源区介质层25；其中，隔离沟槽26暴露出位线结构63的部分上表面；相邻的隔离沟槽26之间的有源区材料层24形成有源区20，如图10a、图10b和图10c所示。
其中，图10b为图10a所示结构沿AA’方向(第一方向)的截面示意图，图10c为图10a所示结构沿BB’方向(第二方向)的截面示意图。示例地，可以采用刻蚀工艺于有源区材料层24中沿第二方向形成若干个间隔排布的隔离沟槽26，隔离沟槽26沿第二方向切割开有源区材料层24和有源区介质 层25，如图10a所示。隔离沟槽26暴露出位线结构63的部分上表面，如图10b所示。相邻隔离沟槽26之间的有源区材料层24形成有源区20，有源区20和有源区介质层25在第二方向上交替排列，如图10c所示。其中，有源区20包括第一连接端21、远离第一连接端21的第二连接端22、以及位于第一连接端21和第二连接端22之间的沟道区23。
在步骤S40中，请参阅图4中的S40步骤及图11至图17，形成绝缘介质层和字线结构的步骤可以包括：
S41：于有源区20相对的两侧形成连接端介质层41，连接端介质层41覆盖第一连接端21、第二连接端22和沟道区23的侧壁，如图11所示。
示例地，可以于有源区20的侧壁沉积氮化硅层，以形成连接端介质层41。可选地，连接端介质层41的顶部与有源区20的顶部齐平，以完全覆盖有源区20的第一连接端21、第二连接端22和沟道区23的侧壁。示例地，沉积氮化硅层的工艺可以包括原子层沉积工艺、等离子体沉积工艺、化学气相沉积工艺或物理气相沉积工艺。
S42：于连接端介质层41的中部形成字线结构30，字线结构30覆盖沟道区23的侧壁。示例地，形成字线结构30的步骤包括：
S421：形成牺牲层27，牺牲层27填满隔离沟槽26，如图12所示。
示例地，可以于隔离沟槽26内填充氧化硅层作为牺牲层27，并且氧化硅层的顶部与有源区20的顶部相齐平。
S422：去除部分连接端介质层41，以暴露出有源区20的第二连接端22和沟道区23，如图13所示。
示例地，可以选用对氮化硅层具有更高刻蚀选择比的气体刻蚀连接端介质层41，以去除部分连接端介质层41，得到如图13所示的结构，将有源区20的第二连接端22和沟道区23暴露出来。
S423：形成字线介质层31，以至少覆盖沟道区23的侧壁，字线介质层31的厚度小于连接端介质层41的厚度，如图14所示。
示例地，可以采用原子层沉积工艺(ALD)在沟道区23的侧壁上沉积氧化硅层，以得到字线介质层31。其中，字线介质层31的厚度小于连接端介质层41的厚度。可选地，字线介质层31还可以同时覆盖第二连接端22和沟道区23的侧壁，字线介质层31的顶部与有源区20的顶部相齐平。
S424：于字线介质层31的外侧形成字线导电层32，字线导电层32的顶部低于有源区20的顶部，如图15所示。
示例地，可以在字线介质层31和牺牲层27之间沉积金属或其他导电材料，以形成字线导电层32。示例地，字线导电层32可以为铜层。字线导电层32的底部与连接端介质层41相接触，且字线导电层 32的顶部低于有源区20的顶部。字线导电层32和字线介质层31共同组成字线结构30。
S425：于字线导电层32的顶部形成连接端介质层41，以覆盖第二连接端22的侧壁，如图16所示。
示例地，于字线导电层32的顶部沉积氮化硅层，形成与有源区20顶部相齐平的连接端介质层41，新形成的连接端介质层41覆盖有源区20的第二连接端22。
S43：形成字线结构绝缘层42，以覆盖字线结构30的外侧，字线结构绝缘层42和连接端介质层41共同组成绝缘介质层40，如图17所示。
示例地，可以先将牺牲层27去除，然后采用原子层沉积工艺(ALD)于连接端介质层41和字线导电层32的外侧壁沉积氧化层，形成字线结构绝缘层42。可选地，字线结构绝缘层42的高度与有源区20的高度相等。字线结构绝缘层42和连接端介质层41共同组成绝缘介质层40。
在一个实施例中，形成字线结构绝缘层42之后，还包括：于隔离沟槽26的底部形成位线结构绝缘层61，以覆盖位线结构63暴露出的部分上表面，如图18所示。
示例地，可以在形成字线结构绝缘层42的同时，于隔离沟槽26的底部沉积氧化层，以覆盖位线结构63暴露出的上表面，形成位线结构绝缘层61。
在步骤S50中，请参阅图4中的S50步骤及图19至图24，形成电容结构50的步骤包括：
S51：形成下电极材料层511，下电极材料层511覆盖位线结构绝缘层61的上表面、第二连接端22的顶面以及绝缘介质层40的顶面和侧壁，如图19所示。
示例地，下电极材料层511可以包括但不限于钨层、氮化钛或其他导电层。
S52：分别沿第一方向和第二方向切割下电极材料层511，以得到若干阵列排布的下电极51，下电极51与有源区20一一对应。示例地，形成下电极51的步骤包括：
S521：形成掩膜层54，掩膜层54填满隔离沟槽26，如图20所示。
示例地，掩膜层54可以是氧化硅层或氮氧化硅层。可采用原子层沉积工艺、等离子体沉积工艺、化学气相沉积工艺或物理气相沉积工艺形成掩膜层54。在一些实施例中，掩膜层54的顶部与下电极材料层511的顶部相齐平。
S522：于掩膜层54的上表面形成图案化光阻层55，基于图案化光阻层55刻蚀下电极材料层511。
图案化光阻层55可用于定义下电极材料层511中需要断开的位置。示例地，图案化光阻层55的俯视图如图21所示，基于图案化光阻层55刻蚀下电极材料层511，将图案化光阻层55暴露出的下电极材料层511去除。从第一方向来看，去除隔离沟槽26底部的部分下电极材料层511；沿第二方向来看，去除与有源区介质层25的位置相对应的部分下电极材料层511(有源区介质层25的位置可参考图10a)，从而形成若干阵列排布的下电极51，如图22所示。
S53：形成电容介质层52，以覆盖所得结构的表面，如图23所示。
示例地，可以先将掩膜层54完全去除，然后于所得结构的上表面沉积电容介质层52。
S54：形成上电极53，上电极53覆盖电容介质层52的表面，且填满隔离沟槽26，如图24所示。
示例地，形成上电极53的材料可以与下电极材料层511相同，例如，均为钨层、氮化钛层或其他导电层。
本申请还公开了一种半导体结构的制备方法，包括：采用前述任一实施例中的方法制备多个存储阵列结构；从下至上依次堆叠存储阵列结构，以得到具有多层存储阵列结构的半导体结构。
可选地，相邻两层存储阵列结构之间还设置有隔离层。各层存储阵列结构之间的字线结构30、位线结构63和电容结构50相互独立。
利用上述半导体结构的制备方法，可以降低单层存储阵列结构的层高，增大堆叠层数，从而增加存储密度。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种存储单元结构，包括：
    衬底，所述衬底中具有位线结构；
    有源区，所述有源区位于所述位线结构上，在沿垂直于所述衬底的方向上，所述有源区包括第一连接端、远离所述第一连接端的第二连接端、以及位于所述第一连接端和所述第二连接端之间的沟道区，所述第一连接端与所述位线结构电连接；
    字线结构，在垂直于所述衬底的方向上，所述字线结构覆盖所述沟道区的侧壁；
    绝缘介质层，所述绝缘介质层覆盖所述字线结构以及所述第一连接端和所述第二连接端的外侧；
    电容结构，所述电容结构覆盖所述绝缘介质层的外侧，且覆盖所述绝缘介质层的顶面和所述第二连接端的顶面，所述电容结构和所述第二连接端电连接。
  2. 根据权利要求1所述的存储单元结构，其中，所述字线结构包括字线介质层和位于所述字线介质层外侧的字线导电层。
  3. 根据权利要求1所述的存储单元结构，其中，所述绝缘介质层包括连接端介质层和字线结构绝缘层，所述连接端介质层覆盖所述第一连接端和所述第二连接端，所述字线结构绝缘层覆盖所述字线结构。
  4. 根据权利要求1所述的存储单元结构，其中，所述电容结构包括上电极、下电极和电容介质层；
    所述下电极覆盖所述绝缘介质层的外侧，且覆盖所述绝缘介质层的顶面和所述第二连接端的顶面，所述下电极与所述第二连接端电连接；
    所述电容介质层覆盖所述下电极的表面；
    所述上电极覆盖所述电容介质层的表面。
  5. 根据权利要求1-4中任一项所述的存储单元结构，其中，所述有源区包括氧化铟镓锌层。
  6. 一种存储阵列结构，包括：多个如权利要求1-5任一项所述的存储单元结构，所述存储单元结构呈多行多列的阵列排布；其中，
    位于同一行的各所述存储单元结构的位线结构彼此电连接；
    位于同一列的各所述存储单元结构的字线结构彼此电连接；
    各所述存储单元结构的电容结构包括从上至下依次叠置的上电极、电容介质层和下电极，各所述电容结构的上电极相互连接，各所述电容结构的电容介质层相互连接，各所述电容结构的下电极之间由所述电容介质层隔开。
  7. 根据权利要求6所述的存储阵列结构，其中，位于同一列的各所述存储单元结构之间包括有 源区介质层，同一列中各所述存储单元结构的有源区由所述有源区介质层分隔开。
  8. 一种半导体结构，包括多层如权利要求6-7任一项所述的存储阵列结构，各层所述存储阵列结构上下叠置，且相邻所述存储阵列结构之间设置有隔离层；
    其中，各层存储阵列结构之间的字线结构、位线结构和电容结构相互独立。
  9. 一种存储阵列结构的制备方法，包括：
    提供衬底；
    在所述衬底中形成多条沿第一方向延伸的位线结构；
    在所述衬底上形成间隔排布的有源区，所述有源区位于所述位线结构上，且在垂直于所述衬底的方向上，所述有源区包括第一连接端、远离所述第一连接端的第二连接端、以及位于所述第一连接端和所述第二连接端之间的沟道区，所述第一连接端与所述位线结构电连接；
    在沿第二方向延伸的所述有源区之间形成在所述第二方向上隔离相邻的所述有源区的有源区介质层；
    在所述有源区暴露的所述第一连接端和所述第二连接端的外侧形成绝缘介质层，在所述有源区暴露的所述沟道区的外侧形成字线结构；
    形成电容结构，所述电容结构覆盖所述绝缘介质层的外侧，且覆盖所述绝缘介质层的顶面和所述第二连接端的顶面，所述电容结构和所述第二连接端电连接。
  10. 根据权利要求9所述的存储阵列结构的制备方法，其中，所述在所述衬底的上形成间隔排布的有源区，包括：
    于所述衬底的上表面形成有源区材料层；
    于所述有源区材料层中形成若干个沿所述第一方向延伸且间隔排布的所述有源区介质层，所述有源区介质层位于相邻的所述位线结构之间；
    于所述有源区材料层中形成若干个沿所述第二方向延伸且间隔排布的隔离沟槽，所述隔离沟槽沿所述第二方向切割开所述有源区材料层和所述有源区介质层；其中，所述隔离沟槽暴露出所述位线结构的部分上表面；相邻所述隔离沟槽之间的有源区材料层形成所述有源区。
  11. 根据权利要求10所述的存储阵列结构的制备方法，其中，所述在所述有源区暴露的所述第一连接端和所述第二连接端的外侧形成绝缘介质层，在所述有源区暴露的所述沟道区的外侧形成字线结构，包括：
    于所述有源区相对的两侧形成连接端介质层，所述连接端介质层覆盖所述第一连接端、所述第二连接端和所述沟道区的侧壁；
    于所述连接端介质层的中部形成所述字线结构，所述字线结构覆盖所述沟道区的侧壁；
    形成字线结构绝缘层，以覆盖所述字线结构的外侧，所述字线结构绝缘层和所述连接端介质层共同组成所述绝缘介质层。
  12. 根据权利要求11所述的存储阵列结构的制备方法，其中，所述于所述连接端介质层的中部形成所述字线结构，所述字线结构覆盖所述沟道区的侧壁，包括：
    形成牺牲层，所述牺牲层填满所述隔离沟槽；
    去除部分所述连接端介质层，以暴露出所述有源区的所述第二连接端和所述沟道区；
    形成字线介质层，以至少覆盖所述沟道区的侧壁，所述字线介质层的厚度小于所述连接端介质层的厚度；
    于所述字线介质层的外侧形成字线导电层，所述字线导电层的顶部低于所述有源区的顶部；
    于所述字线导电层的顶部形成所述连接端介质层，以覆盖所述第二连接端的侧壁。
  13. 根据权利要求11-12任一项所述的存储阵列结构的制备方法，其中，形成所述字线结构绝缘层之后，还包括：
    于所述隔离沟槽的底部形成位线结构绝缘层，以覆盖所述位线结构暴露出的部分上表面。
  14. 根据权利要求13所述的存储阵列结构的制备方法，其中，所述形成电容结构，包括：
    形成下电极材料层，所述下电极材料层覆盖所述位线结构绝缘层的上表面、所述第二连接端的顶面以及所述绝缘介质层的外侧和顶面；
    分别沿所述第一方向和所述第二方向断开所述下电极材料层，以得到若干阵列排布的下电极，所述下电极与所述有源区一一对应；
    形成电容介质层，以覆盖所得结构的表面；
    形成上电极，所述上电极覆盖所述电容介质层的表面，且填满所述隔离沟槽。
  15. 一种半导体结构的制备方法，包括：
    采用权利要求9-14中任一项所述的方法制备多个存储阵列结构；
    从下至上依次堆叠所述存储阵列结构，以得到具有多层存储阵列结构的半导体结构。
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