WO2024092986A1 - 存储装置、存储单元阵列结构、制造方法和电子设备 - Google Patents

存储装置、存储单元阵列结构、制造方法和电子设备 Download PDF

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WO2024092986A1
WO2024092986A1 PCT/CN2022/140444 CN2022140444W WO2024092986A1 WO 2024092986 A1 WO2024092986 A1 WO 2024092986A1 CN 2022140444 W CN2022140444 W CN 2022140444W WO 2024092986 A1 WO2024092986 A1 WO 2024092986A1
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layer
electrode
memory cell
substrate
word line
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PCT/CN2022/140444
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English (en)
French (fr)
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戴瑾
梁静
余泳
杨楠
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北京超弦存储器研究院
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Publication of WO2024092986A1 publication Critical patent/WO2024092986A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B12/00—Superconductive or hyperconductive conductors, cables, or transmission lines
    • H01B12/02—Superconductive or hyperconductive conductors, cables, or transmission lines characterised by their form
    • H01B12/10—Multi-filaments embedded in normal conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/10—DRAM devices comprising bipolar components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • the present disclosure relates to a Chinese patent application entitled “Memory Cell Array Structure and Preparation Method” filed on November 1, 2022 with application number ⁇ 202211358553.5>.
  • the embodiments of the present disclosure relate to, but are not limited to, the field of semiconductor material technology, and in particular to a storage device, a storage cell array, a manufacturing method, and an electronic device.
  • DRAM dynamic random access memory
  • the memory cells in dynamic random access memory are usually arranged in two dimensions, specifically, the memory cells are distributed along rows and columns on a substrate. Improving memory usually involves increasing the density of memory cells.
  • the density is generally increased by miniaturizing the memory cells, for example, reducing the size of the bit lines, word lines, and transistors to add more memory cells.
  • miniaturizing the memory cells for example, reducing the size of the bit lines, word lines, and transistors to add more memory cells.
  • the manufacturing process and product performance become more challenging, and 3D stacking has become a technical direction for device miniaturization to increase storage density.
  • the present disclosure provides a storage device, a storage cell array, a manufacturing method and an electronic device.
  • the storage cells of different layers can be directly stacked in the vertical direction, and multiple layers can be etched at one time to produce word lines and capacitor external plates, thereby optimizing the process flow of array stacking and reducing manufacturing costs.
  • An embodiment of the present disclosure provides a storage device, including:
  • a vertically stacked multi-layer memory cell array wherein the memory cell has transistors and capacitors arranged in sequence in a horizontal direction;
  • Every two adjacent columns of storage units in each layer are a repeating unit, and the repeating units are periodically distributed in the horizontal direction and in the direction vertical to the substrate;
  • the external electrode plate of the capacitor in each storage unit in each repeating unit periodically distributed in the direction perpendicular to the substrate is a common external electrode plate.
  • the two capacitors of the two storage units in any layer and any row respectively include a first inner plate and a second inner plate, the first inner plate and the second inner plate are spaced apart in the row direction, and the common outer plate is arranged between each first inner plate and each second inner plate.
  • the common outer electrode plate fills the area between each of the first inner electrode plates and each of the second inner electrode plates and is insulated from each of the first inner electrode plates and each of the second inner electrode plates by an insulating layer on the surface of each of the first inner electrode plates and each of the second inner electrode plates.
  • each of the first inner pole plates and each of the second inner pole plates extends in a horizontal direction to form a structure having a side surface and an end surface respectively, the end surfaces of each of the first inner pole plates and each of the second inner pole plates are arranged facing each other, and the common outer pole plate is filled between each of the first inner pole plates and each of the second inner pole plates and extends to the side surfaces of each of the first inner pole plates and the side surfaces of each of the second inner pole plates to wrap each of the first inner pole plates and each of the second inner pole plates.
  • the distance that the common outer electrode plate extends to the side surface of the first inner electrode plate or the second inner electrode plate is smaller than the extension length of the first inner electrode plate or the second inner electrode plate in the horizontal direction.
  • the common outer electrode plate extends to each of the first inner electrode plates at an equal distance
  • the common outer electrode plate extends to each of the second inner electrode plates at an equal distance
  • the distance that the common outer electrode plate extends to each of the first inner electrode plates is equal to the distance that the common outer electrode plate extends to each of the second inner electrode plates.
  • the bit line connected to the transistor and the inner plate of the capacitor are located in different regions of the side wall of the word line and the different regions are arranged facing each other;
  • the bit line extends parallel to the substrate and along the column direction and is connected to the transistors of the memory cells in each column direction, wherein two adjacent columns of memory cells share one bit line;
  • bit lines and the common external plates are alternately distributed.
  • the present disclosure provides a memory cell array structure, comprising a substrate, a plurality of stacked memory cells formed on the substrate, a plurality of bit lines and a plurality of word lines; wherein each layer of the memory cells comprises a plurality of rows and columns of memory cells and each memory cell is stacked with a plurality of memory cells at different positions of the substrate, and each memory cell stacked at different layers at the same position shares the same word line, and the word line runs through each stacked memory cell and extends in a direction perpendicular to the substrate;
  • Each storage unit includes a transistor and a capacitor, and the capacitor includes a first electrode, a second electrode and a dielectric layer; the transistor is electrically connected to the first electrode; every two columns of storage units in the same layer are a repeating unit, and in each repeating unit in the stack, the second electrode of each storage unit is a common electrode.
  • each bit line extends along a first direction and is arranged at intervals in a third direction, the first direction is parallel to the substrate along a column direction, and the third direction is parallel to the substrate along a row direction;
  • Each word line extends along a second direction, and the second direction is perpendicular to the substrate surface.
  • memory cells located in the same layer and symmetrically distributed on both sides of the same bit line share the same bit line.
  • capacitors of memory cells between adjacent bit lines in different layers in the vertical direction share the same second electrode.
  • each of the transistors comprises: an annular semiconductor layer surrounding the word line and extending along the side surface of the word line, an annular gate insulating layer, annular semiconductor layer, annular semiconductor layer, gate insulating layer, gate insulating layer, annular semiconductor layer, annular semiconductor layer located between the word line and the annular semiconductor layer;
  • the bit line is parallel to the substrate and extends along the column direction, and the bit line contacts each of the ring-shaped semiconductor layers of a column of the memory cells; the first electrode contacts the ring-shaped semiconductor layer; and a horizontal channel is formed between the first electrode and the bit line.
  • the annular semiconductor layer first electrodes of the memory cells of different layers extend along the row direction, and the common electrode surrounds the sidewalls of each of the first electrodes and is isolated from each of the first electrodes by a dielectric layer.
  • the conductive film layer of the first electrode of the capacitor and the conductive film layer of the bit line are conductive film layers made of the same material and are located in the same film layer.
  • the annular semiconductor layer is a metal oxide semiconductor film layer.
  • the memory cell array structure further includes a preset number of word line control transistors; each word line control transistor is connected to each word line, and is configured to perform switching control on the connected word line.
  • the present disclosure provides a method for manufacturing a memory cell array structure, comprising:
  • multiple capacitors and multiple through holes are symmetrically distributed on both sides of a bit line, and the capacitor includes a first electrode, a second electrode and a capacitor dielectric layer; the capacitors of the storage units between adjacent bit lines of different layers in the vertical direction share the same second electrode; each layer of bit lines extends along a first direction, and the first direction is parallel to the substrate surface; the word line extends along a second direction, and the second direction is perpendicular to the substrate surface.
  • forming an annular semiconductor layer, an annular gate insulating layer and a word line inside each through hole of the through hole array includes:
  • a high-K dielectric is deposited on the inner side of the formed annular semiconductor layer to form an annular gate insulating layer by atomic layer deposition;
  • a conductive material is filled inside the annular gate insulating layer to form a word line.
  • forming a plurality of capacitors and a plurality of bit lines includes:
  • the first groove is formed by etching all the conductive material layers and the dielectric layers between each two adjacent groups of through holes and at a preset distance from each group of through holes; wherein each group of through holes includes two adjacent columns of through holes; the entire dielectric layer is selectively etched, and all the annular semiconductor layers located in the dielectric layer are removed;
  • each conductive material layer is etched according to a preset pattern to form a first electrode of each capacitor and a bit line; the number of the first electrodes of the capacitors formed is the same as the number of the through holes in the group; the number of the bit lines formed is the same as the number of layers of the conductive material layer occupied by the through holes in the group;
  • the second stacked body is a stacked body formed by etching each conductive material layer according to a preset pattern
  • a conductor is filled in the second groove to form a second electrode shared by a plurality of capacitors.
  • the present disclosure provides an electronic device, comprising:
  • the electronic device at least comprises a storage unit array structure
  • the memory cell array structure comprises a substrate, a plurality of stacked memory cells formed on the substrate, a plurality of bit lines and a plurality of word lines; wherein each layer of the memory cells comprises a plurality of rows and columns of memory cells and each memory cell is stacked with a plurality of memory cells at different positions of the substrate, and each memory cell stacked at different layers at the same position shares the same word line, and the word line runs through each stacked memory cell and extends in a direction perpendicular to the substrate;
  • Each storage unit includes a transistor and a capacitor, and the capacitor includes a first electrode, a second electrode and a dielectric layer; the transistor is electrically connected to the first electrode; every two columns of storage units in the same layer are a repeating unit, and in each repeating unit in the stack, the second electrode of each storage unit is a common electrode.
  • each bit line extends along a first direction and is arranged at intervals in a third direction, the first direction is parallel to the substrate along a column direction, and the third direction is parallel to the substrate along a row direction;
  • Each word line extends along a second direction, and the second direction is perpendicular to the substrate surface.
  • memory cells located in the same layer and symmetrically distributed on both sides of the same bit line share the same bit line.
  • capacitors of memory cells between adjacent bit lines in different layers in the vertical direction share the same second electrode.
  • each of the transistors comprises: an annular semiconductor layer surrounding the word line and extending along the side surface of the word line, an annular gate insulating layer, annular semiconductor layer, annular semiconductor layer, gate insulating layer, gate insulating layer, annular semiconductor layer, annular semiconductor layer located between the word line and the annular semiconductor layer;
  • the bit line is parallel to the substrate and extends along the column direction, and the bit line contacts each of the ring-shaped semiconductor layers of a column of the memory cells; the first electrode contacts the ring-shaped semiconductor layer; and a horizontal channel is formed between the first electrode and the bit line.
  • the annular semiconductor layer first electrodes of the memory cells of different layers extend along the row direction, and the common electrode surrounds the sidewalls of the first electrodes and is isolated from the first electrodes by the dielectric layer.
  • the conductive film layer of the first electrode of the capacitor and the conductive film layer of the bit line are conductive film layers made of the same material and are located in the same film layer.
  • the annular semiconductor layer is a metal oxide semiconductor film layer.
  • the memory cell array structure further includes a preset number of word line control transistors; each word line control transistor is connected to each word line, and is configured to perform switching control on the connected word line.
  • FIG1A is a horizontal cross-sectional view of a single layer of a memory cell array according to an embodiment of the present disclosure
  • FIG1B is a vertical cross-sectional view of a memory cell array according to an embodiment of the present disclosure.
  • FIG2 is a flow chart of a method for manufacturing a memory cell array structure according to an embodiment of the present disclosure
  • FIG3 is a vertical cross-sectional view of a stacked body of a memory cell array structure according to an embodiment of the present disclosure
  • FIG4A is a top view of a through hole of a memory cell array structure according to an embodiment of the present disclosure
  • FIG4B is a vertical cross-sectional view of a through hole of a memory cell array structure according to an embodiment of the present disclosure
  • FIG5 is a schematic diagram of a method for manufacturing a structure in a through hole according to an embodiment of the present disclosure
  • FIG6A is a horizontal cross-sectional view of the structure inside the through hole according to an embodiment of the present disclosure
  • FIG6B is a vertical cross-sectional view of the structure inside the through hole according to an embodiment of the present disclosure.
  • FIG7A is a horizontal cross-sectional view of the embodiment of the present disclosure after forming a portion of transistors in a through hole;
  • FIG7B is a vertical cross-sectional view of the embodiment of the present disclosure after forming a portion of transistors in a through hole;
  • FIG8A is a horizontal cross-sectional view of a first groove etched in an embodiment of the present disclosure
  • FIG8B is a vertical cross-sectional view of a first groove etched according to an embodiment of the present disclosure.
  • 9A is a horizontal cross-sectional view of an embodiment of the present disclosure in which a dielectric layer and a ring-shaped semiconductor layer at the dielectric layer are etched away;
  • 9B is a vertical cross-sectional view of an embodiment of the present disclosure in which the dielectric layer and the annular semiconductor layer at the dielectric layer are etched away;
  • FIG10 is a horizontal cross-sectional view of etching a first electrode and a bit line according to an embodiment of the present disclosure
  • FIG11A is a horizontal cross-sectional view of an embodiment of the present disclosure after etching a first groove and refilling with a dielectric;
  • FIG11B is a vertical cross-sectional view of an embodiment of the present disclosure after etching a first groove and refilling the dielectric therein;
  • FIG12A is a horizontal cross-sectional view of an embodiment of the present disclosure after etching a second groove
  • FIG12B is a vertical cross-sectional view of the embodiment of the present disclosure after etching the second groove
  • FIG13A is a horizontal cross-sectional view of a single layer of a memory cell array according to an embodiment of the present disclosure
  • FIG13B is a vertical cross-sectional view of a memory cell array according to an embodiment of the present disclosure.
  • FIG. 14 is a three-dimensional diagram of a memory cell array according to an embodiment of the present disclosure.
  • one of the electrodes is called the first electrode, and the other electrode is called the second electrode.
  • the first electrode can be a source electrode or a drain electrode
  • the second electrode can be a drain electrode or a source electrode.
  • the gate electrode of the transistor is called a control electrode.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in the embodiments of the present disclosure, the "source electrode” and the “drain electrode” can be interchanged.
  • the present disclosure provides a storage device, comprising:
  • a vertically stacked multi-layer memory cell array wherein the memory cells have transistors and capacitors arranged in sequence in a horizontal direction;
  • Every two adjacent columns of storage units in each layer are a repeating unit, and the repeating units are periodically distributed in the horizontal direction and in the direction vertical to the substrate;
  • the external electrode plate of the capacitor in each storage unit in each repeating unit periodically distributed in the direction perpendicular to the substrate is a common external electrode plate.
  • the two capacitors of the two storage units in any layer and any row respectively include a first inner plate and a second inner plate, the first inner plate and the second inner plate are spaced apart in the row direction, and the common outer plate is arranged between each first inner plate and each second inner plate.
  • the common outer electrode plate fills the area between each of the first inner electrode plates and each of the second inner electrode plates and is insulated from each of the first inner electrode plates and each of the second inner electrode plates by an insulating layer on the surface of each of the first inner electrode plates and each of the second inner electrode plates.
  • each of the first inner pole plates and each of the second inner pole plates extends in a horizontal direction to form a structure having a side surface and an end surface respectively, the end surfaces of each of the first inner pole plates and each of the second inner pole plates are arranged facing each other, and the common outer pole plate is filled between each of the first inner pole plates and each of the second inner pole plates and extends to the side surfaces of each of the first inner pole plates and the side surfaces of each of the second inner pole plates to wrap each of the first inner pole plates and each of the second inner pole plates.
  • the distance that the common outer electrode plate extends to the side surface of the first inner electrode plate or the second inner electrode plate is smaller than the extension length of the first inner electrode plate or the second inner electrode plate in the horizontal direction.
  • the common outer electrode plate extends to each of the first inner electrode plates at an equal distance
  • the common outer electrode plate extends to each of the second inner electrode plates at an equal distance
  • the distance that the common outer electrode plate extends to each of the first inner electrode plates is equal to the distance that the common outer electrode plate extends to each of the second inner electrode plates.
  • the bit line connected to the transistor and the inner plate of the capacitor are located in different regions of the side wall of the word line and the different regions are arranged facing each other;
  • the bit line extends parallel to the substrate and along the column direction and is connected to the transistors of the memory cells in each column direction, wherein two adjacent columns of memory cells share one bit line;
  • bit lines and the common external plates are alternately distributed.
  • An embodiment of the present disclosure provides a memory cell array structure, which includes a substrate, a three-dimensional memory cell array formed on the surface of the substrate, the three-dimensional memory cell array includes multiple layers of memory cells, and multiple memory cells located in each layer; it also includes multiple bit lines and multiple word lines.
  • the substrate generally has two main surfaces, one above and one below, and a side surface between the two main surfaces, one of which can be understood as an upper surface and the other as a lower surface.
  • the three-dimensional memory cell array is located on the upper surface of the substrate and is three-dimensionally stacked in a direction perpendicular to the substrate.
  • the surface perpendicular to the substrate mentioned in this article refers to the upper surface of the perpendicular substrate unless otherwise specified.
  • each storage unit is a 1T1C storage unit, including a transistor and a capacitor, the capacitor including a first electrode, a second electrode and a capacitor dielectric layer; the first electrode is the inner plate of the capacitor, the second electrode is the outer plate of the capacitor; the transistor is electrically connected to one of the electrodes in the capacitor; each bit line extends along a first direction, the first direction is parallel to the substrate surface and extends along the column direction (y direction of three-dimensional space); the storage units located in the same layer share a bit line for each adjacent column of storage units, and each adjacent column of storage units shares a capacitor outer plate; the shared outer plates of storage units in different layers are connected as a common outer plate; the outer plates connecting two adjacent columns of storage units in each layer are an integrated design, which can be understood as a non-layered structure, and each region is formed by the same material.
  • the electrolyte layers between adjacent columns of storage units in each layer can be exposed to form grooves that penetrate each layer, and the exposed grooves are filled with conductive materials to form common outer plates. Because the shape of the common outer plate is adapted to the shape of the groove, the common outer plate can also be understood as a common capacitor groove.
  • the structure of the capacitor outer plate as described above is conducive to simplifying the manufacturing process and reducing costs.
  • capacitors of adjacent storage cells in different layers along the direction perpendicular to the substrate share the same second electrode;
  • Each word line extends along a second direction, which is perpendicular to the surface of the insulating substrate; storage cells at different layers in the vertical direction share the same word line.
  • the memory cell array structure may include a multi-layer memory structure.
  • the memory cells symmetrically distributed on both sides of the same bit line share the same bit line, the memory cells of different layers whose projections overlap in the vertical direction share the same word line, and the memory cells between adjacent bit lines whose projections overlap in different layers in the vertical direction share the second electrode of the capacitor, thereby forming a 3D stack between the word lines, the bit lines and the memory cells, and obtaining a semi-conductive material structure with a 3D structure.
  • FIG1A shows a schematic cross-sectional view of a single layer of a memory cell array (the legend of FIG1A applies to all drawings except FIG2 and FIG5 ).
  • the memory cell array may include one or more layers stacked in a vertical direction.
  • the memory cell array may include three or more layers.
  • a memory cell array structure having three layers, each layer having three rows and four columns, and a total of 12 memory cells is used as an example.
  • two adjacent columns of memory cells share a bit line, and at this time, four columns of memory cells correspond to two bit lines.
  • a bit line is separately set for each column of memory cells is also within the scope of the description of this application.
  • the memory cell array structure includes:
  • Each layer of storage structure includes a plurality of word lines 120 (shared by the word lines of each layer of storage cells), a plurality of bit lines 110, and a plurality of storage cell structures.
  • Each storage cell structure may include an annular semiconductor layer 160, an annular gate insulating layer 170, a first electrode 130 of a capacitor, a dielectric layer 140 of the capacitor, and a second electrode 150 of the capacitor.
  • a portion of the bit line serves as a source or drain electrode; it can be understood that the bit line also serves as the source or drain (i.e., the first electrode) of the transistor in the corresponding memory cell, and a portion of the word line serves as a gate, which can be understood that the word line also serves as the gate of the transistor in the corresponding memory cell, and the first electrode of the capacitor is shared with the source or drain (i.e., the second electrode) of the transistor.
  • the bit line extends in a first direction, which is parallel to the substrate direction and extends along the column direction while connecting the semiconductor layers of each memory cell in the column direction.
  • the memory cell structures corresponding to the same bit line are arranged in the extending direction of the bit line.
  • the word line extends in a second direction, which is perpendicular to the substrate.
  • the memory cells with overlapping vertical projection positions share the same word line.
  • the word line runs through the memory cell structures of each layer.
  • Each memory cell structure includes a transistor and a capacitor.
  • the transistor includes an annular semiconductor layer, an annular gate insulating layer, a word line that also serves as the gate of the transistor, a bit line that also serves as the source or drain of the transistor, and a first electrode of the capacitor that also serves as the source or drain of the transistor.
  • One side of the annular semiconductor layer contacts the first electrode of the capacitor to form the source or drain of the transistor, and the source or drain of the formed transistor is electrically connected to the capacitor.
  • Another side of the annular semiconductor layer corresponding to the aforementioned side contacts the bit line to form the source or drain of the transistor, and the source or drain of the transistor is electrically connected to the bit line.
  • the inner side of the annular gate insulating layer contacts the word line all around, and different areas of the word line simultaneously serve as the gates of each transistor in the stacked memory cell.
  • the second electrode of the capacitor can be made of a conductive material.
  • the capacitor dielectric in FIG1A wraps around the second electrode of the transistor, and its shape is similar to the three-dimensional space formed by the outer surface of the second electrode. Multiple capacitors share the second electrode.
  • the substrate is an insulating substrate or the upper surface of the substrate is insulated from each component of the memory cell, and any suitable oxide or nitride can be selected.
  • the isolation dielectric of the memory cell array structure can be a low-K dielectric material, such as silicon oxide, silicon nitride, etc.
  • the annular gate insulating layer and the capacitor dielectric layer can use high-K dielectric materials, which can include but are not limited to silicon oxide, aluminum oxide, hafnium oxide, etc.
  • the annular gate insulating layer can include a multilayer annular gate insulating layer of a variety of different materials.
  • the capacitor dielectric layer can use any suitable high-K dielectric material, for example, it can include but is not limited to silicon oxide, aluminum oxide, hafnium oxide, etc.
  • the word line and the bit line can be formed of any suitable conductive material, such as a conductive material (such as copper, cobalt, tungsten, titanium, aluminum, ruthenium, etc.).
  • the annular semiconductor layer type semiconductor layer can be selected from amorphous, polycrystalline or single crystal, and the specific degree of crystallization needs to be selected according to the needs.
  • the material type can be selected from amorphous silicon, polycrystalline silicon, and metal oxide. Group III-V materials can be selected.
  • the metal oxide semiconductor can contain at least one of indium or zinc, and exemplarily, aluminum, gallium, yttrium or tin, etc.
  • the oxide semiconductor may also include one or more of boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.
  • element M may be aluminum, gallium, yttrium or tin, etc., or may be boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc., and may also be a combination of multiple of the above elements.
  • an oxide semiconductor including indium, gallium and zinc may be called indium gallium zinc oxide (IGZO).
  • the oxide semiconductor material includes at least one of indium oxide, tin oxide, indium zinc oxide, tin zinc oxide, aluminum zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, tin gallium zinc oxide, aluminum gallium zinc oxide, and tin aluminum zinc oxide.
  • the first electrode of the capacitor and the bit line have the same thickness.
  • annular semiconductor layer on the periphery of the word lines between the layers in the second direction (z direction). It can be understood that the annular semiconductor layers between the vertically stacked adjacent layers are isolated from each other. In one embodiment, the gate insulating layer is exposed or the gate insulating layer is not leaked, but the annular semiconductor layer between the adjacent layers is modified into an insulating layer.
  • the cross-sectional shape of the annular semiconductor layer may be annular, such as rectangular, square, etc., which is not limited herein.
  • each memory cell in each layer and each memory cell in adjacent layers have a low-K dielectric material to isolate each memory cell.
  • low-K dielectric materials can be, for example, dielectric materials such as silicon oxide, silicon oxynitride, silicon nitride, and silicon carbide.
  • FIG. 1A and FIG. 1B there are 12 memory cells in each layer and 48 memory cells in total in 4 layers.
  • the 48 memory cell structure of the disclosed embodiment uses only 8 bit lines and 12 word lines.
  • the number of bit lines and word lines is much smaller than the number of memory cells, making the memory cell array structure simple and compact, which not only improves the storage density but also facilitates manufacturing.
  • the memory cell array structure further includes a preset number of word line control transistors; each word line control transistor is connected to each word line, and is configured to perform switch control on the connected word line.
  • the switch control of the entire word line is achieved through the word line control transistor (i.e., the switch transistor on the top layer), which facilitates the design of the peripheral circuit in the vertical direction of the array, thereby effectively reducing the circuit area.
  • the word line control transistor is perpendicular to the substrate and is connected to the word line from top to bottom.
  • the peripheral circuit can achieve switch control on the word line through the word line control transistor.
  • the word line control transistor turns on the corresponding word line and the bit line at the same time.
  • the present disclosure also provides a method for manufacturing a memory cell array structure, as shown in FIG2 , including the following steps S11-S14:
  • S13 forming an annular semiconductor layer, an annular gate insulating layer and a word line inside each through hole in the through hole array;
  • the shape of the semiconductor layer is adapted to the shape of the through hole to form an annular cylindrical structure extending in the vertical direction
  • the shape of the annular gate insulating layer is adapted to the shape of the through hole to form an annular cylindrical structure extending in the vertical direction
  • the word line is filled in the hole formed with the semiconductor layer and the annular gate insulating layer to form a word line that runs through the dielectric layers and the conductive material layers.
  • multiple capacitors and multiple through holes are symmetrically distributed on both sides of a bit line, and the capacitor includes a first electrode, a second electrode and a capacitor dielectric layer; the capacitors of the storage units between adjacent bit lines of different layers in the vertical direction share the same second electrode; each layer of bit lines extends along a first direction, and the first direction is parallel to the surface of the insulating substrate; the word line extends along a second direction, and the second direction is perpendicular to the surface of the insulating substrate.
  • the number of capacitors symmetrically distributed on both sides of a bit line can be the same as the number of through holes sharing the bit line; in step S11, as shown in FIG3, the dielectric layer 200 is located on the substrate (not shown), and the conductive material layer 190 is located on the dielectric layer 200.
  • the dielectric layer 200 and the conductive material layer 190 are alternately stacked to form a stack.
  • the dielectric material of the dielectric layer 200 can be a low-K dielectric material, such as silicon oxide, silicon nitride, etc.
  • the material of the conductive material layer can be any suitable conductive material, including but not limited to metals such as copper, cobalt, tungsten, titanium, aluminum, ruthenium, or a conductive layer formed by a semiconductor material.
  • a through hole array penetrating the stacked body can be formed in the stacked body according to the preset through hole positions.
  • 3 rows and 4 columns of 12 through holes 180 are set in Figure 4A.
  • the through hole 180 penetrates all the dielectric layers 200 and the conductive material layer 190, and is perpendicular to the substrate.
  • the through hole in Figure 4A is a square. In other exemplary embodiments of the present disclosure, other shapes, such as rectangles or circles, etc., can also be used, which are not limited here.
  • the through hole can be formed by photolithography and etching.
  • step S13 an annular semiconductor layer, an annular gate insulating layer and a word line are formed inside each through hole of the through hole array, including the following steps S131-S133 (as shown in FIG5 ):
  • a semiconductor layer such as an IGZO layer, may be formed by atomic layer deposition of an annular semiconductor layer. As shown in FIGS. 6A and 6B, the cross-sectional shape of the annular semiconductor layer may be annular.
  • a ring-shaped gate insulating layer is formed around the inner side of the formed ring-shaped semiconductor layer by atomic layer deposition of a high-K dielectric, such as the ring-shaped gate insulating layer 170 shown in FIGS. 6A and 6B.
  • the material of the ring-shaped gate insulating layer 170 may be a high-K dielectric material, such as but not limited to silicon oxide, aluminum oxide, hafnium oxide, etc.
  • the ring-shaped gate insulating layer 170 is in contact with the ring-shaped semiconductor layer 160, and the cross-sectional shape of the ring-shaped gate insulating layer may be a ring, or other suitable shapes.
  • the annular gate insulating layer 170 is filled with a conductive material to form a word line 120.
  • the material of the word line 120 can be any suitable conductive material, such as a conductive material (such as copper, cobalt, tungsten, titanium, aluminum, ruthenium, etc.).
  • the word line 120 runs through the stacked dielectric layer 200 and the conductive material layer 190, and the memory cells with overlapping vertical projections share one word line.
  • FIG. 7A the cross-sectional view after the through hole 180 forms the annular semiconductor layer, the annular gate insulating layer and the word line is shown in FIG. 7A and the longitudinal cross-sectional view is shown in FIG. 7B .
  • step S14 a plurality of capacitors and a plurality of bit lines are formed, including:
  • the region between adjacent columns is etched toward the substrate to etch the conductive layer 190 and the dielectric layer 200 of each layer to obtain a first groove of the three-dimensional stack.
  • the cross section of the first groove (taken along the x direction) is a U-shaped groove.
  • the first groove is formed by etching all the conductive material layers and dielectric layers between each two adjacent groups of through holes and at a preset distance from each group of through holes; for example, FIG. 8A and FIG. 8B show the formed first groove 210.
  • Each group of through holes includes two adjacent columns of through holes, and a portion of the metal layers between two adjacent groups of through holes in the row direction needs to be removed to ensure that the conductive layers 190 of the storage cells corresponding to the two adjacent groups of through holes are isolated, as shown in FIG8B .
  • the entire dielectric layer 200 is selectively etched until the semiconductor layer around the word line of each storage unit is exposed.
  • the annular semiconductor layer on the same layer as the dielectric layer 200 may also be removed.
  • FIG. 9A and FIG. 9B show the structure after etching away all the dielectric layers and removing all the annular semiconductor layers located in the dielectric layer.
  • each conductive material layer is etched according to a preset pattern to form a first electrode of each capacitor and a bit line; as shown in FIG. 10 , a cross-section of the etched first electrode 130 of each capacitor and a bit line 110 is shown.
  • the preset pattern includes a first preset number of parallel first structures and a second structure that penetrates the first preset number of parallel first structures; the first structure is a "I" shaped structure, and the second structure is a “1" shaped structure.
  • the first preset number is the same as the number of through holes in each column.
  • each conductive material layer according to a preset pattern to form the first electrode of each capacitor and the bit line is the pattern of the mask.
  • the preset pattern isolates the bit line and the first electrode, and isolates the first electrodes in the column direction.
  • the first electrodes of the capacitors of each storage unit in the column direction are spaced from each other, and the first electrodes extend along the row direction and contact the semiconductor layer of the corresponding through hole, and the bit line is located between two adjacent columns of through holes and extends along the column direction to contact the semiconductor layer corresponding to each through hole; at this time, the first electrode and the bit line are located in the same layer, and are located in different areas of the side wall of the semiconductor layer, forming a lateral channel, which can also be understood as a horizontal channel.
  • the structure formed at this time is a second stack.
  • the second stack is refilled with dielectric material; wherein the second stack is a stack formed by etching each conductive material layer according to a preset pattern; FIGS. 11A and 11B show the second stack formed after being refilled with dielectric material.
  • a second groove is formed by etching the dielectric material portion between each two adjacent groups of through holes in the second stack, wherein the second groove exposes the first electrodes of each layer of storage cells, and the length of the exposed first electrodes of each storage cell is equal; the second groove 220 is shown in FIGS. 12A and 12B.
  • the second groove is filled with a conductor material to form a second electrode shared by multiple capacitors.
  • Figures 13A and 13B show a capacitor dielectric layer formed by filling a high-K dielectric in the groove after etching the second groove, and a capacitor second electrode formed by filling a conductor outside the groove.
  • the first electrode of the capacitor is essentially a part of the conductive material layer, and the material of the first electrode of the capacitor is the same as that of the conductive material layer. As shown in FIGS. 13A and 13B , the capacitor dielectric layer surrounds the first electrode of the capacitor, and the second electrode of the capacitor surrounds the capacitor dielectric layer. When the preset pattern changes, the shape of the capacitor dielectric layer surrounding the first electrode of the capacitor also changes.
  • the high-K dielectric material of the capacitor dielectric layer may include but is not limited to silicon oxide, aluminum oxide, hafnium oxide, etc.
  • the material of the second electrode of the capacitor may be a conductive material, such as copper, cobalt, tungsten, titanium, aluminum, ruthenium, etc.
  • the annular semiconductor layer in the dielectric layer is generally removed.
  • removing the entire annular semiconductor layer located in the dielectric layer may include:
  • the annular semiconductor layer located on the dielectric layer is etched away.
  • removing all the annular semiconductor layers located in the dielectric layer includes:
  • the chemical is added to inactivate the channel material of the semiconductor layer in the ring shape around the dielectric layer.
  • the manufacturing method further includes forming a plurality of word line control transistors; each word line control transistor is connected to a corresponding word line.
  • Metal is deposited on the word line on the upper surface of the memory cell array structure formed in step S14 and selectively etched to serve as the bottom electrode of the word line control transistor; a low-K dielectric material is deposited on the bottom electrode of the word line control transistor; metal is deposited on the low-K dielectric material, and a through hole is etched at the bottom of the bottom electrode; IGZO is deposited in the through hole by ALD atomic layer to form a channel, and a high-K dielectric material is deposited to form a gate insulating layer; and metal is then filled in the through hole.
  • ALD atomic layer to form a channel
  • a high-K dielectric material is deposited to form a gate insulating layer
  • the memory cell array structure provided by the embodiments of the present disclosure can optimize the process flow of array stacking and reduce manufacturing costs.
  • the present disclosure also provides an electronic device, the electronic device comprising at least a storage device; or at least a storage unit array structure;
  • the storage device comprises:
  • a vertically stacked multi-layer memory cell array wherein the memory cells have transistors and capacitors arranged in sequence in a horizontal direction;
  • Every two adjacent columns of storage units in each layer are a repeating unit, and the repeating units are periodically distributed in the horizontal direction and in the direction vertical to the substrate;
  • the external electrode plate of the capacitor in each storage unit in each repeating unit periodically distributed in the direction perpendicular to the substrate is a common external electrode plate.
  • the two capacitors of the two storage units in any layer and any row respectively include a first inner plate and a second inner plate, the first inner plate and the second inner plate are spaced apart in the row direction, and the common outer plate is arranged between each first inner plate and each second inner plate.
  • the common outer electrode plate fills the area between each of the first inner electrode plates and each of the second inner electrode plates and is insulated from each of the first inner electrode plates and each of the second inner electrode plates by an insulating layer on the surface of each of the first inner electrode plates and each of the second inner electrode plates.
  • each of the first inner pole plates and each of the second inner pole plates extends in a horizontal direction to form a structure having a side surface and an end surface respectively, the end surfaces of each of the first inner pole plates and each of the second inner pole plates are arranged facing each other, and the common outer pole plate is filled between each of the first inner pole plates and each of the second inner pole plates and extends to the side surfaces of each of the first inner pole plates and the side surfaces of each of the second inner pole plates to wrap each of the first inner pole plates and each of the second inner pole plates.
  • the distance that the common outer electrode plate extends to the side surface of the first inner electrode plate or the second inner electrode plate is smaller than the extension length of the first inner electrode plate or the second inner electrode plate in the horizontal direction.
  • the common outer electrode plate extends to each of the first inner electrode plates at an equal distance
  • the common outer electrode plate extends to each of the second inner electrode plates at an equal distance
  • the distance that the common outer electrode plate extends to each of the first inner electrode plates is equal to the distance that the common outer electrode plate extends to each of the second inner electrode plates.
  • the bit line connected to the transistor and the inner plate of the capacitor are located in different regions of the side wall of the word line and the different regions are arranged facing each other;
  • the bit line extends parallel to the substrate and along the column direction and is connected to the transistors of the memory cells in each column direction, wherein two adjacent columns of memory cells share one bit line;
  • bit lines and the common external plates are alternately distributed.
  • the memory cell array structure comprises a substrate, a plurality of stacked memory cells formed on the substrate, a plurality of bit lines and a plurality of word lines; wherein each layer of the memory cells comprises a plurality of rows and columns of memory cells and each memory cell is stacked with a plurality of memory cells at different positions of the substrate, and each memory cell stacked at different layers at the same position shares the same word line, and the word line runs through each stacked memory cell and extends in a direction perpendicular to the substrate;
  • Each storage unit includes a transistor and a capacitor, and the capacitor includes a first electrode, a second electrode and a dielectric layer; the transistor is electrically connected to the first electrode; every two columns of storage units in the same layer are a repeating unit, and in each repeating unit in the stack, the second electrode of each storage unit is a common electrode.
  • each bit line extends along a first direction and is arranged at intervals in a third direction, the first direction is parallel to the substrate along a column direction, and the third direction is parallel to the substrate along a row direction;
  • Each word line extends along a second direction, and the second direction is perpendicular to the substrate surface.
  • memory cells located in the same layer and symmetrically distributed on both sides of the same bit line share the same bit line.
  • capacitors of memory cells between adjacent bit lines in different layers in the vertical direction share the same second electrode.
  • each of the transistors comprises: an annular semiconductor layer surrounding the word line and extending along the side surface of the word line, an annular gate insulating layer, annular semiconductor layer, annular semiconductor layer, gate insulating layer, gate insulating layer, annular semiconductor layer, annular semiconductor layer located between the word line and the annular semiconductor layer;
  • the bit line is parallel to the substrate and extends along the column direction, and the bit line contacts each of the ring-shaped semiconductor layers of a column of the memory cells; the first electrode contacts the ring-shaped semiconductor layer; and a horizontal channel is formed between the first electrode and the bit line.
  • the annular semiconductor layer first electrodes of the memory cells of different layers extend along the row direction, and the common electrode surrounds the sidewalls of the first electrodes and is isolated from the first electrodes by the dielectric layer.
  • the conductive film layer of the first electrode of the capacitor and the conductive film layer of the bit line are conductive film layers made of the same material and are located in the same film layer.
  • the annular semiconductor layer is a metal oxide semiconductor film layer.
  • the memory cell array structure further includes a preset number of word line control transistors; each word line control transistor is connected to each word line, and is configured to perform switching control on the connected word line.
  • 110 represents a bit line
  • 120 represents a word line
  • 130 represents a first electrode of a capacitor
  • 140 represents a capacitor dielectric layer
  • 150 represents a second electrode of a capacitor
  • 160 represents an annular semiconductor layer
  • 170 represents an annular gate insulating layer
  • 180 represents a through hole
  • 190 represents a conductive material layer
  • 200 represents a dielectric layer
  • 210 represents a first groove
  • 220 represents a second groove
  • 230 represents a storage unit.
  • Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium).
  • a computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data).
  • Computer storage media may include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer.
  • communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

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Abstract

一种存储装置、存储单元阵列结构、制造方法和电子设备，其中，存储装置包括：垂直堆叠的多层存储单元阵列，所述存储单元具有水平方向依次排列的晶体管和电容器；各层中每相邻两列存储单元为一个重复单元，所述重复单元在水平方向周期性分布以及在垂直衬底的方向周期性分布；在垂直衬底的方向周期性分布的各重复单元中的各存储单元中的电容器的外极板为公共外极板。

Description

存储装置、存储单元阵列结构、制造方法和电子设备
交叉引用相关申请
本公开涉及于<2022年11月01日>提交的题为“存储单元阵列结构和制备方法”的申请号为<202211358553.5>的中国专利申请。
技术领域
本公开实施例涉及但不限于半导体材料技术领域，尤指一种存储装置、存储单元阵列、制造方法和电子设备。
背景技术
目前，动态随机存取存储器(Dynamic Random Access memory，DRAM)中的存储单元通常采用二维排列，具体的，存储单元在衬底上沿着行列分布。改进存储器通常包含增加存储器单元的密度。
在存储单元二维排列的场景中，一般通过对存储单元进行微缩实现密度提升，比如，缩小位线、字线以及晶体管等的尺寸，以增加更多的存储单元。但是，随着尺寸越来越小制作工艺和产品性能更具挑战，3D堆叠成为器件微缩以提升存储密度的一个技术方向。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种存储装置、存储单元阵列、制造方法和电子设备，与传统工艺相比，不同层的该存储单元可以直接在垂直方向堆叠，可以一次刻蚀多层制作字线、电容外极板，从而优化了阵列堆叠的工艺流程，降低制造成本。
本公开一实施例提供了一种存储装置，包括：
垂直堆叠的多层存储单元阵列，所述存储单元具有水平方向依次排列的 晶体管和电容器；
各层中每相邻两列存储单元为一个重复单元，所述重复单元在水平方向周期性分布以及在垂直衬底的方向周期性分布；
在垂直衬底的方向周期性分布的各重复单元中的各存储单元中的电容器的外极板为公共外极板。
在一种示例性的实施例中，在垂直衬底的方向周期性分布的各重复单元中，任意一层且任意一行的两个存储单元的两个电容器分别包括第一内极板和第二内极板，所述第一内极板和第二内极板在行方向间隔分布，且各所述第一内极板和各所述第二内极板之间设置有所述公共外极板。
在一种示例性的实施例中，其中，所述公共外极板填充于各所述第一内极板和各所述第二内极板之间的区域通过各所述第一内极板和各所述第二内极板表面的绝缘层与各第一内极板和各所述第二内极板绝缘。
在一种示例性的实施例中，其中，所述各第一内极板和各所述第二内极板在水平方向延伸形成分别具有侧表面和端面的结构，各所述第一内极板和各所述第二内极板的端面相向而置，所述公共外极板填充于所述各所述第一内极板和各所述第二内极板之间并延伸到所述各第一内极板的所述侧表面和各所述第二内极板的侧表面包裹各第一内极板和各第二内极板。
在一种示例性的实施例中，其中，所述公共外极板延伸到所述第一内极板或所述第二内极板的侧表面的距离小于所述第一内极板或所述第二内极板的在水平方向的延伸长度。
在一种示例性的实施例中，其中，所述公共外极板延伸到各所述第一内极板的距离相等；
所述公共外极板延伸到各所述第二内极板的距离相等；
所述公共外极板延伸到各所述第一内极板的距离和延伸到各所述第二内极板的距离相等。
在一种示例性的实施例中，其中，所述水平方向依次排列的晶体管和电容器中，所述晶体管连接的位线与所述电容器的内极板位于所述字线的侧壁的不同区域且所述不同区域相向而置；
所述位线沿着平行衬底且沿着列方向延伸与各列方向的存储单元的晶体管相连，其中，相邻两列存储单元共用一条所述位线；
在水平方向，位线和所述公共外极板交替分布。
本公开提供了一种存储单元阵列结构，包括衬底、形成于所述衬底上的多层堆叠的存储单元，多个位线和多个字线；其中每一层所述存储单元包含多行多列存储单元且每个存储单元在衬底的不同位置分别堆叠有多个存储单元，同一位置不同层堆叠的各存储单元共用同一条字线，所述字线贯穿堆叠的各存储单元沿着垂直衬底的方向延伸；
其中，每个存储单元包括一个晶体管和一个电容器，所述电容器包括第一电极、第二电极和电介质层；所述晶体管与所述第一电极电连接；同一层中每两列存储单元为一个重复单元，叠层中的各重复单元中，各存储单元的所述第二电极为一个公共电极。
在一种示例性的实施例中，每个位线沿第一方向延伸且在第三方向间隔排列，所述第一方向平行于所述衬底沿着列方向，所述第三方向平行于所述衬底沿着行方向；
每个字线沿第二方向延伸，第二方向垂直于所述衬底表面。
在一种示例性的实施例中，位于同一层且对称分布于同一位线的两侧的存储单元共用该同一位线。
在一种示例性的实施例中，垂直方向上不同层相邻位线之间的存储单元的电容器共用同一第二电极。
在一种示例性的实施例中，每个所述晶体管包括：环绕所述字线沿着字线的侧表面延伸的环型半导体层，位于所述字线和所述环型半导体层之间的环形栅绝缘层环形半导体层环形半导体层栅绝缘层栅绝缘层环形半导体层环形半导体层；
所述位线在平行衬底且沿着列方向延伸，所述位线与一列所述存储单元的各所述环型半导体层接触；所述第一电极与所述环型半导体层接触；所述第一电极与所述位线之间形成水平沟道。
在一种示例性的实施例中，不同层的存储单元的环形半导体层第一电极 沿着行方向延伸，所述公共电极环绕各所述第一电极的侧壁并通过电介质层与各所述第一电极隔离。
在一种示例性的实施例中，所述电容器的第一电极的导电膜层和位线的导电膜层为相同材料的导电膜层，且位于同一膜层。
在一种示例性的实施例中，所述环形半导体层为金属氧化物半导体膜层。
在一种示例性的实施例中，所述存储单元阵列结构还包括预设数量的字线控制晶体管；每个字线控制晶体管分别与每个字线连接，设置为对所连接的字线进行开关控制。
本公开提供了一种存储单元阵列结构的制造方法，包括：
提供衬底；
在所述衬底上形成介质层与导电材料层交替的第一堆叠体；
在所述第一堆叠体内按照通孔预设位置形成通孔阵列；
在所述通孔阵列的每个通孔内侧形成环形半导体层、环形栅绝缘层和字线；
形成多个电容器和多个位线；
其中，一个位线的两侧对称分布有多个电容器和多个通孔，所述电容器包括第一电极、第二电极和电容器电介质层；垂直方向上不同层相邻位线之间的存储单元的电容器共用同一第二电极；每层位线沿第一方向延伸，第一方向平行于所述衬底表面；字线沿第二方向延伸，第二方向垂直于所述衬底表面。
在一种示例性的实施例中，在所述通孔阵列的每个通孔内侧形成环形半导体层、环形栅绝缘层和字线，包括：
在每个通孔的内侧四周通过原子层沉积半导电材料沟道材料形成环形半导体层；
在形成的环形半导体层的内侧四周通过原子层沉积高K介质形成环形栅绝缘层；
在所述环形栅绝缘层内侧填充导电材料形成字线。
在一种示例性的实施例中，形成多个电容器和多个位线，包括：
通过刻蚀每相邻两组通孔之间且和每组通孔相距预设距离处的全部导电材料层和介质层形成第一槽；其中，每组通孔包括相邻的两列通孔；选择性刻蚀全部介质层，以及去掉全部位于介质层的环形半导体层；
对于每组通孔，根据预设图案刻蚀每个导电材料层，以形成每个电容器的第一电极、以及位线；形成的电容器的第一电极的数量与该组通孔的数量相同；形成的位线的数量与该组通孔所占导电材料层的层数相同；
通过介质材料重新填充第二堆叠体；其中，所述第二堆叠体为根据预设图案刻蚀每个导电材料层形成的堆叠体；
通过刻蚀所述第二堆叠体的每相邻两组通孔之间的部分形成第二槽；
在所述第二槽与电容器的第一电极之间填充介质材料，以形成电容器的电介质层；
在所述第二槽中填充导体，以形成多个电容器共用的第二电极。
本公开提供了一种电子设备，包括，
所述电子设备至少包括存储单元阵列结构；
所述存储单元阵列结构，包括衬底、形成于所述衬底上的多层堆叠的存储单元，多个位线和多个字线；其中每一层所述存储单元包含多行多列存储单元且每个存储单元在衬底的不同位置分别堆叠有多个存储单元，同一位置不同层堆叠的各存储单元共用同一条字线，所述字线贯穿堆叠的各存储单元沿着垂直衬底的方向延伸；
其中，每个存储单元包括一个晶体管和一个电容器，所述电容器包括第一电极、第二电极和电介质层；所述晶体管与所述第一电极电连接；同一层中每两列存储单元为一个重复单元，叠层中的各重复单元中，各存储单元的所述第二电极为一个公共电极。
在一种示例性的实施例中，每个位线沿第一方向延伸且在第三方向间隔排列，所述第一方向平行于所述衬底沿着列方向，所述第三方向平行于所述衬底沿着行方向；
每个字线沿第二方向延伸，第二方向垂直于所述衬底表面。
在一种示例性的实施例中，位于同一层且对称分布于同一位线的两侧的存储单元共用该同一位线。
在一种示例性的实施例中，垂直方向上不同层相邻位线之间的存储单元的电容器共用同一第二电极。
在一种示例性的实施例中，每个所述晶体管包括：环绕所述字线沿着字线的侧表面延伸的环型半导体层，位于所述字线和所述环型半导体层之间的环形栅绝缘层环形半导体层环形半导体层栅绝缘层栅绝缘层环形半导体层环形半导体层；
所述位线在平行衬底且沿着列方向延伸，所述位线与一列所述存储单元的各所述环型半导体层接触；所述第一电极与所述环型半导体层接触；所述第一电极与所述位线之间形成水平沟道。
在一种示例性的实施例中，不同层的存储单元的环形半导体层第一电极沿着行方向延伸，所述公共电极环绕各所述第一电极的侧壁并通过电介质层与各所述第一电极隔离。
在一种示例性的实施例中，所述电容器的第一电极的导电膜层和位线的导电膜层为相同材料的导电膜层，且位于同一膜层。
在一种示例性的实施例中，所述环形半导体层为金属氧化物半导体膜层。
在一种示例性的实施例中，所述存储单元阵列结构还包括预设数量的字线控制晶体管；每个字线控制晶体管分别与每个字线连接，设置为对所连接的字线进行开关控制。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开实施例的技术方案，并不构成对本公开实施例技术方案的限制。
图1A为本公开实施例的存储单元阵列的单层的水平剖面图；
图1B为本公开实施例的存储单元阵列的垂直剖面图；
图2为本公开实施例的存储单元阵列结构的制造方法的流程图；
图3为本公开实施例的存储单元阵列结构的堆叠体的垂直剖面图；
图4A为本公开实施例的存储单元阵列结构的通孔的俯视图；
图4B为本公开实施例的存储单元阵列结构的通孔的垂直剖面图；
图5为本公开实施例的通孔内结构制造方法的示意图；
图6A为本公开实施例的通孔内结构的水平剖面图；
图6B为本公开实施例的通孔内结构的垂直剖面图；
图7A为本公开实施例的形成通孔内部分晶体管后的水平剖面图；
图7B为本公开实施例的形成通孔内部分晶体管后的垂直剖面图；
图8A为本公开实施例的刻蚀出第一槽的水平剖面图；
图8B为本公开实施例的刻蚀出第一槽的垂直剖面图；
图9A为本公开实施例的刻蚀掉介质层和介质层处的环形半导体层的水平剖面图；
图9B为本公开实施例的刻蚀掉介质层和介质层处的环形半导体层的垂直剖面图；
图10为本公开实施例的刻蚀出第一电极和位线的水平剖面图；
图11A为本公开实施例的刻蚀出第一槽后重新填充介质后的水平剖面图；
图11B为本公开实施例的刻蚀出第一槽后重新填充介质后的垂直剖面图；
图12A为本公开实施例的刻蚀出第二槽后的水平剖面图；
图12B为本公开实施例的刻蚀出第二槽后的垂直剖面图；
图13A为本公开实施例的存储单元阵列的单层的水平剖面图；
图13B为本公开实施例的存储单元阵列的垂直剖面图；
图14为本公开实施例的存储单元阵列的立体图。
详述
在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一个电极称为第一极，另一电极称为第二极，第一极可以为源极或者漏极，第二极可 以为漏极或源极，另外，将晶体管的栅极称为控制极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化等情况下，“源极”及“漏极”的功能有时互相调换。因此，在本公开实施例中，“源极”和“漏极”可以互相调换。
本公开提供了一种存储装置，包括：
垂直堆叠的多层存储单元阵列，所述存储单元具有水平方向依次排列的晶体管和电容器；
各层中每相邻两列存储单元为一个重复单元，所述重复单元在水平方向周期性分布以及在垂直衬底的方向周期性分布；
在垂直衬底的方向周期性分布的各重复单元中的各存储单元中的电容器的外极板为公共外极板。
在一种示例性的实施例中，在垂直衬底的方向周期性分布的各重复单元中，任意一层且任意一行的两个存储单元的两个电容器分别包括第一内极板和第二内极板，所述第一内极板和第二内极板在行方向间隔分布，且各所述第一内极板和各所述第二内极板之间设置有所述公共外极板。
在一种示例性的实施例中，其中，所述公共外极板填充于各所述第一内极板和各所述第二内极板之间的区域通过各所述第一内极板和各所述第二内极板表面的绝缘层与各第一内极板和各所述第二内极板绝缘。
在一种示例性的实施例中，其中，所述各第一内极板和各所述第二内极板在水平方向延伸形成分别具有侧表面和端面的结构，各所述第一内极板和各所述第二内极板的端面相向而置，所述公共外极板填充于所述各所述第一内极板和各所述第二内极板之间并延伸到所述各第一内极板的所述侧表面和各所述第二内极板的侧表面包裹各第一内极板和各第二内极板。
在一种示例性的实施例中，其中，所述公共外极板延伸到所述第一内极板或所述第二内极板的侧表面的距离小于所述第一内极板或所述第二内极板的在水平方向的延伸长度。
在一种示例性的实施例中，其中，所述公共外极板延伸到各所述第一内极板的距离相等；
所述公共外极板延伸到各所述第二内极板的距离相等；
所述公共外极板延伸到各所述第一内极板的距离和延伸到各所述第二内极板的距离相等。
在一种示例性的实施例中，其中，所述水平方向依次排列的晶体管和电容器中，所述晶体管连接的位线与所述电容器的内极板位于所述字线的侧壁的不同区域且所述不同区域相向而置；
所述位线沿着平行衬底且沿着列方向延伸与各列方向的存储单元的晶体管相连，其中，相邻两列存储单元共用一条所述位线；
在水平方向，位线和所述公共外极板交替分布。
本公开实施例提供了一种存储单元阵列结构，该存储单元阵列结构包括衬底、形成于所述衬底表面上的三维存储单元阵列，所述三维存储单元阵列包括多层存储单元，以及位于每一层的多个存储单元；还包括多个位线和多个字线。
所述的衬底一般具有上下两个主表面和两个主表面之间的侧表面，所述主表面其中之一可以理解为上表面，另一为下表面。所述的三维存储单元阵列位于所述衬底的上表面在垂直衬底的方向上三维堆叠。本文中提到的垂直衬底的表面如无特别说明是指垂直衬底的上表面。
其中，每个存储单元为1T1C存储单元，包括一个晶体管和一个电容器，所述电容器包括第一电极、第二电极和电容器电介质层；所述第一电极为电容器的内极板，所述第二电极为电容器的外极板；所述晶体管与所述电容器中的其中一个电极电连接；每个位线沿第一方向延伸，第一方向平行于所述衬底表面并沿着列方向(三维空间的y方向)延伸；位于同一层的存储单元，每相邻两列存储单元共用一条位线，每相邻两列存储单元共用一个电容外极板；不同层的存储单元的所述共用的外极板相连作为公共外极板；连接各层中相邻两列存储单元的外极板为一体式设计，可以理解为无分层结构，且各区域采用相同的材料形成。在制作过程中，可以在形成相邻存储单元的电容内极板和电解质层之后露出各层相邻列存储单元之间的电解质层形成贯通各层的沟槽，并使用导电材料填充该露出的沟槽形成公共外极板，因该公共外极板的形状与所述沟槽的形状相适应，该公共外极板也可以理解为公共电容 槽。
如上所述的电容外极板的结构，有利于简化制作工艺，降低成本。
上述内容可以理解为，沿着垂直衬底方向上不同层相邻存储单元的电容器共用同一第二电极；
每个字线沿第二方向延伸，第二方向垂直于所述绝缘衬底表面；垂直方向上不同层的存储单元共用同一字线。
这样，存储单元阵列结构中可以包括多层存储结构，在每一层存储结构中，对称分布于同一位线的两侧的存储单元共用同一位线，垂直方向上投影重合的不同层的存储单元共用同一字线，垂直方向上不同层投影重合的相邻位线之间的存储单元共用电容器的第二电极，从而使得字线、位线以及存储单元之间形成3D堆叠，得到具有3D结构的半导电材料结构。
下面将结合附图对本公开每个实施例进行详细说明。
图1A示出了存储单元阵列的单层的横截面示意图(图1A的图例适用于除图2和图5外的全部附图)。尽管为简单起见示出了单个层，但是存储单元阵列可以包括在垂直方向上堆叠的一个或多个层。例如，存储单元阵列可以包括三个或更多个层。本公开实施例的附图中，以存储单元阵列结构的层数为3层，每层具有3行4列共12个存储单元为例说明。且以相邻两列存储单元共用位线说明，此时4列存储单元对应有2条位线。当然，每一列存储单元单独设置一条位线的实施例也是本申请描述的范围内。
存储单元阵列结构包括：
形成于衬底之上的至少一层存储结构。每一层存储结构均包括多个字线120(各层存储单元的字线共用)、多个位线110和多个存储单元结构。每个存储单元结构可以包括环形半导体层160、环形栅绝缘层170、电容器的第一电极130、电容器的电介质层140、电容器的第二电极150。
一些实施方式中，位线的一部分作为源电或漏电极；可以理解为位线还同时作为对应存储单元中晶体管的源极或漏极(即第一极)，字线的一部分作为栅极，可以理解为字线还同时作为对应存储单元中晶体管的栅极，电容器第一电极同时作为与晶体管的源极或漏极(即第二极)共用。
位线以第一方向延伸，第一方向为平行于衬底方向且沿着列方向延伸同时连接列方向各存储单元的半导体层。对应同一位线的存储单元结构以位线的延伸方向排列。
字线以第二方向延伸，第二方向为垂直于衬底方向。垂直投影位置重合的存储单元共用同一字线。字线贯穿各层的存储单元结构。
每个存储单元结构包括晶体管和电容器。晶体管包括环形半导体层、环形栅绝缘层、同时作为晶体管栅极的字线、同时作为晶体管源极或漏极的位线、同时作为晶体管源极或漏极的电容器第一电极。环形半导体层的一个侧面与电容器第一电极接触，形成晶体管的源极或漏极，并且使形成的晶体管的源极或漏极与电容器电连接。环形半导体层的与前述侧面对应的另一个侧面与位线接触，形成晶体管的源极或漏极，并使晶体管的源极或漏极与位线电连接。环形栅绝缘层的内侧四周与字线接触，字线不同区域同时作为堆叠存储单元中各晶体管的栅极。
电容器第二电极可以由导电材料构成。图1A中的电容器电介质包裹晶体管的第二极，形状与第二极的外表面构成的立体空间类似。多个电容器共用第二电极。
在本公开的示例性实施例中，衬底为绝缘衬底或衬底的上表面与存储单元的每个元器件绝缘，可以选用任何合适的氧化物或氮化物。存储单元阵列结构的隔离介质可以低K介质材料，例如氧化硅、氮化硅等。环形栅绝缘层和电容器电介质层可以使用高K介质材料，可以包括但不限于氧化硅、氧化铝、氧化铪等。环形栅绝缘层可以包括多种不同材料的多层环形栅绝缘层。电容器电介质层可以使用任何合适的高K介质材料，例如可以包括但不限于氧化硅、氧化铝、氧化铪等。字线和位线可以由任何合适的导电材料形成，例如导电材料(例如铜、钴、钨、钛、铝、钌等)。环形半导体层型半导体层可以选用非晶、多晶或单晶，具体的结晶程度需要根据需求选择。材料类型可以选择非晶硅、多晶硅，金属氧化物。可以选择Ⅲ-Ⅴ族材料。金属氧化物半导体可以包含铟或锌中的至少一种，示例性地，包含铝、镓、钇或锡等。示例性地，氧化物半导体也可以包含硼、硅、钛、铁、镍、锗、锆、钼、镧、铈、钕、铪、钽、钨、镁等中的一种或多种。示例性地，以氧化物半导体包 含铟、元素M及锌为例，元素M可以为铝、镓、钇或锡等，也可以为硼、硅、钛、铁、镍、锗、锆、钼、镧、铈、钕、铪、钽、钨、镁等，还可以组合多个上述元素。示例性地，可以为包含铟、镓及锌的氧化物半导体可以称为铟镓锌氧化物(IGZO)。
例如，所述氧化物半导体材料包括氧化铟、氧化锡、铟锌类氧化物、锡锌类氧化物、铝锌类氧化物、铟镓类氧化物、铟镓锌类氧化物、铟铝锌类氧化物、铟锡锌类氧化物、锡镓锌类氧化物、铝镓锌类氧化物、锡铝锌类氧化物中的至少一种。
在本公开的示例性实施例中，所述电容器的第一电极和位线具有相同的厚度。
在本公开的示例性实施例中，为了减少垂直投影重合的晶体管漏电，第二方向(z方向)上层与层之间的字线外周是没有半导体环形半导体层的，可以理解为垂直堆叠的相邻层之间的环形半导体层之间相互隔离，一种实施方式中，露出栅极绝缘层或不漏出栅极绝缘层但是将相邻层之间的环形半导体层改性为绝缘层。
在本公开的示例性实施例中，环形半导体层的截面形状可以为环形，比如矩形、方形等，在此不做限定。
在本公开的示例性实施例中，每层中每个存储单元之间以及相邻层中每个存储单元之间具有低K介质材料以将每个存储单元隔离开。例如，共享同一位线的多个存储单元之间需要隔离；不共享同一位线的存储单元之间也需要隔离；不同层间同一字线的存储单元同样需要隔离(一般采取高K介质材料和低K介质材料隔离)。暴露出的字线与字线之间需要隔离。低K介质材料可以例如是氧化硅、氮氧化硅、氮化硅、碳化硅等电介质材料。
从图1A和图1B看出，每层12个存储单元，4层共48个存储单元，本公开实施例的48个存储单元结构仅使用了8个位线、12个字线，位线、字线数量均大大小于存储单元数量，使得存储单元阵列结构简单、紧凑，不仅提高了存储密度，且便于制造。
在一种示例性的实施例中，所述存储单元阵列结构还包括预设数量的字线控制晶体管；每个字线控制晶体管分别与每个字线连接，设置为对所连接 的字线进行开关控制。通过字线控制晶体管(即顶层的开关晶体管)实现对整个字线的开关控制，便于外围电路在阵列垂直方向的设计，从而有效减小电路面积。字线控制晶体管垂直于衬底，与字线上下相连，外围电路可通过字线控制晶体管实现对字线的开关控制。读写操作时，字线控制晶体管打开对应的字线同时打开位线。
本公开实施例还提供了一种存储单元阵列结构的制造方法，如图2所示，包括如下S11-S14步骤：
S11、提供衬底；在所述衬底上形成介质层与导电材料层交替的第一堆叠体；
S12、在所述第一堆叠体内按照通孔预设位置形成从堆叠体的顶层到底层的通孔阵列，每个通孔贯穿所述各介质层与导电材料层；
S13、在所述通孔阵列的每个通孔内侧形成环形半导体层、环形栅绝缘层和字线；所述半导体层的形状与所述通孔的形状相适应，形成垂直方向延伸的环形筒状结构，环形栅绝缘层的形状与所述通孔的形状相适应，形成垂直方向延伸的环形筒状结构，字线填充于形成有半导体层和环形栅绝缘层的孔内，形成贯穿所述各介质层与导电材料层的字线。
S14、形成多个电容器和多个位线；
其中，一个位线的两侧对称分布有多个电容器和多个通孔，所述电容器包括第一电极、第二电极和电容器电介质层；垂直方向上不同层相邻位线之间的存储单元的电容器共用同一第二电极；每层位线沿第一方向延伸，第一方向平行于所述绝缘衬底表面；字线沿第二方向延伸，第二方向垂直于所述绝缘衬底表面。
一个位线两侧对称分布的电容器的数量可以与共用该位线的通孔的数量相同；在S11步骤中，如图3所示，衬底(未示出)的上面是介质层200，介质层200的上面是导电材料层190。介质层200和导电材料层190交替堆叠，形成堆叠体。介质层200的介质材料可以是低K介质材料，例如氧化硅、氮化硅等。导电材料层的材料可以是任何合适的导电材料，包括但不限于铜、钴、钨、钛、铝、钌等金属，或半导体材料形成的导电层。
在S12步骤中，可以按照预设通孔位置在堆叠体中形成贯穿堆叠体的通孔阵列。如图4A、4B所示，图4A中设置了3行4列共12个通孔180。如图4B通孔180贯穿了全部介质层200和导电材料层190，且垂直于衬底。图4A中的通孔为正方形，在本公开的其他示例性实施例中，也可以采用其他形状，例如长方形或圆形等，在此不做限制。在本公开的示例性实施例中，可以通过光刻和刻蚀的方式形成通孔。
在S13步骤中，在所述通孔阵列的每个通孔内侧形成环形半导体层、环形栅绝缘层和字线，包括如下步骤S131-S133(如图5所示)：
S131、在每个通孔的内侧四周通过原子层沉积半导电材料形成环形半导体层；
S132、在形成的环形半导体层的内侧四周通过原子层沉积(ALD)高K介质形成环形栅绝缘层；
S133、在所述环形栅绝缘层内侧填充导电材料形成字线。
在S131步骤中，对于每个通孔，可以通过原子层沉积环形半导体层法形成半导体层，比如，IGZO层。如图6A、6B中的环形半导体层的横截面形状可以为环形。
在S132步骤中，在形成的环形半导体层的内侧四周通过原子层沉积高K介质形成环形栅绝缘层，如图6A、6B所示的环形栅绝缘层170。环形栅绝缘层170的材料可以为高K介质材料，例如可以包括但不限于氧化硅、氧化铝、氧化铪等。环形栅绝缘层170与环形半导体层160接触，环形栅绝缘层的横截面形状可以为环形，当然也可以是其他适合的形状。
在S133步骤中，在环形栅绝缘层170内用导电材料填充形成字线120，字线120的材料可以为任何合适的导电材料，例如导电材料(例如铜、钴、钨、钛、铝、钌等)。字线120贯穿堆叠体介质层200和导电材料层190，垂直投影重合的存储单元共享一个字线。
以图4A、图4B所示结构为例，通孔180形成环形半导体层、环形栅绝缘层和字线后的横截面图如图7A所示和纵截面图如图7B所示。
在S14步骤中，形成多个电容器和多个位线，包括：
对相邻列之间的区域进行朝向衬底方向的刻蚀，刻蚀各层的导电层190和介质层200，得到三维叠层的第一槽，该第一槽的横截面(沿着x的方向截取)为U型槽。
可以理解为通过刻蚀每相邻两组通孔之间且和每组通孔相距预设距离处的全部导电材料层和介质层形成第一槽；例如，图8A和图8B示出了形成的第一槽210。
其中，每组通孔包括相邻的两列通孔，需要对行方向相邻的两组通孔之间各层的金属去除一部分，确保相邻两组通孔对应的存储单元的导电层190隔离，如图8B所示。
接着，针对每一组通孔对应的3D叠层结构，选择性刻蚀全部介质层200直到露出每个存储单元的字线周边的半导体层，一些实施例中，还可以去掉与介质层200同层的环形半导体层；图9A和图9B示出了刻蚀掉全部介质层，以及去掉全部位于介质层的环形半导体层后的结构图。
接着，对于每组通孔对应的存储单元，根据预设图案刻蚀每个导电材料层，以形成每个电容器的第一电极、以及位线；如图10所示，示出了刻蚀出的每个电容器的第一电极130、以及位线110的横截面。
所述预设图案包括第一预设数量的平行的第一结构和贯穿第一预设数量的平行的第一结构的第二结构；第一结构为“一”字形结构，第二结构为“1”字形结构。第一预设数量与每列通孔的数量相同。
上述的根据预设图案刻蚀每个导电材料层，以形成每个电容器的第一电极、以及位线，预设图案为掩模版的图案。预设图案使得位线和第一电极隔离，且列方向的各第一电极之间隔离。其中，在列方向的各存储单元的电容器的第一电极相互间隔，且该第一电极沿着行方向延伸且与对应的通孔的半导体层接触，位线位于相邻两列通孔之间沿着列方向延伸与各通孔对应的半导体层接触；此时，第一电极和位线位于同一层，且位于半导体层侧壁的不同区域，形成横向沟道，也可以理解为水平沟道。此时形成的结构为第二堆叠体。
通过介质材料重新填充所述第二堆叠体；其中，第二堆叠体为根据预设图案刻蚀每个导电材料层形成的堆叠体；图11A和图11B示出了通过介质材 料重新填充后形成的第二堆叠体。
通过刻蚀所述第二堆叠体的每相邻两组通孔之间的介质材料部分形成第二槽，所述第二槽露出各层存储单元的所述第一电极，各存储单元露出的第一电极的长度相等；如图12A、12B示出了第二槽220。
在所述第二槽220露出的第一电极上形成介质材料，以形成电容器的电介质层；
在所述第二槽中填充导体材料，以形成多个电容器共用的第二电极。如图13A、13B所示，图13A、13B示出了刻蚀出第二槽后在槽内填充高K介质形成的电容器电介质层，以及在槽外填充导体形成的电容器第二电极。
电容器的第一电极实质为部分导电材料层，电容器第一电极的材料与导电材料层材料相同。如图13A、13B所示，电容器电介质层包围电容器第一电极，电容器第二电极包围电容器电介质层。当预设图案发生变化时，电容器电介质层包围电容器第一电极的形状也随着变化。
在本公开的示例性实施例中，电容器电介质层的高K介质材料可以包括但不限于氧化硅、氧化铝、氧化铪等。电容器第二电极的材料可以为导电材料材料，例如铜、钴、钨、钛、铝、钌等。
在本公开的示例性实施例中，为了减少上下两层相邻的晶体管漏电，一般去除介质层中的环形半导体层。
在本公开的示例性实施例中，去掉全部位于介质层的环形半导体层，可以包括：
蚀刻掉位于介质层的环形半导体层。
在本公开的示例性实施例中，去掉全部位于介质层的环形半导体层，包括：
添加化学物质使位于介质层的环形半导体层的沟道材料失活。
在一种示例性的实施例中，该制造方法还包括在一种示例性的实施例中，该制造方法还包括形成多个字线控制晶体管；每个字线控制晶体管与对应的一个字线连接。
在步骤S14形成的存储单元阵列结构的上表面的字线上沉积金属并选择 性刻蚀，作为字线控制晶体管的底部电极；在字线控制晶体管的底部电极沉积低K介质材料；在低K介质材料上沉积金属，并刻蚀出下部位于底部电极的通孔；在通孔内通过ALD原子层沉积IGZO，形成沟道，再通过沉积高K介质材料，形成栅绝缘层；然后在通孔内填充金属。从而完成字线控制晶体管的制备。
本公开实施例提供的存储单元阵列结构能够优化阵列堆叠的工艺流程，降低制造成本。
本公开还提供了一种电子设备，所述电子设备至少包括存储装置；或者至少包括存储单元阵列结构；
所述存储装置，包括：
垂直堆叠的多层存储单元阵列，所述存储单元具有水平方向依次排列的晶体管和电容器；
各层中每相邻两列存储单元为一个重复单元，所述重复单元在水平方向周期性分布以及在垂直衬底的方向周期性分布；
在垂直衬底的方向周期性分布的各重复单元中的各存储单元中的电容器的外极板为公共外极板。
在一种示例性的实施例中，在垂直衬底的方向周期性分布的各重复单元中，任意一层且任意一行的两个存储单元的两个电容器分别包括第一内极板和第二内极板，所述第一内极板和第二内极板在行方向间隔分布，且各所述第一内极板和各所述第二内极板之间设置有所述公共外极板。
在一种示例性的实施例中，其中，所述公共外极板填充于各所述第一内极板和各所述第二内极板之间的区域通过各所述第一内极板和各所述第二内极板表面的绝缘层与各第一内极板和各所述第二内极板绝缘。
在一种示例性的实施例中，其中，所述各第一内极板和各所述第二内极板在水平方向延伸形成分别具有侧表面和端面的结构，各所述第一内极板和各所述第二内极板的端面相向而置，所述公共外极板填充于所述各所述第一内极板和各所述第二内极板之间并延伸到所述各第一内极板的所述侧表面和各所述第二内极板的侧表面包裹各第一内极板和各第二内极板。
在一种示例性的实施例中，其中，所述公共外极板延伸到所述第一内极板或所述第二内极板的侧表面的距离小于所述第一内极板或所述第二内极板的在水平方向的延伸长度。
在一种示例性的实施例中，其中，所述公共外极板延伸到各所述第一内极板的距离相等；
所述公共外极板延伸到各所述第二内极板的距离相等；
所述公共外极板延伸到各所述第一内极板的距离和延伸到各所述第二内极板的距离相等。
在一种示例性的实施例中，其中，所述水平方向依次排列的晶体管和电容器中，所述晶体管连接的位线与所述电容器的内极板位于所述字线的侧壁的不同区域且所述不同区域相向而置；
所述位线沿着平行衬底且沿着列方向延伸与各列方向的存储单元的晶体管相连，其中，相邻两列存储单元共用一条所述位线；
在水平方向，位线和所述公共外极板交替分布。
所述存储单元阵列结构，包括衬底、形成于所述衬底上的多层堆叠的存储单元，多个位线和多个字线；其中每一层所述存储单元包含多行多列存储单元且每个存储单元在衬底的不同位置分别堆叠有多个存储单元，同一位置不同层堆叠的各存储单元共用同一条字线，所述字线贯穿堆叠的各存储单元沿着垂直衬底的方向延伸；
其中，每个存储单元包括一个晶体管和一个电容器，所述电容器包括第一电极、第二电极和电介质层；所述晶体管与所述第一电极电连接；同一层中每两列存储单元为一个重复单元，叠层中的各重复单元中，各存储单元的所述第二电极为一个公共电极。
在一种示例性的实施例中，每个位线沿第一方向延伸且在第三方向间隔排列，所述第一方向平行于所述衬底沿着列方向，所述第三方向平行于所述衬底沿着行方向；
每个字线沿第二方向延伸，第二方向垂直于所述衬底表面。
在一种示例性的实施例中，位于同一层且对称分布于同一位线的两侧的 存储单元共用该同一位线。
在一种示例性的实施例中，垂直方向上不同层相邻位线之间的存储单元的电容器共用同一第二电极。
在一种示例性的实施例中，每个所述晶体管包括：环绕所述字线沿着字线的侧表面延伸的环型半导体层，位于所述字线和所述环型半导体层之间的环形栅绝缘层环形半导体层环形半导体层栅绝缘层栅绝缘层环形半导体层环形半导体层；
所述位线在平行衬底且沿着列方向延伸，所述位线与一列所述存储单元的各所述环型半导体层接触；所述第一电极与所述环型半导体层接触；所述第一电极与所述位线之间形成水平沟道。
在一种示例性的实施例中，不同层的存储单元的环形半导体层第一电极沿着行方向延伸，所述公共电极环绕各所述第一电极的侧壁并通过电介质层与各所述第一电极隔离。
在一种示例性的实施例中，所述电容器的第一电极的导电膜层和位线的导电膜层为相同材料的导电膜层，且位于同一膜层。
在一种示例性的实施例中，所述环形半导体层为金属氧化物半导体膜层。
在一种示例性的实施例中，所述存储单元阵列结构还包括预设数量的字线控制晶体管；每个字线控制晶体管分别与每个字线连接，设置为对所连接的字线进行开关控制。
附图中的110表示位线，120表示字线，130表示电容器的第一电极，140表示电容器电介质层，150表示电容器的第二电极，160表示环形半导体层，170表示环形栅绝缘层，180表示通孔，190表示导电材料层，200表示介质层，210表示第一槽，220表示第二槽，230表示一个存储单元。
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说显而易见的是，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的 任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。
此外，在描述具有代表性的实施例时，说明书可能已经将方法和/或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由多个物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质可以包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机存取的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。

Claims (20)

  1. 一种存储装置，其中，包括：
    垂直堆叠的多层存储单元阵列，所述存储单元具有水平方向依次排列的晶体管和电容器；
    各层中每相邻两列存储单元为一个重复单元，所述重复单元在水平方向周期性分布以及在垂直衬底的方向周期性分布；
    在垂直衬底的方向周期性分布的各重复单元中的各存储单元中的电容器的外极板为公共外极板。
  2. 根据权利要求1所述的存储装置，其中，
    在垂直衬底的方向周期性分布的各重复单元中，任意一层且任意一行的两个存储单元的两个电容器分别包括第一内极板和第二内极板，所述第一内极板和第二内极板在行方向间隔分布，且各所述第一内极板和各所述第二内极板之间设置有所述公共外极板。
  3. 根据权利要求2所述的存储装置，其中，所述公共外极板填充于各所述第一内极板和各所述第二内极板之间的区域通过各所述第一内极板和各所述第二内极板表面的绝缘层与各第一内极板和各所述第二内极板绝缘。
  4. 根据权利要求3所述的存储装置，其中，所述各第一内极板和各所述第二内极板在水平方向延伸形成分别具有侧表面和端面的结构，各所述第一内极板和各所述第二内极板的端面相向而置，所述公共外极板填充于所述各所述第一内极板和各所述第二内极板之间并延伸到所述各第一内极板的所述侧表面和各所述第二内极板的侧表面包裹各第一内极板和各第二内极板。
  5. 根据权利要求4所述的存储装置，其中，所述公共外极板延伸到所述第一内极板或所述第二内极板的侧表面的距离小于所述第一内极板或所述第 二内极板的在水平方向的延伸长度。
  6. 根据权利要求5所述的存储装置，其中，所述公共外极板延伸到各所述第一内极板的距离相等；
    所述公共外极板延伸到各所述第二内极板的距离相等；
    所述公共外极板延伸到各所述第一内极板的距离和延伸到各所述第二内极板的距离相等。
  7. 根据权利要求1所述的存储装置，其中，所述水平方向依次排列的晶体管和电容器中，所述晶体管连接的位线与所述电容器的内极板位于所述字线的侧壁的不同区域且所述不同区域相向而置；
    所述位线沿着平行衬底且沿着列方向延伸与各列方向的存储单元的晶体管相连，其中，相邻两列存储单元共用一条所述位线；
    在水平方向，位线和所述公共外极板交替分布。
  8. 一种存储单元阵列结构，包括：
    包括衬底、形成于所述衬底上的多层堆叠的存储单元，多个位线和多个字线；其中每一层所述存储单元包含多行多列存储单元且每个存储单元在衬底的不同位置分别堆叠有多个存储单元，同一位置不同层堆叠的各存储单元共用同一条字线，所述字线贯穿堆叠的各存储单元沿着垂直衬底的方向延伸；
    其中，每个存储单元包括一个晶体管和一个电容器，所述电容器包括第一电极、第二电极和电介质层；所述晶体管与所述第一电极电连接；同一层中每两列存储单元为一个重复单元，叠层中的各重复单元中，各存储单元的所述第二电极为一个公共电极。
  9. 如权利要求8所述的存储单元阵列结构，包括：每个位线沿第一方向延伸且在第三方向间隔排列，所述第一方向平行于所述衬底沿着列方向，所述第三方向平行于所述衬底沿着行方向；
    每个字线沿第二方向延伸，第二方向垂直于所述衬底表面。
  10. 如权利要求8所述的存储单元阵列结构，包括：
    位于同一层且对称分布于同一位线的两侧的存储单元共用该同一位线。
  11. 如权利要求8所述的存储单元阵列结构，包括：垂直方向上不同层相邻位线之间的存储单元的电容器共用同一第二电极。
  12. 如权利要求8所述的存储单元阵列结构，包括：
    每个所述晶体管包括：环绕所述字线沿着字线的侧表面延伸的环型半导体层，位于所述字线和所述环型半导体层之间的环形栅绝缘层环形半导体层环形半导体层栅绝缘层栅绝缘层环形半导体层环形半导体层；
    所述位线在平行衬底且沿着列方向延伸，所述位线与一列所述存储单元的各所述环型半导体层接触；所述第一电极与所述环型半导体层接触；所述第一电极与所述位线之间形成水平沟道。
  13. 如权利要求8所述的存储单元阵列结构，包括：
    不同层的存储单元的环形半导体层第一电极沿着行方向延伸，所述公共电极环绕各所述第一电极的侧壁并通过电介质层与各所述第一电极隔离。
  14. 如权利要求13所述的存储单元阵列结构，包括：
    所述电容器的第一电极的导电膜层和位线的导电膜层为相同材料的导电膜层，且位于同一膜层。
  15. 如权利要求1所述的存储单元阵列结构，包括：
    所述环形半导体层为金属氧化物半导体膜层。
  16. 如权利要求8所述的存储单元阵列结构，包括：
    所述存储单元阵列结构还包括预设数量的字线控制晶体管；每个字线控 制晶体管分别与每个字线连接，设置为对所连接的字线进行开关控制。
  17. 一种存储单元阵列结构的制造方法，应用于权利要求8-16任一项的存储单元阵列结构，包括：
    提供衬底；
    在所述衬底上形成介质层与导电材料层交替的第一堆叠体；
    在所述第一堆叠体内按照通孔预设位置形成通孔阵列；
    在所述通孔阵列的每个通孔内侧形成环形半导体层、环形栅绝缘层和字线；
    形成多个电容器和多个位线；
    其中，一个位线的两侧对称分布有多个电容器和多个通孔，所述电容器包括第一电极、第二电极和电容器电介质层；垂直方向上不同层相邻位线之间的存储单元的电容器共用同一第二电极；每层位线沿第一方向延伸，第一方向平行于所述衬底表面；字线沿第二方向延伸，第二方向垂直于所述衬底表面。
  18. 如权利要求17所述的制造方法，包括：
    在所述通孔阵列的每个通孔内侧形成环形半导体层、环形栅绝缘层和字线，包括：
    在每个通孔的内侧四周通过原子层沉积半导电材料沟道材料形成环形半导体层；
    在形成的环形半导体层的内侧四周通过原子层沉积高K介质形成环形栅绝缘层；
    在所述环形栅绝缘层内侧填充导电材料形成字线。
  19. 如权利要求18所述的制造方法，包括：
    形成多个电容器和多个位线，包括：
    通过刻蚀每相邻两组通孔之间且和每组通孔相距预设距离处的全部导电材料层和介质层形成第一槽；其中，每组通孔包括相邻的两列通孔；选择性刻蚀全部介质层，以及去掉全部位于介质层的环形半导体层；
    对于每组通孔，根据预设图案刻蚀每个导电材料层，以形成每个电容器的第一电极、以及位线；形成的电容器的第一电极的数量与该组通孔的数量相同；形成的位线的数量与该组通孔所占导电材料层的层数相同；
    通过介质材料重新填充第二堆叠体；其中，所述第二堆叠体为根据预设图案刻蚀每个导电材料层形成的堆叠体；
    通过刻蚀所述第二堆叠体的每相邻两组通孔之间的部分形成第二槽；
    在所述第二槽与电容器的第一电极之间填充介质材料，以形成电容器的电介质层；
    在所述第二槽中填充导体，以形成多个电容器共用的第二电极。
  20. 一种电子设备，包括，权利要求1-7任一所述的存储装置，或，权利要求8-16任一所述的存储单元阵列结构。
PCT/CN2022/140444 2022-11-01 2022-12-20 存储装置、存储单元阵列结构、制造方法和电子设备 WO2024092986A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104022120A (zh) * 2014-06-23 2014-09-03 中国科学院微电子研究所 三维半导体器件及其制造方法
US20190096808A1 (en) * 2017-09-27 2019-03-28 Sandisk Technologies Llc Three-dimensional memory device with gated contact via structures and method of making thereof
CN110277404A (zh) * 2019-06-27 2019-09-24 长江存储科技有限责任公司 3d存储器件及其制造方法
CN111435661A (zh) * 2019-01-14 2020-07-21 英特尔公司 3d 1t1c堆叠dram结构及制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6576945B2 (en) * 2001-02-05 2003-06-10 International Business Machines Corporation Structure and method for a compact trench-capacitor DRAM cell with body contact
JP2002270788A (ja) * 2001-03-14 2002-09-20 Fujitsu Ltd 半導体装置及びその製造方法
JP2003007850A (ja) * 2001-06-18 2003-01-10 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
KR100869353B1 (ko) * 2007-06-26 2008-11-19 주식회사 하이닉스반도체 수직 채널 트랜지스터를 구비한 반도체 소자의 제조 방법
CN102544049B (zh) * 2010-12-22 2014-04-16 中国科学院微电子研究所 三维半导体存储器件及其制备方法
KR102513205B1 (ko) * 2017-01-27 2023-03-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 용량 소자, 반도체 장치, 및 반도체 장치의 제작 방법
CN114709219A (zh) * 2020-05-18 2022-07-05 长江存储科技有限责任公司 3d存储器件及其制造方法
US11502128B2 (en) * 2020-06-18 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device and method of forming the same
US20220139918A1 (en) * 2020-10-29 2022-05-05 Sang-Yun Lee Novel Three-Dimensional DRAM Structures
CN114927526A (zh) * 2022-06-02 2022-08-19 北京超弦存储器研究院 一种铁电存储器及其铁电电容和制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104022120A (zh) * 2014-06-23 2014-09-03 中国科学院微电子研究所 三维半导体器件及其制造方法
US20190096808A1 (en) * 2017-09-27 2019-03-28 Sandisk Technologies Llc Three-dimensional memory device with gated contact via structures and method of making thereof
CN111435661A (zh) * 2019-01-14 2020-07-21 英特尔公司 3d 1t1c堆叠dram结构及制造方法
CN110277404A (zh) * 2019-06-27 2019-09-24 长江存储科技有限责任公司 3d存储器件及其制造方法

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