WO2023245352A1 - 芯片结构及其制备方法、显示基板和显示装置 - Google Patents

芯片结构及其制备方法、显示基板和显示装置 Download PDF

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WO2023245352A1
WO2023245352A1 PCT/CN2022/099909 CN2022099909W WO2023245352A1 WO 2023245352 A1 WO2023245352 A1 WO 2023245352A1 CN 2022099909 W CN2022099909 W CN 2022099909W WO 2023245352 A1 WO2023245352 A1 WO 2023245352A1
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layer
sub
substrate
unit
initial
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PCT/CN2022/099909
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English (en)
French (fr)
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李伟
王明星
张笑
玄明花
张粲
王灿
张栋梁
靳倩
李翔
张晶晶
牛晋飞
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京东方科技集团股份有限公司
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Priority to CN202280001819.2A priority Critical patent/CN117616577A/zh
Priority to PCT/CN2022/099909 priority patent/WO2023245352A1/zh
Publication of WO2023245352A1 publication Critical patent/WO2023245352A1/zh

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  • the present disclosure relates to the field of display technology, and in particular, to a chip structure and a preparation method thereof, a display substrate and a display device.
  • Micro-LED (micro light-emitting diode) display devices are a new generation of display technology with the advantages of high brightness, high luminous efficiency, low power consumption, and fast response speed.
  • Micro-LED microwave light-emitting diode
  • a chip structure includes: a chip wafer unit and a color conversion layer unit disposed on the light exit side of the chip wafer unit; wherein the chip wafer unit includes a plurality of sub-pixel light-emitting functional layers;
  • the color conversion layer unit includes a color conversion layer disposed on the light exit side of the chip wafer unit.
  • the chip structure further includes: a bonding layer, the bonding layer is provided between the chip wafer unit and the color conversion layer unit, and is used to bond the chip wafer unit and the color conversion layer unit.
  • the bonding layer is any one of an indium zinc oxide bonding layer, a metal bonding layer, and an adhesive layer.
  • the size of the adhesion layer in the first direction is smaller than the distance between two adjacent sub-pixel light-emitting functional layers in the plurality of sub-pixel light-emitting functional layers.
  • the first direction is a direction from the chip wafer unit to the color conversion layer unit.
  • the adhesion layer is the indium zinc oxide bonding layer, and the size of the indium zinc oxide bonding layer in the first direction ranges from 100 nm to 300 nm.
  • the adhesion layer is the metal bonding layer, and the size of the metal bonding layer in the first direction ranges from 6 ⁇ m to 12 ⁇ m.
  • the lamination layer is the adhesive layer, and the size range of the adhesive layer in the first direction is 5 ⁇ m to 10 ⁇ m.
  • the bonding layer is the indium zinc oxide bonding layer
  • the indium zinc oxide bonding layer includes a first indium zinc oxide layer and a second indium zinc oxide layer stacked along a first direction.
  • the first indium zinc oxide layer and the second indium zinc oxide layer are connected through molecular bonding.
  • the adhesion layer is the metal bonding layer
  • the metal bonding layer includes a first sub-metal layer, a second sub-metal layer and a third sub-metal layer that are stacked along a first direction, and the third sub-metal layer
  • the two sub-metal layers are arranged as eutectic alloy layers connecting the first sub-metal layer and the third sub-metal layer.
  • the first direction is a direction from the chip wafer unit to the color conversion layer unit.
  • the adhesion layer is the indium zinc oxide bonding layer, and the projection of the indium zinc oxide bonding layer on the multiple sub-pixel light-emitting functional layers covers the multiple sub-pixel light-emitting functions. layer.
  • the adhesion layer is the metal bonding layer, and the metal bonding layer is provided with opening areas corresponding to the plurality of sub-pixel light-emitting functional layers.
  • the adhesion layer is the adhesive layer, and the projection of the adhesive layer on the multiple sub-pixel light-emitting functional layers covers the multiple sub-pixel light-emitting functional layers.
  • the chip structure further includes a first substrate, the first substrate is disposed on a side of the color conversion layer unit away from the chip wafer unit; the color conversion layer unit is on the first A projection on a substrate covers the projection of the lamination layer on the first substrate.
  • the distance between the projection boundary of the color conversion layer unit on the first substrate and the projection boundary of the lamination layer on the first substrate ranges from 0 ⁇ m to 10 ⁇ m.
  • each of the plurality of sub-pixel light-emitting functional layers includes an anode electrode, a current spreading layer, a p-type gallium nitride layer and a quantum well layer that are stacked along a first direction.
  • the chip wafer unit further includes a common cathode layer, which includes a cathode electrode and a cathode metal layer that are stacked along the first direction.
  • the cathode metal layer further includes a portion located between two adjacent sub-pixel light-emitting functional layers; the first direction is a direction from the chip wafer unit to the color conversion layer unit.
  • the spacing range between the sub-pixel light-emitting functional layer and the cathode metal layer is 1/10 to 1/3 of the spacing range between two adjacent sub-pixel light-emitting functional layers.
  • the spacing range between two adjacent anode electrodes is less than or equal to the two sub-pixel light-emitting functional layers where the two anode electrodes are located. spacing range between.
  • the chip wafer unit further includes an n-type gallium nitride layer and a gallium nitride buffer layer that are stacked along the first direction; the n-type gallium nitride layer is arranged to emit light from the plurality of sub-pixels. The light exit side of the functional layer.
  • the adhesion layer is disposed on a side of the gallium nitride buffer layer away from the n-type gallium nitride layer; the first direction is a direction from the chip wafer unit to the color conversion layer unit.
  • the plurality of sub-pixel light-emitting functional layers include a first sub-pixel light-emitting functional layer, a second sub-pixel light-emitting functional layer and a third sub-pixel light-emitting functional layer.
  • the chip structure also includes a first substrate, and the color conversion layer unit includes a color filter layer disposed on one side of the first substrate; the color filter layer includes a black matrix layer, and the color conversion layer unit is composed of a black matrix layer and a black matrix layer.
  • a plurality of defined filter film layers; the plurality of filter film layers include: a first filter film layer, a second filter film layer and a third filter film layer, the first filter film layer and the The first sub-pixel light-emitting functional layer is arranged correspondingly, the second filter film layer and the second sub-pixel light-emitting functional layer are arranged correspondingly, and the third filter film layer and the third sub-pixel light-emitting functional layer are arranged correspondingly.
  • the color conversion layer unit further includes a limiting dam layer disposed on a side of the color filter layer away from the first substrate.
  • the limiting dam layer is provided with a plurality of opening areas; the plurality of opening areas include: An opening area, a second opening area and a third opening area; the first opening area is provided corresponding to the first sub-pixel light-emitting functional layer, and the second opening area is corresponding to the second sub-pixel light-emitting functional layer The third opening area is arranged corresponding to the third sub-pixel light-emitting functional layer.
  • the color conversion layer also includes a first quantum dot conversion part, a second quantum dot conversion part and a scattering particle part; the first quantum dot conversion part is disposed in the first opening area, and the scattering particle part is disposed in In the second opening area, the second quantum dot conversion part is disposed in the third opening area.
  • the projection of the filter film layer on the first substrate covers the projection of the sub-pixel light-emitting functional layer corresponding to the filter film layer on the first substrate.
  • the projection of the quantum dot conversion part on the first substrate covers the projection of the filter film layer corresponding to the quantum dot conversion part on the first substrate.
  • the projection of the scattering particle part on the first substrate covers the projection of the second filter film layer on the first substrate.
  • the projection boundary of the filter film layer on the first substrate, and the projection of the sub-pixel light-emitting functional layer corresponding to the filter film layer on the first substrate The distance between the boundaries ranges from 20 ⁇ m to 60 ⁇ m.
  • the projection boundary of the quantum dot conversion part on the first substrate and the projection boundary of the filter film layer corresponding to the quantum dot conversion part on the first substrate range from 23 ⁇ m to 68 ⁇ m.
  • the distance between the projection boundary of the scattering particle part on the first substrate and the projection boundary of the second filter film layer on the first substrate ranges from 23 ⁇ m to 68 ⁇ m.
  • the size of the limiting dam layer in the first direction ranges from 10 ⁇ m to 30 ⁇ m.
  • the first direction is a direction from the chip wafer unit to the color conversion layer unit.
  • the method for preparing a chip structure includes: forming an initial chip wafer unit.
  • the initial chip wafer unit includes a temporary substrate arranged in a stack, a plurality of sub-pixel light-emitting functional layers, n A gallium nitride layer and a gallium nitride buffer layer; forming a color conversion layer unit on one side of the initial first substrate; attaching the color conversion layer unit to the initial chip crystal On the light exit side of the circular unit, a chip wafer unit and a color conversion layer unit are formed to obtain a chip structure.
  • the step of attaching the color conversion layer unit to the light exit side of the initial chip wafer unit includes: forming a layer on a side of the initial chip wafer unit away from the temporary substrate. a first indium zinc oxide layer; forming a second indium zinc oxide layer on the side of the color conversion layer unit away from the initial first substrate; bonding the first indium zinc oxide layer and the second indium oxide The zinc layer forms a bonding layer connecting the initial chip wafer unit and the color conversion layer unit.
  • the step of attaching the color conversion layer unit to the light exit side of the initial chip wafer unit includes: forming a layer on a side of the initial chip wafer unit away from the temporary substrate.
  • the step of attaching the color conversion layer unit to the light exit side of the initial chip wafer unit includes: using a bonding glue to connect the initial chip wafer unit and the color conversion layer unit.
  • the step of bonding the first indium zinc oxide layer and the second indium zinc oxide layer includes: moving the first indium zinc oxide layer away from a side surface of the temporary substrate Oxygen plasma is used for treatment; the side surface of the second indium zinc oxide layer away from the initial first substrate is treated with oxygen plasma; the first indium zinc oxide layer and the second oxide zinc oxide layer are treated with oxygen plasma.
  • the indium zinc layer is pressed together at a temperature of 150°C to 240°C to form a bonding layer.
  • the step includes: removing the temporary substrate to form a chip wafer unit.
  • the thickness of the initial first substrate is reduced to form a first substrate to obtain a chip structure.
  • a display substrate in another aspect, includes the chip structure as described in any of the above embodiments.
  • a display device in another aspect, includes the display substrate as described above.
  • Figure 1 is a structural diagram of a chip structure provided according to some embodiments of the present disclosure.
  • Figure 2 is another structural diagram of a chip structure provided according to some embodiments of the present disclosure.
  • Figure 3 is another structural diagram of a chip structure provided according to some embodiments of the present disclosure.
  • Figure 4 is a structural diagram of a wafer provided according to some embodiments of the present disclosure.
  • Figure 5 is a flow chart of a method for preparing an initial chip wafer unit according to some embodiments of the present disclosure
  • 6 to 13 are step diagrams of a method for preparing an initial chip wafer unit according to some embodiments of the present disclosure
  • Figure 14 is a flow chart of a method for preparing a color conversion layer unit according to some embodiments of the present disclosure
  • 15A to 17 are step diagrams of a method for preparing a color conversion layer unit according to some embodiments of the present disclosure.
  • Figure 18 is a flow chart of a color conversion layer unit and an initial chip wafer unit pairing to form a chip structure according to some embodiments of the present disclosure
  • Figures 19 to 26 are step diagrams of forming a chip structure using a color conversion layer unit and an initial chip wafer unit according to some embodiments of the present disclosure
  • Figure 27 is a flow chart of forming another chip structure by pairing the color conversion layer unit and the initial chip wafer unit according to some embodiments of the present disclosure
  • Figures 28 and 29 are step diagrams of forming another chip structure using a color conversion layer unit and an initial chip wafer unit according to some embodiments of the present disclosure
  • Figure 30 is a flow chart of a color conversion layer unit and an initial chip wafer unit to form yet another chip structure according to some embodiments of the present disclosure
  • 31A to 33 are step diagrams of forming yet another chip structure by pairing the color conversion layer unit and the initial chip wafer unit according to some embodiments of the present disclosure
  • Figure 34 is a top view of a chip structure provided according to some embodiments of the present disclosure.
  • Figure 35 is a cross-sectional view taken along section line HH in a top view of a chip structure provided according to some embodiments of the present disclosure
  • Figure 36 is a structural diagram of a display substrate provided according to some embodiments of the present disclosure.
  • Figure 37 is a structural diagram of a display device provided according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the present disclosure provides a chip structure 10.
  • the chip structure 10 includes: a chip wafer unit 11 and a color conversion layer unit 21 disposed on the light exit side G of the chip wafer unit.
  • the chip wafer unit 11 includes a plurality of sub-pixel light-emitting functional layers 12, and the color conversion layer unit 21 includes a color conversion layer 22 disposed on the light exit side G of the chip wafer unit 11.
  • the chip structure 10 also includes: a bonding layer 13, which is disposed between the chip wafer unit 11 and the color conversion layer unit 21, and is used to bond the chip wafer unit 11 and the color conversion layer unit 21.
  • one sub-pixel light-emitting functional layer 12 among the plurality of sub-pixel light-emitting functional layers 12 of the chip wafer unit 11 is configured to emit one of a plurality of colors of light, and
  • the plurality of sub-pixel light-emitting functional layers 12 may be configured to emit light of the same color.
  • the multiple colors of light include blue light.
  • the first sub-pixel light-emitting functional layer 12a is configured to emit blue light.
  • the color conversion layer unit 21 is provided on the light exit side G of the chip wafer unit 11.
  • the color conversion layer unit 21 is provided with a color conversion layer 22 corresponding to the light exit side G of each sub-pixel light emitting functional layer 12.
  • the chip wafer unit 11 and the color conversion layer unit 21 are separately manufactured, and then the chip wafer unit 11 and the color conversion layer unit 21 are bonded through the bonding layer 13 to form the chip structure 10 .
  • the bonding effect of the bonding layer 13 can be an adhesive bonding effect or a metal bonding effect. See the following for details and will not be repeated here.
  • the bonding layer 13 is any one of an indium zinc oxide bonding layer 131 , a metal bonding layer 132 and an adhesive layer 133 .
  • the bonding layer 13 is an indium zinc oxide bonding layer 131 .
  • the indium zinc oxide bonding layer 131 includes a first indium zinc oxide layer 131 a and a second indium zinc oxide layer 131 a stacked along the first direction X.
  • the indium zinc oxide layer 131b, the first indium zinc oxide layer 131a and the second indium zinc oxide layer 131b are connected through molecular bonding.
  • the first indium zinc oxide layer 131a is stacked and connected to the chip wafer unit 11, and the second indium zinc oxide layer 131b is stacked and connected to the color conversion layer unit 21.
  • the chip wafer unit 11 and the color conversion layer unit 21 are bonded together through the molecular bonding between the first indium zinc oxide layer 131a and the second indium zinc oxide layer 131b, thereby forming the chip structure 10.
  • the specific preparation method is described below and will not be described again here.
  • the first direction X is the direction in which the chip wafer unit 11 points to the color conversion layer unit 21 . It can be understood that the first direction X is parallel to the light emitting direction of the chip wafer unit 11 .
  • the first indium zinc oxide layer 131a is stacked with the chip wafer unit 11 through a photolithography process
  • the second indium zinc oxide layer 131b is stacked with the color conversion layer unit 21 through a photolithography process to form the first indium zinc oxide layer.
  • the error size between 131a and the second indium zinc oxide layer 131b is small. Therefore, the precision of the formed indium zinc oxide film layer is high.
  • the indium zinc oxide bonding layer 131 as the bonding layer 13, the formed bonding layer can be improved. The accuracy of layer 13.
  • the size d1 of the indium zinc oxide bonding layer 131 in the first direction X ranges from 100 nm to 300 nm.
  • the size d1 of the indium zinc oxide bonding layer 131 in the first direction X is 100 nm, 150 nm, 200 nm, 250 nm or 250 nm, etc., and is not limited here. It can be understood that the dimension d1 of the indium zinc oxide bonding layer 131 in the first direction X is the film thickness of the indium zinc oxide bonding layer 131 . If the thickness of the indium zinc oxide bonding layer 131 is less than 100 nm, the indium zinc oxide bonding layer 131 cannot have a relatively stable bonding effect. If the thickness of the indium zinc oxide bonding layer 131 is too thick, the thickness of the chip structure 10 will be increased. By providing the indium zinc oxide bonding layer 131 with a thickness of 100 nm to 300 nm, the bonding of the chip wafer unit 11 and the color conversion layer unit 21 can be better achieved.
  • the conforming layer 13 is an adhesive glue layer 133 .
  • the material of the adhesive layer 133 is an epoxy resin-based organic adhesive material.
  • the chip wafer unit 11 and the color conversion layer unit 21 are bonded together through the adhesive effect of the adhesive layer 133 , thereby forming the chip structure 10 .
  • the specific preparation method is described below and will not be described again here.
  • the size d2 of the adhesive layer 133 in the first direction X ranges from 5 ⁇ m to 10 ⁇ m.
  • the size d2 of the adhesive layer 133 in the first direction X may be, for example, 5 ⁇ m, 6 ⁇ m, 7 ⁇ m, 8 ⁇ m, 9 ⁇ m, or 10 ⁇ m, and is not limited here.
  • the bonding layer 13 is a metal bonding layer 132 .
  • the metal bonding layer 132 includes a first sub-metal layer 132 a , a second sub-metal layer 132 b and a first sub-metal layer 132 b that are stacked along the first direction X.
  • the third sub-metal layer 132c and the second sub-metal layer 132b are provided as eutectic alloy layers connecting the first sub-metal layer 132a and the third sub-metal layer 132c.
  • the first sub-metal layer 132a is stacked and connected to the chip wafer unit 11, and the third sub-metal layer 132c is stacked and connected to the color conversion layer unit 21, which is realized by the eutectic alloy layer (second sub-metal layer 132b).
  • the connection between the first sub-metal layer 132a and the third sub-metal layer 132c realizes the bonding of the chip wafer unit 11 and the color conversion layer unit 21 to form the chip structure 10 .
  • the specific preparation method is shown below and will not be described again here.
  • the size d3 of the metal bonding layer 132 in the first direction X ranges from 6 ⁇ m to 12 ⁇ m.
  • the size d3 of the metal bonding layer 132 in the first direction X is 6 ⁇ m, 8 ⁇ m, 9 ⁇ m, 10 ⁇ m, 11 ⁇ m, or 12 ⁇ m, etc., and is not limited here.
  • the preparation method of the chip structure 10 includes: preparing the initial chip wafer unit 110 and the color conversion layer unit 21, then forming the bonding layer 13, and bonding the initial chip wafer unit 110 and the color conversion layer unit 21, to obtain The chip wafer unit 11 forms the chip structure 10 .
  • three embodiments are provided below to introduce the preparation method of the chip structure 10 .
  • the following description takes the formation of a chip structure 10 as an example. It can be understood that the method of preparing the chip structure 10 is to first form a wafer 101 including multiple chip structures 10 arranged in an array, and then cut the wafer 101 to form a single chip structure 10. The structure of the wafer 101 is as shown in the figure 4 shown.
  • the chip structure 10 shown in FIG. 1 is formed. It should be noted that in the steps of preparing the chip structure 10 , the structural example of the chip structure 10 can be understood with reference to the content shown in FIG. 1 and the step diagram.
  • FIG. 5 shows the preparation steps of the initial chip wafer unit 110, including: S101 to S108.
  • an initial gallium nitride buffer layer 150 , an initial n-type gallium nitride layer 160 , an initial quantum well layer 1210 and an initial P-type gallium nitride layer 1220 are sequentially formed on one side of the second substrate 14 .
  • the second substrate 14 may be any one of a sapphire substrate and a silicon-based substrate.
  • the initial quantum well layer 1210 may be a blue quantum well layer, and the sub-pixel light-emitting functional layer 12 (not shown in the figure, see FIG. 1 ) formed by the blue quantum well layer emits blue light.
  • S102 As shown in FIG. 7A and FIG. 7B, pattern the initial P-type gallium nitride layer 1220 and the initial quantum well layer 1210, and pattern the initial n-type gallium nitride layer 160 and the initial gallium nitride buffer layer 150.
  • a P-type gallium nitride layer 122, a quantum well layer 121, an n-type gallium nitride layer 16 and a gallium nitride buffer layer 15 are obtained.
  • the initial quantum well layer 1210 and the initial P-type gallium nitride layer 1220 are patterned through a photolithography process, and the initial quantum well layer 1210 and the initial quantum well layer 1210 in the area between the adjacent sub-pixel light-emitting functional layers 12 and the negative electrode area S17 are removed. P-type gallium nitride layer 1220.
  • the initial chip wafer unit 110 includes three sub-pixel areas S1 and one negative electrode area S17 .
  • the three sub-pixel areas S1 are respectively the first sub-pixel area S11 , the second sub-pixel area S12 and the negative electrode area S17 .
  • the initial quantum well layer 1210 and the initial P-type gallium nitride layer 1220 are patterned through a photolithography process, and the initial quantum well layer 1210 and the initial P-type gallium nitride layer 1220 outside the three sub-pixel areas S1 and the negative electrode area S17 are removed. .
  • the three sub-pixel areas S1 are the light-emitting areas of the chip structure 10 . That is, the sub-pixel region S1 and the negative electrode region S17 are also the sub-pixel region S1 and the negative electrode region S17 of the chip structure 10 .
  • the plurality of sub-pixel light-emitting functional layers 12 of the chip wafer unit 11 include a first sub-pixel light-emitting functional layer 12a, a second sub-pixel light-emitting functional layer 12b and a third sub-pixel light-emitting functional layer 12c.
  • the first sub-pixel light-emitting functional layer 12a is located in the first sub-pixel area S11
  • the second sub-pixel light-emitting functional layer 12b is located in the second sub-pixel area S12
  • the third sub-pixel light-emitting functional layer 12c is located in the third sub-pixel area S13.
  • the negative electrode region S17 is used to form the common cathode layer 17. The details of the common cathode layer 17 are described below and will not be described again here.
  • this step forms the first quantum well layer 121a and the first p-type gallium nitride layer 122a of the first sub-pixel light-emitting functional layer 12a, and the second sub-pixel light-emitting functional layer 12b.
  • FIG. 7A is a cross-sectional view taken along the AA cross-section line in FIG. 7B.
  • a photolithography process is used to pattern the initial n-type gallium nitride layer 160 and the initial gallium nitride buffer layer 150 to form the n-type gallium nitride layer 16 and the gallium nitride buffer layer 15, where the n-type gallium nitride layer 160 and the initial gallium nitride buffer layer 150 are formed.
  • the layer 16 is a conductive layer connecting the first sub-pixel light-emitting functional layer 12a, the second sub-pixel light-emitting functional layer 12b, the third sub-pixel light-emitting functional layer 12c and the common cathode layer 17.
  • an initial current expansion layer is first formed, and the initial current expansion layer is patterned through a photolithography process to form the current expansion layer 125 .
  • the current spreading layer 125 includes a first current spreading layer 125a located in the first sub-pixel area S11, a second current spreading layer located in the second sub-pixel area S12 (not shown in the figure, see FIG. 7B) and a third current spreading layer located in the third sub-pixel area S12.
  • the third current spreading layer of the pixel area S13 (not shown in the figure, please refer to FIG. 7B).
  • the material of the current spreading layer 125 is ITO (indium tin oxide).
  • the current spreading layer 125 is provided in the sub-pixel area S1 to facilitate the transmission of holes and improve the electrical performance of the chip structure 10 .
  • the method of preparing the initial chip wafer unit 110 further includes the step of forming a reflective metal layer 123 .
  • an initial reflective metal layer is formed on the side of the current spreading layer 125 away from the second substrate 14, and the initial reflective metal layer is patterned through a photolithography process to form the reflective metal layer 123 of each sub-pixel light-emitting functional layer 12.
  • the reflective metal layer 123 has the function of reflecting light and can improve the light extraction rate of the sub-pixel light-emitting functional layer 12 .
  • the reflective metal layer 123 is not shown.
  • FIG. 10A and FIG. 10B form the cathode metal layer 17a.
  • FIG. 10A is a cross-sectional view taken along the BB cross-section line in FIG. 10B.
  • the cathode metal layer 17a is formed through a photolithography process.
  • the material of the cathode metal layer 17a may be any one of titanium, aluminum, nickel, and gold.
  • the cathode metal layer 17a includes a first part S17c covering the negative electrode region S17, and a second part S17b located between the common cathode layer 17 and the adjacent sub-pixel light-emitting functional layer 12.
  • the cathode metal layer 17 a also includes a portion located between two adjacent sub-pixel light-emitting functional layers 12 .
  • the cathode metal layer 17a has the function of connecting the n-type gallium nitride layer 16 and raising the cathode electrode 17b (not shown in the figure, see FIG. 11A).
  • the part of the cathode metal layer 17a located between two adjacent sub-pixel light-emitting functional layers 12 is called the supporting metal layer S17a.
  • the chip structure 10 is reinforced to prevent the chip structure 10 from cracking.
  • increasing the volume of the cathode metal layer 17a can reduce the resistance of the chip structure 10.
  • the portion of the cathode metal layer 17a located between two adjacent sub-pixel light-emitting functional layers 12 has a distance d4 between the two adjacent sub-pixel light-emitting functional layers 12 .
  • the range of the distance d4 between the sub-pixel light-emitting functional layer 12 and the cathode metal layer 17a is 1/10 to 1/3 of the range of the distance d5 between two adjacent sub-pixel light-emitting functional layers 12.
  • the range d4 of the distance between the sub-pixel light-emitting functional layer 12 and the cathode metal layer 17a is 1/10, 1/4 or 1/1 of the range of the distance d5 between two adjacent sub-pixel light-emitting functional layers 12 Level 3, there is no limit here.
  • the distance d4 between 12 is 1/10 to 1/3 of the range, which can increase the area of the cathode metal layer 17a while ensuring the aperture ratio of the area where the sub-pixel light-emitting functional layer 12 of the chip structure 10 is located, thereby reducing the cost of the chip.
  • the resistance of the structure 10 is reduced, and the chip structure 10 is prevented from cracking, thereby improving the stability of the chip structure 10 .
  • the distance d4 between the sub-pixel light-emitting functional layer 12 and the cathode metal layer 17a ranges from 8 ⁇ m to 10 ⁇ m.
  • the distance d4 between the sub-pixel light-emitting functional layer 12 and the cathode metal layer 17a is 8 ⁇ m, 9 ⁇ m, or 10 ⁇ m, etc., and is not limited here.
  • S105 As shown in FIG. 10A and FIG. 10B, an insulating layer 18 is formed, and a plurality of via holes H are provided on the insulating layer 18.
  • an initial insulating layer is formed on the side of the cathode metal layer 17a away from the second substrate 14 through a deposition process, and a plurality of via holes H are formed through a photolithography process.
  • the plurality of via holes H include a first via hole H1 , a second via hole H2 , a third via hole H3 and a fourth via hole H4 .
  • the first via hole H1 is provided correspondingly to the first sub-pixel light-emitting functional layer 12a
  • the second via hole H2 is provided correspondingly to the second sub-pixel light-emitting functional layer 12b
  • the third via hole H3 is provided correspondingly to the third sub-pixel light-emitting functional layer 12c.
  • the fourth via hole H4 is provided corresponding to the negative electrode region S17.
  • FIGS. 11A and 11B the electrode 19 is formed, where the electrode 19 includes a first anode 124a, a second anode 192, a third anode 193 and a cathode electrode 17b.
  • FIG. 11A is a cross-sectional view taken along the CC cross-section line in FIG. 11B.
  • the first anode 124a, the second anode 192 and the third anode 193 are called anode electrodes.
  • the electrode 19 is formed through a patterning process.
  • the first anode 124a is arranged corresponding to the first sub-pixel light-emitting functional layer 12a
  • the second anode 192 is arranged corresponding to the second sub-pixel light-emitting functional layer 12b
  • the third anode 193 is arranged corresponding to the third sub-pixel light-emitting functional layer 12c
  • the cathode electrode 17b and cathode metal 17a form a common cathode layer 17.
  • the temporary adhesive layer 41 and the debonding layer 42 are used to temporarily bond the temporary substrate 20.
  • the temporary adhesive layer 41 has an adhesive effect, and the debonding layer 42 can be debonded under the irradiation of ultraviolet light.
  • the temporary adhesion layer 41 and the debonding layer 42 have the function of temporarily adhering the temporary substrate 20 .
  • the initial chip wafer unit 110 is formed after the second substrate 14 is removed.
  • the second substrate 14 may be a sapphire substrate, and the sapphire substrate is peeled off by laser.
  • the second substrate 14 can be a silicon-based substrate, and an acid-proof film or wax seal is used to protect the temporary substrate 20, and the initial chip wafer unit 110 is placed in a hydrofluoric acid (HF) etching tank. The second substrate 14 is removed by etching.
  • HF hydrofluoric acid
  • the initial chip wafer unit 110 is provided with a temporary substrate 20 on the side of the electrode 19 away from the gallium nitride buffer layer 15.
  • the temporary substrate 20 and the adhesive layer 41 and the debonding layer 42 on the initial chip wafer unit 110 are removed to form the chip wafer unit 11 .
  • the preparation steps of the color conversion layer unit 21 are introduced below, as shown in FIG. 14 , including steps R201 to R203.
  • R201 As shown in FIG. 15A , the color filter layer 24 and the defining dam layer 25 are formed on the initial first substrate 310 .
  • the color filter layer 24 includes a black matrix layer 23 and a plurality of filter film layers 28 defined by the black matrix layer 23 .
  • the limiting dam layer 25 is disposed on a side of the color filter layer 24 away from the initial first substrate 310 .
  • the initial first substrate 310 may be a glass substrate.
  • the plurality of filter film layers 28 include a first filter film 241 , a second filter film 242 and a third filter film 243 .
  • the first filter film 241 is a red filter film
  • the second filter film 242 is a blue filter film
  • the third filter film 243 is a green filter film.
  • FIG. 15A is a cross-sectional view taken along the DD cross-section line in FIG. 15B.
  • a limiting dam layer 25 is formed on the side of the black matrix layer 23 away from the initial first substrate 310 by means of coating, exposure, development, post-baking, etc.
  • the limiting dam layer 25 is defined with Multiple opening areas K.
  • the plurality of opening areas K include a first opening area K1, a second opening area K2, and a third opening area K3.
  • R202 As shown in FIG. 16A, the color conversion layer 22 is formed.
  • the color conversion layer is produced in the first opening area K1, the second opening area K2 and the third opening area K3 by coating, exposure, development, post-baking or inkjet printing. twenty two.
  • the color conversion layer 22 includes a first quantum dot conversion part 22a, a scattering particle part 22b and a third quantum dot conversion part 22c.
  • the first quantum dot conversion part 22a is formed in the first opening area K1, and the first quantum dot conversion part 22a is made of red quantum dot luminescent material; the scattering particle part 22b is formed in the second opening area K2, and the scattering particles are arranged; the third opening A third quantum dot conversion part 22c is formed in the area K3, and the third quantum dot conversion part 22c uses green quantum dot luminescent material.
  • FIG. 16A is a cross-sectional view taken along the EE cross-section line in FIG. 16B.
  • R203 As shown in Figure 17, the inorganic encapsulation layer 26 is formed.
  • the color conversion layer unit 21 is obtained.
  • CVD chemical vapor deposition
  • T301 As shown in FIG. 19 , a first indium zinc oxide layer 131a is formed on the side of the initial chip wafer unit 110 away from the temporary substrate 20 .
  • the first indium zinc oxide layer 131a is formed on the side of the gallium nitride buffer layer 15 away from the temporary substrate 20 .
  • the first indium zinc oxide layer 131a is formed through a photolithography process.
  • the first large plate M including a plurality of initial chip wafer units 110 arranged in an array is simultaneously formed, as shown in FIG. 20 .
  • a first indium zinc oxide layer is formed on the initial chip wafer unit 110 of the first large plate M.
  • cut the first large plate M for example, perform special-shaped cutting to form a plurality of first initial wafers A.
  • the first initial wafer A is circular, and the first initial wafer A includes a first Multiple initial chip wafer units 110 of indium zinc oxide layer 131a.
  • the size of the first initial wafer A is 4 inches or 6 inches.
  • T302 As shown in FIG. 22 , a second indium zinc oxide layer 131b is formed on the side of the color conversion layer unit 21 away from the initial first substrate 310 .
  • the second indium zinc oxide layer 131b is formed on the side of the inorganic encapsulation layer 26 away from the initial first substrate 310 .
  • the second indium zinc oxide layer 131b is formed through a photolithography process.
  • a second large plate N including a plurality of color conversion layer units 21 arranged in an array is simultaneously formed, as shown in FIG. 23.
  • a second indium zinc oxide layer 131b is formed on the color conversion layer unit 21 of the second large plate N.
  • cut the second large plate N for example, perform special-shaped cutting to form a plurality of second initial wafers B.
  • the second initial wafer B is circular, and the second initial wafer B includes a second initial wafer B.
  • the second initial wafer B is the same size as the first initial wafer A.
  • the following describes the steps of pairing the first initial wafer A and the second initial wafer B to finally form a single chip structure 10 . It should be noted that the following takes the formation of a chip structure 10 as an example.
  • T303 As shown in FIG. 25, the first indium zinc oxide layer 131a and the second indium zinc oxide layer 131b are bonded.
  • the bonding of the initial chip wafer unit 110 and the color conversion layer unit 21 is achieved.
  • the thickness d11 of the first indium zinc oxide layer 131a and the thickness d12 of the second indium zinc oxide layer 131b may be the same or different, and are not limited here.
  • the sum of the thickness d11 of the first indium zinc oxide layer 131 a and the thickness d12 of the second indium zinc oxide layer 131 b is the film thickness of the indium zinc oxide bonding layer 131 .
  • the step of bonding the first indium zinc oxide layer 131a and the second indium zinc oxide layer 131b includes U1 to U3:
  • the phase is heated to 150°C, then a pressure of 15,000N is applied, and then the temperature is raised to 200°C, with a heating rate of 10°C/min. Then keep it for 30 minutes to form the laminating layer 13.
  • T304 Remove the temporary substrate 20.
  • the initial chip wafer unit 110 is formed into a chip wafer unit 11, with a structure as shown in FIG. 26.
  • the debonding layer 42 is debonded by irradiation with ultraviolet light, and the temporary adhesive layer 41 , the debonding layer 42 and the temporary substrate 20 are removed.
  • T305 Thinning the initial first substrate 310 to form the first substrate 31.
  • the thickness of the initial first substrate 310 is reduced to 60 ⁇ m to 200 ⁇ m.
  • the shape of the chip structure 10 formed in this way is close to a cube, which makes the chip structure 10 more stable and facilitates the use of subsequent processes.
  • Using a thicker initial first substrate 310 during the preparation of the chip structure 10 is beneficial to the processing of the chip structure 10 .
  • a plurality of sub-pixel light-emitting functional layers 12 are disposed on the initial first side.
  • First side of substrate 310 First side of substrate 310 .
  • a blue film is pasted on the side of the first substrate 31 away from the electrode 19 for protection, and then laser cutting is used to obtain a single chip structure 10 .
  • the chip structure 10 as shown in Figure 1 is formed.
  • the projection of the indium zinc oxide bonding layer 131 on the multiple sub-pixel light-emitting functional layers 12 covers the multiple sub-pixels to emit light.
  • Functional layer 12 That is to say, when the indium zinc oxide bonding layer 131 is used as the bonding layer 13, the indium zinc oxide bonding layer 131 is provided as a whole layer, and the orthographic projection of the indium zinc oxide bonding layer 131 on the first substrate 31 is completely Covering the orthographic projection of the plurality of sub-pixel light-emitting functional layers 12 on the first substrate 31 .
  • the indium zinc oxide bonding layer 131 is a transparent film layer.
  • the entire indium zinc oxide bonding layer 131 does not affect the light emitted by the multiple sub-pixel light-emitting functional layers 12 .
  • This embodiment uses the indium zinc oxide bonding layer 131 as the bonding layer 13, which can improve the accuracy of the formed bonding layer 13, thereby improving the product yield of the chip structure 10, and the thickness of the formed chip structure 10 is thinner.
  • the chip structure 10 shown in FIG. 2 is formed. It should be noted that in the steps of preparing the chip structure 10 , the structural example of the chip structure 10 can be understood with reference to the content shown in FIG. 2 and the step diagram.
  • the preparation steps of the initial chip wafer unit 110 refer to steps S101 to S108
  • the preparation steps of the color conversion layer unit 21 refer to steps R201 to R203, which will not be described again here.
  • this step includes P301 to P305.
  • P301 As shown in Figure 28, apply an adhesive layer 133 on the side of the initial chip wafer unit 110 away from the temporary substrate 20.
  • the adhesive layer 133 is coated on the side of the gallium nitride buffer layer 15 away from the temporary substrate 20 .
  • the material of the adhesive layer 133 is an organic adhesive material such as epoxy resin.
  • the adhesive layer 133 is formed through a stencil printing process, and it is ensured that there is no residual material forming the adhesive layer 133 in the cutting path 102 .
  • the dicing lane 102 is located between two adjacent chip structures 10 on the wafer 101 . Only one dicing lane 102 is shown in FIG. 4 . It can be understood that, in order to obtain a single chip structure 10 , the area between each two adjacent chip structures 10 is a dicing lane 102 .
  • a large board including a plurality of initial chip wafer units 110 arranged in an array is simultaneously formed.
  • a large plate including a plurality of color conversion layer units 21 arranged in an array is simultaneously formed.
  • a step of cutting the large plate of the initial chip wafer unit 110 and the large plate of the color conversion layer unit 21 is also included.
  • the large plate of the initial chip wafer unit 110 is cut to form a plurality of third initial wafers C.
  • the third initial wafers C include a plurality of initial chip wafer units 110 provided with adhesive layers 133 .
  • the large plate of the color conversion layer unit 21 is cut to form a plurality of fourth initial wafers D.
  • the fourth initial wafer D includes a plurality of color conversion layer units 21 .
  • the third initial wafer C includes a plurality of initial chip wafer units 110 provided with adhesive layers 133
  • the first initial wafer A includes a plurality of initial chip wafer units provided with a first indium zinc oxide layer 131a.
  • the fourth initial wafer D includes a plurality of color conversion layer units 21, and the second initial wafer B includes a plurality of color conversion layer units 21 provided with the second indium zinc oxide layer 131b.
  • the following describes the steps of pairing the third initial wafer C and the fourth initial wafer D to finally form a single chip structure 10 .
  • P302 As shown in Figure 29, pair the color conversion layer unit 21 and the initial chip wafer unit 110.
  • the color conversion layer unit 21 and the initial chip wafer unit 110 are bonded through the adhesive layer 133 .
  • step T304 For specific steps, please refer to step T304, which will not be described again here.
  • P304 Thin the initial first substrate 310 to form the first substrate 31.
  • step T305 For specific steps, please refer to step T305, which will not be described again here.
  • step T306 For specific steps, please refer to step T306, which will not be described again here.
  • the bonding layer 13 is an adhesive layer 133, and the adhesive layer 133 is in the multiple sub-pixel light-emitting functional layers 12.
  • the projection on the screen covers multiple sub-pixel light-emitting functional layers 12 . That is to say, the adhesive layer 133 is provided as a whole layer, and the orthographic projection of the adhesive layer 133 on the first substrate 31 covers the orthographic projection of the multiple sub-pixel light-emitting functional layers 12 on the first substrate 31 .
  • the adhesive layer 133 is made of a transparent organic adhesive material, and the entire adhesive layer 133 does not affect the light emitted from the multiple sub-pixel light-emitting functional layers 12 .
  • the adhesive layer 133 is used as the laminating layer 13, which can improve the transfer efficiency of Micro-LED, reduce the chip thickness, and improve the product yield.
  • the chip structure 10 shown in FIG. 3 is formed. It should be noted that in the steps of preparing the chip structure 10 , the structural example of the chip structure 10 can be understood with reference to the content shown in FIG. 3 and the step diagram.
  • the preparation steps of the initial chip wafer unit 110 refer to steps S101 to S108
  • the preparation steps of the color conversion layer unit 21 refer to steps R201 to R203, which will not be described again here.
  • this step includes Q301 to Q306.
  • a first initial sub-metal layer 1310 and a second initial sub-metal layer 1320 are formed on the side of the initial chip wafer unit 110 away from the temporary substrate 20.
  • FIG. 31A is a cross-sectional view taken along the FF cross-sectional line in FIG. 31B.
  • a whole layer of material for forming the first initial sub-metal layer 1310 is deposited on the side of the gallium nitride buffer layer 15 away from the temporary substrate 20 through a deposition process, and a photolithography process is used to pattern the first initial sub-metal layer 1310 .
  • the material of the metal layer 1310 and the first initial sub-metal layer 1310 may be any one of Au (gold), Ag (silver), Pb (lead) and Sn (tin).
  • the first initial sub-metal layer 1310 includes three opening areas K, and the three opening areas K are divided into a first sub-opening area K11, a second sub-opening area K21 and a third sub-opening. District K31.
  • the first sub-opening area K11 is provided correspondingly to the first sub-pixel area S11
  • the second sub-opening area K21 is provided correspondingly to the second sub-pixel area S12
  • the third sub-opening area K31 is provided correspondingly to the third sub-pixel area S13.
  • the corresponding arrangement of A and B means that the orthographic projections of A and B on the temporary substrate 20 coincide or substantially coincide.
  • the first sub-opening area K11 and the first sub-pixel area S11 are arranged correspondingly, which means that the orthographic projections of the first sub-opening area K11 and the first sub-pixel area S11 on the temporary substrate 20 coincide or substantially overlap.
  • the second initial sub-metal layer 1320 includes a plurality of first-type metal bumps 132t, and the structure of the first-type metal bumps 132t may be cylindrical or conical.
  • the material of the second initial sub-metal layer 1320 may be In (indium), the temperature at which Au (gold) and In (indium) form a eutectic alloy is 160°C, and the temperature at which Ag (silver) and In (indium) form a eutectic alloy The temperature at which Pb (lead) and In (indium) form a eutectic alloy is 200°C, and the temperature at which Sn (tin) and In (indium) form a eutectic alloy is 120°C.
  • a third initial sub-metal layer 1330 is formed on the side of the color conversion layer unit 21 away from the initial first substrate 310.
  • the third initial sub-metal layer 1330 is formed on the side of the inorganic encapsulation layer 26 away from the initial first substrate 310 .
  • a whole layer of material for forming the third initial sub-metal layer 1330 is deposited on the side of the inorganic encapsulation layer 26 away from the initial first substrate 310 through a deposition process, and a photolithography process is used to pattern the third initial sub-metal layer 1330 .
  • the material of the third initial sub-metal layer 1330 may be any one of Au (gold), Ag (silver), Pb (lead), and Sn (tin).
  • the material of the third initial sub-metal layer 1330 may be the same as the material of the first initial sub-metal layer 1310 .
  • the third initial sub-metal layer 1330 includes three opening areas K, and the three opening areas K are respectively the fourth sub-opening area K41, the fifth sub-opening area K51 and the sixth sub-opening area. K61.
  • the fourth sub-opening area K41 is provided correspondingly to the first sub-pixel area S11
  • the fifth sub-opening area K51 is provided correspondingly to the second sub-pixel area S12
  • the sixth sub-opening area K61 is provided correspondingly to the third sub-pixel area S13.
  • Metal wafer bonding technology refers to a technology that relies on the formation of a eutectic alloy between two different metals to completely bond at a temperature lower than the respective melting points of the metals.
  • Metal wafer bonding technology can be divided into solid-liquid interdiffusion bonding technology and solid-state diffusion bonding technology according to different bonding temperatures. Among them, solid-liquid interdiffusion bonding technology has lower requirements for film layer flatness than solid-state diffusion bonding technology. Moreover, the solid-liquid interdiffusion bonding technology has high bonding strength and short bonding time. Therefore, solid-liquid interdiffusion bonding technology can be used to form the metal bonding layer 132 to realize the alignment of the color conversion layer unit 21 and the initial chip wafer unit 110 .
  • the formed metal bonding layer 132 includes a first sub-metal layer 132a, a second sub-metal layer 132b and a third sub-metal layer 132c.
  • the first initial sub-metal layer 1310, the second initial sub-metal layer 1320 and the third initial sub-metal layer 1330 form the metal bonding layer 132 through metal wafer bonding technology
  • the second sub-metal layer 132b is part of the first initial sub-metal Layer 1310, the second initial sub-metal layer 1320 and a portion of the third initial sub-metal layer 1330 form a eutectic alloy layer.
  • the metal bonding layer 132 includes a fourth opening area K4, a fifth opening area and a sixth opening area.
  • the fourth opening area K4 is provided corresponding to the first sub-pixel area S11, and the fifth opening area The area is arranged correspondingly to the second sub-pixel area S12, and the sixth opening area is arranged correspondingly to the third sub-pixel area S13.
  • the second sub-pixel area S12 and the third sub-pixel area S13 see FIG. 32B.
  • the first sub-opening area K11 and the fourth sub-opening area K41 form a fourth opening area K4.
  • the second sub-opening area K21 and the fifth sub-opening area K51 form the fifth opening area
  • the third sub-opening area K31 and the sixth sub-opening area K61 form the sixth opening area.
  • the arrangement of the second sub-opening area K21, the third sub-opening area K31, the fifth sub-opening area K51 and the sixth sub-opening area K61 see Figure 31B and Figure 32B.
  • step T304 For specific steps, please refer to step T304, which will not be described again here.
  • step T305 For specific steps, please refer to step T305, which will not be described again here.
  • step T306 For specific steps, please refer to step T306, which will not be described again here.
  • the chip structure 10 shown in Figure 3 is formed through the above steps S101 to S108, steps R201 to R203 and Q301 to Q306.
  • the bonding layer 13 is a metal bonding layer 132.
  • the metal bonding layer 132 needs to be provided with opening areas K corresponding to the multiple sub-pixel light-emitting functional layers 12. Since the metal bonding layer 132 is not light-transmitting, it is necessary to The layer 132 is provided with an opening corresponding to the area of the sub-pixel light-emitting functional layer 12 to emit light.
  • the area corresponding to the metal bonding layer 132 and the sub-pixel light-emitting functional layer 12 refers to the area where the orthographic projections of the sub-pixel light-emitting functional layer 12 and the metal bonding layer 132 on the first substrate 31 overlap.
  • the metal bonding layer 132 is used as the bonding layer 13, which can improve the accuracy of the formed bonding layer 13.
  • the distance d5 between two adjacent sub-pixel light-emitting functional layers 12 in the plurality of sub-pixel light-emitting functional layers 12 ranges from 30 ⁇ m to 80 ⁇ m.
  • the distance d5 between two adjacent sub-pixel light-emitting functional layers 12 is 30 ⁇ m, 40 ⁇ m, or 50 ⁇ m. , 60 ⁇ m, 70 ⁇ m, 75 ⁇ m or 80 ⁇ m, etc., there is no limit here.
  • the distance d5 between two adjacent sub-pixel light-emitting functional layers 12 is too small.
  • the distance d5 is less than 30 ⁇ m, or it may cause cross-color problems between adjacent sub-pixel light-emitting functional layers 12 and cause the two adjacent sub-pixels to emit light.
  • the design that the spacing d5 between the functional layers 12 ranges from 30 ⁇ m to 80 ⁇ m can effectively prevent color cross-fertilization while maintaining the brightness of the chip structure 10 .
  • the size d1 of the indium zinc oxide bonding layer 131 in the first direction X ranges from 100 nm to 300 nm
  • the size d2 of the adhesive layer 133 in the first direction X ranges from 5 ⁇ m to 5 ⁇ m. 10 ⁇ m
  • the size d3 of the metal bonding layer 132 in the first direction X ranges from 6 ⁇ m to 12 ⁇ m.
  • the size of the adhesion layer 13 in the first direction This arrangement can avoid cross-color interference between the sub-pixel light-emitting functional layers 12 and improve the light extraction effect of the chip structure 10 .
  • the distance d6 between two adjacent anode electrodes is less than or equal to the two sub-pixel light-emitting functional layers where the two anode electrodes are located.
  • the spacing between 12 is d5.
  • the first sub-pixel light-emitting functional layer 12a is provided correspondingly to the first anode 124a
  • the second sub-pixel light-emitting functional layer 12b is provided correspondingly to the second anode 192
  • the first anode 124a and the second anode 192 are arranged correspondingly.
  • the distance d6 between 192 is smaller than the distance d5 between the first sub-pixel light-emitting functional layer 12a and the second sub-pixel light-emitting functional layer 12b.
  • the boundary of the anode electrode exceeds the sub-pixel where the two anode electrodes are located.
  • the boundary of the light-emitting functional layer 12 allows the anode electrode to not only have a conductive function, but also ensure that the anode electrode has a larger area for light reflection, thereby improving the light extraction effect of the chip structure 10 .
  • the distance d13 between the cathode electrode 17b and the adjacent electrode 19 can be set with reference to the distance d6 between the two adjacent anode electrodes, which will not be described again here.
  • the distance d6 between two adjacent anode electrodes ranges from 30 ⁇ m to 75 ⁇ m, wherein the anode electrode includes a first anode 124a, a second anode 192, and a third anode 193.
  • the distance d6 between two adjacent anodes for example, the distance d6 between the first anode 124a and the second anode 192 is 30 ⁇ m, 35 ⁇ m, 40 ⁇ m, 45 ⁇ m, 50 ⁇ m, 55 ⁇ m, 65 ⁇ m or 75 ⁇ m, etc., where There are no limits.
  • the projection of the filter film layer 28 on the first substrate 31 covers the sub-pixel light-emitting functional layer 12 corresponding to the filter film layer 28 on the first substrate. projection on.
  • the projection of the color conversion layer 22 on the first substrate 31 covers the projection of the filter film layer 28 corresponding to the color conversion layer 22 on the first substrate 31 .
  • the projection of the scattering particle part 22b on the first substrate 31 covers the projection of the second filter film 242 on the first substrate 31.
  • Fig. 35 is a cross-sectional view taken along the HH cross-section line in Fig. 34.
  • the projected size of the filter film layer 28 on the first substrate 31 is larger than the projected size of the sub-pixel light-emitting functional layer 12 corresponding to the filter film layer 28 on the first substrate 31 .
  • the projected size of the color conversion layer 22 on the first substrate 31 is larger than the projected size of the filter film layer 28 corresponding to the color conversion layer 22 on the first substrate 31 .
  • the projected size of the scattering particle part 22b on the first substrate 31 is larger than the projected size of the second filter film 242 on the first substrate 31.
  • the distance d7 between the projection boundary of the filter film layer 28 on the first substrate 31 and the projection boundary of the sub-pixel light-emitting functional layer 12 corresponding to the filter film layer 28 on the first substrate 31 ranges from 20 ⁇ m. ⁇ 60 ⁇ m.
  • the distance d7 between the projection boundary of the filter film layer 28 on the first substrate 31 and the projection boundary of the sub-pixel light-emitting functional layer 12 corresponding to the filter film layer 28 on the first substrate 31 is 20 ⁇ m, 40 ⁇ m, 50 ⁇ m or 60 ⁇ m, etc., there is no limit here.
  • the distance d8 between the projection boundary of the color conversion layer 22 on the first substrate 31 and the projection boundary of the filter film layer 28 corresponding to the color conversion layer 22 on the first substrate 31 ranges from 23 ⁇ m to 68 ⁇ m.
  • the distance d8 between the projection boundary of the color conversion layer 22 on the first substrate 31 and the projection boundary of the filter film layer 28 corresponding to the color conversion layer 22 on the first substrate 31 is 23 ⁇ m, 30 ⁇ m, 35 ⁇ m, and 42 ⁇ m. , 50 ⁇ m, 60 ⁇ m or 68 ⁇ m, etc., there is no limit here.
  • the distance d9 between the projection boundary of the scattering particle part 22b on the first substrate 31 and the projection boundary of the second filter film 242 on the first substrate 31 ranges from 23 ⁇ m to 68 ⁇ m.
  • the distance d9 between the projection boundary of the scattering particle part 22b on the first substrate 31 and the projection boundary of the second filter film 242 on the first substrate 31 is 23 ⁇ m, 32 ⁇ m, 38 ⁇ m, 45 ⁇ m, 55 ⁇ m, 62 ⁇ m or 68 ⁇ m, etc., there is no limit here.
  • the size d10 of the dam layer 25 in the first direction X ranges from 10 ⁇ m to 30 ⁇ m.
  • the size d10 of the dam layer 25 in the first direction Setting the dimension d10 of the limiting dam layer 25 in the first direction , the thickness of the color conversion layer 22 is simultaneously increased, so that the design can improve the luminous effect of the chip structure 10 .
  • the projection of the color conversion layer unit 21 on the first substrate 31 covers the projection of the adhesion layer 13 on the first substrate 31 .
  • the material of the adhesion layer 13 is an organic adhesive material such as epoxy resin.
  • the adhesion layer 13 is covered on the first substrate 31. The projection can ensure that no organic adhesive material remains at the position of the cutting lane 102 (shown in FIG. 4 ), which facilitates cutting to form the chip structure 10 .
  • the distance d14 between the projection boundary of the color conversion layer unit 21 on the first substrate 31 and the projection boundary of the adhesion layer 13 on the first substrate 31 ranges from 0 ⁇ m to 10 ⁇ m. .
  • the distance d14 between the projection boundary of the color conversion layer unit 21 on the first substrate 31 and the projection boundary of the adhesion layer 13 on the first substrate 31 is 0 ⁇ m, 2 ⁇ m, 5 ⁇ m, 7 ⁇ m or 10 ⁇ m, etc., There are no restrictions here.
  • the distance d14 ranges from 0 ⁇ m to 10 ⁇ m, thereby ensuring the bonding of the chip structure 10
  • the material of the laminating layer 13 is an epoxy resin-based organic adhesive material, it is ensured that no organic adhesive material remains at the position of the cutting track 102 (see Figure 4).
  • the display substrate 100 includes a plurality of chip structures 10 as described in any of the above embodiments.
  • the display substrate 100 includes a driving backplane.
  • the driving backplane includes a circuit layer.
  • a plurality of chip structures 10 are disposed on the driving backplane.
  • the circuit layer includes, for example, a plurality of pad groups. Each pad group includes A plurality of separately arranged bonding pads, the cathode electrode 17b, the first anode 124a, the second anode 192 and the third anode 193 of each chip structure 10 are respectively electrically connected to one of the plurality of bonding pads.
  • multiple chip structures 10 are transferred to the driving backplane through mass transfer technology.
  • Some embodiments of the present disclosure also provide a display device 1000, as shown in Figure 37, including the display substrate 100 as described above.
  • the display device may be any device that displays text or images, whether moving (eg, video) or fixed (eg, still images). More specifically, it is contemplated that the embodiments may be implemented in or in association with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer display, etc.), navigator, cockpit controller and/or display, camera view display (e.g. display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, building structures, packaging and aesthetic structure (for example, for the display of an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • handheld or portable computers GPS receivers/navigators
  • MP4 video players camcorders

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Abstract

一种芯片结构（10），芯片结构（10）包括：芯片晶圆单元（11）和设置于芯片晶圆单元（11）出光侧（G）的色转换层单元（21）；其中，芯片晶圆单元（11）包括多个子像素发光功能层（12，12a，12b，12c）；色转换层单元（21）包括设置于芯片晶圆单元（11）出光侧（G）的色转换层（22，22a，22b，22c）。芯片结构（10）还包括：贴合层（13，131，133，132），贴合层设置于芯片晶圆单元（11）和色转换层单元（21）之间，用于贴合芯片晶圆单元（11）和色转换层单元（21）。

Description

芯片结构及其制备方法、显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种芯片结构及其制备方法、显示基板和显示装置。
背景技术
Micro-LED(微型发光二极管)显示器件是新一代显示技术，具有高亮度，高发光效率，低功耗，响应速度快等优点。然而在将Micro-LED应用于显示装置时，还存在批量转移问题、产品良率等问题。
发明内容
一方面，提供一种芯片结构，芯片结构包括：芯片晶圆单元和设置于所述芯片晶圆单元出光侧的色转换层单元；其中，所述芯片晶圆单元包括多个子像素发光功能层；所述色转换层单元包括设置于所述芯片晶圆单元出光侧的色转换层。芯片结构还包括：贴合层，贴合层设置于所述芯片晶圆单元和所述色转换层单元之间，用于贴合所述芯片晶圆单元和所述色转换层单元。
在一些实施例中，所述贴合层为氧化铟锌键合层、金属键合层和粘合胶层中的任一种。
在一些实施例中，所述贴合层在第一方向上的尺寸，小于所述多个子像素发光功能层中的相邻两个子像素发光功能层之间的间距。其中，所述第一方向为由所述芯片晶圆单元指向所述色转换层单元的方向。
在一些实施例中，所述贴合层为所述氧化铟锌键合层，所述氧化铟锌键合层在所述第一方向上的尺寸范围为100nm～300nm。或者，所述贴合层为所述金属键合层，所述金属键合层在所述第一方向上的尺寸范围为6μm～12μm。或者，所述贴合层为所述粘合胶层，所述粘合胶层在所述第一方向上的尺寸范围为5μm～10μm。
在一些实施例中，所述贴合层为所述氧化铟锌键合层，所述氧化铟锌键合层包括沿第一方向层叠设置的第一氧化铟锌层和第二氧化铟锌层，所述第一氧化铟锌层和所述第二氧化铟锌层通过分子键键合作用相连接。或者，所述贴合层为所述金属键合层，所述金属键合层包括沿第一方向层叠设置的第一子金属层、第二子金属层和第三子金属层，所述第二子金属层设置为连接所述第一子金属层和所述第三子金属层的共晶合金层。其中，所述第一方向为由所述芯片晶圆单元指向所述色转换层单元的方向。
在一些实施例中，所述贴合层为所述氧化铟锌键合层，所述氧化铟锌键 合层在所述多个子像素发光功能层上的投影，覆盖所述多个子像素发光功能层。或者，所述贴合层为所述金属键合层，所述金属键合层上设置有与所述多个子像素发光功能层对应的开口区。或者，所述贴合层为所述粘合胶层，所述粘合胶层在所述多个子像素发光功能层上的投影，覆盖所述多个子像素发光功能层。
在一些实施例中，所述芯片结构还包括第一衬底，所述第一衬底设置于色转换层单元远离所述芯片晶圆单元的一侧；所述色转换层单元在所述第一衬底上的投影，覆盖所述贴合层在所述第一衬底上的投影。其中，所述色转换层单元在所述第一衬底上的投影边界，与所述贴合层在所述第一衬底上的投影边界的间距范围为0μm～10μm。
在一些实施例中，所述多个子像素发光功能层中的每个子像素发光功能层包括沿第一方向层叠设置的阳极电极、电流扩展层、p型氮化镓层和量子阱层。所述芯片晶圆单元还包括公共阴极层，所述公共阴极层包括沿第一方向层叠设置的阴极电极和阴极金属层。其中，所述阴极金属层还包括位于相邻两个所述子像素发光功能层之间的部分；所述第一方向为由所述芯片晶圆单元指向所述色转换层单元的方向。
在一些实施例中，所述阴极金属层位于相邻两个所述子像素发光功能层之间的部分，与两个所述子像素发光功能层之间存在间距。所述子像素发光功能层与所述阴极金属层之间的间距范围，为相邻的两个子像素发光功能层之间的间距范围的1/10～1/3。
在一些实施例中，在多个所述阳极电极中，相邻的两个所述阳极电极之间的间距范围，小于或等于两个所述阳极电极所在的两个所述子像素发光功能层之间的间距范围。
在一些实施例中，所述芯片晶圆单元还包括沿第一方向层叠设置的n型氮化镓层和氮化镓缓冲层；所述n型氮化镓层设置于所述多个子像素发光功能层的出光侧。所述贴合层设置于所述氮化镓缓冲层远离所述n型氮化镓层的一侧；所述第一方向为由所述芯片晶圆单元指向所述色转换层单元的方向。
在一些实施例中，所述多个子像素发光功能层包括第一子像素发光功能层、第二子像素发光功能层和第三子像素发光功能层。所述芯片结构还包括第一衬底，所述色转换层单元包括设置于所述第一衬底一侧的彩膜层；所述彩膜层包括黑矩阵层、以及由所述黑矩阵层限定的多个滤光膜层；所述多个滤光膜层包括：第一滤光膜层、第二滤光膜层和第三滤光膜层，所述第一滤光膜层与所述第一子像素发光功能层对应设置，所述第二滤光膜层与所述第 二子像素发光功能层对应设置，所述第三滤光膜层与所述第三子像素发光功能层。
所述色转换层单元还包括设置于所述彩膜层远离所述第一衬底一侧的限定坝层，所述限定坝层设置有多个开口区；所述多个开口区包括：第一开口区、第二开口区和第三开口区；所述第一开口区与所述第一子像素发光功能层对应设置，所述第二开口区与所述第二子像素发光功能层对应设置，所述第三开口区与所述第三子像素发光功能层对应设置。
所述色转换层还包括第一量子点转换部、第二量子点转换部和散射粒子部；所述第一量子点转换部设置于所述第一开口区内，所述散射粒子部设置于所述第二开口区内，所述第二量子点转换部设置于所述第三开口区内。
在一些实施例中，所述滤光膜层在所述第一衬底上的投影，覆盖与所述滤光膜层对应的所述子像素发光功能层在所述第一衬底上的投影。所述量子点转换部在所述第一衬底上的投影，覆盖与所述量子点转换部对应的所述滤光膜层在所述第一衬底上的投影。所述散射粒子部在所述第一衬底上的投影，覆盖所述第二滤光膜层在所述第一衬底上的投影。
在一些实施例中，所述滤光膜层在所述第一衬底上的投影边界，与所述滤光膜层对应的所述子像素发光功能层在所述第一衬底上的投影边界的间距范围为20μm～60μm。所述量子点转换部在所述第一衬底上的投影边界，与所述量子点转换部对应的所述滤光膜层在所述第一衬底上的投影边界的间距范围为23μm～68μm。所述散射粒子部在所述第一衬底上的投影边界，与所述第二滤光膜层在所述第一衬底上的投影边界的间距范围为23μm～68μm。
在一些实施例中，所述限定坝层在第一方向上的尺寸范围为10μm～30μm。其中，所述第一方向为由所述芯片晶圆单元指向所述色转换层单元的方向。
另一方面，提供一种芯片结构的制备方法，芯片结构的制备方法包括：形成初始芯片晶圆单元，所述初始芯片晶圆单元包括层叠设置的临时衬底、多个子像素发光功能层、n型氮化镓层和氮化镓缓冲层；形成色转换层单元，在初始第一衬底的一侧形成所述色转换层单元；将所述色转换层单元贴合在所述初始芯片晶圆单元的出光侧，形成芯片晶圆单元和色转换层单元，得到芯片结构。
在一些实施例中，所述将所述色转换层单元贴合在所述初始芯片晶圆单元的出光侧的步骤包括：在所述初始芯片晶圆单元远离所述临时衬底的一侧形成第一氧化铟锌层；在所述色转换层单元远离所述初始第一衬底的一侧形成第二氧化铟锌层；键合所述第一氧化铟锌层和所述第二氧化铟锌层，形成 连接所述初始芯片晶圆单元和所述色转换层单元的贴合层。
在一些实施例中，所述将所述色转换层单元贴合在所述初始芯片晶圆单元的出光侧的步骤包括：在所述初始芯片晶圆单元远离所述临时衬底的一侧形成第一初始子金属层和第二初始子金属层，其中，所述第二初始子金属层为形成于所述第一初始子金属层远离所述临时衬底一侧的多个第一类金属凸点；在所述色转换层单元远离所述初始第一衬底的一侧形成第三初始子金属层；键合所述第一初始子金属层、所述第二初始子金属层和所述第三初始子金属层，形成连接所述初始芯片晶圆单元和所述色转换层单元的贴合层。
在一些实施例中，所述将所述色转换层单元贴合在所述初始芯片晶圆单元的出光侧的步骤包括：采用贴合胶连接所述初始芯片晶圆单元和所述色转换层单元。
在一些实施例中，所述键合所述第一氧化铟锌层和所述第二氧化铟锌层的步骤包括：将所述第一氧化铟锌层远离所述临时衬底的一侧表面采用氧气等离子体进行处理；将所述第二氧化铟锌层远离所述初始第一衬底的一侧表面采用氧气等离子体进行处理；将所述第一氧化铟锌层和所述第二氧化铟锌层在150℃～240℃的温度条件下压合形成贴合层。
在一些实施例中，所述将所述色转换层单元贴合在所述初始芯片晶圆单元的出光侧之后，包括：去除所述临时衬底，形成芯片晶圆单元。将所述初始第一衬底的厚度减薄，形成第一衬底，得到芯片结构。
又一方面，提供一种显示基板，显示基板包括如上任一项实施例所述的芯片结构。
又一方面，提供一种显示装置，显示装置包括如上所述的显示基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开一些实施例所提供的芯片结构的结构图；
图2为根据本公开一些实施例所提供的芯片结构的另一种结构图；
图3为根据本公开一些实施例所提供的芯片结构的又一种结构图；
图4为根据本公开一些实施例所提供的晶圆的结构图；
图5为根据本公开一些实施例所提供的初始芯片晶圆单元的制备方法的流程图；
图6～图13为根据本公开一些实施例所提供的初始芯片晶圆单元的制备方法的步骤图；
图14为根据本公开一些实施例所提供的色转换层单元的制备方法的流程图；
图15A～图17为根据本公开一些实施例所提供的色转换层单元的制备方法的步骤图；
图18为根据本公开一些实施例所提供的色转换层单元和初始芯片晶圆单元对盒形成芯片结构的流程图；
图19～图26为根据本公开一些实施例所提供的色转换层单元和初始芯片晶圆单元对盒形成芯片结构的步骤图；
图27为根据本公开一些实施例所提供的色转换层单元和初始芯片晶圆单元对盒形成另一种芯片结构的流程图；
图28和图29为根据本公开一些实施例所提供的色转换层单元和初始芯片晶圆单元对盒形成另一种芯片结构的步骤图；
图30为根据本公开一些实施例所提供的色转换层单元和初始芯片晶圆单元对盒形成又一种芯片结构的流程图；
图31A～图33为根据本公开一些实施例所提供的色转换层单元和初始芯片晶圆单元对盒形成又一种芯片结构的步骤图；
图34为根据本公开一些实施例所提供的芯片结构的俯视图；
图35为根据本公开一些实施例所提供的芯片结构的俯视图中沿截面线HH得到的截面图；
图36为根据本公开一些实施例所提供的显示基板的结构图；
图37为根据本公开一些实施例所提供的显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但 不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域 的实际形状，并且并非旨在限制示例性实施方式的范围。
目前的红光Micro-LED(Micrometer-sized Light Emitting Diodes,微型发光二极管)多由AlGaInP(红光半导体)材料制成，在正常芯片尺寸下，其效率达60％以上。然而，当芯片尺寸缩小到微米量级时，其效率会降低至1％以下。此外，在巨量转移制程上，AlGaInP材料的劣势也比较明显。巨量转移要求材料具有良好的机械强度，以避免在芯片抓取和放置的过程中出现开裂，而AlGaInP材料较差的力学性能会给巨量转移增加难度。
基于此，本公开提供一种芯片结构10，如图1～图3所示，芯片结构10包括：芯片晶圆单元11和设置于芯片晶圆单元出光侧G的色转换层单元21。其中，芯片晶圆单元11包括多个子像素发光功能层12，色转换层单元21包括设置于芯片晶圆单元11出光侧G的色转换层22。芯片结构10还包括：贴合层13，设置于芯片晶圆单元11和色转换层单元21之间，用于贴合芯片晶圆单元11和色转换层单元21。
在一些示例中，如图1～图3所示，芯片晶圆单元11的多个子像素发光功能层12中的一个子像素发光功能层12被配置为出射多种颜色光中的一种，且多个子像素发光功能层12可以配置为发射相同颜色的光。示例性的，多种颜色的光包括蓝光。例如，第一子像素发光功能层12a被配置为出射蓝色的光。色转换层单元21设置于芯片晶圆单元11的出光侧G，色转换层单元21对应每一个子像素发光功能层12的出光侧G均设置有色转换层22。
示例性的，分别独立制作芯片晶圆单元11和色转换层单元21，再将芯片晶圆单元11和色转换层单元21通过贴合层13的贴合，形成芯片结构10。可以提升Micro-LED的转移效率，降低芯片厚度、提高制备精度和产品良率。其中，贴合层13的贴合作用可以为胶粘合作用，或者金属键合作用。具体见下述内容，此处不再赘述。
在一些实施例中，如图1～图3所示，贴合层13为氧化铟锌键合层131、金属键合层132和粘合胶层133中的任一种。
在一些示例中，如图1所示，贴合层13为氧化铟锌键合层131，氧化铟锌键合层131包括沿第一方向X层叠设置的第一氧化铟锌层131a和第二氧化铟锌层131b，第一氧化铟锌层131a和第二氧化铟锌层131b通过分子键键合作用相连接。第一氧化铟锌层131a与芯片晶圆单元11叠设并连接设置，第二氧化铟锌层131b与色转换层单元21叠设并连接设置。通过第一氧化铟锌层131a和第二氧化铟锌层131b之间的分子键键合作用实现芯片晶圆单元11和色转换层单元21的贴合，从而形成芯片结构10。具体制备方法见下述 内容，此处不再赘述。
其中，第一方向X为芯片晶圆单元11指向色转换层单元21的方向。可以理解的是，第一方向X与芯片晶圆单元11的出光方向相平行。
第一氧化铟锌层131a通过光刻工艺与芯片晶圆单元11叠设设置，第二氧化铟锌层131b通过光刻工艺与色转换层单元21叠设设置，形成的第一氧化铟锌层131a和第二氧化铟锌层131b的误差尺寸较小，因此，形成的氧化铟锌形成膜层的精度较高，通过使用氧化铟锌键合层131作为贴合层13，可以提高形成的贴合层13的精度。
在一些示例中，如图1所示，氧化铟锌键合层131在第一方向X上的尺寸d1范围为100nm～300nm。
示例性的，氧化铟锌键合层131在第一方向X上的尺寸d1为100nm、150nm、200nm、250nm或250nm等，此处并不设限。可以理解的是，氧化铟锌键合层131在第一方向X上的尺寸d1即为氧化铟锌键合层131的膜层厚度。氧化铟锌键合层131厚度小于100nm会导致氧化铟锌键合层131不能具有较稳固的键合作用。氧化铟锌键合层131厚度太厚会增大芯片结构10的厚度。通过设置厚度为100nm～300nm的氧化铟锌键合层131，可以较好的实现芯片晶圆单元11和色转换层单元21的贴合。
在一些示例中，如图2所示，贴合层13为粘合胶层133。示例性的，粘合胶层133的材料为环氧树脂类的有机粘合材料。通过粘合胶层133的粘合作用实现芯片晶圆单元11和色转换层单元21的贴合，从而形成芯片结构10。具体制备方法见下述内容，此处不再赘述。
在一些示例中，如图2所示，粘合胶层133在第一方向X上的尺寸d2范围为5μm～10μm。
示例性的，粘合胶层133在第一方向X上的尺寸d2例如可以为5μm、6μm、7μm、8μm、9μm或10μm等，此处并不设限。
在一些示例中，如图3所示，贴合层13为金属键合层132，金属键合层132包括沿第一方向X层叠设置的第一子金属层132a、第二子金属层132b和第三子金属层132c，第二子金属层132b设置为连接第一子金属层132a和第三子金属层132c的共晶合金层。
第一子金属层132a与芯片晶圆单元11叠设并连接设置，第三子金属层132c与色转换层单元21叠设并连接设置，通过共晶合金层(第二子金属层132b)实现第一子金属层132a和第三子金属层132c的连接，实现芯片晶圆单元11和色转换层单元21的键合，形成芯片结构10。具体制备方 法见下述内容，此处不再赘述。
在一些示例中，如图3所示，金属键合层132在第一方向X上的尺寸d3范围为6μm～12μm。
示例性的，金属键合层132在第一方向X上的尺寸d3为6μm、8μm、9μm、10μm、11μm或12μm等，此处并不设限。
在一些示例中，芯片结构10的制备方法包括：制备初始芯片晶圆单元110和色转换层单元21，然后形成贴合层13，贴合初始芯片晶圆单元110和色转换层单元21，得到芯片晶圆单元11，形成芯片结构10。为了更清楚的说明本技术方案，以下提供三种实施例介绍芯片结构10的制备方法。
需要说明的是，为了清楚的示例芯片结构10的制备方法，以下均以一个芯片结构10的形成为例进行描述。可以理解的是，本芯片结构10的制备方法是先形成包括阵列排布的多个芯片结构10的晶圆101，然后通过切割该晶圆101形成单个芯片结构10，晶圆101的结构如图4所示。
以下介绍芯片结构10的制备方法的第一种实施例，根据该实施例形成如图1所示的芯片结构10。需要说明的是，在芯片结构10制备的步骤中，可以参照图1与步骤图所示的内容理解芯片结构10的结构示例。
实施例1
具体的，如图5所示为初始芯片晶圆单元110的制备步骤，包括：S101～S108。
S101：如图6所示，在第二衬底14的一侧依次形成初始氮化镓缓冲层150、初始n型氮化镓层160、初始量子阱层1210和初始P型氮化镓层1220。
示例性的，第二衬底14可以为蓝宝石衬底和硅基衬底中的任一种。
示例性的，初始量子阱层1210可以为蓝色量子阱层，由蓝色量子阱层形成的子像素发光功能层12(图中未示出，可以参见图1)出射蓝光。
S102：如图7A和图7B所示，图案化初始P型氮化镓层1220和初始量子阱层1210，并图案化初始n型氮化镓层160和初始氮化镓缓冲层150。得到P型氮化镓层122、量子阱层121、n型氮化镓层16和氮化镓缓冲层15。
示例性的，通过光刻工艺图案化初始量子阱层1210和初始P型氮化镓层1220，去除相邻的子像素发光功能层12之间区域和负极区域S17的初始量子阱层1210和初始P型氮化镓层1220。
例如，如图7A和图7B所示，初始芯片晶圆单元110包括三个子像素 区域S1和一个负极区域S17，三个子像素区域S1分别为第一子像素区S11、第二子像素区S12和第三子像素区S13。通过光刻工艺图案化初始量子阱层1210和初始P型氮化镓层1220，去除了三个子像素区域S1和负极区域S17之外区域的初始量子阱层1210和初始P型氮化镓层1220。可以理解的是，三个子像素区域S1即为芯片结构10的发光区。即子像素区域S1和负极区域S17同时也是芯片结构10的子像素区域S1和负极区域S17。
芯片晶圆单元11的多个子像素发光功能层12包括第一子像素发光功能层12a、第二子像素发光功能层12b和第三子像素发光功能层12c。第一子像素发光功能层12a位于第一子像素区S11，第二子像素发光功能层12b位于第二子像素区S12，第三子像素发光功能层12c位于第三子像素区S13。负极区域S17用于形成公共阴极层17，公共阴极层17的介绍具体见下述内容，此处不在赘述。
如图7A和图7B所示，本步骤形成了第一子像素发光功能层12a的第一量子阱层121a和第一p型氮化镓层122a，第二子像素发光功能层12b的第二量子阱层、第二p型氮化镓层，第三子像素发光功能层12c的第三量子阱层、第三p型氮化镓层。其中，图7A为图7B沿AA截面线得到的截面图。
示例性的，采用光刻工艺图案化初始n型氮化镓层160和初始氮化镓缓冲层150，形成n型氮化镓层16和氮化镓缓冲层15，其中，n型氮化镓层16为连接第一子像素发光功能层12a、第二子像素发光功能层12b、第三子像素发光功能层12c和公共阴极层17的导电层。
S103：如图8所示，形成电流扩展层125。
示例性的，先形成初始电流扩展层，通过光刻工艺图案化初始电流扩展层，形成电流扩展层125。电流扩展层125包括位于第一子像素区S11的第一电流扩展层125a、位于第二子像素区S12(图中未示出，可以参见图7B)的第二电流扩展层和位于第三子像素区S13(图中未示出，可以参见图7B)的第三电流扩展层。
电流扩展层125的材料采用ITO(氧化铟锡)，在子像素区域S1设置电流扩展层125，有利于空穴的传输，提高芯片结构10的电学性能。
在一些示例中，如图9所示，初始芯片晶圆单元110的制备方法还包括形成反射金属层123的步骤。
示例性的，在电流扩展层125远离第二衬底14的一侧形成初始反射金属层，通过光刻工艺图案化初始反射金属层，形成每个子像素发光功能 层12的反射金属层123。反射金属层123具有反射光线的作用，可以提高子像素发光功能层12的出光率。
需要说明的是，在以下示例性附图中，未示出反射金属层123。
S104：如图10A和图10B所示，形成阴极金属层17a。其中，图10A为图10B沿BB截面线得到的截面图。
示例性的，通过光刻工艺形成阴极金属层17a。
示例性的，阴极金属层17a的材料可以为钛、铝、镍和金中的任一种。
示例性的，如图10B所示，阴极金属层17a包括覆盖负极区域S17的第一部分S17c，和位于公共阴极层17和相邻的子像素发光功能层12之间的第二部分S17b。
如图10B所示，阴极金属层17a还包括位于相邻两个子像素发光功能层12之间的部分。阴极金属层17a具有连接n型氮化镓层16和垫高阴极电极17b(图中未示出，可以参见图11A)的作用。位于相邻两个子像素发光功能层12之间的阴极金属层17a的部分称为支撑金属层S17a。通过在公共阴极层17和相邻的子像素发光功能层12之间的设置阴极金属层17a的第二部分S17b，以及在子像素发光功能层12之间设置支撑金属层S17a，一方面可以对芯片结构10进行加固，防止芯片结构10开裂。另一方面增大阴极金属层17a的体积，可以降低芯片结构10的电阻。
在一些示例中，如图10B所示，阴极金属层17a位于相邻两个子像素发光功能层12之间的部分，与两个子像素发光功能层12之间存在间距d4。子像素发光功能层12与阴极金属层17a之间的间距d4范围，为相邻的两个子像素发光功能层12之间的间距d5范围的1/10～1/3。
示例性的，子像素发光功能层12与阴极金属层17a之间的间距d4范围，为相邻的两个子像素发光功能层12之间的间距d5范围的1/10、1/4或1/3等，此处并不设限。
通过在相邻两个子像素发光功能层12之间设置支撑金属层S17a，并且将子像素发光功能层12与阴极金属层17a之间的间距d4范围，设置为相邻的两个子像素发光功能层12之间的间距d5范围的1/10～1/3，可以在保证芯片结构10的子像素发光功能层12所在区域的开口率的情况下，增大阴极金属层17a的面积，从而降低芯片结构10的电阻，并防止芯片结构10开裂，提高芯片结构10的稳定性。
示例性的，如图10B所示，子像素发光功能层12与阴极金属层17a之间的间距d4范围为8μm～10μm。
示例性的，子像素发光功能层12与阴极金属层17a之间的间距d4为8μm、9μm或10μm等，此处并不设限。
S105：如图10A和图10B所示，形成绝缘层18，绝缘层18上设置有多个过孔H。
示例性的，通过沉积工艺在阴极金属层17a远离第二衬底14的一侧形成初始绝缘层，通过光刻工艺形成多个过孔H。如图10B所示，多个过孔H包括第一过孔H1、第二过孔H2、第三过孔H3和第四过孔H4。第一过孔H1与第一子像素发光功能层12a对应设置，第二过孔H2与第二子像素发光功能层12b对应设置，第三过孔H3与第三子像素发光功能层12c对应设置，第四过孔H4与负极区域S17对应设置。
S106：如图11A和图11B所示，形成电极19，其中，电极19包括第一阳极124a、第二阳极192、第三阳极193和阴极电极17b。其中，图11A为图11B沿CC截面线得到的截面图。
其中，第一阳极124a、第二阳极192和第三阳极193称为阳极电极。
示例性的，通过构图工艺形成电极19。其中，第一阳极124a与第一子像素发光功能层12a对应设置，第二阳极192与第二子像素发光功能层12b对应设置，第三阳极193与第三子像素发光功能层12c，阴极电极17b和阴极金属17a形成公共阴极层17。
S107：如图12所示，在电极19远离第二衬底14的一侧键合临时衬底20。
示例性的，通过采用临时粘合层41和解粘层42临时键合临时衬底20，临时粘合层41具有粘合作用，解粘层42可以在紫外光的照射下解粘。临时粘合层41和解粘层42具有临时粘合临时衬底20的作用。
S108：如图13所示，去除第二衬底14。
去除第二衬底14后形成初始芯片晶圆单元110。
示例性的，第二衬底14可以为蓝宝石衬底，通过激光剥离蓝宝石衬底。
示例性的，第二衬底14可以硅基衬底，采用防酸膜或蜡封的方式保护临时衬底20，将初始芯片晶圆单元110放置在氢氟酸(HF)刻蚀槽中，通过刻蚀去除第二衬底14。
可以理解的，初始芯片晶圆单元110与芯片晶圆单元11相比，初始 芯片晶圆单元110在电极19远离氮化镓缓冲层15的一侧设置有临时衬底20。将初始芯片晶圆单元110上的临时衬底20以及粘合层41和解粘层42去除，即为芯片晶圆单元11。
以下介绍色转换层单元21的制备步骤，如图14所示，包括步骤R201～R203。
R201：如图15A所示，在初始第一衬底310上形成彩膜层24和限定坝层25。
彩膜层24包括黑矩阵层23、以及由黑矩阵层23限定的多个滤光膜层28，限定坝层25设置于彩膜层24远离初始第一衬底310的一侧。
示例性的，初始第一衬底310可以为玻璃衬底。
示例性的，采用涂覆、曝光、显影、后烘等方式形成黑矩阵层23，以及由黑矩阵层23限定的多个滤光膜层28。例如，如图15B所示，多个滤光膜层28包括第一滤光膜241、第二滤光膜242和第三滤光膜243。例如，第一滤光膜241为红色滤光膜，第二滤光膜242为蓝色滤光膜，第三滤光膜243为绿色滤光膜。其中，图15A为图15B沿DD截面线得到的截面图。
示例性的，如图15A所示，在黑矩阵层23远离初始第一衬底310的一侧采用涂覆、曝光、显影、后烘等方式形成限定坝层25，限定坝层25上限定有多个开口区K。例如，如图15B所示，多个开口区K包括第一开口区K1，第二开口区K2和第三开口区K3。
R202：如图16A所示，形成色转换层22。
示例性的，如图16B所示，在第一开口区K1、第二开口区K2和第三开口区K3采用涂覆、曝光、显影、后烘等方式或喷墨打印的方式制作色转换层22。示例性的，色转换层22包括第一量子点转换部22a、散射粒子部22b和第三量子点转换部22c。其中，第一开口区K1内形成第一量子点转换部22a，第一量子点转换部22a采用红色量子点发光材料；第二开口区K2内形成散射粒子部22b，设置散射粒子；第三开口区K3内形成第三量子点转换部22c，第三量子点转换部22c采用绿色量子点发光材料。其中，图16A为图16B沿EE截面线得到的截面图。
R203：如图17所示，形成无机封装层26。
形成无机封装层26后，即得到色转换层单元21。
示例性的，采用CVD(化学气相沉积)方式在色转换层22远离初始第一衬底310的一侧沉积无机封装层26，无机封装层26覆盖色转换层22和限定坝层25。
以下介绍形成贴合层13的步骤，以及通过贴合层13实现色转换层单元21和初始芯片晶圆单元110的对盒，形成芯片结构10的步骤，如图18所示，包括步骤T301～T306。
T301：如图19所示，在初始芯片晶圆单元110远离临时衬底20的一侧形成第一氧化铟锌层131a。
即在氮化镓缓冲层15远离临时衬底20的一侧形成第一氧化铟锌层131a。
示例性的，通过光刻工艺形成第一氧化铟锌层131a。
需要说明的是，在初始芯片晶圆单元110制备过程中，是同步形成包括多个阵列排布的初始芯片晶圆单元110的第一大板M，如图20所示。本步骤在第一大板M的初始芯片晶圆单元110上形成第一氧化铟锌层。然后，对第一大板M进行切割，例如进行异形切割，形成多个第一初始晶片A，如图21所示，第一初始晶片A为圆形，第一初始晶片A包括设置有第一氧化铟锌层131a的多个初始芯片晶圆单元110。示例性的，第一初始晶片A的尺寸为4寸或者6寸。
T302：如图22所示，在色转换层单元21远离初始第一衬底310的一侧形成第二氧化铟锌层131b。
即在无机封装层26远离初始第一衬底310的一侧形成第二氧化铟锌层131b。
示例性的，通过光刻工艺形成第二氧化铟锌层131b。
在色转换层单元21制备的过程中，是同步形成包括多个阵列排布的色转换层单元21的第二大板N，如图23所示。本步骤在第二大板N的色转换层单元21上形成第二氧化铟锌层131b。然后，对第二大板N进行切割，例如进行异形切割，形成多个第二初始晶片B，如图24所示，第二初始晶片B为圆形，第二初始晶片B包括设置有第二氧化铟锌层131b的多个色转换层单元21。第二初始晶片B与第一初始晶片A尺寸相同。
以下介绍由第一初始晶片A和第二初始晶片B对盒，最终形成单个芯片结构10的步骤。需要说明的是，以下均以一个芯片结构10的形成为例表示。
T303：如图25所示，键合第一氧化铟锌层131a和第二氧化铟锌层131b。
通过第一氧化铟锌层131a和第二氧化铟锌层131b的键合，实现初始芯片晶圆单元110和色转换层单元21的键合。
示例性的，第一氧化铟锌层131a的厚度d11和第二氧化铟锌层131b的厚度d12可以相同，也可以不同，此处并不设限。第一氧化铟锌层131a 的厚度d11与第二氧化铟锌层131b的厚度d12之和即为氧化铟锌键合层131的膜层厚度。
示例性的，键合第一氧化铟锌层131a和第二氧化铟锌层131b的步骤包括U1～U3：
U1：将第一氧化铟锌层131a远离临时衬底20的一侧表面采用氧气等离子体进行处理，使得第一氧化铟锌层131a的表面活化。
U2：将第二氧化铟锌层131b远离初始第一衬底310的一侧表面采用氧气等离子体进行处理，使得第二氧化铟锌层131b的表面活化。
U3：将第一氧化铟锌层131a和第二氧化铟锌层131b在150℃～240℃的温度条件下压合形成贴合层13。
示例性的，相升温至150℃，然后施加15000N的压力，再升温至200℃，升温速度为10℃/min。然后保持30min，即可形成贴合层13。
T304：去除临时衬底20。
去除临时衬底20后，初始芯片晶圆单元110形成为芯片晶圆单元11，结构如图26所示。
示例性的，通过紫外光的照射下使得解粘层42解粘，去除临时粘合层41、解粘层42以及临时衬底20。
T305：减薄初始第一衬底310，形成第一衬底31。
该步骤后，得到包含多个如图1所示的芯片结构10的结构。
示例性的，将初始第一衬底310的厚度减薄至60μm～200μm。这样形成的芯片结构10的形状接近正方体，使得芯片结构10放置更稳固，而且有利于后续工序的使用。在芯片结构10制备的过程中使用较厚的初始第一衬底310有利于芯片结构10的加工。
示例性的，通过在初始第一衬底310第一侧贴防酸膜，然后将初始第一衬底310的第二侧进行减薄，其中，多个子像素发光功能层12设置于初始第一衬底310的第一侧。
T306：切割，得到单个芯片结构10。
示例性的，在第一衬底31远离电极19的一侧贴蓝膜进行保护，然后采用激光进行切割，得到单个芯片结构10。
通过以上步骤S101～S108、步骤R201～R203和步骤T301～T306形成如图1所示芯片结构10，氧化铟锌键合层131在多个子像素发光功能层12上的投影，覆盖多个子像素发光功能层12。也就是说，采用氧化铟锌键合层131作为贴合层13时，氧化铟锌键合层131为整层设置，氧化铟 锌键合层131在第一衬底31上的正投影，完全覆盖多个子像素发光功能层12在第一衬底31上的正投影。氧化铟锌键合层131为透明的膜层，因此，整层设置的氧化铟锌键合层131不影响多个子像素发光功能层12出射光线。本实施例使用氧化铟锌键合层131作为贴合层13，可以提高形成的贴合层13的精度，从而提高芯片结构10的产品良率，并且形成的芯片结构10的厚度较薄。
以下介绍芯片结构10的制备方法的第二种实施例，根据该实施例形成如图2所示的芯片结构10。需要说明的是，在芯片结构10制备的步骤中，可以参照图2与步骤图所示的内容理解芯片结构10的结构示例。
实施例2
示例性的，初始芯片晶圆单元110的制备步骤参见步骤S101～S108，色转换层单元21的制备步骤参见步骤R201～R203，此处不再赘述。
在形成初始芯片晶圆单元110和色转换层单元21后，通过粘合胶层133形成的贴合层13实现色转换层单元21和初始芯片晶圆单元110的对盒，形成芯片结构10，如图27所示，该步骤包括P301～P305。
P301：如图28所示，在初始芯片晶圆单元110远离临时衬底20的一侧涂覆粘合胶层133。
即在氮化镓缓冲层15远离临时衬底20的一侧涂覆粘合胶层133。
示例性的，粘合胶层133的材料为环氧树脂类的有机粘合材料，通过钢网印刷工艺形成粘合胶层133，且保证切割道102没有残留的形成粘合胶层133的材料。其中，如图4所示，切割道102位于晶圆101上相邻的两个芯片结构10之间。图4中仅示出了一条切割道102，可以理解的是，为了得到单个芯片结构10，每相邻的两个芯片结构10之间的区域均为切割道102。
可以理解的是，在初始芯片晶圆单元110制备过程中，是同步形成包括多个阵列排布的初始芯片晶圆单元110的大板。在色转换层单元21制备的过程中，是同步形成包括多个阵列排布的色转换层单元21的大板。在色转换层单元21和初始芯片晶圆单元110对盒之前，还包括切割初始芯片晶圆单元110的大板和色转换层单元21的大板的步骤。
对初始芯片晶圆单元110的大板进行切割，形成多个第三初始晶片C，第三初始晶片C包括设置有粘合胶层133的多个初始芯片晶圆单元110。对色转换层单元21的大板进行切割，形成多个第四初始晶片D，第四初始晶片D包括多个色转换层单元21。
对于第三初始晶片C和第四初始晶片D的结构可以参见图21和图 24关于第一初始晶片A和第二初始晶片B的示例，此处不再赘述。不同的是，第三初始晶片C为包括设置有粘合胶层133的多个初始芯片晶圆单元110，第一初始晶片A为包括设置有第一氧化铟锌层131a的多个初始芯片晶圆单元110。第四初始晶片D包括多个色转换层单元21，而第二初始晶片B为包括设置有第二氧化铟锌层131b的多个色转换层单元21。
以下介绍由第三初始晶片C和第四初始晶片D对盒，最终形成单个芯片结构10的步骤。
P302：如图29所示，对盒色转换层单元21和初始芯片晶圆单元110。
通过粘合胶层133将色转换层单元21和初始芯片晶圆单元110粘合。
P303：去除临时衬底20。
具体步骤可以参见步骤T304，此处不再赘述。
P304：减薄初始第一衬底310，形成第一衬底31。
具体步骤可以参见步骤T305，此处不再赘述。
P305：切割，得到单个芯片结构10。
具体步骤可以参见步骤T306，此处不再赘述。
通过以上步骤S101～S108、步骤R201～R203和P301～P305形成如图2所示的芯片结构10，贴合层13为粘合胶层133，粘合胶层133在多个子像素发光功能层12上的投影，覆盖多个子像素发光功能层12。也就是说，粘合胶层133为整层设置，粘合胶层133在第一衬底31上的正投影，覆盖多个子像素发光功能层12在第一衬底31上的正投影，粘合胶层133采用的是透明的有机粘合材料，整层设置的粘合胶层133不影响多个子像素发光功能层12出射光线。本实施例采用粘合胶层133作为贴合层13，可以提升Micro-LED的转移效率、降低芯片厚度以及提高制产品良率。
以下介绍芯片结构10的制备方法的第三种实施例，根据该实施例形成如图3所示的芯片结构10。需要说明的是，在此芯片结构10制备的步骤中，可以参照图3与步骤图所示的内容理解芯片结构10的结构示例。
实施例3
示例性的，初始芯片晶圆单元110的制备步骤参见步骤S101～S108，色转换层单元21的制备步骤参见步骤R201～R203，此处不再赘述。
在形成初始芯片晶圆单元110和色转换层单元21后，通过金属键合层132形成的贴合层13实现色转换层单元21和初始芯片晶圆单元110的对盒，形成芯片结构10，如图30所示，该步骤包括Q301～Q306。
Q301：如图31A和图31B所示，在初始芯片晶圆单元110远离临时衬底 20的一侧形成第一初始子金属层1310和第二初始子金属层1320。
即在氮化镓缓冲层15远离临时衬底20的一侧形成第一初始子金属层1310和第二初始子金属层1320。其中，图31A为图31B沿FF截面线得到的截面图。
示例性的，通过沉积工艺在氮化镓缓冲层15远离临时衬底20的一侧沉积整层的用于形成第一初始子金属层1310的材料，采用光刻工艺图案化形成第一初始子金属层1310，第一初始子金属层1310的材料可以采用Au(金)、Ag(银)、Pb(铅)和Sn(锡)中的任一种。
示例性的，如图31B所示，第一初始子金属层1310包括三个开口区K，三个开口区K分比为第一子开口区K11、第二子开口区K21和第三子开口区K31。第一子开口区K11与第一子像素区S11对应设置，第二子开口区K21与第二子像素区S12对应设置，第三子开口区K31与第三子像素区S13对应设置。其中，A与B对应设置是指，A和B在临时衬底20上的正投影相重合或者大致重合。例如，第一子开口区K11与第一子像素区S11对应设置，是指第一子开口区K11与第一子像素区S11在临时衬底20上的正投影相重合或者大致重合。
示例性的，如图31A和图31B所示，第二初始子金属层1320包括多个第一类金属凸点132t，第一类金属凸点132t的结构可以为圆柱形或圆锥形。
第二初始子金属层1320的材料可以为In(铟)，Au(金)和In(铟)形成共晶合金的温度为160℃，Ag(银)和In(铟)形成共晶合金的温度为180℃，Pb(铅)和In(铟)形成共晶合金的温度为200℃，Sn(锡)和In(铟)形成共晶合金的温度为120℃。
Q302：如图32A和图32B所示，在色转换层单元21远离初始第一衬底310的一侧形成第三初始子金属层1330。
即在无机封装层26远离初始第一衬底310的一侧形成第三初始子金属层1330。
示例性的，通过沉积工艺在无机封装层26远离初始第一衬底310的一侧沉积整层的用于形成第三初始子金属层1330的材料，采用光刻工艺图案化形成第三初始子金属层1330。第三初始子金属层1330的材料可以采用Au(金)、Ag(银)、Pb(铅)和Sn(锡)中的任一种。第三初始子金属层1330的材料可以与第一初始子金属层1310的材料相同。
示例性的，如图32B所示，第三初始子金属层1330包括三个开口区K，三个开口区K分别为第四子开口区K41、第五子开口区K51和第六子开口区 K61。第四子开口区K41与第一子像素区S11对应设置，第五子开口区K51与第二子像素区S12对应设置，第六子开口区K61与第三子像素区S13对应设置。
Q303：如图33所示，键合第一初始子金属层1310、第二初始子金属层1320和第三初始子金属层1330。
示例性的，通过金属晶圆键合技术实现第一初始子金属层1310、第二初始子金属层1320和第三初始子金属层1330的键合。金属晶圆键合技术是指，依靠两种不同的金属之间形成共晶合金以低于金属各自熔点的温度完全键合的技术。金属晶圆键合技术根据键合温度不同，可以分为固液互扩散键合技术和固态扩散键合技术。其中，固液互扩散键合技术对于膜层平整度的要求小于固态扩散键合技术。且固液互扩散键合技术键合强度高，键合时间短。因此，可以采用固液互扩散键合技术形成金属键合层132，实现色转换层单元21和初始芯片晶圆单元110的对盒。
如图33所示，形成的金属键合层132包括第一子金属层132a、第二子金属层132b和第三子金属层132c。第一初始子金属层1310、第二初始子金属层1320和第三初始子金属层1330通过金属晶圆键合技术形成金属键合层132，第二子金属层132b为部分第一初始子金属层1310、第二初始子金属层1320和部分第三初始子金属层1330形成的共晶合金层。
示例性的，如图33所示，金属键合层132包括第四开口区K4，第五开口区和第六开口区，第四开口区K4与第一子像素区S11对应设置，第五开口区与第二子像素区S12对应设置，第六开口区与第三子像素区S13对应设置。关于第二子像素区S12和第三子像素区S13的设置可以参见图32B。第一子开口区K11和第四子开口区K41形成第四开口区K4。同理，第二子开口区K21和第五子开口区K51形成第五开口区，第三子开口区K31和第六子开口区K61形成第六开口区。关于第二子开口区K21、第三子开口区K31、第五子开口区K51和第六子开口区K61的设置可以参见图31B和图32B。
Q304：去除临时衬底20。
具体步骤可以参见步骤T304，此处不再赘述。
Q305：减薄初始第一衬底310，形成第一衬底31。
具体步骤可以参见步骤T305，此处不再赘述。
Q306：切割，得到单个芯片结构10。
具体步骤可以参见步骤T306，此处不再赘述。
通过以上步骤S101～S108、步骤R201～R203和Q301～Q306形成如图3所 示的芯片结构10。贴合层13为金属键合层132，金属键合层132上需要设置与多个子像素发光功能层12对应的开口区K，由于金属键合层132不透光，因此，需要在金属键合层132对应子像素发光功能层12的区域设置开口以出射光线。需要说明的是，金属键合层132与子像素发光功能层12对应的区域，是指，子像素发光功能层12和金属键合层132在第一衬底31上的正投影重叠的区域。本实施例采用金属键合层132作为贴合层13，可以提高形成的贴合层13的精度。
在一些实施例中，如图34和图35所示，多个子像素发光功能层12中相邻的两个子像素发光功能层12之间的间距d5范围为30μm～80μm。
示例性的，相邻的两个子像素发光功能层12之间的间距d5，例如，第一子像素发光功能层12a和第二子像素发光功能层12b之间的间距d5为30μm、40μm、50μm、60μm、70μm、75μm或80μm等，此处并不设限。相邻的两个子像素发光功能层12之间的间距d5过小，例如，间距d5小于30μm，或引起相邻子像素发光功能层12之间的串色问题，将相邻的两个子像素发光功能层12之间的间距d5范围为30μm～80μm的设计，可以在保持芯片结构10亮度的情况下有效地防止串色。
结合上述内容，如图35所示，氧化铟锌键合层131在第一方向X上的尺寸d1范围为100nm～300nm，粘合胶层133在第一方向X上的尺寸d2范围为5μm～10μm，金属键合层132在第一方向X上的尺寸d3范围为6μm～12μm。贴合层13在第一方向X上的尺寸(例如，尺寸d1、尺寸d2或尺寸d3)，小于多个子像素发光功能层12中的相邻两个子像素发光功能层12之间的间距d5，这样设置可以避免子像素发光功能层12之间的串色干扰，提高芯片结构10的出光效果。
在一些实施例中，如图34和图35所示，在多个阳极电极中，相邻的两个阳极电极之间的间距d6，小于或等于两个阳极电极所在的两个子像素发光功能层12之间的间距d5。
示例性的，如图35所示，第一子像素发光功能层12a与第一阳极124a对应设置，第二子像素发光功能层12b与第二阳极192对应设置，第一阳极124a与第二阳极192之间的间距d6，小于第一子像素发光功能层12a和第二子像素发光功能层12b之间的间距d5。
通过设置相邻的两个阳极电极之间的间距d6，小于或等于两个阳极电极所在的两个子像素发光功能层12之间的间距d5，也就是说，阳极电极的边界超出所在的子像素发光功能层12的边界，这样阳极电极在具有导通作用的同 时，还可以保证阳极电极具有较大的面积进行光线反射，提升芯片结构10的出光效果。
需要说明的是，如图11B所示，阴极电极17b与相邻的电极19之间的间距d13，可以参照相邻的两个阳极电极之间的间距d6设置，此处不再赘述。
示例性的，相邻的两个阳极电极之间的间距d6范围为30μm～75μm，其中，阳极电极包括第一阳极124a、第二阳极192和第三阳极193。例如，相邻的两个阳极之间的间距d6，例如，第一阳极124a和第二阳极192之间的间距d6为30μm、35μm、40μm、45μm、50μm、55μm、65μm或75μm等，此处并不设限。
在一些实施例中，如图34和图35所示，滤光膜层28在第一衬底31上的投影，覆盖与滤光膜层28对应的子像素发光功能层12在第一衬底上的投影。色转换层22在第一衬底31上的投影，覆盖与色转换层22对应的滤光膜层28在第一衬底31上的投影。散射粒子部22b在第一衬底31上的投影，覆盖第二滤光膜242在第一衬底31上的投影。其中，图35为图34沿HH截面线得到的截面图。
也就是说，沿任何方向，滤光膜层28在第一衬底31上的投影尺寸，均大于滤光膜层28对应的子像素发光功能层12在第一衬底31上的投影尺寸。色转换层22在第一衬底31上的投影尺寸，大于与色转换层22对应的滤光膜层28在第一衬底31上的投影尺寸。散射粒子部22b在第一衬底31上的投影尺寸，大于第二滤光膜242在第一衬底31上的投影尺寸。
示例性的，滤光膜层28在第一衬底31上的投影边界，与滤光膜层28对应的子像素发光功能层12在第一衬底31上的投影边界的间距d7范围为20μm～60μm。例如，滤光膜层28在第一衬底31上的投影边界，与滤光膜层28对应的子像素发光功能层12在第一衬底31上的投影边界的间距d7为20μm、40μm、50μm或60μm等，此处并不设限。
示例性的，色转换层22在第一衬底31上的投影边界，与色转换层22对应的滤光膜层28在第一衬底31上的投影边界的间距d8范围为23μm～68μm。例如，色转换层22在第一衬底31上的投影边界，与色转换层22对应的滤光膜层28在第一衬底31上的投影边界的间距d8为23μm、30μm、35μm、42μm、50μm、60μm或68μm等，此处并不设限。
示例性的，散射粒子部22b在第一衬底31上的投影边界，与第二滤光膜242在第一衬底31上的投影边界的间距d9范围为23μm～68μm。例如，散射粒子部22b在第一衬底31上的投影边界，与第二滤光膜242在第一衬底31 上的投影边界的间距d9为23μm、32μm、38μm、45μm、55μm、62μm或68μm等，此处并不设限。
在一些实施例中，如图34和图35所示，限定坝层25在第一方向X上的尺寸d10范围为10μm～30μm。
示例性的，限定坝层25在第一方向X上的尺寸d10为10μm、15μm、20μm、25μm、28μm或30μm等，此处并不设限。将限定坝层25在第一方向X上的尺寸d10，即其厚度设置为10μm～30μm，增大了限定坝层25的厚度，由于色转换层22设置于限定坝层25的开口区K内，同步的增加了色转换层22的厚度，这样设计可以提高芯片结构10的发光效果。
在一些实施例中，如图35所示，色转换层单元21在第一衬底31上的投影，覆盖贴合层13在第一衬底31上的投影。
示例性的，贴合层13的材料采用环氧树脂类的有机粘合材料，通过设置色转换层单元21在第一衬底31上的投影，覆盖贴合层13在第一衬底31上的投影，可以保证切割道102(见附图4所示)的位置不会残留有机粘合材料，方便切割形成芯片结构10。
在一些示例中，如图35所示，色转换层单元21在第一衬底31上的投影边界，与贴合层13在第一衬底31上的投影边界的间距d14范围为0μm～10μm。
示例性的，色转换层单元21在第一衬底31上的投影边界，与贴合层13在第一衬底31上的投影边界的间距d14为0μm、2μm、5μm、7μm或10μm等，此处并不设限。
通过设置色转换层单元21在第一衬底31上的投影边界，与贴合层13在第一衬底31上的投影边界的间距d14范围为0μm～10μm，可以在保证芯片结构10贴合稳定性的情况下，在贴合层13的材料采用环氧树脂类的有机粘合材料时，保证切割道102(见附图4所示)的位置不会残留有机粘合材料。
本公开的一些实施例还提供一种显示基板100，如图36所示，显示基板100包括如上任一项实施例所述的多个芯片结构10。
在一些实施例中，显示基板100包括驱动背板，驱动背板包括线路层，多个芯片结构10设置于驱动背板上，线路层中例如包括多个焊盘组，每个焊盘组包括分离设置的多个焊盘，每个芯片结构10的阴极电极17b、第一阳极124a、第二阳极192和第三阳极193分别与多个焊盘中的一个焊盘对应电连接。
示例性地，多个芯片结构10通过巨量转移技术转移至驱动背板上。
本公开的一些实施例还提供一种显示装置1000，如图37所示，包括如 上所述的显示基板100。
示例性的，本公开实施例所提供的显示装置可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种芯片结构，包括：芯片晶圆单元和设置于所述芯片晶圆单元出光侧的色转换层单元；其中，所述芯片晶圆单元包括多个子像素发光功能层；所述色转换层单元包括设置于所述芯片晶圆单元出光侧的色转换层；
    还包括：贴合层，设置于所述芯片晶圆单元和所述色转换层单元之间，用于贴合所述芯片晶圆单元和所述色转换层单元。
  2. 根据权利要求1所述的芯片结构，其中，所述贴合层为氧化铟锌键合层、金属键合层和粘合胶层中的任一种。
  3. 根据权利要求1或2所述的芯片结构，其中，所述贴合层在第一方向上的尺寸，小于所述多个子像素发光功能层中的相邻两个子像素发光功能层之间的间距；
    其中，所述第一方向为由所述芯片晶圆单元指向所述色转换层单元的方向。
  4. 根据权利要求3所述的芯片结构，其中，所述贴合层为所述氧化铟锌键合层，所述氧化铟锌键合层在所述第一方向上的尺寸范围为100nm～300nm；
    或者，所述贴合层为所述金属键合层，所述金属键合层在所述第一方向上的尺寸范围为6μm～12μm；
    或者，所述贴合层为所述粘合胶层，所述粘合胶层在所述第一方向上的尺寸范围为5μm～10μm。
  5. 根据权利要求3或4所述的芯片结构，其中，
    所述贴合层为所述氧化铟锌键合层，所述氧化铟锌键合层包括沿第一方向层叠设置的第一氧化铟锌层和第二氧化铟锌层，所述第一氧化铟锌层和所述第二氧化铟锌层通过分子键键合作用相连接；
    或者，所述贴合层为所述金属键合层，所述金属键合层包括沿第一方向层叠设置的第一子金属层、第二子金属层和第三子金属层，所述第二子金属层设置为连接所述第一子金属层和所述第三子金属层的共晶合金层。
  6. 根据权利要求2～5任一项所述的芯片结构，其中，所述贴合层为所述氧化铟锌键合层，所述氧化铟锌键合层在所述多个子像素发光功能层上的投影，覆盖所述多个子像素发光功能层；
    或者，所述贴合层为所述金属键合层，所述金属键合层上设置有与所述多个子像素发光功能层对应的开口区；
    或者，所述贴合层为所述粘合胶层，所述粘合胶层在所述多个子像素发光功能层上的投影，覆盖所述多个子像素发光功能层。
  7. 根据权利要求2～6任一项所述的芯片结构，其中，所述芯片结构还包 括第一衬底，所述第一衬底设置于所述色转换层单元远离所述芯片晶圆单元的一侧；所述色转换层单元在所述第一衬底上的投影，覆盖所述贴合层在所述第一衬底上的投影。
  8. 根据权利要求7所述的芯片结构，其中，所述色转换层单元在所述第一衬底上的投影边界，与所述贴合层在所述第一衬底上的投影边界的间距范围为0μm～10μm。
  9. 根据权利要求1～8任一项所述的芯片结构，其中，所述多个子像素发光功能层中的每个子像素发光功能层包括沿第一方向层叠设置的阳极电极、电流扩展层、p型氮化镓层和量子阱层；
    所述芯片晶圆单元还包括公共阴极层，所述公共阴极层包括沿第一方向层叠设置的阴极电极和阴极金属层；
    其中，所述阴极金属层还包括位于相邻两个所述子像素发光功能层之间的部分；所述第一方向为由所述芯片晶圆单元指向所述色转换层单元的方向。
  10. 根据权利要求9所述的芯片结构，其中，所述阴极金属层位于相邻两个所述子像素发光功能层之间的部分，与两个所述子像素发光功能层之间存在间距；
    所述子像素发光功能层与所述阴极金属层之间的间距范围，为相邻的两个子像素发光功能层之间的间距范围的1/10～1/3。
  11. 根据权利要求9或10所述的芯片结构，其中，在多个所述阳极电极中，相邻的两个所述阳极电极之间的间距范围，小于或等于两个所述阳极电极所在的两个所述子像素发光功能层之间的间距范围。
  12. 根据权利要求1～11任一项所述的芯片结构，其中，所述芯片晶圆单元还包括沿第一方向层叠设置的n型氮化镓层和氮化镓缓冲层；所述n型氮化镓层设置于所述多个子像素发光功能层的出光侧；
    所述贴合层设置于所述氮化镓缓冲层远离所述n型氮化镓层的一侧；其中，所述第一方向为由所述芯片晶圆单元指向所述色转换层单元的方向。
  13. 根据权利要求1～12任一项所述的芯片结构，其中，所述多个子像素发光功能层包括第一子像素发光功能层、第二子像素发光功能层和第三子像素发光功能层；
    所述芯片结构还包括第一衬底，所述色转换层单元包括设置于所述第一衬底一侧的彩膜层；所述彩膜层包括黑矩阵层、以及由所述黑矩阵层限定的多个滤光膜层；所述多个滤光膜层包括：第一滤光膜层、第二滤光膜层和第三滤光膜层，所述第一滤光膜层与所述第一子像素发光功能层对应设置，所 述第二滤光膜层与所述第二子像素发光功能层对应设置，所述第三滤光膜层与所述第三子像素发光功能层；
    所述色转换层单元还包括设置于所述彩膜层远离所述第一衬底一侧的限定坝层，所述限定坝层设置有多个开口区；所述多个开口区包括：第一开口区、第二开口区和第三开口区；所述第一开口区与所述第一子像素发光功能层对应设置，所述第二开口区与所述第二子像素发光功能层对应设置，所述第三开口区与所述第三子像素发光功能层对应设置；
    所述色转换层还包括第一量子点转换部、第二量子点转换部和散射粒子部；所述第一量子点转换部设置于所述第一开口区内，所述散射粒子部设置于所述第二开口区内，所述第二量子点转换部设置于所述第三开口区内。
  14. 根据权利要求13所述的芯片结构，其中，
    所述滤光膜层在所述第一衬底上的投影，覆盖与所述滤光膜层对应的所述子像素发光功能层在所述第一衬底上的投影；
    所述量子点转换部在所述第一衬底上的投影，覆盖与所述量子点转换部对应的所述滤光膜层在所述第一衬底上的投影；
    所述散射粒子部在所述第一衬底上的投影，覆盖所述第二滤光膜层在所述第一衬底上的投影。
  15. 根据权利要求14所述的芯片结构，其中，
    所述滤光膜层在所述第一衬底上的投影边界，与所述滤光膜层对应的所述子像素发光功能层在所述第一衬底上的投影边界的间距范围为20μm～60μm；
    所述量子点转换部在所述第一衬底上的投影边界，与所述量子点转换部对应的所述滤光膜层在所述第一衬底上的投影边界的间距范围为23μm～68μm；
    所述散射粒子部在所述第一衬底上的投影边界，与所述第二滤光膜层在所述第一衬底上的投影边界的间距范围为23μm～68μm。
  16. 根据权利要求13～15任一项所述的芯片结构，其中，所述限定坝层在第一方向上的尺寸范围为10μm～30μm；
    其中，所述第一方向为由所述芯片晶圆单元指向所述色转换层单元的方向。
  17. 一种芯片结构的制备方法，包括：
    形成初始芯片晶圆单元，所述初始芯片晶圆单元包括层叠设置的临时衬底、多个子像素发光功能层、n型氮化镓层和氮化镓缓冲层；
    形成色转换层单元，在初始第一衬底上形成所述色转换层单元；
    将所述色转换层单元贴合在所述初始芯片晶圆单元的出光侧，得到芯片结构。
  18. 根据权利要求17所述的芯片结构的制备方法，其中，所述将所述色转换层单元贴合在所述初始芯片晶圆单元的出光侧的步骤包括：
    在所述初始芯片晶圆单元远离所述临时衬底的一侧形成第一氧化铟锌层；
    在所述色转换层单元远离所述初始第一衬底的一侧形成第二氧化铟锌层；
    键合所述第一氧化铟锌层和所述第二氧化铟锌层，形成连接所述初始芯片晶圆单元和所述色转换层单元的贴合层；
    或，所述将所述色转换层单元贴合在所述初始芯片晶圆单元的出光侧的步骤包括：
    在所述初始芯片晶圆单元远离所述临时衬底的一侧形成第一初始子金属层和第二初始子金属层，其中，所述第二初始子金属层为形成于所述第一初始子金属层远离所述临时衬底一侧的多个第一类金属凸点；
    在所述色转换层单元远离所述初始第一衬底的一侧形成第三初始子金属层；
    键合所述第一初始子金属层、所述第二初始子金属层和所述第三初始子金属层，形成连接所述初始芯片晶圆单元和所述色转换层单元的贴合层；
    或，所述将所述色转换层单元贴合在所述初始芯片晶圆单元的出光侧的步骤包括：
    采用贴合胶连接所述初始芯片晶圆单元和所述色转换层单元。
  19. 根据权利要求18所述的芯片结构的制备方法，其中，所述键合所述第一氧化铟锌层和所述第二氧化铟锌层的步骤包括：
    将所述第一氧化铟锌层远离所述临时衬底的一侧表面采用氧气等离子体进行处理；
    将所述第二氧化铟锌层远离所述初始第一衬底的一侧表面采用氧气等离子体进行处理；
    将所述第一氧化铟锌层和所述第二氧化铟锌层在150℃～240℃的温度条件下压合形成贴合层。
  20. 根据权利要求17～19任一项所述的芯片结构的制备方法，其中，所述将所述色转换层单元贴合在所述初始芯片晶圆单元的出光侧之后，包括：
    去除所述临时衬底，形成芯片晶圆单元；
    将所述初始第一衬底的厚度减薄，形成第一衬底，得到芯片结构。
  21. 一种显示基板，包括如权利要求1～16任一项所述的芯片结构。
  22. 一种显示装置，包括如权利要求21所述的显示基板。
PCT/CN2022/099909 2022-06-20 2022-06-20 芯片结构及其制备方法、显示基板和显示装置 WO2023245352A1 (zh)

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