WO2023159405A1 - 线路板及其制造方法、功能背板、背光模组、显示装置 - Google Patents

线路板及其制造方法、功能背板、背光模组、显示装置 Download PDF

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Publication number
WO2023159405A1
WO2023159405A1 PCT/CN2022/077542 CN2022077542W WO2023159405A1 WO 2023159405 A1 WO2023159405 A1 WO 2023159405A1 CN 2022077542 W CN2022077542 W CN 2022077542W WO 2023159405 A1 WO2023159405 A1 WO 2023159405A1
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Prior art keywords
layer
stacked structure
base substrate
circuit board
conductive layer
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PCT/CN2022/077542
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English (en)
French (fr)
Inventor
张家祥
姚念琦
王珂
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/017,902 priority Critical patent/US20240260185A1/en
Priority to PCT/CN2022/077542 priority patent/WO2023159405A1/zh
Priority to CN202280000254.6A priority patent/CN116965159A/zh
Publication of WO2023159405A1 publication Critical patent/WO2023159405A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/12—Application of an electrode to the exposed surface of the selenium or tellurium after the selenium or tellurium has been applied to the foundation plate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/067—Etchants
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10151—Sensor

Definitions

  • the present disclosure relates to the field of display technology, in particular, to a circuit board and a manufacturing method thereof, a functional backplane, a backlight module, a display device, and a display panel.
  • a circuit board in one aspect, includes: a base substrate; traces disposed on the base substrate, the traces comprising a first conductive layer; at least one insulating layer disposed on the The first conductive layer is away from the side of the base substrate, and the at least one insulating layer covers the first conductive layer; wherein the first conductive layer includes a first stacked structure on the side away from the base substrate and a second stacked structure close to the base substrate, the first stacked structure at least includes an etching stopper layer, and the etching stopper layer covers the second stacked structure.
  • the first stacked structure includes the etching barrier layer, the first metal layer, and the first oxidation barrier layer that are sequentially away from the base substrate; wherein, the etching Orthographic projections of the barrier layer, the first metal layer and the first oxidation barrier layer on the base substrate overlap.
  • the first oxidation barrier layer covers the first metal layer, and the first metal layer covers the etch barrier layer.
  • the second stacked structure includes an adhesive layer, a second metal layer, and a second oxidation barrier layer that are sequentially away from the base substrate, and the second oxidation barrier layer and the The orthographic projection of the second metal layer on the base substrate is located within the orthographic projection of the adhesive layer on the base substrate.
  • the included angle between the side of the first stacked structure in the length direction and the plane where the base substrate is located is in the range of 60° to 90°.
  • the included angle between the side of the second stacked structure in the length direction and the plane where the base substrate is located is in the range of 60° to 80°.
  • the thickness of the etch stop layer is greater than The thickness of the first metal layer is to range, the thickness of the first oxidation barrier layer is less than
  • the etching barrier layer includes NiV alloy and NiW alloy
  • the first metal layer includes copper
  • the first oxidation barrier layer includes CuNi alloy
  • the thickness of the adhesive layer is between to In the range of , the thickness of the second metal layer is in to In the range of , the thickness of the second oxidation barrier layer is to In the range.
  • the adhesive layer includes Mo or MoNb alloy
  • the second metal layer includes copper
  • the second oxidation barrier layer includes NiV alloy and NiW alloy.
  • the NiV alloy has a V element mass content in the range of 3% to 15%, and the NiW alloy has a W element mass content in the range of 10% to 50%.
  • the content of Ni element in the CuNi alloy is in the range of 10% to 30% by mass.
  • the wiring further includes: a second conductive layer disposed between the base substrate and the first conductive layer, the first conductive layer and the first conductive layer The two conductive layers are separated by at least one insulating layer.
  • the circuit board further includes: an alignment mark disposed between the base substrate and the first conductive layer.
  • the circuit board further includes a via hole penetrating through the at least one insulating layer, wherein the via hole exposes a part of the surface of the first conductive layer away from the base substrate.
  • a method for manufacturing a circuit board including: forming a base substrate; forming traces on the base substrate, forming the traces includes forming a first conductive layer; forming at least one an insulating layer, the insulating layer is disposed on a side of the first conductive layer away from the base substrate, and the at least one insulating layer covers the first conductive layer; wherein, the first conductive layer includes A first stacked structure on one side of the base substrate and a second stacked structure close to the base substrate, the first stacked structure at least includes an etching barrier layer, and the etching barrier layer covers the second stacked structure .
  • the forming the first conductive layer includes: depositing and forming a second stacked structure film layer including a second stacked structure on a side close to the base substrate, for the second Etching the film layer of the stacked structure to form the second stacked structure; forming a film layer of the first stacked structure including the first stacked structure on the side of the second stacked structure away from the base substrate, for the second stacked structure Etching is performed on one stacked structure film layer to form a first stacked structure.
  • a functional backplane which includes: the circuit board as described above; along the direction perpendicular to the base substrate of the circuit board and away from the base substrate, stacked on the The intermetallic compound layer and the conductive connection layer on the circuit board; the electronic components are electrically connected with the conductive connection layer.
  • a backlight module including: the functional backplane as described above.
  • a display device comprising: a display panel; the above-mentioned backlight module; the display panel is disposed on the light emitting side of the backlight module.
  • a display panel including: the functional backplane as described above.
  • a display device including: the display panel as described above.
  • FIG. 1 is a schematic plan view of a circuit board according to an embodiment of the present disclosure
  • Fig. 2 is a schematic cross-sectional structure diagram of a circuit board along the line AA' in Fig. 1 according to an embodiment of the present disclosure
  • FIG. 3 is a photomicrograph of defects generated when the thickness of the second oxidation barrier layer is relatively large in the second stacked structure of the wiring board according to an embodiment of the present disclosure
  • FIG. 5 is a photomicrograph of a circuit board forming a first stacked structure on a second stacked structure according to an embodiment of the present disclosure
  • FIG. 6 is a flowchart of a method for manufacturing a circuit board according to an embodiment of the present disclosure
  • FIG. 7 is a flow chart of forming a first conductive layer in a manufacturing method of a circuit board according to an embodiment of the present disclosure
  • Fig. 8 is a schematic structural diagram of a functional backplane according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a backlight module according to an embodiment of the disclosure.
  • Fig. 10 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of another display device according to an embodiment of the present disclosure.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” or “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality” means two or more.
  • connection When describing some embodiments, the expression “connected” and its derivatives may be used.
  • electrically connected may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel As used herein, “parallel”, “perpendicular”, and “equal” include the stated situation and the situation similar to the stated situation, the range of the similar situation is within the acceptable deviation range, wherein the The stated range of acceptable deviation is as determined by one of ordinary skill in the art taking into account the measurement in question and errors associated with measurement of the particular quantity (ie, limitations of the measurement system).
  • “parallel” includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; Deviation within 5°.
  • “Equal” includes absolute equality and approximate equality, where the difference between the two that may be equal is less than or equal to 5% of either within acceptable tolerances for approximate equality, for example.
  • a layer or element when referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or that the layer or element can be on another layer or substrate. There is an intermediate layer in between.
  • the "same layer” in this article refers to the layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using a mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights Or have different thicknesses.
  • heterolayer refers to the layer structure formed by using the corresponding film forming process to form the film layer for forming a specific pattern, and then using the corresponding mask plate to form the layer structure through the patterning process, for example, "two layer structure "Different layer arrangement” refers to the formation of two layer structures under corresponding process steps (film-forming process and patterning process).
  • Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
  • SMT surface mount technology
  • IMC intermetallic compound
  • an embodiment of the present disclosure provides a circuit board, which includes but is not limited to: a base substrate; traces provided on the base substrate, the traces include a first conductive layer; at least one insulating layer, It is arranged on the side of the first conductive layer away from the base substrate, and at least one insulating layer covers the first conductive layer; wherein, the first conductive layer includes a first stacked structure on the side away from the base substrate and a layer close to the base substrate.
  • the second stacked structure, the first stacked structure at least includes an etching barrier layer, and the etching barrier layer covers the second stacked structure.
  • the etch stop layer by setting the etch stop layer, it is possible to effectively prevent the second stack structure from forming an undercut structure (undercut) or a roof structure (tip) during etching, so that other stack structures laid on the conductive layer
  • the structure can effectively cover the conductive layer, on the one hand, improve the yield rate when the circuit board is repeatedly soldered at the first conductive layer, and at the same time improve the yield rate of the circuit board production.
  • circuit board of the embodiment of the present disclosure will be described in detail below with reference to FIG. 1 to FIG. 5 .
  • FIG. 1 is a schematic plan view of a circuit board according to an embodiment of the present disclosure.
  • the circuit board 100 includes a device area 110 and a binding area 120 , for example, the binding area 120 is located on one side of the device area 110 .
  • the circuit board 100 includes a first conductive layer 30 and a second conductive layer 40 (40') disposed in the device region 110, wherein the exposed area of the first conductive layer 30 is configured to be connected to the pins of the electronic component 230, and also includes The plurality of conductive terminals H2 disposed on the bonding area 120 to be connected to the circuit board, the plurality of conductive terminals H2 may be disposed on the same layer as the second conductive layer 40 .
  • the electronic components may include at least one of inorganic light-emitting diodes, sensor chips, and integrated circuit chips with a size below 500 microns, wherein the inorganic light-emitting diodes and/or sensor chips may be driven by integrated circuit chips, or inorganic light-emitting diodes
  • the diode and/or sensor chip is driven by a combination of multiple interconnected and mated thin film transistors arranged on a circuit board.
  • Fig. 2 is a schematic cross-sectional structure diagram of a circuit board along line AA' in Fig. 1 according to an embodiment of the present disclosure.
  • the circuit board 100 includes a base substrate 10 , a wiring 20 disposed on the base substrate, and the wiring 20 includes a first conductive layer 30 and a second conductive layer 40 .
  • At least one insulating layer is disposed on a side of the first conductive layer 30 away from the base substrate 10 , and the insulating layer covers the first conductive layer 30 .
  • the first conductive layer 30 includes a first stacked structure 31 on a side away from the base substrate 10 and a second stacked structure 32 on a side close to the base substrate 10 .
  • the first stacked structure 31 and the second stacked structure 32 are covered by at least one insulating layer.
  • each stacked structure has a plurality of sublayers, wherein at least one sublayer of the first stacked structure 31 is set as an etch stop layer 311 covering the second stacked structure 32 .
  • the etch barrier layer By setting the etch barrier layer to cover the second stacked structure 32, it is ensured that when the first stacked structure 31 is etched, the etch barrier layer 311 can block the etching medium from etching the second stacked structure 32, effectively avoiding
  • the difference in etching rate of the second stacked structure by the etchant causes defects such as an undercut structure in the second stacked structure 32 relative to the first stacked structure 31 and a roof structure in the first stacked structure 31 relative to the second stacked structure 32 .
  • the first stacked structure 31 includes an etching barrier layer 311 , a first metal layer 312 and a first oxidation barrier layer 313 which are sequentially separated from the base substrate 10 .
  • the function of the etching stopper layer 311 is as described above, for blocking the second stacked structure 32 from being etched by the etching medium.
  • the first metal layer 312 is used for transmission of electrical signals in the circuit.
  • the first oxidation barrier layer 313 is disposed on a side of the first metal layer 312 away from the base substrate 10 for blocking oxidation of the first metal layer 312 . That is, during the process of soldering with electronic components, the material used for transmitting electrical signals of the first metal layer 312 is prone to oxidation, and the first metal layer 312 can be protected by providing the first oxidation barrier layer 313 .
  • the orthographic projections of the etching barrier layer 311 , the first metal layer 312 and the first oxidation barrier layer 313 on the base substrate 10 overlap.
  • the orthographic projection of the etch barrier layer 311 on the base substrate 10 is located within the orthographic projection of the first metal layer 312 on the base substrate 10, and the first metal layer 312 is on the base substrate 10
  • the orthographic projection of is located within the orthographic projection of the first oxidation barrier layer 313 on the base substrate 10, that is, when the first stacked structure is formed, the etching barrier layer 311, the first metal layer 312, and the first oxidation barrier layer 313 are on the substrate
  • the area of the orthographic projection on the substrate 10 gradually increases.
  • the orthographic projections of the etching barrier layer 311 , the first metal layer 312 and the first oxidation barrier layer 313 on the base substrate 10 may be completely coincident.
  • the first oxidation barrier layer 313 covers the first metal layer 312 , and the first metal layer 312 covers the etch barrier layer 311 .
  • the first oxidation barrier layer 313 covers the first metal layer 312, so as to protect the first metal layer 312.
  • the first metal layer 312 covers the etching barrier layer 311, so as to reduce the corrosion caused by etching when forming the first stacked structure.
  • the etchant has a slow etching speed for the etching barrier layer, but a fast etching speed for the first metal layer 312 and the first oxidation barrier layer 313, which again causes the undercut of the second stacked structure 32 relative to the first stacked structure 31
  • the first laminated structure 31 has defects such as a roof structure. Through this setting method, the generation of defects can be effectively reduced, and the yield rate of products can be improved.
  • the second stacked structure 32 includes an adhesive layer 321 , a second metal layer 322 and a second oxidation barrier layer 323 which are sequentially away from the base substrate 10 .
  • the second laminated structure 32 By arranging the second laminated structure 32 as a structure with multiple sub-layers, when the first conductive layer 30 is soldered, the soldering performance between the first conductive layer 30 and the electronic components can be ensured, preventing occurrence of multiple soldering failures. Poor contact and other issues.
  • At least one insulating layer is disposed between the base substrate 10 and the first conductive layer 30, for example, including a buffer layer for improving the stress between the base substrate 10 and other stacked structures, and then forming multiple An insulating layer, such as the first insulating layer 60 and the second insulating layer 51, forms the adhesive layer 321 on the second insulating layer 51, then forms the second metal layer 322 on the adhesive layer 321, and then forms the second metal layer 322 on the second metal A second oxidation barrier layer 323 is formed on layer 322 .
  • forming the adhesive layer 321 facilitates better adhesion between the second metal layer 322 and the resulting second metal layer 322 can adhere more firmly.
  • the second oxidation barrier layer 323 is formed on the second metal layer 322 to prevent the second metal layer 322 from being oxidized during soldering, thereby having a better protection effect on the second metal layer 322 .
  • the orthographic projections of the second oxidation barrier layer 323 and the second metal layer 322 on the base substrate 10 are located within the orthographic projection of the adhesive layer 321 on the base substrate 10 .
  • the second oxidation barrier layer 323 is located within the orthographic projection of the adhesive layer 321 on the base substrate 10, and the orthographic projection of the second metal layer 322 on the base substrate 10 is located within the projection of the adhesive layer 321 on the base substrate. . That is, the area of the orthographic projection of the second oxidation barrier layer 323 and the second metal layer 322 on the base substrate is smaller than the area of the orthographic projection of the adhesive layer on the base substrate 10 .
  • the widths of the two sides of the second oxidation barrier layer 323 and the second metal layer 322 are smaller than the width of the two sides of the adhesive layer 321, so as to reduce the difficulty of the process when forming the second stacked structure and effectively improve the product yield.
  • the angle ⁇ between the side of the first stacked structure 31 in the length direction and the plane where the base substrate 10 is located is in the range of 60° to 90°, for example, Set to 60°, 70°, 80° or 90°.
  • the angle ⁇ between the side of the second stacked structure 32 in the longitudinal direction and the plane of the base substrate 10 is in the range of 60° to 80°, for example, can be set to 60°, 70° or 80°.
  • the length direction of the first stacked structure 31 and the second stacked structure 32 is, for example, the direction perpendicular to the plane of the paper, and the side in the length direction refers to the direction parallel to the base substrate 10 in FIG. 2 both sides of the direction.
  • the material of the etch stop layer 311 of the first stacked structure 31 includes a nickel-based alloy.
  • the nickel-based alloy refers to nickel as a base metal doped with other metals.
  • the material of the first metal layer 312 includes copper (Cu). When copper is used as the material of the first metal layer, it is prone to oxidation during the soldering process.
  • the first oxidation barrier layer 313 is provided on the side of the first metal layer 312 away from the base substrate 10, which can effectively avoid the problem of oxidation of the first metal layer 312 during soldering, and improve the repairability and frequency of the circuit board 100 (maintenance rate), which reduces the scrap rate of the circuit board 100 and improves the cumulative yield.
  • the first oxidation barrier layer 313 includes copper-nickel alloy (CuNi).
  • the material of the adhesive layer 321 of the second stack structure 32 includes molybdenum-nickel-titanium alloy (MoNiTi), molybdenum (Mo) or molybdenum-niobium alloy (MoNb) and the like.
  • the second metal layer 322 includes conductive materials such as copper (Cu).
  • the second oxidation barrier layer 323 includes nickel vanadium alloy (NiV), nickel tungsten alloy (NiW), and the like. The second oxidation barrier layer 323 is disposed on the side of the second metal layer 322 away from the base substrate 10 , which effectively avoids oxidation of the second metal layer 322 during soldering, and further improves the rebuildability of the circuit board 100 .
  • the thickness and material of each sub-layer of the second stacked structure 32 are different, and their etching rates for the etching medium are different. Therefore, when the second stacked structure is etched by a photolithography process During the process, the etching speeds of different sub-layers are inconsistent, which will lead to problems of undercut structure (undercut) and roof structure (tip).
  • FIG. 3 is a photomicrograph of defects generated when the thickness of the second oxidation barrier layer is large in the second stacked structure of the wiring board according to an embodiment of the present disclosure.
  • the inventors of the present disclosure have found the relationship between the thickness of the film layer and the appearance of the film layer after etching. law.
  • the thickness of the second oxidation barrier layer 323 is greater than
  • the H 2 O 2 system is used. Since the etchant has different etching rates for different materials, for example, the etchant rate of the etchant for the second oxidation barrier layer 323 is compared to the etching rate of the second metal layer. The etch rate is slower.
  • the second oxidation barrier layer 323 When the thickness of the second oxidation barrier 323 is greater than At this time, the second oxidation barrier layer 323 will have a protruding roof structure relative to the film layer on the side close to the base substrate 10, and the length of the roof structure is greater than 0.2um. If other film layers continue to be formed on the second laminated structure 32, then This will cause the upper structure to fail to cover the lower structure well, that is, the film layer formed on the second laminated structure 32 cannot cover the lower area corresponding to the roof structure area of the second oxidation barrier layer 323 , reducing the yield of the product.
  • the inventors of the present disclosure found that by setting the thickness of the second barrier layer 323 within a certain range, it is possible to prevent the second barrier layer 323 from having a roof structure relative to the film layer on the side close to the substrate. question.
  • the inventors of the present disclosure found that when the thickness of the second oxidation barrier layer 323 is set at to Within the range, the protection of the second metal layer 322 can be achieved, and at the same time, the problem of the roof structure can be avoided when the second stacked structure is formed by etching.
  • FIG. 4 is a photomicrograph of defects generated when the thickness of the second oxidation barrier layer is small in the second stacked structure of the wiring board according to an embodiment of the present disclosure.
  • the second stacked structure 32 is photolithographically etched using a photolithography process, and the etching solution adopts the H 2 O 2 system. After etching, it can be seen that the length of the roof structure of the second barrier layer 323 relative to the film layer on the side close to the base substrate 10 is less than 0.05 um, which is almost negligible.
  • the film layer formed on the second stacked structure 32 can effectively cover the film layer on the lower side of the second oxidation barrier layer 323 close to the base substrate.
  • FIG. 5 is a photomicrograph when a wiring board forms a first stacked structure on a second stacked structure according to an embodiment of the present disclosure.
  • the etching solution used in the photolithography process is 20% high HNO 3 and Acetic acid and additives.
  • the etching rate of the etchant for the first oxidation barrier layer of the first stacked structure is slower than the etching rate of the etchant for the first metal layer, and the first metal layer 312 is covered with the first oxidation barrier layer 313, the first The solution that the metal layer 312 covers the etching barrier layer 311 can well solve the problem caused by the different etching rates of the etching solution.
  • the circuit board of the present disclosure has good repairability and times (repairable rate), and has a good production yield during production.
  • the etch stop layer 311 has a thickness greater than The thickness of the first metal layer 312 is to range, the thickness of the first oxidation barrier layer 313 is less than
  • the thickness of the etch stop layer 311 is or wait.
  • the thickness of the first metal layer 312 is or etc.
  • the thickness of the first oxidation barrier layer 313 is or wait.
  • the thickness of the adhesive layer 321 is between to In the range of , the thickness of the second metal layer 322 is in to In the range of , the thickness of the second oxidation barrier layer 323 is to In the range.
  • the thickness of the adhesive layer 321 is or The thickness of the second metal layer 322 is or wait.
  • the thickness of the second oxidation barrier layer 323 is or wait.
  • the etching barrier layer 311 of the first stacked structure 31 and the second oxidation barrier layer 323 of the second stacked structure 32 can be made of the same material.
  • NiV alloy or NiW alloy are used. Wherein the mass ratio content of V element in NiV alloy is in the range of 3% to 15%, and the mass ratio content of W element in NiW alloy is in the range of 10% to 50%.
  • the mass ratio content of the V element in the NiV alloy is 3%, 10% or 15%.
  • the W element mass ratio content of the NiW alloy is 10%, 20%, 40% or 50% and so on.
  • the first oxidation barrier layer 313 is made of CuNi alloy material, wherein the Ni element mass ratio content of the CuNi alloy is in the range of 10% to 30%.
  • the Ni element content of the CuNi alloy is 10%, 20% or 30% by mass.
  • the wiring 20 of the circuit board 100 further includes a second conductive layer 40 .
  • the second conductive layer 40 is disposed between the base substrate 10 and the first conductive layer 30 , and the first conductive layer 30 and the second conductive layer 40 are separated by at least one insulating layer.
  • the second conductive layer 40 includes an adhesive layer 41 on a side close to the base substrate 10 and a metal layer 42 on a side away from the base substrate 10 .
  • the material of the adhesive layer 41 may be the same as that of the above-mentioned adhesive layer 321 , for example.
  • the material of the metal layer 42 can be copper, for example.
  • the circuit board 100 further includes an alignment mark 80 disposed between the base substrate 10 and the first conductive layer 30 .
  • the alignment mark is located on the periphery of the second conductive layer 40 for alignment.
  • the circuit board 100 further includes a via hole 90 penetrating at least one insulating layer, wherein the via hole 90 exposes a part of the surface of the first conductive layer 30 away from the base substrate.
  • the circuit board 100 includes a base substrate 10 on which a buffer layer 50 is disposed, and at least one alignment mark 80 is disposed on a side of the buffer layer 50 away from the base substrate 10 . and the second conductive layer 40 .
  • a first insulating layer 60 covering the second conductive layer 40 and at least one alignment mark 80 is disposed on the side of the conductive layer 40 away from the substrate 10 , wherein the first insulating layer 60 can be made of SiN or SiO, for example.
  • a first planar layer 70 covering the insulating layer 60 is disposed on a side of the first insulating layer 60 away from the base substrate 10 .
  • a second insulating layer 51 covering the first planar layer 70 is disposed on a side of the first planar layer 70 away from the base substrate 10 .
  • the second insulating layer 51 can be made of, for example, SiN or SiO to prevent outgas from the first planar layer 70 during the manufacturing process, and the second insulating layer 51 can improve the adhesion of the first conductive layer 30 .
  • a plurality of stacked first conductive layers 30 are disposed on the second insulating layer 51 on a side away from the base substrate 10 .
  • a third insulating layer 61 covering the first conductive layer 30 is provided on the side of the first conductive layer 30 away from the base substrate 10 , and a third insulating layer 61 covering the first conductive layer 30 is formed on the side of the third insulating layer 61 away from the base substrate 10 .
  • the second planar layer 71 of the insulating layer 61 is formed on the side of the third insulating layer 61 away from the base substrate 10 .
  • the second planar layer 71 of the insulating layer 61 The circuit board 100 also includes a via hole 90 penetrating through the second planar layer 71 and the third insulating layer 61 .
  • the electronic components are electrically connected to the first conductive layer 30 through the via hole 90 .
  • Some embodiments of the present disclosure also provide a method for manufacturing a circuit board.
  • the manufacturing method of the circuit board according to the embodiment of the present disclosure will be described in detail below with reference to FIG. 6 to FIG. 7 .
  • FIG. 6 is a flowchart of a method of manufacturing a wiring board according to an embodiment of the present disclosure.
  • FIG. 7 is a flow chart of forming a first conductive layer in a manufacturing method of a circuit board according to an embodiment of the present disclosure.
  • the manufacturing method of the circuit board includes step S10 to step S30 .
  • step S10 a base substrate is formed.
  • step S20 forming wiring on the base substrate, forming the wiring includes forming a first conductive layer, and the first conductive layer includes a first stacked structure on a side away from the base substrate and a second stacked structure close to the base substrate , the first stacked structure includes at least an etching stopper layer, and the etch stopper layer covers the second stacked structure.
  • the first conductive layer 30 may be disposed on the base substrate 10 by deposition. Before forming the first conductive layer 30 , it also includes forming at least one insulating layer on the base substrate 10 .
  • the buffer layer 50 is formed by deposition, and the first insulating layer 60 , the first flat layer 70 and the second insulating layer 51 are formed.
  • it also includes forming the second conductive layer 40 between the first insulating layer 60 and the base substrate 10 .
  • step S30 at least one insulating layer is formed, the insulating layer is disposed on a side of the first conductive layer away from the base substrate, and the at least one insulating layer covers the first conductive layer.
  • At least one insulating layer is also formed on the side of the first conductive layer 30 away from the base substrate 10, for example, including forming a third insulating layer 61 covering the first conductive layer 30 and a second planar layer covering the third insulating layer 61 71.
  • the third insulating layer 61 and the second flat layer 71 may be formed by deposition.
  • forming the first conductive layer includes steps S21 to S22 .
  • step S21 a second stacked structure film layer including the second stacked structure is deposited on a side close to the base substrate, and the second stacked structure film layer is etched to form a second stacked structure.
  • the second stacked structure film layer including the second stacked structure is deposited and formed on the insulating layer (for example, the second insulating layer 51 ) on the side close to the base substrate, and then the second stacked structure A photoresist is arranged on the structural film layer, and the second stacked structure film layer is etched to form a second stacked structure.
  • the etchant may be, for example, an etchant in the H 2 O 2 system.
  • the thickness of the second oxidation barrier layer 323 in the second stacked structure 32 is to Within the range, defects such as roof structure can be effectively avoided during etching, and the yield rate of products can be improved.
  • step S22 a film layer of the first stack structure including the first stack structure is formed on a side of the second stack structure away from the base substrate, and the film layer of the first stack structure is etched to form the first stack structure.
  • the second stacked structure after the formation of the second stacked structure, continue to deposit and form the first stacked structure film layer including the first stacked structure on the side of the second stacked structure away from the substrate, and then deposit the first stacked structure film layer on the first stacked structure.
  • a photoresist is arranged on the film layer of the stacked structure, and the first stacked structure is etched, thereby forming the first stacked structure.
  • the etchant may be, for example, an etchant with 20% high HNO 3 components, acetic acid and additives.
  • the thickness of the etching barrier layer in the first stacked structure is set to be greater than On the one hand, it can effectively block the etchant from etching the second stacked structure, and on the other hand, it can realize the function of protecting the second metal layer in the second stacked structure.
  • it in addition to the steps described above, it also includes forming other stacked structures as shown in FIG. 2 .
  • Fig. 8 is a schematic structural diagram of a functional backplane according to an embodiment of the disclosure.
  • a functional backplane is also provided, as shown in FIG. 8 , wherein the functional backplane 200 includes the circuit board 100 described above, and In the direction away from the base substrate and away from the base substrate, the intermetallic compound layer 210 and the conductive connection layer 220 are stacked on the circuit board; the electronic component 230 is electrically connected to the first conductive layer 30 through the conductive connection layer 220 and the intermetallic compound layer 210 .
  • the intermetallic compound layer 210 may be formed by interdiffusion or reaction between the metal in the first oxidation barrier layer 313 and the metal in the conductive connection layer 220 at a high temperature, and the intermetallic compound layer A portion of 210 is located within the surface of the first oxidation barrier layer 313 .
  • the electronic components may be light-emitting devices, such as micro-inorganic light-emitting diode chips, and the functional backplane 200 includes a plurality of light-emitting devices.
  • FIG. 9 is a schematic structural diagram of a backlight module according to an embodiment of the disclosure.
  • some embodiments of the present disclosure further provide a backlight module 300 , which includes the functional backplane 200 in any of the above-mentioned embodiments.
  • the functional backplane 200 includes a plurality of electronic components 230 (i.e., light emitting devices), and the light emitting devices may be miniature inorganic light emitting diode chips, that is, the backlight module 300 is composed of a plurality of miniature inorganic light emitting diodes arranged in an array. glow board.
  • the light emitting devices may be miniature inorganic light emitting diode chips, that is, the backlight module 300 is composed of a plurality of miniature inorganic light emitting diodes arranged in an array. glow board.
  • the beneficial effects achieved by the backlight module 300 in the above embodiments of the present disclosure are the same as the beneficial effects achieved by the functional backplane 200 and the circuit board 100 described above, and will not be repeated here.
  • Fig. 10 is a schematic diagram of a display device according to an embodiment of the disclosure.
  • some embodiments of the present disclosure provide a display device 400 , which includes a display panel 410 and the backlight module 300 described above. Measurement.
  • the display panel 410 may be a liquid crystal display panel (Liquid Crystal Display, LCD for short).
  • LCD Liquid Crystal Display
  • the display device 400 further includes a plurality of optical films 420 located between the backlight module 300 and the display panel 410 for adjusting light output from the backlight module 300 .
  • Some embodiments of the present disclosure provide a display panel including the functional backplane as described in the above embodiments.
  • the functional backplane 200 includes a plurality of light-emitting devices, and the light-emitting devices may be inorganic light-emitting diode chips with a size below 500 microns, for example, the size may be between 100-300 microns, or below 100 microns.
  • the light emitting device may include a red phosphor, a green phosphor or a blue phosphor.
  • FIG. 11 is a schematic diagram of another display device according to an embodiment of the present disclosure.
  • some embodiments of the present disclosure further provide a display device 500, which includes the display panel 410 in the above embodiments.
  • the beneficial effects achieved by the display device 500 in the above-mentioned embodiments of the present disclosure are the same as the beneficial effects achieved by the above-mentioned display panel 410 , and will not be repeated here.
  • the display device 500 described above may be any device that displays an image regardless of whether it is moving (for example, video) or fixed (for example, still image) and regardless of text or text. More specifically, it is contemplated that the described embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , Handheld or Laptop Computers, GPS Receivers/Navigators, Cameras, MP4 Video Players, Camcorders, Game Consoles, Watches, Clocks, Calculators, Television Monitors, Flat Panel Displays, Computer Monitors, Automotive Displays (eg, odometer displays, etc.), navigators, cockpit controls and/or displays, displays for camera views (e.g., displays for rear-view cameras in vehicles), electronic photographs, electronic billboards or signage, projectors, building structures, packaging and aesthetic structures (for example, for a display of an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • Handheld or Laptop Computers GPS Receiv

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Abstract

提供一种线路板及其制造方法、功能背板、背光模组、显示装置、显示面板。线路板包括：衬底基板；设置于所述衬底基板的走线，所述走线包括第一导电层；至少一个绝缘层，设置在所述第一导电层远离所述衬底基板的一侧，所述至少一个绝缘层覆盖所述第一导电层；其中，所述第一导电层包括远离所述衬底基板一侧的第一层叠结构和靠近所述衬底基板的第二层叠结构，所述第一层叠结构至少包括刻蚀阻挡层，所述刻蚀阻挡层覆盖所述第二层叠结构。

Description

线路板及其制造方法、功能背板、背光模组、显示装置 技术领域
本公开涉及显示技术领域，具体而言，涉及一种线路板及其制造方法、功能背板、背光模组、显示装置及显示面板。
背景技术
在线路板制备工艺中，由于线路板的焊盘位置需要与电子元件进行焊接，而焊盘位置的导电材料铜与焊料的反应非常快，造成焊盘位置处的界面金属共化物(Intermetallic Compound，IMC)的厚度非常厚，导致进行重复焊接的良率非常低。而在引进新的合金层来一致焊盘位置的界面金属共化物的厚度的问题，将导致在刻蚀导电层出现刻蚀速率不均匀，产生底切结构(undercut)以及屋顶结构(tip)的问题，使得在铺设在导电层上的其他层叠结构无法有效对导电层进行有效覆盖。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域技术人员已知的现有技术的信息。
发明内容
在一个方面，提供一种线路板，所述线路板包括：衬底基板；设置于所述衬底基板的走线，所述走线包括第一导电层；至少一个绝缘层，设置在所述第一导电层远离所述衬底基板的一侧，所述至少一个绝缘层覆盖所述第一导电层；其中，所述第一导电层包括远离所述衬底基板一侧的第一层叠结构和靠近所述衬底基板的第二层叠结构，所述第一层叠结构至少包括刻蚀阻挡层，所述刻蚀阻挡层覆盖所述第二层叠结构。
在本公开的一些示例性实施例中，所述第一层叠结构包括依次远离所述衬底基板的所述刻蚀阻挡层、第一金属层以及第一氧化阻挡层；其中，所述刻蚀阻挡层、所述第一金属层以及第一氧化阻挡层在所述衬底基板上的正投影重叠。
在本公开的一些示例性实施例中，所述第一氧化阻挡层覆盖所述第一金属层，所述第一金属层覆盖所述刻蚀阻挡层。
在本公开的一些示例性实施例中，所述第二层叠结构包括依次远离所述衬底基板的粘接层、第二金属层以及第二氧化阻挡层，所述第二氧化阻挡层和所述第二金属层在所述衬底基板上的正投影位于所述粘接层在所述衬底基板上的正投影内。
在本公开的一些示例性实施例中，所述第一层叠结构在其长度方向的侧面与所述衬底基板所在的平面的夹角在60°至90°的范围内。
在本公开的一些示例性实施例中，所述第二层叠结构在其长度方向的侧面与所述衬底基板所在的平面的夹角在60°至80°的范围内。
在本公开的一些示例性实施例中，所述刻蚀阻挡层的厚度大于
Figure PCTCN2022077542-appb-000001
所述第一金属层的厚度在
Figure PCTCN2022077542-appb-000002
至
Figure PCTCN2022077542-appb-000003
的范围，所述第一氧化阻挡层的厚度小于
Figure PCTCN2022077542-appb-000004
在本公开的一些示例性实施例中，所述刻蚀阻挡层包括NiV合金、NiW合金，所述第一金属层包括铜，所述第一氧化阻挡层包括CuNi合金。
在本公开的一些示例性实施例中，所述粘接层的厚度在
Figure PCTCN2022077542-appb-000005
至
Figure PCTCN2022077542-appb-000006
的范围内，所述第二金属层的厚度在
Figure PCTCN2022077542-appb-000007
至
Figure PCTCN2022077542-appb-000008
的范围内，所述第二氧化阻挡层的厚度在
Figure PCTCN2022077542-appb-000009
至
Figure PCTCN2022077542-appb-000010
的范围内。
在本公开的一些示例性实施例中，所述粘接层包括Mo或MoNb合金，所述第二金属层包括铜，所述第二氧化阻挡层包括NiV合金、NiW合金。
在本公开的一些示例性实施例中，所述NiV合金的V元素质量比含量在3％至15％的范围，所述NiW合金的W元素质量比含量在10％至50％的范围。
在本公开的一些示例性实施例中，所述CuNi合金的Ni元素质量比含量在10％至30％的范围。
在本公开的一些示例性实施例中，所述走线还包括：设置于所述衬底基板和所述第一导电层之间的第二导电层，所述第一导电层和所述第二导电层通过至少一层绝缘层分隔开。
在本公开的一些示例性实施例中，所述线路板还包括：设置于所述衬底基板和所述第一导电层之间的对位标记。
在本公开的一些示例性实施例中，所述的线路板还包括贯穿所述至少一个绝缘层的过孔，其中过孔暴露出第一导电层远离衬底基板一侧的部分表面。
在另一方面，提供了一种线路板的制造方法，其中，包括：形成衬底基板；在所述衬底基板上形成走线，形成所述走线包括形成第一导电层；形成至少一个绝缘层， 所述绝缘层设置在所述第一导电层远离所述衬底基板的一侧，所述至少一个绝缘层覆盖所述第一导电层；其中，所述第一导电层包括远离所述衬底基板一侧的第一层叠结构和靠近所述衬底基板的第二层叠结构，所述第一层叠结构至少包括刻蚀阻挡层，所述刻蚀阻挡层覆盖所述第二层叠结构。
在本公开的一些示例性实施例中，所述形成第一导电层包括：在靠近所述衬底基板的一侧沉积形成包含第二层叠结构的第二层叠结构膜层，对所述第二层叠结构膜层进行刻蚀，形成所述第二层叠结构；在所述第二层叠结构远离所述衬底基板的一侧形成包含第一层叠结构的第一层叠结构膜层，对所述第一层叠结构膜层进行刻蚀，形成第一层叠结构。
在又一方面，提供了一种功能背板，其中，包括：如上文所述的线路板；沿垂直于所述线路板的衬底基板且远离所述衬底基板的方向，层叠设置于所述线路板上的金属间化合物层和导电连接层；电子元件，与所述导电连接层电连接。
在又一方面，提供了一种背光模组，包括：如上文所述的功能背板。
在又一方面，提供了一种显示装置，包括：显示面板；如上文所述的背光模组；所述显示面板设置于所述背光模组的出光侧。
在又一方面，提供了一种显示面板，包括：如上文所述的功能背板。
在又一方面，提供了一种显示装置，包括：如上文所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1是根据本公开的实施例的线路板的平面示意图；
图2是根据本公开的实施例的线路板沿图1中的AA’线的截面结构示意图；
图3是根据本公开的实施例的线路板的第二层叠结构在第二氧化阻挡层厚度较大时产生缺陷的显微照片；
图4是根据本公开的实施例的线路板的第二层叠结构在第二氧化阻挡层厚度较小时产生缺陷的显微照片；
图5是根据本公开的实施例的线路板在第二层叠结构上形成第一层叠结构时的显微照片；
图6是根据本公开实施例的线路板的制造方法的流程图；
图7是根据本公开实施例的线路板的制造方法在形成第一导电层的流程图；
图8是根据本公开实施例的一种功能背板的结构示意图；
图9是根据本公开实施例的一种背光模组的结构示意图；
图10是根据本公开实施例的一种显示装置示意图；
图11是根据本公开实施例的另一种显示装置示意图。
需要注意的是，为了清晰起见，在用于描述本公开的实施例的附图中，层、结构或区域的尺寸可能被放大或缩小，即这些附图并非按照实际的比例绘制。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征 可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“电连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文中“同层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以 是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。与之相反地，“异层”指的是分别采用相应的成膜工艺形成用于形成特定图形的膜层，然后利用相应的掩模板通过构图工艺形成的层结构，例如，“两个层结构异层设置”是指两个层结构分别在相应的工艺步骤(成膜工艺和构图工艺)下形成。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在相关技术中，为了将电子元件与线路板进行电连接，一般采用表面组装技术(SMT，Surface Mounted Technology的缩写)，通过将具有引脚的电子元件放置在线路板的导电图案的裸露表面上，通过回流焊或浸焊等方法加以焊接组装的技术。在实际焊接过程中，由于线路板中的导电材料一般选用铜，而铜与焊料的反应非常快，会在焊盘表面的界面形成金属共化物(Intermetallic Compound，IMC)以形成电学连接，然而，当电子元件与焊盘之间的连接出现不良，需要将电子元件去除以进行二次焊接时，上述结构的再次焊接的良率很低。
为了解决上述问题，本公开的实施例提供了一种线路板，线路板包括但不限于：衬底基板；设置于衬底基板的走线，走线包括第一导电层；至少一个绝缘层，设置在第一导电层远离衬底基板的一侧，至少一个绝缘层覆盖所述第一导电层；其中，第一导电层包括远离衬底基板一侧的第一层叠结构和靠近衬底基板的第二层叠结构，第一层叠结构至少包括刻蚀阻挡层，刻蚀阻挡层覆盖第二层叠结构。根据本公开的实施例，通过设置刻蚀阻挡层，能够有效抑制第二层叠结构在刻蚀时形成底切结构(undercut)或屋顶结构(tip)，从而使得在铺设在导电层上的其他层叠结构能够有效对导电层进行有效覆盖，一方面提高线路板在第一导电层处重复焊接时的良率，同时提高线路板生产的良率。
下面结合图1至图5对本公开实施例的线路板的结构进行详细说明。
图1是根据本公开的实施例的线路板的平面示意图。如图1所示，线路板100包括器件区110和和绑定区120，示例性地，绑定区120位于器件区110的一侧。线路 板100包括设置于器件区110第一导电层30和第二导电层40(40’)，其中第一导电层30中表面裸露的区域被配置为与电子元件230的引脚连接，还包括设置于绑定区120的待与电路板相连接的多个导电端子H2，多个导电端子H2可以与第二导电层40同层设置。在本公开中，电子元件可以包括尺寸在500微米以下的无机发光二极管、传感器芯片、集成电路芯片等至少一者，其中，无机发光二极管和/或传感器芯片可以由集成电路芯片驱动，或者无机发光二极管和/或传感器芯片由设置在线路板上的多个相互连接且配合的薄膜晶体管的组合驱动。
图2是根据本公开的实施例的线路板沿图1中的AA’线的截面结构示意图。如图2所示，线路板100包括衬底基板10、设置于衬底基板上的走线20、走线20包括第一导电层30以及第二导电层40。至少一个绝缘层设置在第一导电层30的远离衬底基板10的一侧，该绝缘层覆盖第一导电层30。
在本公开的实施例中，第一导电层30包括远离衬底基板10一侧的第一层叠结构31以及靠近衬底基板10一侧的第二层叠结构32。其中，第一层叠结构31和第二层叠结构32被至少一个绝缘层所覆盖。
如图2所示，每个层叠结构都具有多个子层，其中第一层叠结构31的至少一个子层设置为刻蚀阻挡层311，该刻蚀阻挡层311覆盖第二层叠结构32。通过将刻蚀阻挡层设置为覆盖第二层叠结构32，保证在刻蚀第一层叠结构31时，刻蚀阻挡层311能够阻挡刻蚀介质对第二层叠结构32的刻蚀，有效避免因刻蚀介质对第二层叠结构刻蚀速率不同而造成的第二层叠结构32相对于第一层叠结构31出现底切结构以及第一层叠结构31相对于第二层叠结构32出现屋顶结构等缺陷。
在本公开的实施例中，第一层叠结构31包括依次远离衬底基板10的刻蚀阻挡层311、第一金属层312以及第一氧化阻挡层313。
刻蚀阻挡层311的作用如上文所述，用于阻挡刻蚀介质对第二层叠结构32的刻蚀。第一金属层312用于电路中的电信号的传输。第一氧化阻挡层313设置在第一金属层312的远离衬底基板10的一侧，用于阻挡第一金属层312的氧化。即，在与电子元件进行焊接的过程中，第一金属层312的用于传输电信号的材料易于发生氧化，通过设置第一氧化阻挡层313，可以对第一金属层312进行保护。
刻蚀阻挡层311、第一金属层312以及第一氧化阻挡层313在衬底基板10上的正投影重叠。例如，在本实施例中，刻蚀阻挡层311在衬底基板10上的正投影位于第一 金属层312在衬底基板10上的正投影内，第一金属层312在衬底基板10上的正投影位于第一氧化阻挡层313在衬底基板10上的正投影内，即形成第一层叠结构时，刻蚀阻挡层311、第一金属层312、第一氧化阻挡层313在衬底基板10上的正投影的面积逐渐增加。在其他的可选实施例中，刻蚀阻挡层311、第一金属层312以及第一氧化阻挡层313在衬底基板10上的正投影可以是完全重合。
在本公开的实施例中，第一氧化阻挡层313覆盖第一金属层312，第一金属层312覆盖刻蚀阻挡层311。
第一氧化阻挡层313覆盖第一金属层312，从而实现对第一金属层312的保护，第一金属层312覆盖刻蚀阻挡层311，便于在刻蚀形成第一层叠结构时，减少因刻蚀液对刻蚀阻挡层刻蚀速度慢，而对第一金属层312以及第一氧化阻挡层313刻蚀速度快而再次造成的第二层叠结构32相对于第一层叠结构31出现的底切结构以及第一层叠结构31相对于第二层叠结构32出现屋顶结构等缺陷。通过该种设置方式，可以有效减少缺陷的产生，提高产品的良率。
在本公开的实施例中，如图2所示，第二层叠结构32包括依次远离衬底基板10的粘接层321、第二金属层322以及第二氧化阻挡层323。
通过将第二层叠结构32设置成具有多个子层的结构，可以使在第一导电层30进行焊接时，保证第一导电层30与电子元件之间的焊接性能，防止因多次焊接而出现接触不良等问题。在本实施例中，衬底基板10与第一导电层30之间设置有至少一层绝缘层，例如，包括缓冲层用于改善衬底基板10与其他层叠结构之间的应力，再形成多个绝缘层，例如第一绝缘层60以及第二绝缘层51，在第二绝缘层51上形成粘接层321，接下来在粘接层321上形成第二金属层322，然后在第二金属层322上形成第二氧化阻挡层323。
在本实施例中，通过形成粘接层321便于第二金属层322与具有更好的粘附力，使生成的第二金属层322能够更稳固的粘附。在第二金属层322上形成第二氧化阻挡层323，防止第二金属层322在进行焊接时产生氧化，从而对第二金属层322具有更好的保护作用。
在本公开的实施例中，第二氧化阻挡层323和第二金属层322在衬底基板10上的正投影位于粘接层321在衬底基板10上的正投影内。
例如，第二氧化阻挡层323位于粘接层321在衬底基板10的正投影内，第二金属层322在衬底基板10上的正投影位于粘接层321在衬底基板上的投影内。即第二氧化阻挡层323和第二金属层322在衬底基板上的正投影的面积小于粘接层在衬底基板10上的正投影面积。第二氧化阻挡层323、第二金属层322的两侧边的宽度小于粘接层321两侧边的宽度，从而便于在形成第二层叠结构时降低工艺难度，有效提高产品良率。
在本公开的实施例中，如图2所示，第一层叠结构31在其长度方向的侧面与衬底基板10所在的平面的夹角α在60°至90°的范围内，例如，可以设置为60°、70°、80°或者90°。第二层叠结构32在其长度方向的侧面与衬底基板10所在的平面的夹角β在60°至80°的范围内，例如，可以设置为60°、70°或者80°。
在本实施例中，例如，第一层叠结构31和第二层叠结构32的长度方向例如为垂直与纸面所在的方向，长度方向的侧边即是指图2中平行于衬底基板10所在方向的两侧边。
通过将夹角α在60°至90°的范围内，将夹角β在60°至80°的范围内，保证在形成第一层叠结构31和形成第二层叠结构32使，降低工艺难度，提高产品良率。
在本公开的实施例中，第一层叠结构31的刻蚀阻挡层311的材料包括镍基合金，镍基合金是指，以镍为基体金属掺杂其它的金属。示例性地，包括镍钒合金(NiV)、镍钨合金(NiW)等。第一金属层312的材料包括铜(Cu)，当采用铜作为第一金属层的材料时，其在焊接过程中，容易产生氧化的问题。在第一金属层312的远离衬底基板10的一侧设置第一氧化阻挡层313，其可以有效避免第一金属层312在进行焊接时氧化的问题，提高了线路板100的重修能力和次数(可维修率)，降低了线路板100的报废率，提升了累积良率。第一氧化阻挡层313包括铜镍合金(CuNi)。
在本公开的实施例中，第二层叠结构32的粘接层321的材料包括钼镍钛合金(MoNiTi)、钼(Mo)或者钼铌合金(MoNb)等。第二金属层322包括铜(Cu)等导电材料。第二氧化阻挡层323包括镍钒合金(NiV)、镍钨合金(NiW)等。第二氧化阻挡层323设置在第二金属层322的远离衬底基板10的一侧，有效避免第二金属层322在进行焊接时氧化的问题，进一步提高线路板100的重修能力。
在本公开的实施例中，第二层叠结构32的各个子层的厚度和材料不同，其对于刻蚀介质的刻蚀速率不同，因而，在采用光刻工艺对第二层叠结构进行刻蚀的过程中， 不同子层的刻蚀速度不一致，将导致出现底切结构(undercut)以及屋顶结构(tip)的问题。
图3是根据本公开的实施例的线路板的第二层叠结构在第二氧化阻挡层厚度较大时产生缺陷的显微照片。
如图3所示，通过将第二层叠结构32的各个子层的厚度设置为不一样的厚度，本公开的发明人在实验中发现了膜层厚度与膜层刻蚀后形貌之间的规律。当第二氧化阻挡层323的厚度大于
Figure PCTCN2022077542-appb-000011
时，采用刻蚀液采用H 2O 2体系，由于刻蚀液对于不同材料的刻蚀速率不同，例如刻蚀液对第二氧化阻挡层323的刻蚀速率相对于刻蚀第二金属层的刻蚀速率较慢。当第二氧化阻挡323的厚度大于
Figure PCTCN2022077542-appb-000012
时，第二氧化阻挡层323将相对于靠近衬底基板10一侧的膜层具有突出的屋顶结构，并且屋顶结构长度大于0.2um，若继续在第二层叠结构32上形成其他膜层，则将导致上层结构无法良好覆盖下层结构，即在第二层叠结构32上形成的膜层无法覆盖第二氧化阻挡层323的屋顶结构区域对应的下方区域，降低产品的良率。
本公开的发明人在进一步的实验中，通过将第二阻挡层323的厚度设置在一定的范围内，则可以避免第二阻挡层323相对于靠近衬底基板一侧的膜层出现屋顶结构的问题。本公开的发明人得出，当将第二氧化阻挡层323的厚度设置在
Figure PCTCN2022077542-appb-000013
至
Figure PCTCN2022077542-appb-000014
的范围内，则可以实现对第二金属层322的保护，同时，可以避免刻蚀形成第二层叠结构时出现屋顶结构的问题。
图4是根据本公开的实施例的线路板的第二层叠结构在第二氧化阻挡层厚度较小时产生缺陷的显微照片。
如图4所示，当第二刻蚀阻挡层323的厚度设置为小于
Figure PCTCN2022077542-appb-000015
时，采用光刻工艺对第二层叠结构32进行光刻，刻蚀液采用H 2O 2体系。刻蚀后，可以看出，第二阻挡层323相对于靠近衬底基板10一侧的膜层出现屋顶结构的长度小于0.05um，几乎可以忽略。此外，在第二层叠结构32上形成的膜层可以有效覆盖第二氧化阻挡层323下侧靠近衬底基板一侧的膜层。
图5是根据本公开的实施例的线路板在第二层叠结构上形成第一层叠结构时的显微照片。
在形成第二层叠结构32之后，继续在第二层叠结构32的远离衬底基板10的一侧形成第一层叠结构31。
在形成第二层叠结构32之后，继续在第二层叠结构32的远离衬底基板10的一侧形成第一层叠结构31时，其中光刻工艺中采用的刻蚀液为20％高HNO 3和醋酸及添加剂。刻蚀液对第一层叠结构的第一氧化阻挡层的刻蚀速率较刻蚀液对第一金属层的刻蚀速率较慢，采用第一氧化阻挡层313覆盖第一金属层312，第一金属层312覆盖刻蚀阻挡层311的方案，可以很好解决刻蚀液因刻蚀速率不同造成的问题，在实际的实验中，如图5所示，第二层叠结构32中没有出现屋顶结构，同时第一层叠结构31能够良好覆盖第二层叠结构32，在第一层叠结构31的远离衬底基板10的一侧形成的膜层也能够良好覆盖第一层叠结构31。由此，本公开的线路板一方面具有良好的重修能力和次数(可维修率)，在进行生产时，具有较好的生产良率。
在本公开的实施例中，刻蚀阻挡层311的厚度大于
Figure PCTCN2022077542-appb-000016
第一金属层312的厚度在
Figure PCTCN2022077542-appb-000017
至
Figure PCTCN2022077542-appb-000018
的范围，第一氧化阻挡层313的厚度小于
Figure PCTCN2022077542-appb-000019
示例性地，刻蚀阻挡层311的厚度为
Figure PCTCN2022077542-appb-000020
或者
Figure PCTCN2022077542-appb-000021
等。第一金属层312的厚度为
Figure PCTCN2022077542-appb-000022
或者
Figure PCTCN2022077542-appb-000023
等等。第一氧化阻挡层313的厚度为
Figure PCTCN2022077542-appb-000024
Figure PCTCN2022077542-appb-000025
或者
Figure PCTCN2022077542-appb-000026
等。
在本公开的实施例中，粘接层321的厚度在
Figure PCTCN2022077542-appb-000027
至
Figure PCTCN2022077542-appb-000028
的范围内，第二金属层322的厚度在
Figure PCTCN2022077542-appb-000029
至
Figure PCTCN2022077542-appb-000030
的范围内，第二氧化阻挡层323的厚度在
Figure PCTCN2022077542-appb-000031
至
Figure PCTCN2022077542-appb-000032
的范围内。
示例性地，粘接层321的厚度为
Figure PCTCN2022077542-appb-000033
或者
Figure PCTCN2022077542-appb-000034
第二金属层322的厚度为
Figure PCTCN2022077542-appb-000035
或者
Figure PCTCN2022077542-appb-000036
等。第二氧化阻挡层323的厚度为
Figure PCTCN2022077542-appb-000037
或者
Figure PCTCN2022077542-appb-000038
等。
在本公开的实施例中，第一层叠结构31的刻蚀阻挡层311和第二层叠结构32的第二氧化阻挡层323可以选用相同的材料制造。例如，都选用NiV合金或者NiW合金。其中NiV合金的V元素质量比含量在3％至15％的范围，NiW合金的W元素质量比含量在10％至50％的范围。
示例性地，例如NiV合金的V元素质量比含量为3％、10％或者15％等。NiW合金的W元素质量比含量为10％、20％、40％或50％等。
在本公开的实施例中，第一氧化阻挡层313选用CuNi合金材料制造，其中CuNi合金的Ni元素质量比含量在10％至30％的范围。
示例性地，例如，CuNi合金的Ni元素质量比含量为10％、20％或者30％等。
在本公开的实施例中，如图2所示，线路板100的走线20还包括第二导电层40。其中第二导电层40设置于衬底基板10和第一导电层30之间，第一导电层30和第二导电层40之间通过至少一层绝缘层分隔开。
其中，第二导电层40包括靠近衬底基板10一侧的粘附层41以及远离衬底基板10一侧的金属层42。其中粘附层41的材料例如可以与上文所述的粘接层321的材料相同。金属层42的材料例如可以是铜。
在本公开的实施例中，线路板100还包括设置于衬底基板10和第一导电层30之间的对位标记80。其中对位标记位于第二导电层40的外围，用于对位使用。
在本公开的实施例中，线路板100还包括贯穿至少一个绝缘层的过孔90，其中过孔90暴露出第一导电层30远离衬底基板一侧的部分表面。
下面结合图2对本公开实施例的线路板100的各个层叠结构进行详细描述。
如图2所示，线路板100包括衬底基板10，在衬底基板10上设置有缓冲层50，在缓冲层50的远离衬底基板10的一侧设置有至少一个对位标记80。以及第二导电层40。在导电层40的远离衬底基板10的一侧设置有覆盖第二导电层40和至少一个对位标记80的第一绝缘层60，其中第一绝缘层60例如可以采用SiN或者SiO材料制造。在第一绝缘层60的远离衬底基板10的一侧设置有覆盖绝缘层60的第一平坦层70。在第一平坦层70的远离衬底基板10的一侧设置有覆盖第一平坦层70的第二绝缘层51。第二绝缘层51例如可以采用SiN或SiO材料制造，用于防止第一平坦层70在制造过程中产生气体(outgas)，同时第二绝缘层51可以提高第一导电层30的附着力。在第二绝缘层51上远离衬底基板10的一侧设置有多个层叠结构的第一导电层30。在第一导电层30的远离衬底基板10的一侧设置有覆盖第一导电层30的第三绝缘层61，在第三绝缘层61的远离衬底基板10的一侧形成有覆盖第三绝缘层61的第二平坦层71。线路板100还包括贯穿第二平坦层71和第三绝缘层61的过孔90。电子元件通过过孔90与第一导电层30电连接。
本公开的一些实施例还提供了一种线路板的制造方法。下面结合图6至图7对本公开实施例的线路板的制造方法进行详细说明。
图6是根据本公开实施例的线路板的制造方法的流程图。图7是根据本公开实施例的线路板的制造方法在形成第一导电层的流程图。
如图6所示，线路板的制造方法包括步骤S10至步骤S30。
在步骤S10中，形成衬底基板。
在步骤S20中，在衬底基板上形成走线，形成走线包括形成第一导电层，第一导电层包括远离衬底基板一侧的第一层叠结构和靠近衬底基板的第二层叠结构，第一层叠结构至少包括刻蚀阻挡层，刻蚀阻挡层覆盖所述第二层叠结构。
示例性地，结合图2可知，第一导电层30可以通过沉积的方式设置在衬底基板10上。在形成第一导电层30之前，还包括在衬底基板10上形成至少一层绝缘层。例如沉积形成缓冲层50，以及形成第一绝缘层60、第一平坦层70以及第二绝缘层51。其中，还包括在第一绝缘层60和衬底基板10之间形成第二导电层40。
在步骤S30中，形成至少一个绝缘层，绝缘层设置在第一导电层远离衬底基板的一侧，至少一个绝缘层覆盖第一导电层。
在第一导电层30的远离衬底基板10的一侧还形成至少一个绝缘层，例如，包括形成覆盖第一导电层30的第三绝缘层61以及覆盖第三绝缘层61的第二平坦层71。
示例性地，第三绝缘层61和第二平坦层71可以通过沉积形成。
如图7所示，形成第一导电层包括步骤S21至步骤S22。
在步骤S21中，在靠近衬底基板的一侧沉积形成包含第二层叠结构的第二层叠结构膜层，对第二层叠结构膜层进行刻蚀，形成第二层叠结构。
在本公开的实施例中，在靠近衬底基板的一侧的绝缘层(例如，第二绝缘层51)上沉积形成包含第二层叠结构的第二层叠结构膜层，接下来在第二层叠结构膜层上设置光刻胶，并对第二层叠结构膜层进行刻蚀，从而形成第二层叠结构。在本实施例中，刻蚀液例如可以选用H 2O 2体系的刻蚀液。第二层叠结构32中的第二氧化阻挡层323的厚度在
Figure PCTCN2022077542-appb-000039
至
Figure PCTCN2022077542-appb-000040
的范围内，刻蚀时可以有效避免出现屋顶结构等缺陷，提高产品的良率。
在步骤S22中，在第二层叠结构远离衬底基板的一侧形成包含第一层叠结构的第一层叠结构膜层，对第一层叠结构膜层进行刻蚀，形成第一层叠结构。
在本公开的实施例中，在第二层叠结构形成后，继续在第二层叠结构的远离衬底基板的一侧沉积形成包含第一层叠结构的第一层叠结构膜层，接下来在第一层叠结构膜层上设置光刻胶，并对第一层叠结构进行刻蚀，从而形成第一层叠结构。在本实施例中，刻蚀液例如可以选用20％高HNO 3成分和醋酸及添加剂的刻蚀液。其中，第一层叠结构中的刻蚀阻挡层的厚度设置为大于
Figure PCTCN2022077542-appb-000041
一方面可以有效阻挡刻蚀液对第 二层叠结构的刻蚀，另一方面，可以实现对第二层叠结构中的第二金属层进行保护的作用。
在本公开的实施例中，除了上文所述的步骤外，还包括形成如图2中所呈现的其他层叠结构。
图8是根据本公开实施例的一种功能背板的结构示意图。
可选地，在本公开的一些实施例中，还提供了一种功能背板，如图8所示，其中功能背板200包括上文所述的线路板100，以及沿垂直于线路板的衬底基板且远离衬底基板的方向，层叠设置于线路板的金属间化合物层210和导电连接层220；电子元件230通过导电连接层220和金属间化合物层210与第一导电层30电连接。在本公开的实施例中，金属间化合物层210例如可以是第一氧化阻挡层313中的金属与导电连接层220中的金属在高温状态下相互扩散或发生反应而形成的，金属间化合物层210的一部分位于第一氧化阻挡层313的表面内。
可以理解的是，电子元件可以是发光器件，例如微型无机发光二极管芯片，功能背板200包括多个发光器件。
图9是根据本公开实施例的一种背光模组的结构示意图。
如图9所示，本公开的一些实施例还提供了一种背光模组300，该背光模组300包括上述任一实施例中的功能背板200。
可以理解的是，功能背板200包括多个电子元件230(即发光器件)，发光器件可以是微型无机发光二极管芯片，即背光模组300为包括多个呈阵列排布的微型无机发光二极管的发光板。
本公开的上述实施例中的背光模组300所能实现的有益效果，与上述功能背板200及线路板100所能达到的有益效果相同，此处不再赘述。
图10是根据本公开实施例的一种显示装置示意图。
如图10所示，本公开的一些实施例提供了一种显示装置400，该显示装置400包括显示面板410和上文所述的背光模组300，显示面板410设置于背光模组300的出光测。
示例性地，显示面板410可以为液晶显示面板(Liquid Crystal Display，简称LCD)。
示例性地，如图10所示，显示装置400还包括多个光学膜片420，多个光学膜片420位于背光模组300与显示面板410之间，用于调节背光模组300的出光。
本公开的一些实施例提供了一种显示面板包括如上文实施例所述的功能背板。
可以理解的是，功能背板200包括多个发光器件，发光器件可以是尺寸在500微米以下的无机发光二极管芯片，例如其尺寸可以在100-300微米之间，或者100微米以下。示例性地，发光器件可包括红光无机发光二极管芯片、绿光无机发光二极管芯片或蓝光无机发光二极管芯片。
图11是根据本公开实施例的另一种显示装置示意图。
如图11所示，本公开的一些实施例还提供了一种显示装置500，该显示装置500包括上述实施例中的显示面板410。
本公开的上述实施例中的显示装置500所能实现的有益效果，与上述显示面板410所能达到的有益效果相同，此处不再赘述。
上述显示装置500可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
虽然本公开总体构思的一些实施例已被图示和说明，本领域普通技术人员将理解，在不背离本总体发明构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (20)

  1. 一种线路板，所述线路板包括：
    衬底基板；
    设置于所述衬底基板的走线，所述走线包括第一导电层；
    至少一个绝缘层，设置在所述第一导电层远离所述衬底基板的一侧，所述至少一个绝缘层覆盖所述第一导电层；
    其中，所述第一导电层包括远离所述衬底基板一侧的第一层叠结构和靠近所述衬底基板的第二层叠结构，
    所述第一层叠结构至少包括刻蚀阻挡层，所述刻蚀阻挡层覆盖所述第二层叠结构。
  2. 根据权利要求1所述的线路板，其中，
    所述第一层叠结构包括依次远离所述衬底基板的所述刻蚀阻挡层、第一金属层以及第一氧化阻挡层；
    其中，所述刻蚀阻挡层、所述第一金属层以及第一氧化阻挡层在所述衬底基板上的正投影重叠。
  3. 根据权利要求2所述的线路板，其中，
    所述第一氧化阻挡层覆盖所述第一金属层，所述第一金属层覆盖所述刻蚀阻挡层。
  4. 根据权利要求1所述的线路板，其中，
    所述第二层叠结构包括依次远离所述衬底基板的粘接层、第二金属层以及第二氧化阻挡层，
    所述第二氧化阻挡层和所述第二金属层在所述衬底基板上的正投影位于所述粘接层在所述衬底基板上的正投影内。
  5. 根据权利要求1所述的线路板，其中，
    所述第一层叠结构在其长度方向的侧面与所述衬底基板所在的平面的夹角在60°至90°的范围内。
  6. 根据权利要求1所述的线路板，其中，
    所述第二层叠结构在其长度方向的侧面与所述衬底基板所在的平面的夹角在60°至80°的范围内。
  7. 根据权利要求2所述的线路板，其中，
    所述刻蚀阻挡层的厚度大于
    Figure PCTCN2022077542-appb-100001
    所述第一金属层的厚度在
    Figure PCTCN2022077542-appb-100002
    至
    Figure PCTCN2022077542-appb-100003
    的范围，所述第一氧化阻挡层的厚度小于
    Figure PCTCN2022077542-appb-100004
  8. 根据权利要求2所述的线路板，其中，
    所述刻蚀阻挡层包括NiV合金、NiW合金，所述第一金属层包括铜，所述第一氧化阻挡层包括CuNi合金。
  9. 根据权利要求4所述的线路板，其中，
    所述粘接层的厚度在
    Figure PCTCN2022077542-appb-100005
    至
    Figure PCTCN2022077542-appb-100006
    的范围内，所述第二金属层的厚度在
    Figure PCTCN2022077542-appb-100007
    至
    Figure PCTCN2022077542-appb-100008
    的范围内，所述第二氧化阻挡层的厚度在
    Figure PCTCN2022077542-appb-100009
    至
    Figure PCTCN2022077542-appb-100010
    的范围内。
  10. 根据权利要求4所述的线路板，其中，所述粘接层包括Mo或MoNb合金，所述第二金属层包括铜，所述第二氧化阻挡层包括NiV合金、NiW合金。
  11. 根据权利要求8或10所述的线路板，其中，所述NiV合金的V元素质量比含量在3％至15％的范围，所述NiW合金的W元素质量比含量在10％至50％的范围。
  12. 根据权利要求8所述的线路板，其中，所述CuNi合金的Ni元素质量比含量在10％至30％的范围。
  13. 根据权利要求1所述的线路板，其中，所述走线还包括：
    设置于所述衬底基板和所述第一导电层之间的第二导电层，所述第一导电层和所述第二导电层通过至少一层绝缘层分隔开。
  14. 根据权利要求1至10中任一项所述的线路板，其中，还包括：
    贯穿所述至少一个绝缘层的过孔，其中过孔暴露出第一导电层远离衬底基板一侧的部分表面。
  15. 一种线路板的制造方法，其中，包括：
    形成衬底基板；
    在所述衬底基板上形成走线，形成所述走线包括形成第一导电层；
    形成至少一个绝缘层，所述绝缘层设置在所述第一导电层远离所述衬底基板的一侧，所述至少一个绝缘层覆盖所述第一导电层；
    其中，所述第一导电层包括远离所述衬底基板一侧的第一层叠结构和靠近所述衬底基板的第二层叠结构，
    所述第一层叠结构至少包括刻蚀阻挡层，所述刻蚀阻挡层覆盖所述第二层叠结构。
  16. 根据权利要求15所述的制造方法，其中，
    所述形成第一导电层包括：
    在靠近所述衬底基板的一侧沉积形成包含第二层叠结构的第二层叠结构膜层，对所述第二层叠结构膜层进行刻蚀，形成所述第二层叠结构；
    在所述第二层叠结构远离所述衬底基板的一侧形成包含第一层叠结构的第一层叠结构膜层，对所述第一层叠结构膜层进行刻蚀，形成第一层叠结构。
  17. 一种功能背板，其中，包括：
    如权利要求1至14中任一项所述的线路板；
    沿垂直于所述线路板的衬底基板且远离所述衬底基板的方向，层叠设置于所述线路板上的金属间化合物层和导电连接层；
    电子元件，与所述导电连接层电连接。
  18. 一种背光模组，包括：如权利要求17所述的功能背板。
  19. 一种显示装置，包括：
    显示面板；
    如权利要求18所述的背光模组；所述显示面板设置于所述背光模组的出光侧。
  20. 一种显示装置，包括显示面板，所述显示面板包括如权利要求17中任一项所述的功能背板。
PCT/CN2022/077542 2022-02-24 2022-02-24 线路板及其制造方法、功能背板、背光模组、显示装置 WO2023159405A1 (zh)

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TW200816488A (en) * 2006-09-29 2008-04-01 Innolux Display Corp Thin film transistor substrate
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