WO2023230932A1 - 芯片结构、芯片制备方法、显示基板和显示装置 - Google Patents

芯片结构、芯片制备方法、显示基板和显示装置 Download PDF

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Publication number
WO2023230932A1
WO2023230932A1 PCT/CN2022/096491 CN2022096491W WO2023230932A1 WO 2023230932 A1 WO2023230932 A1 WO 2023230932A1 CN 2022096491 W CN2022096491 W CN 2022096491W WO 2023230932 A1 WO2023230932 A1 WO 2023230932A1
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Prior art keywords
layer
sub
initial
gallium nitride
bonding
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PCT/CN2022/096491
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English (en)
French (fr)
Inventor
李伟
王明星
孙倩
闫华杰
焦志强
梁轩
靳倩
李翔
王灿
玄明花
张粲
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京东方科技集团股份有限公司
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Priority to CN202280001597.4A priority Critical patent/CN117501355A/zh
Priority to PCT/CN2022/096491 priority patent/WO2023230932A1/zh
Publication of WO2023230932A1 publication Critical patent/WO2023230932A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a chip structure, a chip preparation method, a display substrate and a display device.
  • Micro-LED (micro light-emitting diode) display devices are a new generation of display technology with the advantages of high brightness, high luminous efficiency, low power consumption, and fast response speed.
  • Micro-LED microwave light-emitting diode
  • the chip structure includes: a chip wafer unit and a color conversion layer substrate unit disposed on the light exit side of the chip wafer unit.
  • the chip wafer unit includes a plurality of sub-pixel light-emitting functional layers.
  • the color conversion layer substrate unit includes a color conversion layer disposed on the light exit side of the chip wafer unit.
  • the chip wafer unit also includes: a first bonding layer, disposed between the sub-pixel light-emitting functional layer and the color conversion layer, for bonding the chip wafer unit and the color conversion layer substrate unit.
  • the first bonding layer includes a stacked first sub-metal layer, a second sub-metal layer and a third sub-metal layer.
  • the third sub-metal layer is closer to the color conversion layer substrate unit than the first sub-metal layer, and the second sub-metal layer is configured to connect the first sub-metal layer and the third sub-metal layer.
  • Eutectic alloy layer is configured to connect the first sub-metal layer and the third sub-metal layer.
  • the first bonding layer includes a first sub-bonding layer and a second sub-bonding layer arranged in a stack.
  • the material of the first sub-bonding layer and the second sub-bonding layer is indium zinc oxide.
  • the chip wafer unit includes a first sub-pixel light-emitting functional layer, a second sub-pixel light-emitting functional layer and a third sub-pixel light-emitting functional layer.
  • the first bonding layer includes a first opening area corresponding to the first sub-pixel light-emitting functional layer, a second opening area corresponding to the second sub-pixel light-emitting functional layer, and a first opening area corresponding to the third sub-pixel light-emitting functional layer.
  • the third opening area corresponding to the functional layer is a first opening area corresponding to the first sub-pixel light-emitting functional layer, a second opening area corresponding to the second sub-pixel light-emitting functional layer, and a first opening area corresponding to the third sub-pixel light-emitting functional layer.
  • the chip wafer unit further includes a common cathode layer.
  • the first sub-pixel light-emitting functional layer includes a first quantum well, a first p-type gallium nitride and a first anode stacked along a first direction.
  • the second sub-pixel light-emitting functional layer includes a second quantum well, a second p-type gallium nitride and a second anode stacked along a first direction.
  • the third sub-pixel light-emitting functional layer includes a third quantum well, a third p-type gallium nitride and a third anode stacked along the first direction.
  • the common cathode layer includes a cathode metal and a cathode electrode stacked along a first direction. Wherein, the first direction is a direction from the color conversion layer substrate unit to the chip wafer unit.
  • the cathode metal material of the common cathode layer includes any one of titanium, aluminum, nickel, and gold.
  • the chip wafer unit further includes a second bonding layer, the second bonding layer includes a first bonding portion, a second bonding portion, a third bonding portion and a fourth bonding portion.
  • the first bonding portion is stacked between the first p-type gallium nitride and the first anode
  • the second bonding portion is stacked between the second p-type gallium nitride and the first anode.
  • the third bonding portion is stacked between the third p-type gallium nitride and the third anode
  • the cathode metal of the common cathode layer includes the fourth bonding portion .
  • the second bonding layer includes a stacked fourth sub-metal layer, a fifth sub-metal layer and a sixth sub-metal layer.
  • the sixth sub-metal layer is farther from the color conversion layer substrate than the fourth sub-metal layer, and the fifth sub-metal layer is configured to connect the sixth sub-metal layer and the fourth sub-metal layer. crystal alloy layer.
  • the chip wafer unit further includes a second bonding layer
  • the first bonding layer includes a stacked first sub-metal layer, a second sub-metal layer and a third sub-metal layer, so The thickness range of the maximum thickness of the first bonding layer is equal to the thickness range of the second bonding layer.
  • the first bonding layer includes a stacked first sub-bonding layer and a second sub-bonding layer, and the thickness range of the first bonding layer is smaller than the thickness range of the second bonding layer.
  • the chip wafer unit further includes a second bonding layer
  • the first bonding layer includes a stacked first sub-metal layer, a second sub-metal layer and a third sub-metal layer, so The maximum thickness of the first bonding layer ranges from 3 ⁇ m to 6 ⁇ m.
  • the first bonding layer includes a stacked first sub-bonding layer and a second sub-bonding layer, and the thickness of the first bonding layer ranges from 200 nm to 1200 nm.
  • the thickness of the second bonding layer ranges from 3 ⁇ m to 6 ⁇ m.
  • the first bonding layer includes a stacked first sub-metal layer, a second sub-metal layer and a third sub-metal layer.
  • the second sub-metal layer is a eutectic alloy layer with a melting temperature less than 240°C.
  • the chip wafer unit further includes an n-type gallium nitride conductive layer and a gallium nitride buffer layer stacked along a second direction, and the second direction is directed by the chip wafer unit. Describe the direction of the color conversion layer substrate unit.
  • the n-type gallium nitride conductive layer is connected to the first quantum well, the second quantum well, the third quantum well and the cathode metal.
  • the area of the gallium nitride buffer layer corresponding to the first sub-pixel light-emitting functional layer, the second sub-pixel light-emitting functional layer and the third sub-pixel light-emitting functional layer is a first area, and the first area faces A plurality of first-type micro-protrusion structures are provided on one side of the color conversion layer substrate; the portion of the gallium nitride buffer layer excluding the first area is a second area, and the first bonding layer is located The gallium nitride buffer layer in the second region faces the side of the color conversion layer substrate.
  • the chip wafer unit further includes an n-type gallium nitride conductive layer, and the n-type gallium nitride conductive layer includes a first n-type gallium nitride, a second n-type gallium nitride, a third n-type gallium nitride and fourth n-type gallium nitride.
  • the first n-type gallium nitride is stacked on a side of the first quantum well away from the first p-type gallium nitride, and the second n-type gallium nitride is stacked on the second quantum well
  • the third n-type gallium nitride is stacked on the side of the third quantum well away from the third p-type gallium nitride.
  • n-type gallium nitride is stacked on the side of the fourth bonding region facing the color conversion layer substrate, and the first bonding layer is disposed on the n-type gallium nitride conductive layer facing the color conversion layer One side of the base unit.
  • the stacked first sub-metal layer and the second sub-metal layer include a first area provided with the first opening area and a second area provided with the second opening area. , a third area provided with the third opening area and a fourth area covering the common cathode layer, the third sub-metal layer covering the first area, the second area, the third area and the second sub-metal layer of the fourth region, and the third sub-metal layer is configured to connect the first n-type gallium nitride, the second n-type gallium nitride, the third three n-type gallium nitride and the fourth n-type gallium nitride conductive layer.
  • the area of the n-type gallium nitride conductive layer corresponding to the first sub-pixel light-emitting functional layer, the second sub-pixel light-emitting functional layer and the third sub-pixel light-emitting functional layer is a third region, and a plurality of second type micro-protrusion structures are provided on the side of the third region facing the color conversion layer substrate unit.
  • the chip wafer unit further includes a reflective metal layer, the reflective metal layer includes a first reflective part, a second reflective part and a third reflective part, the first reflective part is stacked on the between the first p-type gallium nitride and the first anode, the second reflective part is stacked between the second p-type gallium nitride and the second anode, and the third reflective part is stacked Disposed between the third p-type gallium nitride and the third anode.
  • the reflective metal layer includes a first reflective part, a second reflective part and a third reflective part
  • the first reflective part is stacked on the between the first p-type gallium nitride and the first anode
  • the second reflective part is stacked between the second p-type gallium nitride and the second anode
  • the third reflective part is stacked Disposed between the third p-type gallium nitride and the third anode.
  • the chip wafer unit includes a second bonding layer
  • the second bonding layer includes a first bonding portion, a second bonding portion, a third bonding portion, and a fourth bonding portion.
  • the first reflective part is stacked on the side of the first bonding part facing the color conversion layer substrate unit
  • the second reflective part is stacked on the second bonding part facing the color conversion layer.
  • the third reflective part is stacked on the side of the third bonding part facing the color conversion layer substrate unit.
  • an insulating layer is provided on the side of the second bonding layer facing the color conversion layer substrate unit, and a first via hole, a second via hole, and a third via hole are provided on the insulating layer. and a fourth via hole.
  • the fourth sub-metal layer of the first bonding part fills the first via hole and is connected to the first reflective part.
  • the fourth sub-metal layer of the second bonding part fills the first via hole.
  • the second via hole is connected to the second reflective part
  • the fourth sub-metal layer of the third bonding part fills the third via hole and is connected to the third reflective part
  • the fourth bonding part The fourth sub-metal layer fills the fourth via hole and is connected to the n-type gallium nitride conductive layer.
  • the chip wafer unit includes a first sub-pixel light-emitting functional layer, a second sub-pixel light-emitting functional layer and a third sub-pixel light-emitting functional layer
  • the color conversion layer includes a defined dam layer, and is composed of the The dam layer defines a fourth opening area, a fifth opening area and a sixth opening area.
  • the fourth opening area is provided with a first quantum dot conversion part corresponding to the first sub-pixel light-emitting functional layer
  • the fifth opening area is provided with a scattering particle part corresponding to the second sub-pixel light-emitting functional layer.
  • the sixth opening area is provided with a scattering particle portion corresponding to the third sub-pixel light-emitting functional layer.
  • the orthographic projection of the fourth opening area on the color conversion layer substrate unit covers the orthographic projection of the first sub-pixel light-emitting functional layer on the color conversion layer substrate unit, and the fifth The orthographic projection of the opening area on the color conversion layer substrate unit covers the orthographic projection of the second sub-pixel light-emitting functional layer on the color conversion layer substrate unit, and the sixth opening area is on the color conversion layer substrate unit.
  • the orthographic projection covers the orthographic projection of the third sub-pixel light-emitting functional layer on the color conversion layer substrate unit.
  • the color conversion layer substrate unit further includes a light-gathering layer, the light-gathering layer is disposed on a side of the color conversion layer close to the chip wafer unit, the light-gathering layer includes a a first light condensing part corresponding to the first quantum dot conversion part, a second light condensing part corresponding to the scattering particle part, and a third light condensing part corresponding to the third quantum dot conversion part.
  • the color conversion layer substrate unit further includes a substrate and a color filter layer.
  • the substrate, the color filter layer and the color conversion layer are stacked along a second direction.
  • the second direction In the direction from the chip wafer unit to the color conversion layer substrate unit, the color film layer includes a black matrix, and a first filter film defined by the black matrix and corresponding to the first quantum dot conversion part , a second filter film corresponding to the scattering particle part and a third filter film corresponding to the scattering particle part.
  • a display substrate including the chip structure as described in any of the above embodiments.
  • the chip preparation method includes: forming an initial chip wafer unit.
  • the initial chip wafer unit includes a temporary substrate arranged in a stack, a plurality of sub-pixel light-emitting functional layers, a first initial sub-metal layer and a second initial sub-metal layer, wherein the second initial sub-metal layer includes a plurality of first type metal bumps.
  • the chip preparation method also includes forming a color conversion layer substrate unit.
  • the color conversion layer substrate unit includes a stacked color conversion layer and a first substrate.
  • a third substrate is formed on a side of the color conversion layer away from the first substrate.
  • Three initial sub-metallic layers are bonded to form a first bonding layer.
  • the first bonding layer includes a first sub-metal layer, a second sub-metal layer and a third sub-metal layer, and the second sub-metal layer connects the first sub-metal layer and the third sub-metal layer.
  • Eutectic alloy layer of metal layer is forming a color conversion layer substrate unit.
  • the chip preparation method further includes peeling off the temporary substrate to form a chip wafer unit, and the chip wafer unit and the color conversion layer substrate unit are connected by the first bonding layer.
  • the step of forming an initial chip wafer unit includes: providing a second substrate, forming the initial chip wafer unit on one side of the second substrate, the initial chip wafer unit It includes multiple initial sub-pixel light-emitting functional layers and an initial common cathode layer.
  • the step of forming an initial chip wafer unit further includes: forming a plurality of initial sub-pixel light-emitting functional layers and an initial common cathode layer on a side of the initial chip wafer unit away from the second substrate.
  • the temporary substrate The step of forming the initial chip wafer further includes: peeling off the second substrate.
  • the initial chip wafer unit is formed on one side of the second substrate, and the initial chip wafer unit includes a plurality of initial sub-pixel light-emitting functional layers and an initial common cathode layer.
  • the step of forming the temporary substrate on the side of the initial sub-pixel light-emitting functional layer and the initial common cathode layer away from the second substrate of the initial chip wafer unit includes: A gallium nitride buffer layer, an n-type gallium nitride layer, a quantum well layer and a P-type gallium nitride layer are formed on one side of the substrate in sequence, and the quantum well layer and P-type gallium nitride layer are patterned to form an initial chip The quantum well layer and P-type gallium nitride layer of the wafer unit.
  • a first insulating layer is formed on a side of the P-type gallium nitride layer away from the quantum well layer, and a plurality of via holes are provided on the first insulating layer.
  • a fourth sub-initial metal layer and a fifth sub-initial metal layer are formed on the side of the first insulating layer away from the second substrate; the fourth sub-initial metal layer fills a plurality of sub-initial metal layers provided on the first insulating layer.
  • the fifth sub-initial metal layer includes a plurality of second type metal bumps.
  • a temporary substrate is provided, and a sixth sub-initial metal layer of the initial chip wafer unit is formed on one side of the temporary substrate. Bonding the sixth sub-initial metal layer, the fifth sub-initial metal layer and the fourth sub-initial metal layer to form a second bonding layer, the second bonding layer includes a fourth sub-metal layer, a fifth sub-metal layer layer and a sixth sub-metal layer, the fifth sub-metal layer is configured as a eutectic alloy layer connecting the sixth sub-metal layer and the fourth sub-metal layer.
  • the step of peeling off the second substrate further includes the following steps: removing the gallium nitride buffer layer, and patterning the n-type gallium nitride layer and the first insulating layer.
  • the first initial sub-metal layer and the second initial sub-metal layer are formed on the side of the n-type gallium nitride layer of each initial chip wafer unit away from the temporary substrate, and the The surface of the n-type gallium nitride layer is roughened to form the initial chip wafer unit.
  • the step of peeling off the second substrate further includes the following step: patterning the gallium nitride buffer layer, the n-type gallium nitride layer and the first insulating layer.
  • a first initial sub-metal layer and a second initial sub-metal layer are formed on the gallium nitride buffer layer of the initial chip wafer unit, and the surface of the gallium nitride buffer layer is roughened to form the The initial chip wafer unit is described.
  • the step of peeling off the temporary substrate to form a chip wafer unit includes: forming a second insulating layer on a side of each second bonding layer away from the color conversion layer substrate unit. There are multiple vias on the layer. An electrode is formed, and the electrode includes a cathode electrode and an anode electrode, and the cathode electrode and the anode electrode fill one of the corresponding via holes on the second insulating layer. The first substrate is thinned to form the chip wafer.
  • the initial chip wafer unit is formed on one side of the second substrate, and the initial chip wafer unit includes a plurality of initial sub-pixel light-emitting functional layers and an initial common cathode layer.
  • the step of forming the temporary substrate on the side of the initial sub-pixel light-emitting functional layer and the initial common cathode layer away from the second substrate of the initial chip wafer unit includes: A gallium nitride buffer layer, an n-type gallium nitride layer, a quantum well layer and a P-type gallium nitride layer are formed on one side of the substrate in sequence, and the quantum well layer and P-type gallium nitride layer are patterned to form an initial chip The quantum well layer and P-type gallium nitride layer of the wafer unit.
  • the cathode metal forming the initial common cathode layer.
  • a second insulating layer is formed on a side of the P-type gallium nitride layer and the cathode metal away from the color conversion layer substrate unit, and a plurality of via holes are provided on the second insulating layer.
  • An electrode is formed, and the electrode includes a cathode electrode and an anode electrode, and the cathode electrode and the anode electrode fill one of the corresponding via holes on the second insulating layer.
  • the plurality of initial sub-pixel light-emitting functional layers and the initial common cathode layer of the initial chip wafer unit are formed.
  • the plurality of sub-pixel light-emitting functional layers and the initial common cathode layer are bonded to the temporary substrate.
  • the step of peeling off the second substrate further includes the following steps: patterning the gallium nitride buffer layer, the n-type gallium nitride layer and the second insulating layer, and forming a third insulating layer on the gallium nitride buffer layer.
  • An initial sub-metal layer and the second initial sub-metal layer, and the surface of the gallium nitride buffer layer is roughened to form the initial chip wafer unit.
  • a display device including the display substrate as described above.
  • Figure 1 is a structural diagram of a display substrate provided according to some embodiments of the present disclosure.
  • Figure 2 is a structural diagram of a first initial wafer A provided according to some embodiments of the present disclosure
  • Figure 3 is a structural diagram of a second initial wafer B provided according to some embodiments of the present disclosure.
  • Figure 4 is a structural diagram of a chip structure provided according to some embodiments of the present disclosure.
  • Figure 5 is another structural diagram of a chip structure provided according to some embodiments of the present disclosure.
  • Figure 6a is another structural diagram of a chip structure provided according to some embodiments of the present disclosure.
  • Figure 6b is another structural diagram of a chip structure provided according to some embodiments of the present disclosure.
  • Figure 7 is a flow chart of an initial chip wafer unit preparation method provided according to some embodiments of the present disclosure.
  • FIGS. 8 to 10 are step diagrams of an initial chip wafer unit preparation method provided according to some embodiments of the present disclosure.
  • Figure 11 is a flow chart of metal wafer bonding technology provided according to some embodiments of the present disclosure.
  • Figure 12 is a step diagram of metal wafer bonding technology provided according to some embodiments of the present disclosure.
  • Figures 13 to 16b are step diagrams of an initial chip wafer unit preparation method provided according to some embodiments of the present disclosure.
  • Figure 17 is a flow chart of a method for preparing an initial color conversion layer substrate unit according to some embodiments of the present disclosure
  • Figures 18a to 22b are step diagrams of a method for preparing an initial color conversion layer substrate unit according to some embodiments of the present disclosure
  • Figure 23 is a flow chart of the box assembly process in the chip preparation method provided according to some embodiments of the present disclosure.
  • Figures 24 to 28 are step diagrams of the box assembly process in the chip preparation method provided according to some embodiments of the present disclosure.
  • Figure 29 is a flow chart of another initial chip wafer unit preparation method provided according to some embodiments of the present disclosure.
  • Figures 30 to 32 are step diagrams of another method for preparing an initial chip wafer unit according to some embodiments of the present disclosure.
  • Figure 33 is a flow chart of yet another initial chip wafer unit preparation method provided according to some embodiments of the present disclosure.
  • Figures 34 to 41 are step diagrams of yet another initial chip wafer unit preparation method provided according to some embodiments of the present disclosure.
  • Figure 42 is a flow chart of yet another box assembly process in a chip preparation method provided according to some embodiments of the present disclosure.
  • Figure 43 is a step diagram of yet another box assembly process in the chip preparation method provided according to some embodiments of the present disclosure.
  • Figure 44 is a structural diagram of a display device provided according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “in response to” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrase “if it is determined" or “if [stated condition or event] is detected” is optionally interpreted to mean “when it is determined" or “in response to the determination" or “on detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • parallel includes absolutely parallel and approximately parallel, and the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°;
  • perpendicular includes absolutely vertical and approximately vertical, and the acceptable deviation range of approximately vertical may also be, for example, Deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the difference between the two that may be equal within the acceptable deviation range of approximately equal is less than or equal to 5% of either one, for example.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the present disclosure provides a chip structure 10.
  • the chip structure 10 includes a chip wafer unit 11 and a color conversion layer substrate unit 21 disposed on the light exit side G of the chip wafer unit 11.
  • the chip wafer unit 11 includes a plurality of sub-pixel light-emitting functional layers 12
  • the color conversion layer substrate unit 21 includes a color conversion layer 22 disposed on the light exit side G of the chip wafer unit 11 .
  • the chip wafer unit 11 also includes: a first bonding layer 13, which is provided between the sub-pixel light-emitting functional layer 12 and the color conversion layer 22, and is used to bond the chip wafer unit 11 and the color conversion layer substrate unit 21.
  • the chip structure 10 includes a chip wafer unit 11 and a color conversion layer substrate unit 21.
  • One of the multiple sub-pixel light-emitting functional layers 12 of the chip wafer unit 11 is configured.
  • To emit one of multiple colors of light, and multiple sub-pixel light emitting functional layers 12 may be configured to emit light of the same color.
  • the color conversion layer substrate unit 21 is disposed on the light exit side G of the chip wafer unit 11.
  • the color conversion layer substrate unit 21 is provided with a color conversion layer 22 corresponding to the light exit side G of each sub-pixel light emitting functional layer 12.
  • the present disclosure connects the chip wafer unit 11 and the color conversion layer substrate unit 21 through the metal wafer bonding effect of the first bonding layer 13.
  • the first bonding layer 13 is made of metal material.
  • the metal material has a high refractive index and can This prevents the light emitted from the sub-pixel light-emitting functional layer 12 from light leakage and cross-color, and improves the light extraction effect of the chip structure 10 .
  • the chip wafer unit 11 and the color conversion layer substrate unit 21 are connected through metal wafer bonding of the first bonding layer 13 to form the chip structure 10.
  • the preparation method includes: preparing an initial chip wafer unit 110 and an initial color conversion layer substrate unit. 210, and then bond the initial chip wafer unit 110 and the initial color conversion layer substrate unit 210 through metal wafer bonding technology to form the chip structure 10.
  • the following three examples are provided.
  • the preparation method of the chip structure 10 is to first form a plurality of chip structures including an array arrangement. A wafer of a chip structure 10 is then formed into a single chip structure 10 by cutting the wafer.
  • a first embodiment of a method for manufacturing the chip structure 10 is introduced below.
  • the chip structure 10 formed according to this embodiment is the chip structure 10 shown in FIG. 4 .
  • FIG. 7 shows the preparation steps of the initial chip wafer unit 110, including S101 to S107.
  • an initial gallium nitride buffer layer 150, an initial n-type gallium nitride layer 160, an initial quantum well layer 1210 and an initial P-type nitride layer are sequentially formed on one side of the second substrate 14.
  • the second substrate 14 may be a sapphire substrate or a silicon-based substrate.
  • the quantum well layer 121 may be a blue quantum well, and the sub-pixel light-emitting functional layer 12 formed of the blue quantum well emits blue light.
  • the initial quantum well layer 1210 and the initial P-type gallium nitride layer 1220 are patterned through a photolithography process, and the initial quantum well layer 1210 and the initial quantum well layer 1210 in the area between the adjacent sub-pixel light-emitting functional layers 12 and the negative electrode area S17 are removed.
  • the multiple sub-pixel light-emitting functional layers 12 of the chip wafer unit 11 include a first sub-pixel light-emitting functional layer 12a, a second sub-pixel light-emitting functional layer 12b and a third sub-pixel Light emitting functional layer 12c.
  • the first quantum well 121a and the first p-type gallium nitride 122a of the first sub-pixel light-emitting functional layer 12a are formed, and the second quantum well and the second p-type gallium nitride of the second sub-pixel light-emitting functional layer 12b are formed.
  • Fig. 9a is a cross-sectional view taken along the AA cross-section line in Fig. 9b.
  • an initial reflective metal layer is stacked on the side of the P-type gallium nitride layer 122 away from the second substrate 14, and the initial reflective metal layer is patterned to form multiple initial chip wafers. Reflective metal layer 123 of each initial chip wafer unit 110 in unit 110 .
  • an initial reflective metal layer is deposited through a deposition process.
  • the material of the reflective metal layer 123 can be ITO-Ag-ITO.
  • the reflective metal layer 123 has the function of reflecting light and can improve the light extraction rate of the sub-pixel light-emitting functional layer 12 .
  • the reflective metal layer 123 includes a first reflective part 123a, a second reflective part 123b and a third reflective part 123c.
  • the first sub-pixel light-emitting functional layer 12a includes a first reflective part 123a
  • the second sub-pixel light-emitting functional layer 12b includes a second reflective part 123b
  • the third sub-pixel light-emitting functional layer 12c includes a third reflective part 123c.
  • a preliminary first insulating layer 18a is formed, and a plurality of via holes H are provided on the preliminary first insulating layer 18a.
  • an initial first insulating layer is formed on the side of the reflective metal layer 123 and the initial n-type gallium nitride layer 160 away from the second substrate 14 through a deposition process, and is formed on the initial first insulating layer through a photolithography process.
  • a plurality of via holes H form a preliminary first insulating layer 18a. As shown in FIG. 9b, the plurality of via holes H include a first via hole H1, a second via hole H2, a third via hole H3, and a fourth via hole H4.
  • the first via hole H1 is provided correspondingly to the first sub-pixel light-emitting functional layer 12a
  • the second via hole H2 is provided correspondingly to the second sub-pixel light-emitting functional layer 12b
  • the third via hole H3 is provided correspondingly to the third sub-pixel light-emitting functional layer 12c.
  • the fourth via hole H4 is provided corresponding to the negative electrode region S17.
  • a part of the second bonding layer 19 is formed as the common cathode layer 17 , and the second bonding layer 19 also has the function of bonding the temporary substrate 20 of the initial chip wafer unit 110 .
  • the temporary substrate 20 is a silicon substrate.
  • metal wafer bonding technology may be used to form the second bonding layer 19 .
  • Metal wafer bonding technology refers to a technology that relies on the formation of a eutectic alloy between two different metals to completely bond at a temperature lower than the respective melting points of the metals.
  • Metal wafer bonding technology can be divided into solid-liquid interdiffusion bonding technology and solid-state diffusion bonding technology according to different bonding temperatures. Among them, solid-liquid interdiffusion bonding technology has lower requirements for film layer flatness than solid-state diffusion bonding technology. Moreover, the solid-liquid interdiffusion bonding technology has high bonding strength and short bonding time. Therefore, the second bonding layer 19 can be formed using solid-liquid interdiffusion bonding technology.
  • the steps of forming the second bonding layer 19 include steps S131 to S133.
  • S131 As shown in FIG. 12 , form a patterned fourth sub-initial metal layer 1910 and a fifth sub-initial metal layer 1920 on the side of the preliminary first insulating layer 18a away from the second substrate 14 .
  • the fourth sub-initial metal layer 1910 fills the plurality of vias H provided on the preliminary first insulating layer 18a, and the fifth sub-initial metal layer 1920 includes a plurality of second-type metal bumps 192a.
  • forming a patterned film layer refers to first forming an entire initial film layer, and then patterning the initial film layer through a patterning process (such as a photolithography process).
  • a patterning process such as a photolithography process
  • a whole layer of material for forming the fourth sub-initial metal layer 1910 is deposited on the side of the preliminary first insulating layer 18a away from the second substrate 14 through a deposition process, and a photolithography process is used to form the patterned fourth sub-initial metal layer 1910 .
  • the material of the fourth sub-initial metal layer 1910 may be any one of Au (gold), Ag (silver), Pb (lead), Sn (tin), and Cu (copper).
  • the structure of the second type metal bumps 192a of the fifth sub-initial metal layer 1920 may be cylindrical or conical.
  • the second type metal bumps will become liquid and form a eutectic alloy layer with the adjacent fourth sub-initial metal layer 1910 and the subsequent sixth sub-initial metal layer 1930.
  • the material of the fifth sub-initial metal layer 1920 can be In (indium), the temperature at which Au (gold) and In (indium) form a eutectic alloy is 160°C, and the temperature at which Ag (silver) and In (indium) form a eutectic alloy The temperature at which Pb (lead) and In (indium) form a eutectic alloy is 200°C, and the temperature at which Sn (tin) and In (indium) form a eutectic alloy is 120°C.
  • the material of the fifth sub-initial metal layer 1920 can also be Sn (tin).
  • the temperature of Cu (copper) and Sn (tin) forming a eutectic alloy is 280° C.
  • Au (gold) and Sn (tin) form a eutectic alloy.
  • the temperature of the alloy is 280°C
  • the temperature at which Ag (silver) and Sn (tin) form a eutectic alloy is 250°C.
  • the melting temperature of the eutectic alloy formed by the material of the fourth sub-initial metal layer 1910 and the material of the fifth sub-initial metal layer 1920 is less than 400°C. °C is enough.
  • the fifth sub-initial metal layer 1920 is formed using a lift-off process.
  • photoresist is first used to form an inverted trapezoidal array-arranged protrusion structure on the fourth sub-initial metal layer 1910, and then the material (In or Sn) forming the fifth sub-initial metal layer 1920 is evaporated to form the second sub-initial metal layer 1920.
  • the fifth sub-initial metal layer 1920 of the metal-like bump 192a is a lift-off process.
  • a patterned sixth sub-initial metal layer 1930 is formed on one side of the temporary substrate 20 .
  • a whole layer of material of the sixth sub-initial metal layer 1930 is deposited on one side of the temporary substrate 20 through a deposition process, and a photolithography process is used to form the patterned sixth sub-initial metal layer 1930.
  • the material of the sixth sub-initial metal layer 1930 may be any one of Au (gold), Ag (silver), Pb (lead), Sn (tin), and Cu (copper).
  • the material of the sixth sub-initial metal layer 1930 may be the same as the material of the fourth sub-initial metal layer 1910 .
  • the second bonding layer 19 includes a stacked fourth sub-metal layer 191 , a fifth sub-metal layer 192 and a sixth sub-metal layer 193 .
  • the fifth sub-metal layer 192 is connected to the fourth sub-metal layer. 191 and the eutectic alloy layer of the sixth sub-metal layer 193 .
  • the purpose of connecting the temporary substrate 20 to the initial chip wafer unit 110 is achieved.
  • the bonding of the second bonding layer 19 including the fourth sub-metal layer 191 , the fifth sub-metal layer 192 and the sixth sub-metal layer 193 is achieved through solid-liquid interdiffusion bonding technology.
  • solid-liquid interdiffusion bonding For an introduction to the combined technology, see the above content and will not go into details here.
  • the second bonding layer 19 includes a first bonding portion 19a, a second bonding portion, a third bonding portion and a fourth bonding portion 19d.
  • the cathode metal 17a of the common cathode layer 17 includes a fourth bonding portion 19d. That is, the portion of the second bonding layer 19 located in the negative electrode region S17 shown in FIG. 9a is the fourth bonding portion 19d.
  • the fourth sub-metal layer 191 of the first bonding part 19a fills the first via hole H1 and is connected to the first reflective part 123a.
  • the fourth sub-metal layer of the second bonding part 19a 191 fills the second via hole H2 and is connected to the second reflective part 123b
  • the fourth sub-metal layer of the third bonding part fills 191 the third via hole H3 and connects to the third reflective part 123c
  • the fourth of the fourth bonding part 19d The sub-metal layer 191 fills the fourth via hole H4 and is connected to the initial n-type gallium nitride layer 160 .
  • the positions of the first via hole H1, the second via hole H2, the third via hole H3 and the fourth via hole H4, and the first reflection part 123a, the second reflection part 123b and the third reflection part 123c are as shown in FIG. 9b. Show.
  • the thickness d1 of the second bonding layer 19 ranges from 3 ⁇ m to 6 ⁇ m.
  • the thickness d1 of the second bonding layer 19 is 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, or 6 ⁇ m, etc., and is not limited here.
  • S104 Remove the second substrate 14.
  • the structure of an initial chip wafer unit 110 after removing the second substrate 14 is shown in FIG. 13 .
  • an acid-proof film or wax seal is used to protect the temporary substrate 20, the initial chip wafer unit 110 is placed in a hydrofluoric acid (HF) etching bath, and the second substrate 14 is removed by etching.
  • HF hydrofluoric acid
  • the initial n-type gallium nitride layer 160 is patterned through a photolithography process to form the patterned n-type gallium nitride layer 16 .
  • the preliminary first insulating layer 18a is patterned through a photolithography process to form a patterned first insulating layer 18.
  • the n-type gallium nitride layer 16 includes a first n-type gallium nitride 16a, a second n-type gallium nitride 16b, a third n-type gallium nitride 16c and a fourth n-type gallium nitride.
  • Gallium 16d Exemplarily, as shown in Figure 14b, the n-type gallium nitride layer 16 includes a first n-type gallium nitride 16a, a second n-type gallium nitride 16b, a third n-type gallium nitride 16c and a fourth n-type gallium nitride.
  • the first n-type gallium nitride 16a is arranged corresponding to the first sub-pixel light-emitting functional layer 12a
  • the second n-type gallium nitride 16b is arranged corresponding to the second sub-pixel light-emitting functional layer 12b
  • the third n-type gallium nitride 16c is arranged corresponding to the second sub-pixel light-emitting functional layer 12b.
  • the three sub-pixel light-emitting functional layers 12c are arranged correspondingly
  • the fourth n-type gallium nitride 16d is arranged correspondingly to the common cathode layer 17.
  • Figure 14a is a cross-sectional view taken along the BB section line of Figure 14b.
  • S106 As shown in FIG. 15a, form a patterned first initial sub-metal layer 1310 and a second initial sub-metal layer 1320 on the side of the n-type gallium nitride layer 16 away from the temporary substrate 20.
  • the first initial sub-metal layer 1310 and the second initial sub-metal layer 1320 are used to form the first bonding layer 13 that bonds the chip wafer unit 11 and the color conversion layer substrate unit 21.
  • first bonding layer 13 bonds the chip wafer unit 11 and the color conversion layer substrate unit 21.
  • a whole layer of material for forming the first initial sub-metal layer 1310 is deposited on the side of the n-type gallium nitride layer 16 away from the temporary substrate 20 through a deposition process, and a photolithography process is used to form the patterned first sub-metal layer 1310 .
  • the material of the first initial sub-metal layer 1310 may be any one of Au (gold), Ag (silver), Pb (lead), and Sn (tin).
  • the patterned first initial sub-metal layer 1310 includes a first region 13a, a second region 13b, a third region 13c and a fourth region 13d.
  • the first region 13a, the second region 13b, the third region 13c and the fourth area 13d are provided separately.
  • the first sub-pixel light-emitting functional layer 12a is located in the first light-emitting area F1, and the first area 13a is arranged corresponding to the first light-emitting area F1; the second sub-pixel light-emitting functional layer 12b is located in the second light-emitting area F2, and the second area 13b is arranged corresponding to the first light-emitting area F1.
  • the second light-emitting area F2 is provided correspondingly; the third sub-pixel light-emitting functional layer 12c is located in the third light-emitting area F3; the third area 13c is provided correspondingly to the third light-emitting area F3; the common cathode layer 17 is located in the negative electrode area S17, and the fourth area 13d is provided corresponding to the negative electrode region S17.
  • Figure 15a is a cross-sectional view taken along the CC section line of Figure 15b.
  • the first region 13a of the first initial sub-metal layer 1310 includes the first sub-opening region K11
  • the second region 13b includes the second sub-opening region K21
  • the third region 13c includes the third sub-opening region K31.
  • the second initial sub-metal layer 1320 includes a plurality of first-type metal bumps 132a, and the structure of the first-type metal bumps 132a may be cylindrical or conical.
  • the material of the second initial sub-metal layer 1320 may be In (indium), the temperature at which Au (gold) and In (indium) form a eutectic alloy is 160°C, and the temperature at which Ag (silver) and In (indium) form a eutectic alloy The temperature at which Pb (lead) and In (indium) form a eutectic alloy is 200°C, and the temperature at which Sn (tin) and In (indium) form a eutectic alloy is 120°C.
  • the above content is not a limitation on the material of the second initial sub-metal layer 1320.
  • the eutectic alloy needs to be formed.
  • the melting temperature is less than 240°C. If the melting temperature of the eutectic alloy layer is too high, the color conversion layer 22 in the color conversion layer substrate unit 21 will be damaged.
  • the formation process of the second initial sub-metal layer 1320 may refer to the above-mentioned formation process of the fifth sub-initial metal layer 1920, which will not be described again here.
  • a strong alkali of 70° C. to 80° C. is used to roughen the surface of the n-type gallium nitride layer 16, and a plurality of second-type micro-protrusion structures 16t are formed on the exposed surface of the n-type gallium nitride layer 16.
  • the second type of micro-protrusion structure 16t can make light easily emitted and improve the light extraction efficiency of the chip structure 10 .
  • the first region 13a of the first initial sub-metal layer 1310 includes the first sub-opening region K11
  • the second region 13b includes the second sub-opening region K21
  • the third region 13c includes the third sub-opening region K31.
  • the first n-type gallium nitride 16a exposed in the first sub-opening area K11, the second n-type gallium nitride 16b exposed in the second sub-opening area K21, and the third n-type gallium nitride exposed in the third sub-opening area K31 Due to the action of strong alkali, multiple second type micro-protrusion structures 16t are formed on the surface of gallium 16c.
  • Figure 16a is a cross-sectional view taken along the DD section line of Figure 16b.
  • the area of the n-type gallium nitride layer 16 corresponding to the first sub-pixel light-emitting functional layer 12a, the second sub-pixel light-emitting functional layer 12b and the third sub-pixel light-emitting functional layer 12c is the third area S3, and the third area S3 is In this step, the n-type gallium nitride layer 16 is exposed in areas corresponding to the first sub-opening area K11, the second sub-opening area K21, and the third sub-opening area K31.
  • a large plate including a plurality of initial chip wafer units 110 arranged in an array is simultaneously formed, and the large plate is cut, such as special-shaped cutting, to form a plurality of first initial wafers A.
  • the first initial wafer A is circular, and the first initial wafer A includes a plurality of initial chip wafer units 110 .
  • the size of the first initial wafer A is 4 inches or 6 inches.
  • the preparation steps of the initial color conversion layer substrate unit 210 are introduced below, as shown in FIG. 17 , including steps R201 to R205.
  • R201 As shown in Figure 18a, a black matrix layer 23, a color filter layer 24 and a limiting dam layer 25 are formed on the first substrate 31.
  • the first substrate 31 may be a glass substrate.
  • the plurality of color filter layers 24 include a first filter film 241, a second filter film 242, and a third filter film 243.
  • the first filter film 241 is a red filter film
  • the second filter film 242 is a blue filter film
  • the third filter film 243 is a green filter film.
  • Figure 18a is a cross-sectional view taken along the EE section line of Figure 18b.
  • a limiting dam layer 25 is formed on the side of the black matrix layer 23 away from the first substrate 31 by coating, exposure, development, post-baking, etc.
  • the limiting dam layer 25 is defined with multiple an opening area K.
  • the plurality of opening areas K include a fourth opening area K4, a fifth opening area K5 and a sixth opening area K6.
  • R202 As shown in Figure 19a, the color conversion layer 22 is formed.
  • the color conversion layer is produced in the fourth opening area K4, the fifth opening area K5 and the sixth opening area K6 by coating, exposure, development, post-baking or inkjet printing. twenty two.
  • the first quantum dot conversion part 22a is formed in the fourth opening area K4, and the first quantum dot conversion part 22a is made of red quantum dot luminescent material;
  • the scattering particle part 22b is formed in the fifth opening area K5, and the scattering particles are arranged;
  • the sixth opening A third quantum dot conversion part 22c is formed in the area K6, and the third quantum dot conversion part 22c uses green quantum dot luminescent material.
  • Figure 19a is a cross-sectional view taken along the FF section line of Figure 19b.
  • the orthographic projection of the fourth opening area K4 on the color conversion layer substrate unit 2 covers the orthographic projection of the first sub-pixel light-emitting functional layer 12 a on the color conversion layer substrate unit 2 .
  • the orthographic projection of the fifth opening area K5 on the color conversion layer substrate unit 2 covers the orthographic projection of the second sub-pixel light-emitting functional layer 12b on the color conversion layer substrate unit 2, and the sixth opening area K6 is on the color conversion layer substrate unit.
  • the orthographic projection of 2 covers the orthographic projection of the third sub-pixel light-emitting functional layer 12c on the color conversion layer substrate unit 2. This arrangement can improve the light extraction effect of the chip structure 10 .
  • R203 As shown in Figure 20, the inorganic encapsulation layer 26 is formed.
  • CVD chemical vapor deposition
  • the inorganic encapsulation layer 26 covers the color conversion layer 22 and the defining dam layer 25 .
  • a patterned third initial sub-metal layer 1330 is formed on the side of the inorganic encapsulation layer 26 away from the first substrate 31.
  • a whole layer of material for forming the third initial sub-metal layer 1330 is deposited on the side of the inorganic encapsulation layer 26 away from the first substrate 31 through a deposition process, and a photolithography process is used to form the patterned third initial sub-metal layer.
  • the material of the third initial sub-metal layer 1330 may be any one of Au (gold), Ag (silver), Pb (lead), and Sn (tin).
  • the material of the third initial sub-metal layer 1330 may be the same as the material of the first initial sub-metal layer 1310 .
  • the patterned third initial sub-metal layer 1330 is provided with a plurality of opening areas K.
  • the plurality of opening areas K include a fourth sub-opening area K14, a fifth sub-opening area K25 and a sixth sub-opening area K36.
  • the fourth sub-opening area K14 is provided corresponding to the first quantum dot conversion part 22a
  • the fifth sub-opening area K25 is provided corresponding to the scattering particle part 22b
  • the sixth sub-opening area K36 is provided corresponding to the third quantum dot conversion part 22c.
  • Figure 21a is a cross-sectional view taken along the GG section line of Figure 21b.
  • R205 As shown in Figure 22a, the light condensing layer 27 is produced to form the initial color conversion layer substrate unit 210.
  • the light condensing layer 27 includes a first light condensing part 27a corresponding to the first quantum dot conversion part 22a, a second light condensing part 27b corresponding to the scattering particle part 22b, and a third light condensing part 27b.
  • the third light condensing part 27c corresponding to the quantum dot conversion part 22c.
  • Figure 22a is a cross-sectional view taken along the HH section line of Figure 22b.
  • the light-condensing layer 27 is made of acrylic or epoxy materials.
  • the light-condensing layer 27 has the function of condensing light and can improve the light extraction effect of the chip structure 10 .
  • a large plate including a plurality of initial color conversion layer substrate units 210 arranged in an array is simultaneously formed. Cut the large plate, such as special-shaped cutting, to form a plurality of second initial wafers B. As shown in FIG. 3 , the second initial wafer B is circular, and the second initial wafer B includes a plurality of initial color conversion layer substrate units 210 . The second initial wafer B is the same size as the first initial wafer A.
  • the initial chip wafer unit 110 and the initial color conversion layer substrate unit 210 are bonded through metal wafer bonding technology.
  • the bonded initial color conversion layer substrate unit 210 forms the color conversion layer substrate unit 21 .
  • the first quantum dot conversion part 22a corresponds to the first sub-pixel light-emitting functional layer 12a
  • the scattering particle part 22b corresponds to the second sub-pixel light-emitting functional layer 12b
  • the third quantum dot conversion part 22c corresponds to the third sub-pixel light-emitting functional layer Corresponds to the 12c position.
  • the first type of metal bumps 132a will become liquid, and the second sub-initial metal layer 1320 formed using a metal bump structure will not enter the light-emitting area when melting into a liquid state.
  • the light-emitting area includes a first light-emitting area F1, a second light-emitting area F2, and a third light-emitting area F3, thereby preventing the first bonding layer 13 from affecting light emission.
  • the formed first bonding layer 13 includes a stacked first sub-metal layer 131 , a second sub-metal layer 132 and a third sub-metal layer 133 .
  • the maximum thickness d2 of the first bonding layer 13 ranges from 3 ⁇ m to 6 ⁇ m.
  • the thickness d2 of the first bonding layer 13 is 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, or 6 ⁇ m, etc., and is not limited here.
  • the first bonding layer 13 includes three layers: the first sub-metal layer 131 , the second sub-metal layer 132 and the third sub-metal layer 133 , since the first sub-metal layer 131 , the second sub-metal layer 132 and the third sub-metal layer 133 have patterns, so the thickness of the first bonding layer 13 is not equal at each position.
  • the first bonding layer 13 only Including the third sub-metal layer 133
  • the thickness d2 of the maximum thickness of the first bonding layer 13 mentioned in this disclosure refers to the thickness at the stacking position of the three sub-metal layers included in the first bonding layer 13 .
  • the third initial sub-metal layer 1330 away from the second initial sub-metal layer 1320 forms a third sub-metal layer 133
  • the first initial sub-metal layer 1330 away from the second initial sub-metal layer 1320 The metal layer 1310 forms the first sub-metal layer 131 .
  • the third sub-metal layer 133 is closer to the color conversion layer substrate unit 21 than the first sub-metal layer 131 . That is to say, the first sub-metal layer 131 is closer to the light-emitting side G of the sub-pixel light-emitting functional layer 12 than the third sub-metal layer 133 .
  • the third initial sub-metal layer 1330 adjacent to the second initial sub-metal layer 1320, the second initial sub-metal layer 1320, and the first initial sub-metal layer 1310 adjacent to the second initial sub-metal layer 1320 form the second sub-metal layer 132.
  • the second sub-metal layer 132 is provided as a eutectic alloy layer connecting the first sub-metal layer 131 and the third sub-metal layer 133 .
  • the first bonding layer 13 includes a first opening area K1 corresponding to the first sub-pixel light-emitting functional layer 12a, and a second sub-pixel light-emitting functional layer 12b (not shown in the figure). ) corresponding to the second opening area and the third opening area (not shown in the figure) corresponding to the third sub-pixel light-emitting functional layer 12c (not shown in the figure).
  • the first initial sub-metal layer 1310 forms the first bonding layer 13
  • the first sub-opening area K11 and the second sub-opening area of the first initial sub-metal layer 1310 K21 and the third sub-opening area K31 respectively correspond to the first sub-opening area K11, the second sub-opening area K21 and the third sub-opening area K31 of the first sub-metal layer 131;
  • the third initial sub-metal layer 1330 forms the first key
  • the fourth sub-opening area K14, the fifth sub-opening area K25 and the sixth sub-opening area K36 of the third initial sub-metal layer 1330 respectively correspond to the fourth sub-opening area K14 of the third sub-metal layer 133.
  • the second initial sub-metal layer 1320 forms a eutectic alloy with the first initial sub-metal layer 1310 and the third initial sub-metal layer 1330. In this process, the second initial sub-metal layer 1320 has a strong influence on the first initial sub-metal layer 1310 and the third initial sub-metal layer 1330. The open areas of the three initial sub-metal layers 1330 have no effect.
  • the first sub-opening area K11 and the fourth sub-opening area K14 The first opening area K1, the second sub-opening area K21 and the fifth sub-opening area K25 of the first bonding layer 13 are stacked to form the second opening area, the third sub-opening area K31 and the third sub-opening area K25 of the first bonding layer 13.
  • the sixth sub-opening area K36 is stacked to form a third opening area of the first bonding layer 13 .
  • the first substrate 31 is protected by an acid-proof film
  • the temporary substrate 20 is placed in a hydrofluoric acid (HF) etching bath for partial etching, and then the remaining temporary substrate 20 is removed using a dry etching process.
  • HF hydrofluoric acid
  • M303 As shown in Figure 27, a second insulating layer 40 is formed, and a plurality of via holes are provided on the second insulating layer 40.
  • the via holes on the second insulating layer 40 include the fifth via hole 401, the sixth via hole, the seventh via hole and the eighth via hole 404.
  • the fifth via hole 401 and the first sub-pixel light emitting functional layer 12a Correspondingly arranged, the sixth via hole is arranged correspondingly to the second sub-pixel light-emitting functional layer 12b, the seventh via hole is arranged correspondingly to the third sub-pixel light-emitting functional layer 12c, and the eighth via hole 404 is arranged correspondingly to the common cathode layer 17.
  • an electrode is formed, wherein the electrode includes a first anode 124a, a second anode, a third anode and a cathode electrode 17b.
  • the first anode 124a, the second anode and the third anode are called anode electrodes.
  • the electrodes are formed through a patterning process.
  • the first anode 124a is arranged corresponding to the first sub-pixel light-emitting functional layer 12a
  • the second anode is arranged corresponding to the second sub-pixel light-emitting functional layer 12b
  • the third anode is arranged corresponding to the third sub-pixel light-emitting functional layer 12c
  • the cathode electrode 17b and The cathode metal 17a forms the common cathode layer 17.
  • M305 Thinning the first substrate 31.
  • the thickness of the first substrate 31 is reduced to 60 ⁇ m to 200 ⁇ m.
  • the shape of the chip structure 10 formed after thinning the first substrate 31 is close to a cube, which makes the chip structure 10 more stable and facilitates the use of subsequent processes. Using a thicker first substrate 31 during the preparation of the chip structure 10 is beneficial to the processing of the chip structure 10 .
  • a plurality of sub-pixel light-emitting functional layers 12 are disposed on the first substrate. 31 on the first side.
  • the first sub-pixel light-emitting functional layer 12a of the chip wafer unit 11 includes a first quantum well 121a stacked along the first direction X, a first p-type gallium nitride 122a, a first A reflective part 123a, a first bonding part 19a and a first anode 124a;
  • the second sub-pixel light-emitting functional layer 12b (not shown in the figure) includes a second quantum well and a second p-type layer stacked along the first direction X.
  • the third sub-pixel light-emitting functional layer 12c (not shown in the figure) includes a third quantum well stacked along the first direction X, a third Three p-type gallium nitride, the third reflective part 123c, the third bonding part and the third anode.
  • the common cathode layer 17 includes a cathode metal 17a and a cathode electrode 17b that are stacked along the first direction X.
  • the first direction X is the direction from the color conversion layer substrate unit 2 to the chip wafer unit 1 .
  • the third sub-metal layer 133 is a conductive layer connecting the first n-type gallium nitride 16a, the second n-type gallium nitride 16b, the third n-type gallium nitride 16c and the fourth n-type gallium nitride 16d. That is to say, the third sub-metal layer 133 has the function of connecting the first sub-pixel light-emitting functional layer 12a, the second sub-pixel light-emitting functional layer 12b, the third sub-pixel light-emitting functional layer 12c and the common cathode layer 17.
  • the red light external quantum efficiency of the chip structure 10 formed in this embodiment is increased to 10% to 20%.
  • the chip structure 10 of this embodiment connects the chip wafer unit 11 and the color conversion layer substrate unit 21 through the metal wafer bonding effect of the first bonding layer 13.
  • the first bonding layer 13 is made of metal material, and the metal material has high The refractive index can prevent the light emitted from the sub-pixel light-emitting functional layer 12 from light leakage and cross-color effects, and improve the light extraction effect of the chip structure 10.
  • the following describes a second embodiment of a method for manufacturing the chip structure 10 .
  • the chip structure 10 formed according to this embodiment is the chip structure 10 shown in FIG. 5 .
  • Figure 29 shows the preparation steps of the initial chip wafer unit 110, including T101 to T107.
  • an initial gallium nitride buffer layer 150, an initial n-type gallium nitride layer 160, an initial quantum well layer 1210 and an initial P-type nitride layer are sequentially formed on one side of the second substrate 14.
  • step S101 For specific steps, please refer to step S101, which will not be described again here.
  • T102 As shown in FIG. 9a and FIG. 9b, a preliminary first insulating layer 18a is formed, and a plurality of via holes H are provided on the preliminary first insulating layer 18a.
  • step S102 For specific steps, please refer to step S102, which will not be described again here.
  • T103 As shown in Figure 10, the second bonding layer 19 is formed.
  • step S103 For specific steps, please refer to step S103, which will not be described again here.
  • T104 Remove the second substrate 14.
  • the structure of an initial chip wafer unit 110 after removing the second substrate 14 is shown in FIG. 13 .
  • step S104 For specific steps, please refer to step S104, which will not be described again here.
  • T105 As shown in Figure 30, a patterned gallium nitride buffer layer 15, an n-type gallium nitride layer 16 and a first insulating layer 18 are formed.
  • the initial gallium nitride buffer layer 150, the initial n-type gallium nitride layer 160, and the preliminary first insulating layer 18a are processed through a photolithography process to form the patterned gallium nitride buffer layer 15 and the n-type gallium nitride layer 16. and first insulating layer 18.
  • T106 As shown in FIG. 31a, a patterned first initial sub-metal layer 1310 and a second initial sub-metal layer 1320 are formed on the side of the gallium nitride buffer layer 15 away from the temporary substrate 20.
  • step S106 Regarding the steps of forming the first initial sub-metal layer 1310 and the second initial sub-metal layer 1320, please refer to step S106 and will not be described again here.
  • the stacked gallium nitride buffer layer 15 and the n-type gallium nitride layer 16 are provided with a first sub-opening area K11, a second sub-opening area K21 and a third sub-opening area. K31.
  • the first sub-opening area K11 is provided correspondingly to the first sub-pixel light-emitting functional layer 12a
  • the second sub-opening area K21 is provided correspondingly to the second sub-pixel light-emitting functional layer 12b
  • the third sub-opening area K31 is provided corresponding to the third sub-pixel light-emitting functional layer. 12c corresponding settings.
  • Fig. 31a is a cross-sectional view taken along the II section line of Fig. 31b.
  • T107 As shown in FIG. 32 , the surface of the gallium nitride buffer layer 15 is roughened to form the initial chip wafer unit 110 .
  • a strong alkali of 70° C. to 80° C. is used to roughen the surface of the gallium nitride buffer layer 15 , and a plurality of first-type micro-protrusion structures 15t are formed on the exposed surface of the gallium nitride buffer layer 15 .
  • the first type of micro-protrusion structure 15t can make light easily emitted and improve the light extraction efficiency of the chip structure 10 .
  • the area of the gallium nitride buffer layer 15 corresponding to the first sub-pixel light-emitting functional layer 12a, the second sub-pixel light-emitting functional layer 12b and the third sub-pixel light-emitting functional layer 12c is the first area S1
  • the surface of the first area S1 is also That is, in this step, the surface of the gallium nitride buffer layer 15 is exposed in the area corresponding to the first sub-opening area K11, the second sub-opening area K21, and the third sub-opening area K31.
  • a plurality of first-type micro-protrusion structures 15t are formed on the surface of the first area S1.
  • the remaining portion of the gallium nitride buffer layer 15 except the first region S1 is the second region S2.
  • the first initial sub-metal layer 1310 is formed on the surface of the second region S2 of the gallium nitride buffer layer 15.
  • the preparation steps of the initial color conversion layer substrate unit 210 can refer to the above-mentioned steps R201 to R205. No further details will be given here.
  • the chip structure 10 formed in this embodiment is shown in Figure 5.
  • the chip wafer unit 10 also includes an n-type gallium nitride layer 16 and a gallium nitride buffer layer 15 stacked along a second direction.
  • the second direction is formed by the chip wafer.
  • the circular unit 11 points in the direction of the color conversion layer substrate unit 21. It can be understood that the second direction is parallel to the direction in which the light exit side G points.
  • the n-type gallium nitride layer 16 is connected to the first quantum well 121a, the second quantum well, the third quantum well and the cathode metal 17a. That is to say, the n-type gallium nitride layer 16 has a connection with the first quantum well 121a, the second quantum well, the third quantum well and the cathode metal 17a.
  • the red light external quantum efficiency of the chip structure 10 formed in this embodiment is increased to 10% to 20%.
  • the chip structure 10 of this embodiment connects the chip wafer unit 11 and the color conversion layer substrate unit 21 through the metal wafer bonding effect of the first bonding layer 13.
  • the first bonding layer 13 is made of metal material, and the metal material has high The refractive index can prevent the light emitted from the sub-pixel light-emitting functional layer 12 from light leakage and cross-color effects, and improve the light extraction effect of the chip structure 10.
  • the first bonding layer 13 in this embodiment only has a connection function, and the n-type gallium nitride layer 16 is used to connect the first sub-pixel light-emitting function layer 12a, the second sub-pixel light-emitting function layer 12b, and the third sub-pixel light-emitting function layer.
  • the conductive layer of layer 12c and common cathode layer 17 can reduce resistance.
  • the chip structure 10 formed according to this embodiment is the chip structure 10 shown in FIG. 6a.
  • Figure 33 shows the preparation steps of the initial chip wafer unit 110, including N101 to N109.
  • an initial gallium nitride buffer layer 150, an initial n-type gallium nitride layer 160, an initial quantum well layer 1210 and an initial P-type nitride layer are sequentially formed on one side of the second substrate 14.
  • step S101 For specific steps, please refer to step S101, which will not be described again here.
  • a patterned photoresist is made through photolithography and waterproofing, the material to form the cathode metal 17a is evaporated, and the cathode metal 17a is patterned.
  • the material of the cathode metal 17a may be any one of titanium, aluminum, nickel, and gold.
  • N103 As shown in Figure 35, a preliminary second insulation layer 40a is formed, and multiple via holes are provided on the preliminary second insulation layer 40a.
  • step M303 For specific steps, please refer to the content of step M303, which will not be described again here.
  • N104 As shown in FIG. 36, an electrode is formed, wherein the electrode includes a first anode 124a, a second anode, a third anode, and a cathode electrode 17b.
  • step M304 For specific steps, please refer to the content of step M304, which will not be described again here.
  • N105 As shown in Figure 37, bond the temporary substrate 20 on the side of the electrode away from the second substrate 14.
  • temporary bonding glue is used to bond the temporary substrate 20
  • the temporary bonding glue can be an acrylic thermoplastic glue.
  • N106 As shown in Figure 38, remove the second substrate 14.
  • step S104 For specific steps, please refer to step S104, which will not be described again here.
  • N107 As shown in Figure 39, the patterned gallium nitride buffer layer 15, the n-type gallium nitride layer 16 and the second insulating layer 40 are formed.
  • the initial gallium nitride buffer layer 150, the initial n-type gallium nitride layer 160, and the preliminary second insulating layer 40a are processed through a photolithography process to form the patterned gallium nitride buffer layer 15 and the n-type gallium nitride layer 16. and second insulating layer 40.
  • a patterned first initial sub-metal layer 1310 and a second initial sub-metal layer 1320 are formed on the side of the gallium nitride buffer layer 15 away from the temporary substrate 20 .
  • step T106 For specific steps, please refer to step T106, which will not be described again here.
  • N109 As shown in Figure 41, the surface of the gallium nitride buffer layer 15 is roughened to form the initial chip wafer unit 110.
  • step T107 For specific steps, please refer to step T107, which will not be described again here.
  • the preparation steps of the initial color conversion layer substrate unit 210 can refer to the above-mentioned steps R201 to R205. No further details will be given here.
  • the steps of forming the chip structure 10 from the initial chip wafer unit 110 and the initial color conversion layer substrate unit 210 prepared by the above steps, as shown in Figure 42, include V301 to V304.
  • V301 As shown in Figure 43, the initial chip wafer unit 110 and the initial color conversion layer substrate unit 210 are bonded through metal wafer bonding technology.
  • step M301 For specific steps, please refer to step M301, which will not be described again here.
  • V302 Remove temporary substrate 20.
  • the temporary bonding glue on the temporary substrate 20 is debonded through ultraviolet laser irradiation, and the temporary substrate 20 and the temporary bonding glue are removed.
  • V303 Thinning the first substrate 31.
  • step M305 For specific steps, please refer to step M305, which will not be described again here.
  • V304 Cut to obtain chip structure 10.
  • step M306 For specific steps, please refer to step M306, which will not be described again here.
  • the red light external quantum efficiency of the chip structure 10 formed in this embodiment is increased to 10% to 20%.
  • the chip structure 10 of this embodiment connects the chip wafer unit 11 and the color conversion layer substrate unit 21 through the metal wafer bonding effect of the first bonding layer 13.
  • the first bonding layer 13 is made of metal material, and the metal material has high The refractive index can prevent the light emitted from the sub-pixel light-emitting functional layer 12 from light leakage and cross-color effects, and improve the light extraction effect of the chip structure 10.
  • the first bonding layer 13 in this embodiment only has a connection function, and the n-type gallium nitride layer 16 is used to connect the first sub-pixel light-emitting function layer 12a, the second sub-pixel light-emitting function layer 12b, and the third sub-pixel light-emitting function layer.
  • the layer 12c and the conductive layer of the common cathode layer 17 use any material among titanium, aluminum, nickel and gold as the cathode metal 17a of the common cathode layer 17, so that the resistance can be reduced.
  • the first bonding layer 13 includes a first sub-bonding layer 135 and a second sub-bonding layer 136 arranged in a stack.
  • the material of the first sub-bonding layer 135 and the second sub-bonding layer 136 is indium zinc oxide.
  • the thickness d3 of the first bonding layer 13 formed by the first sub-bonding layer 135 and the second sub-bonding layer 136 ranges from 200 nm to 1200 nm.
  • the thickness d3 of the first bonding layer 13 is 200 nm. 400nm, 600nm, 800nm or 1200nm, etc., there is no limit here.
  • the display substrate 100 includes a plurality of chip structures 10 as described in any of the above embodiments.
  • the display substrate 100 includes a driving backplane.
  • the driving backplane includes a circuit layer.
  • a plurality of chip structures 10 are disposed on the driving backplane.
  • the circuit layer includes, for example, a plurality of pad groups. Each pad group includes A plurality of separately arranged bonding pads, the cathode electrode 17b, the first anode 124a, the second anode and the third anode of each chip structure 10 are respectively electrically connected to one of the plurality of bonding pads.
  • multiple chip structures 10 are transferred to the driving backplane through mass transfer technology.
  • Some embodiments of the present disclosure also provide a display device 1000, as shown in FIG. 44, including the display substrate 100 as described above.
  • the display device may be any device that displays text or images, whether moving (eg, video) or fixed (eg, still images). More specifically, it is contemplated that the embodiments may be implemented in or in association with a variety of electronic devices, such as, but not limited to, mobile phones, wireless devices, personal data assistants (PDAs) , handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer display, etc.), navigator, cockpit controller and/or display, camera view display (e.g. display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, building structures, packaging and aesthetic structure (for example, for the display of an image of a piece of jewelry), etc.
  • PDAs personal data assistants
  • handheld or portable computers GPS receivers/navigators
  • MP4 video players camcorders

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Abstract

一种芯片结构、芯片制备方法以及采用其的显示基板和显示装置，芯片结构包括：芯片晶圆单元和设置于芯片晶圆单元出光侧的色转换层基板单元，其中，芯片晶圆单元包括多个子像素发光功能层；色转换层基板单元包括设置于芯片晶圆单元出光侧的色转换层；芯片晶圆单元还包括：第一键合层，设置于子像素发光功能层和色转换层之间，用于键合芯片晶圆单元和色转换层基板单元。

Description

芯片结构、芯片制备方法、显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种芯片结构、芯片制备方法、显示基板和显示装置。
背景技术
Micro-LED(微型发光二极管)显示器件是新一代显示技术，具有高亮度，高发光效率，低功耗，响应速度快等优点。然而在将Micro-LED应用于显示装置时，还存在批量转移问题、产品良率等问题。
发明内容
一方面，提供一种芯片结构，芯片结构包括：芯片晶圆单元和设置于所述芯片晶圆单元出光侧的色转换层基板单元。其中，所述芯片晶圆单元包括多个子像素发光功能层。所述色转换层基板单元包括设置于所述芯片晶圆单元出光侧的色转换层。
所述芯片晶圆单元还包括：第一键合层，设置于所述子像素发光功能层和所述色转换层之间，用于键合所述芯片晶圆单元和所述色转换层基板单元。
在一些实施例中，所述第一键合层包括层叠设置的第一子金属层、第二子金属层和第三子金属层。所述第三子金属层比所述第一子金属层靠近所述色转换层基板单元，所述第二子金属层设置为连接所述第一子金属层和所述第三子金属层的共晶合金层。
在一些实施例中，所述第一键合层包括层叠设置的第一子键合层和第二子键合层。所述第一子键合层和所述第二子键合层的材料为氧化铟锌。
在一些实施例中，所述芯片晶圆单元包括第一子像素发光功能层、第二子像素发光功能层和第三子像素发光功能层。所述第一键合层包括与所述第一子像素发光功能层对应的第一开口区、与所述第二子像素发光功能层对应的第二开口区和与所述第三子像素发光功能层对应的第三开口区。
在一些实施例中，所述芯片晶圆单元还包括公共阴极层。所述第一子像素发光功能层包括沿第一方向层叠设置的第一量子阱、第一p型氮化镓和第一阳极。所述第二子像素发光功能层包括沿第一方向层叠设置的第二量子阱、第二p型氮化镓和第二阳极。所述第三子像素发光功能层包括沿第一方向层叠设置的第三量子阱、第三p型氮化镓和第三阳极。所述公共阴极层包括沿第一方向层叠设置的阴极金属和阴极电极。其中，所述第一方向为由所述色转换层基板单元指向所述芯片晶圆单元的方向。
在一些实施例中，所述公共阴极层的阴极金属材料包括钛、铝、镍和金中的任一种。
在一些实施例中，所述芯片晶圆单元还包括第二键合层，所述第二键合层包括第一键合部、第二键合部、第三键合部和第四键合部。所述第一键合部叠设于所述第一p型氮化镓和所述第一阳极之间，所述第二键合部叠设于所述第二p型氮化镓和所述第二阳极之间，所述第三键合部叠设于所述第三p型氮化镓和所述第三阳极之间，所述公共阴极层的阴极金属包括所述第四键合部。
在一些实施例中，所述第二键合层包括层叠设置的第四子金属层、第五子金属层和第六子金属层。所述第六子金属层比所述第四子金属层远离所述色转换层基板，所述第五子金属层设置为连接所述第六子金属层和所述第四子金属层的共晶合金层。
在一些实施例中，所述芯片晶圆单元还包括第二键合层，所述第一键合层包括层叠设置的第一子金属层、第二子金属层和第三子金属层，所述第一键合层的最大厚度的厚度范围，等于所述第二键合层的厚度范围。或者，所述第一键合层包括层叠设置的第一子键合层和第二子键合层，所述第一键合层的厚度范围，小于所述第二键合层的厚度范围。
在一些实施例中，所述芯片晶圆单元还包括第二键合层，所述第一键合层包括层叠设置的第一子金属层、第二子金属层和第三子金属层，所述第一键合层的最大厚度的厚度的范围为3μm～6μm。所述第一键合层包括层叠设置的第一子键合层和第二子键合层，所述第一键合层的厚度范围为200nm～1200nm。所述第二键合层的厚度范围为3μm～6μm。
在一些实施例中，所述第一键合层包括层叠设置的第一子金属层、第二子金属层和第三子金属层。所述第二子金属层为熔融温度小于240℃的共晶合金层。
在一些实施例中，所述芯片晶圆单元还包括沿第二方向层叠设置的n型氮化镓导电层和氮化镓缓冲层，所述第二方向为由所述芯片晶圆单元指向所述色转换层基板单元的方向。所述n型氮化镓导电层与所述第一量子阱、所述第二量子阱、所述第三量子阱及所述阴极金属连接。所述氮化镓缓冲层对应所述第一子像素发光功能层、所述第二子像素发光功能层和所述第三子像素发光功能层的区域为第一区域，所述第一区域朝向所述色转换层基板的一侧设置有多个第一类微凸起结构；所述氮化镓缓冲层不包括所述第一区域的部分为第二区域，所述第一键合层位于所述第二区域的所述氮化镓缓冲层朝 向所述色转换层基板的一侧。
在一些实施例中，所述芯片晶圆单元还包括n型氮化镓导电层，所述n型氮化镓导电层包括第一n型氮化镓、第二n型氮化镓、第三n型氮化镓和第四n型氮化镓。所述第一n型氮化镓叠设于所述第一量子阱远离所述第一p型氮化镓的一侧，所述第二n型氮化镓叠设于所述第二量子阱远离所述第二p型氮化镓的一侧，所述第三n型氮化镓叠设于所述第三量子阱远离所述第三p型氮化镓的一侧，所述第四n型氮化镓叠设于所述第四键合区朝向所述色转换层基板的一侧，所述第一键合层设置于所述n型氮化镓导电层朝向所述色转换层基板单元的一侧。
在一些实施例中，层叠设置的所述第一子金属层和所述第二子金属层包括设置有所述第一开口区的第一区、设置有所述第二开口区的第二区、设置有所述第三开口区的第三区和覆盖所述公共阴极层的第四区，所述第三子金属层覆盖所述第一区、所述第二区、所述第三区及所述第四区的所述第二子金属层，且所述第三子金属层被配置为连通所述第一n型氮化镓、所述第二n型氮化镓、所述第三n型氮化镓和所述第四n型氮化镓的导电层。
在一些实施例中，所述n型氮化镓导电层对应所述第一子像素发光功能层、所述第二子像素发光功能层和所述第三子像素发光功能层的区域为第三区域，所述第三区域朝向所述色转换层基板单元的一侧设置有多个第二类微凸起结构。
在一些实施例中，所述芯片晶圆单元还包括反射金属层，所述反射金属层包括第一反射部、第二反射部和第三反射部，所述第一反射部叠设于所述第一p型氮化镓和所述第一阳极之间，所述第二反射部叠设于所述第二p型氮化镓和所述第二阳极之间，所述第三反射部叠设于所述第三p型氮化镓和所述第三阳极之间。
在一些实施例中，所述芯片晶圆单元包括第二键合层，所述第二键合层包括第一键合部、第二键合部、第三键合部和第四键合部，所述第一反射部叠设于所述第一键合部朝向所述色转换层基板单元的一侧，所述第二反射部叠设于所述第二键合部朝向所述色转换层基板单元的一侧，所述第三反射部叠设于所述第三键合部朝向所述色转换层基板单元的一侧。
在一些实施例中，所述第二键合层朝向所述色转换层基板单元的一侧设置有绝缘层，所述绝缘层上设置有第一过孔、第二过孔、第三过孔和第四过孔，所述第一键合部的第四子金属层填充所述第一过孔与所述第一反射部连接，所述第二键合部的第四子金属层填充所述第二过孔与所述第二反射部连 接，所述第三键合部的第四子金属层填充所述第三过孔与所述第三反射部连接，所述第四键合部的第四子金属层填充所述第四过孔与所述n型氮化镓导电层连接。
在一些实施例中，所述芯片晶圆单元包括第一子像素发光功能层、第二子像素发光功能层和第三子像素发光功能层，所述色转换层包括限定坝层，以及由所述限定坝层限定的第四开口区、第五开口区和第六开口区。所述第四开口区设置有与所述第一子像素发光功能层对应的第一量子点转换部，所述第五开口区设置有与所述第二子像素发光功能层对应的散射粒子部，所述第六开口区设置有与所述第三子像素发光功能层对应的散射粒子部。
在一些实施例中，所述第四开口区在所述色转换层基板单元的正投影覆盖所述第一子像素发光功能层在所述色转换层基板单元上的正投影，所述第五开口区在所述色转换层基板单元的正投影覆盖所述第二子像素发光功能层在所述色转换层基板单元上的正投影，所述第六开口区在所述色转换层基板单元的正投影覆盖所述第三子像素发光功能层在所述色转换层基板单元上的正投影。
在一些实施例中，所述色转换层基板单元还包括聚光层，所述聚光层设置于所述色转换层靠近所述芯片晶圆单元的一侧，所述聚光层包括与所述第一量子点转换部对应的第一聚光部，与所述散射粒子部对应的第二聚光部，以及与所述第三量子点转换部对应的第三聚光部。
在一些实施例中，所述色转换层基板单元还包括衬底和彩膜层，所述衬底、所述彩膜层和所述色转换层沿第二方向层叠设置，所述第二方向为由所述芯片晶圆单元指向所述色转换层基板单元的方向，所述彩膜层包括黑矩阵，以及由所述黑矩阵限定的与第一量子点转换部对应的第一滤光膜、与散射粒子部对应的第二滤光膜和与散射粒子部对应的第三滤光膜。
另一方面，提供一种显示基板，包括如上任一项实施例所述的芯片结构。
另一方面，提供一种芯片制备方法，芯片制备方法包括：形成初始芯片晶圆单元，所述初始芯片晶圆单元包括层叠设置的临时衬底、多个子像素发光功能层、第一初始子金属层和第二初始子金属层，其中，所述第二初始子金属层包括多个第一类金属凸点。
芯片制备方法还包括形成色转换层基板单元，所述色转换层基板单元包括层叠设置的色转换层和第一衬底，在所述色转换层远离所述第一衬底的一侧形成第三初始子金属层。键合所述第一初始子金属层、第二初始子金属层和所述第三初始子金属层，形成第一键合层。其中，所述第一键合层包括第 一子金属层、第二子金属层和第三子金属层，所述第二子金属层为连接所述第一子金属层和所述第三子金属层的共晶合金层。
芯片制备方法还包括剥离所述临时衬底，形成芯片晶圆单元，所述芯片晶圆单元和所述色转换层基板单元由所述第一键合层连接。
在一些实施例中，所述形成初始芯片晶圆单元的步骤包括：提供第二衬底，在所述第二衬底的一侧形成所述初始芯片晶圆单元，所述初始芯片晶圆单元包括多个初始子像素发光功能层和初始公共阴极层。所述形成初始芯片晶圆单元的步骤还包括：在所述初始芯片晶圆单元的所述多个初始子像素发光功能层和所述初始公共阴极层远离所述第二衬底的一侧形成所述临时衬底。所述形成初始芯片晶圆的步骤还包括：剥离所述第二衬底。
在一些实施例中，所述在所述第二衬底的一侧形成所述初始芯片晶圆单元，所述初始芯片晶圆单元包括多个初始子像素发光功能层和初始公共阴极层，在所述初始芯片晶圆单元的所述多个初始子像素发光功能层和所述初始公共阴极层远离所述第二衬底的一侧形成所述临时衬底的步骤包括：在所述第二衬底的一侧依次形成氮化镓缓冲层、n型氮化镓层、量子阱层和P型氮化镓层，并图案化所述量子阱层和P型氮化镓层，形成初始芯片晶圆单元的量子阱层和P型氮化镓层。
在所述P型氮化镓层远离所述量子阱层的一侧形成第一绝缘层，所述第一绝缘层上设置有多个过孔。在所述第一绝缘层远离所述第二衬底的一侧形成第四子初始金属层和第五子初始金属层；第四子初始金属层填充所述第一绝缘层上设置的多个过孔，所述第五子初始金属层包括多个第二类金属凸点。
提供临时衬底，在所述临时衬底的一侧形成所述初始芯片晶圆单元的第六子初始金属层。键合所述第六子初始金属层、第五子初始金属层和第四子初始金属层，形成第二键合层，所述第二键合层包括第四子金属层、第五子金属层和第六子金属层，所述第五子金属层设置为连接所述第六子金属层和所述第四子金属层的共晶合金层。
所述剥离所述第二衬底的步骤之后还包括以下步骤：去除所述氮化镓缓冲层，图案化所述n型氮化镓层和所述第一绝缘层。在每一个所述初始芯片晶圆单元的所述n型氮化镓层远离所述临时衬底的一侧形成所述第一初始子金属层和所述第二初始子金属层，并将所述n型氮化镓层的表面粗化，形成所述初始芯片晶圆单元。
或者，所述剥离所述第二衬底的步骤之后还包括以下步骤：图案化所述氮化镓缓冲层、n型氮化镓层和第一绝缘层。在所述初始芯片晶圆单元的所述 氮化镓缓冲层上形成第一初始子金属层和所述第二初始子金属层，并将所述氮化镓缓冲层的表面粗化，形成所述初始芯片晶圆单元。
所述剥离所述临时衬底，形成芯片晶圆单元的步骤包括：在每一个所述第二键合层远离所述色转换层基板单元的一侧形成第二绝缘层，所述第二绝缘层上设置有多个过孔。形成电极，所述电极包括阴极电极和阳极电极，所述阴极电极、所述阳极电极填充所述第二绝缘层上对应的所述多个过孔中的一个。将所述第一衬底减薄，形成所述芯片晶圆。
在一些实施例中，所述在所述第二衬底的一侧形成所述初始芯片晶圆单元，所述初始芯片晶圆单元包括多个初始子像素发光功能层和初始公共阴极层，在所述初始芯片晶圆单元的所述多个初始子像素发光功能层和所述初始公共阴极层远离所述第二衬底的一侧形成所述临时衬底的步骤包括：在所述第二衬底的一侧依次形成氮化镓缓冲层、n型氮化镓层、量子阱层和P型氮化镓层，并图案化所述量子阱层和P型氮化镓层，形成初始芯片晶圆单元的量子阱层和P型氮化镓层。
形成所述初始公共阴极层的阴极金属。在所述P型氮化镓层和所述阴极金属远离所述色转换层基板单元的一侧形成第二绝缘层，所述第二绝缘层上设置有多个过孔。形成电极，所述电极包括阴极电极和阳极电极，所述阴极电极、所述阳极电极填充所述第二绝缘层上对应的所述多个过孔中的一个。形成所述初始芯片晶圆单元的所述多个初始子像素发光功能层和初始公共阴极层。将所述多个子像素发光功能层和初始公共阴极层键合在临时衬底上。
所述剥离所述第二衬底的步骤之后还包括以下步骤：图案化所述氮化镓缓冲层、n型氮化镓层和第二绝缘层，在所述氮化镓缓冲层上形成第一初始子金属层和所述第二初始子金属层，并将所述氮化镓缓冲层的表面粗化，形成所述初始芯片晶圆单元。
又一方面，提供一种显示装置，包括如上所述的显示基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据本公开一些实施例所提供的显示基板的结构图；
图2为根据本公开一些实施例所提供的第一初始晶片A的结构图；
图3为根据本公开一些实施例所提供的第二初始晶片B的结构图；
图4为根据本公开一些实施例所提供的芯片结构的结构图；
图5为根据本公开一些实施例所提供的芯片结构的另一种结构图；
图6a为根据本公开一些实施例所提供的芯片结构的又一种结构图；
图6b为根据本公开一些实施例所提供的芯片结构的又一种结构图；
图7为根据本公开一些实施例所提供的初始芯片晶圆单元制备方法的流程图；
图8～图10为根据本公开一些实施例所提供的初始芯片晶圆单元制备方法的步骤图；
图11为根据本公开一些实施例所提供的金属晶圆键合技术的流程图；
图12为根据本公开一些实施例所提供的金属晶圆键合技术的步骤图；
图13～图16b为根据本公开一些实施例所提供的初始芯片晶圆单元制备方法的步骤图；
图17为根据本公开一些实施例所提供的初始色转换层基板单元制备方法的流程图；
图18a～22b为根据本公开一些实施例所提供的初始色转换层基板单元制备方法的步骤图；
图23为根据本公开一些实施例所提供的芯片制备方法中对盒工艺的流程图；
图24～图28为根据本公开一些实施例所提供的芯片制备方法中对盒工艺的步骤图；
图29为根据本公开一些实施例所提供的另一种初始芯片晶圆单元制备方法的流程图；
图30～图32为根据本公开一些实施例所提供的另一种初始芯片晶圆单元制备方法的步骤图；
图33为根据本公开一些实施例所提供的又一种初始芯片晶圆单元制备方法的流程图；
图34～图41为根据本公开一些实施例所提供的又一种初始芯片晶圆单元制备方法的步骤图；
图42为根据本公开一些实施例所提供的芯片制备方法中又一种对 盒工艺的流程图；
图43为根据本公开一些实施例所提供的芯片制备方法中又一种对盒工艺的步骤图；
图44为根据本公开一些实施例所提供的显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
目前的红光Micro-LED(Micrometer-sized Light Emitting Diodes,微型发光二极管)多由AlGaInP(红光半导体)材料制成，在正常芯片尺寸下，其效率达60％以上。然而，当芯片尺寸缩小到微米量级时，其效率会降低至1％以下。此外，在巨量转移制程上，AlGaInP材料的劣势也比较明显。巨量转移要求材 料具有良好的机械强度，以避免在芯片抓取和放置的过程中出现开裂，而AlGaInP材料较差的力学性能会给巨量转移增加难度。
基于此，本公开提供一种芯片结构10，如图4～图6b所示，芯片结构10包括芯片晶圆单元11和设置于芯片晶圆单元11出光侧G的色转换层基板单元21。芯片晶圆单元11包括多个子像素发光功能层12，色转换层基板单元21包括设置于芯片晶圆单元11出光侧G的色转换层22。芯片晶圆单元11还包括：第一键合层13，设置于子像素发光功能层12和色转换层22之间，用于键合芯片晶圆单元11和色转换层基板单元21。
如图4～图6b所示，芯片结构10包括芯片晶圆单元11和色转换层基板单元21，芯片晶圆单元11的多个子像素发光功能层12中的一个子像素发光功能层12被配置为出射多种颜色光中的一种，且多个子像素发光功能层12可以配置为发射相同颜色的光。色转换层基板单元21设置于所述芯片晶圆单元11的出光侧G，色转换层基板单元21对应每一个子像素发光功能层12的出光侧G均设置有色转换层22。
本公开通过第一键合层13的金属晶圆键合作用连接芯片晶圆单元11和色转换层基板单元21，第一键合层13采用金属材料，金属材料具有较高的折射率，可以防止子像素发光功能层12出射的光出现漏光和串色的作用，提高芯片结构10的出光效果。
通过第一键合层13的金属晶圆键合作用连接芯片晶圆单元11和色转换层基板单元21形成芯片结构10，制备方法包括：制备初始芯片晶圆单元110和初始色转换层基板单元210，然后通过金属晶圆键合技术键合初始芯片晶圆单元110和初始色转换层基板单元210，形成芯片结构10。为了更清楚的说明本技术方案，提供以下三种实施例。
需要说明的是，为了清楚的表示芯片结构10的制备方法，以下均以一个芯片结构10的形成为例描述，可以理解的是，本芯片结构10的制备方法是先形成包括阵列排布的多个芯片结构10的晶圆，然后通过切割该晶圆形成单个芯片结构10。
以下介绍芯片结构10的制备方法的第一种实施例，根据该实施例形成的芯片结构10为图4所示的芯片结构10。
实施例1
具体的，如图7所示为初始芯片晶圆单元110的制备步骤，包括S101～S107。
S101：如图8和图9a所示，在第二衬底14的一侧依次形成初始氮化镓 缓冲层150、初始n型氮化镓层160、初始量子阱层1210和初始P型氮化镓层1220，并图案化初始量子阱层1210和初始P型氮化镓层1220，形成初始芯片晶圆单元110的量子阱层121和P型氮化镓层122。
示例性的，第二衬底14可以为蓝宝石衬底或硅基衬底。
示例性的，量子阱层121可以为蓝色量子阱，由蓝色量子阱形成的子像素发光功能层12出射蓝光。
示例性的，通过光刻工艺图案化初始量子阱层1210和初始P型氮化镓层1220，去除相邻的子像素发光功能层12之间区域和负极区域S17的初始量子阱层1210和初始P型氮化镓层1220，其中，负极区域S17的介绍具体参见后续内容，此处不再赘述。
在一些示例中，如图9a和图9b所示，芯片晶圆单元11的多个子像素发光功能层12包括第一子像素发光功能层12a、第二子像素发光功能层12b和第三子像素发光功能层12c。本步骤形成了第一子像素发光功能层12a的第一量子阱121a和第一p型氮化镓122a，第二子像素发光功能层12b的第二量子阱、第二p型氮化镓，第三子像素发光功能层12c的第三量子阱、第三p型氮化镓。其中，图9a为图9b沿AA截面线得到的截面图。
在一些示例中，如图9a所示，P型氮化镓层122远离第二衬底14的一侧还叠设有初始反射金属层，图案化初始反射金属层，形成多个初始芯片晶圆单元110中的每一个初始芯片晶圆单元110的反射金属层123。
示例性的，通过沉积工艺沉积初始反射金属层。
示例性的，反射金属层123的材料可以采用ITO-Ag-ITO，反射金属层123具有反射光的作用，可以提高子像素发光功能层12的出光率。
示例性的，如图9b所示，反射金属层123包括第一反射部123a、第二反射部123b和第三反射部123c。第一子像素发光功能层12a包括第一反射部123a，第二子像素发光功能层12b包括第二反射部123b，第三子像素发光功能层12c包括第三反射部123c。
S102：如图9a和图9b所示，形成初步第一绝缘层18a，初步第一绝缘层18a上设置有多个过孔H。
示例性的，通过沉积工艺，在反射金属层123和初始n型氮化镓层160远离第二衬底14的一侧形成初始第一绝缘层，在初始第一绝缘层上通过光刻工艺形成多个过孔H，形成初步第一绝缘层18a。如图9b所示，多个过孔H包括第一过孔H1、第二过孔H2、第三过孔H3和第四过孔H4。第一过孔H1与第一子像素发光功能层12a对应设置，第二过孔H2与第二子像素发光功能 层12b对应设置，第三过孔H3与第三子像素发光功能层12c对应设置，第四过孔H4与负极区域S17对应设置。
S103：如图10所示，形成第二键合层19。
第二键合层19的一部分形成为公共阴极层17，且第二键合层19还具有键合初始芯片晶圆单元110的临时衬底20的作用。
示例性的，临时衬底20采用硅衬底。
示例性的，可以采用金属晶圆键合技术形成第二键合层19。金属晶圆键合技术是指，依靠两种不同的金属之间形成共晶合金以低于金属各自熔点的温度完全键合的技术。金属晶圆键合技术根据键合温度不同，可以分为固液互扩散键合技术和固态扩散键合技术。其中，固液互扩散键合技术对于膜层平整度的要求小于固态扩散键合技术。且固液互扩散键合技术键合强度高，键合时间短。因此，可以采用固液互扩散键合技术形成第二键合层19。
关于形成第二键合层19的步骤如图11所示，包括步骤S131～S133。
S131：如图12所示，在初步第一绝缘层18a远离第二衬底14的一侧形成图案化的第四子初始金属层1910和第五子初始金属层1920。
第四子初始金属层1910填充初步第一绝缘层18a上设置的多个过孔H，第五子初始金属层1920包括多个第二类金属凸点192a。
需要说明的是，在本申请中，“形成图案化的某个膜层”是指首先形成整层设置的初始膜层，再经过图案化处理(例如光刻工艺)将初始膜层形成图案化的某个膜层，该膜层具有特定图案，后续出现的相关描述均沿用该解释。示例性的，通过沉积工艺在初步第一绝缘层18a远离第二衬底14的一侧沉积整层的用于形成第四子初始金属层1910的材料，采用光刻工艺形成图案化的第四子初始金属层1910。第四子初始金属层1910的材料可以采用Au(金)、Ag(银)、Pb(铅)、Sn(锡)和Cu(铜)中的任一种。
示例性的，第五子初始金属层1920的第二类金属凸点192a的结构可以为圆柱形或圆锥形。在形成第二键合层19的过程中，第二类金属凸点会变成液态，与相邻的第四子初始金属层1910以及后续的第六子初始金属层1930形成共晶合金层。
第五子初始金属层1920的材料可以为In(铟)，Au(金)和In(铟)形成共晶合金的温度为160℃，Ag(银)和In(铟)形成共晶合金的温度为180℃，Pb(铅)和In(铟)形成共晶合金的温度为200℃，Sn(锡)和In(铟)形成共晶合金的温度为120℃。
另外，第五子初始金属层1920的材料还可以为Sn(锡)，Cu(铜)和 Sn(锡)形成共晶合金的温度为280℃，Au(金)和Sn(锡)形成共晶合金的温度为280℃，Ag(银)和Sn(锡)形成共晶合金的温度为250℃。
需要说明的是，上述内容并不是对第五子初始金属层1920材料的限制，第四子初始金属层1910的材料和第五子初始金属层1920的材料形成的共晶合金的熔融温度小于400℃即可。
示例性的，第五子初始金属层1920采用揭开-剥离(lift-off)工艺形成。例如，首先使用光刻胶在第四子初始金属层1910上形成倒梯形的阵列排布的凸起结构，然后蒸镀形成第五子初始金属层1920的材料(In或Sn)，形成第二类金属凸点192a的第五子初始金属层1920。
S132：如图12所示，在临时衬底20的一侧形成图案化的第六子初始金属层1930。
示例性的，通过沉积工艺在临时衬底20的一侧沉积整层的第六子初始金属层1930的材料，采用光刻工艺形成图案化的第六子初始金属层1930。第六子初始金属层1930的材料可以采用Au(金)、Ag(银)、Pb(铅)、Sn(锡)和Cu(铜)中的任一种。并且，第六子初始金属层1930的材料可以与第四子初始金属层1910的材料相同。
S133：如图12所示，键合第四子初始金属层1910、第五子初始金属层1920和第六子初始金属层1930，形成第二键合层19。
如图10所示，第二键合层19包括层叠设置的第四子金属层191、第五子金属层192和第六子金属层193，第五子金属层192为连接第四子金属层191和第六子金属层193的共晶合金层。从而达到将临时衬底20连接至初始芯片晶圆单元110的目的。
示例性的，通过固液互扩散键合技术实现第二键合层19包括第四子金属层191、第五子金属层192和第六子金属层193的键合，关于固液互扩散键合技术的介绍见上述内容，此处不再赘述。
示例性的，如图10所示，第二键合层19包括第一键合部19a、第二键合部、第三键合部和第四键合部19d。公共阴极层17的阴极金属17a包括第四键合部19d。即第二键合层19位于图9a所示的负极区域S17的部分为第四键合部19d。
结合图9a、图9b和图10所示，第一键合部19a的第四子金属层191填充第一过孔H1与第一反射部123a连接，第二键合部的第四子金属层191填充第二过孔H2与第二反射部123b连接，第三键合部的第四子金属层填充191第三过孔H3与第三反射部123c连接，第四键合部19d的第四子金属层191 填充第四过孔H4与初始n型氮化镓层160连接。其中，第一过孔H1、第二过孔H2、第三过孔H3和第四过孔H4、及第一反射部123a、第二反射部123b和第三反射部123c的位置参照图9b所示。
示例性的，如图10所示，第二键合层19的厚度d1范围为3μm～6μm。例如，第二键合层19的厚度d1为3μm、4μm、5μm或6μm等，此处并不设限。
通过第二键合层19形成设置有临时衬底20的初始芯片晶圆单元110后，进行以下步骤。
S104：去除第二衬底14。去除第二衬底14后的一个初始芯片晶圆单元110的结构如图13所示。
示例性的，采用防酸膜或蜡封的方式保护临时衬底20，将初始芯片晶圆单元110放置在氢氟酸(HF)刻蚀槽中，通过刻蚀去除第二衬底14。
S105：去除初始氮化镓缓冲层150，形成图案化的n型氮化镓层16和第一绝缘层18，结构如图14a所示。
示例性的，通过光刻工艺图案化初始n型氮化镓层160，形成图案化的n型氮化镓层16。通过光刻工艺图案化初步第一绝缘层18a，形成图案化的第一绝缘层18。
示例性的，如图14b所示，n型氮化镓层16包括第一n型氮化镓16a、第二n型氮化镓16b、第三n型氮化镓16c和第四n型氮化镓16d。第一n型氮化镓16a与第一子像素发光功能层12a对应设置，第二n型氮化镓16b与第二子像素发光功能层12b对应设置，第三n型氮化镓16c与第三子像素发光功能层12c对应设置，第四n型氮化镓16d与公共阴极层17对应设置。其中，图14a为图14b沿BB截面线得到的截面图。
S106：如图15a所示，在n型氮化镓层16远离临时衬底20的一侧形成图案化的第一初始子金属层1310和第二初始子金属层1320。
第一初始子金属层1310和第二初始子金属层1320用于形成键合芯片晶圆单元11和色转换层基板单元21的第一键合层13，具体参见后续内容介绍。
示例性的，通过沉积工艺在n型氮化镓层16远离临时衬底20的一侧沉积整层的用于形成第一初始子金属层1310的材料，采用光刻工艺形成图案化的第一初始子金属层1310。第一初始子金属层1310的材料可以采用Au(金)、Ag(银)、Pb(铅)和Sn(锡)中的任一种。
如图15b所示，图案化的第一初始子金属层1310包括第一区13a、第二区13b、第三区13c和第四区13d，第一区13a、第二区13b、第三区13c和第 四区13d分离设置。第一子像素发光功能层12a位于第一发光区F1内，第一区13a与第一发光区F1对应设置；第二子像素发光功能层12b位于第二发光区F2内，第二区13b与第二发光区F2对应设置；第三子像素发光功能层12c位于第三发光区F3内，第三区13c与第三发光区F3对应设置；公共阴极层17位于负极区域S17内，第四区13d与负极区域S17对应设置。其中，图15a为图15b沿CC截面线得到的截面图。
第一初始子金属层1310的第一区13a包括第一子开口区K11、第二区13b包括第二子开口区K21、第三区13c包括第三子开口区K31。
示例性的，第二初始子金属层1320包括多个第一类金属凸点132a，第一类金属凸点132a的结构可以为圆柱形或圆锥形。
第二初始子金属层1320的材料可以为In(铟)，Au(金)和In(铟)形成共晶合金的温度为160℃，Ag(银)和In(铟)形成共晶合金的温度为180℃，Pb(铅)和In(铟)形成共晶合金的温度为200℃，Sn(锡)和In(铟)形成共晶合金的温度为120℃。
需要说明的是，上述内容并不是对第二初始子金属层1320材料的限制，第一初始子金属层1310和第二初始子金属层1320形成共晶合金层时，需要形成的共晶合金的熔融温度小于240℃，如果共晶合金层的熔融温度过高，会对色转换层基板单元21中的色转换层22造成破坏。
示例性的，第二初始子金属层1320的形成工艺可以参照上述第五子初始金属层1920的形成工艺，此处不再赘述。
S107：如图16a所示，将n型氮化镓层16表面进行粗化，形成初始芯片晶圆单元110。
示例性的，使用70℃～80℃的强碱使得n型氮化镓层16表面粗化，在暴露的n型氮化镓层16表面形成多个第二类微凸起结构16t。第二类微凸起结构16t可以使得光线易于出射，提高芯片结构10的出光效率。
如图16b所示，第一初始子金属层1310的第一区13a包括第一子开口区K11、第二区13b包括第二子开口区K21、第三区13c包括第三子开口区K31，第一子开口区K11暴露出来的第一n型氮化镓16a、第二子开口区K21暴露出来的第二n型氮化镓16b及第三子开口区K31暴露出来的第三n型氮化镓16c的表面由于强碱的作用，形成多个第二类微凸起结构16t。其中，图16a为图16b沿DD截面线得到的截面图。
其中，n型氮化镓层16对应第一子像素发光功能层12a、第二子像素发光功能层12b和第三子像素发光功能层12c的区域为第三区域S3，第三区域 S3也就是n型氮化镓层16在此步骤中暴露出来对应第一子开口区K11、第二子开口区K21和第三子开口区K31的区域。
在初始芯片晶圆单元110制备过程中，是同步形成包括多个阵列排布的初始芯片晶圆单元110的大板，对大板进行切割，例如进行异形切割，形成多个第一初始晶片A，如图2所示，第一初始晶片A为圆形，第一初始晶片A包括多个初始芯片晶圆单元110。示例性的，第一初始晶片A的尺寸为4寸或者6寸。
以下介绍初始色转换层基板单元210的制备步骤，如图17所示，包括步骤R201～R205。
R201：如图18a所示，在第一衬底31上形成黑矩阵层23、彩膜层24和限定坝层25。
示例性的，第一衬底31可以为玻璃衬底。
示例性的，采用涂覆、曝光、显影、后烘等方式形成黑矩阵层23，以及由黑矩阵层23限定的多个彩膜层24。例如，如图18b所示，多个彩膜层24包括第一滤光膜241、第二滤光膜242和第三滤光膜243。例如，第一滤光膜241为红色滤光膜，第二滤光膜242为蓝色滤光膜，第三滤光膜243为绿色滤光膜。其中，图18a为图18b沿EE截面线得到的截面图。
示例性的，如图18a所示，在黑矩阵层23远离第一衬底31的一侧采用涂覆、曝光、显影、后烘等方式形成限定坝层25，限定坝层25上限定有多个开口区K。例如，如图18b所示，多个开口区K包括第四开口区K4，第五开口区K5和第六开口区K6。
R202：如图19a所示，形成色转换层22。
示例性的，如图19b所示，在第四开口区K4、第五开口区K5和第六开口区K6采用涂覆、曝光、显影、后烘等方式或喷墨打印的方式制作色转换层22。其中，第四开口区K4内形成第一量子点转换部22a，第一量子点转换部22a采用红色量子点发光材料；第五开口区K5内形成散射粒子部22b，设置散射粒子；第六开口区K6内形成第三量子点转换部22c，第三量子点转换部22c采用绿色量子点发光材料。其中，图19a为图19b沿FF截面线得到的截面图。
并且，结合图4和图19b所示，第四开口区K4在色转换层基板单元2的正投影覆盖第一子像素发光功能层12a在色转换层基板单元2上的正投影。
同理，第五开口区K5在色转换层基板单元2的正投影覆盖第二子像素发光功能层12b在色转换层基板单元2上的正投影，第六开口区K6在色转换层 基板单元2的正投影覆盖第三子像素发光功能层12c在色转换层基板单元2上的正投影。这样设置可以提高芯片结构10的出光效果。
R203：如图20所示，形成无机封装层26。
示例性的，采用CVD(化学气相沉积)方式在色转换层22远离第一衬底31的一侧沉积无机封装层26，无机封装层26覆盖色转换层22和限定坝层25。
R204：如图21a所示，在无机封装层26远离第一衬底31的一侧形成图案化的第三初始子金属层1330。
示例性的，通过沉积工艺在无机封装层26远离第一衬底31的一侧沉积整层的用于形成第三初始子金属层1330的材料，采用光刻工艺形成图案化的第三初始子金属层1330。第三初始子金属层1330的材料可以采用Au(金)、Ag(银)、Pb(铅)和Sn(锡)中的任一种。第三初始子金属层1330的材料可以与第一初始子金属层1310的材料相同。
如图21b所示，图案化的第三初始子金属层1330设置有多个开口区K。例如，如图21b所示，多个开口区K包括第四子开口区K14，第五子开口区K25和第六子开口区K36。第四子开口区K14与第一量子点转换部22a对应设置，第五子开口区K25与散射粒子部22b对应设置，第六子开口区K36与第三量子点转换部22c对应设置。其中，图21a为图21b沿GG截面线得到的截面图。
R205：如图22a所示，制作聚光层27，形成初始色转换层基板单元210。
示例性的，如图22b所示，聚光层27包括与第一量子点转换部22a对应的第一聚光部27a，与散射粒子部22b对应的第二聚光部27b，以及与第三量子点转换部22c对应的第三聚光部27c。其中，图22a为图22b沿HH截面线得到的截面图。
聚光层27的材料采用丙烯酸酯类或者环氧类材料，聚光层27具有聚光的作用，可以提高芯片结构10的出光效果。
在初始色转换层基板单元210制备的过程中，是同步形成包括多个阵列排布的初始色转换层基板单元210的大板。对大板进行切割，例如进行异形切割，形成多个第二初始晶片B，如图3所示，第二初始晶片B为圆形，第二初始晶片B包括多个初始色转换层基板单元210。第二初始晶片B与第一初始晶片A尺寸相同。
以下介绍由第一初始晶片A和第二初始晶片B对盒，最终形成单个芯片结构10的步骤。如图23所示，包括步骤M301～M306。需要说明的是，以下均以一个芯片结构10的形成为例表示。
M301：如图24和图25所示，通过金属晶圆键合技术键合初始芯片晶圆单元110和初始色转换层基板单元210。键合后的初始色转换层基板单元210形成色转换层基板单元21。
其中，如图24所示，初始芯片晶圆单元110和初始色转换层基板单元210相键合。第一量子点转换部22a与第一子像素发光功能层12a位置对应，散射粒子部22b与第二子像素发光功能层12b位置对应，第三量子点转换部22c与第三子像素发光功能层12c位置对应。
在形成第一键合层13的过程中，第一类金属凸点132a会变成液态，采用金属凸点的结构形成的第二子初始金属层1320在融化成液态时，不会进入发光区域，发光区域包括第一发光区F1、第二发光区F2和第三发光区F3，从而避免第一键合层13影响发光。
示例性的，如图25所示，形成的第一键合层13包括层叠设置的第一子金属层131、第二子金属层132和第三子金属层133。第一键合层13的最大厚度的厚度d2范围为3μm～6μm。例如，第一键合层13的厚度d2为3μm、4μm、5μm或6μm等，此处并不设限。
需要说明的是，如图25所示，当第一键合层13包括第一子金属层131、第二子金属层132和第三子金属层133三层时，由于第一子金属层131、第二子金属层132和第三子金属层133具有图案，因此第一键合层13在各位置处的厚度并不相等，例如在图25中的T区域，第一键合层13仅包括第三子金属层133，本公开中提到的第一键合层13的最大厚度的厚度d2是指，第一键合层13所包括的三个子金属层堆叠位置处的厚度。
示例性的，如图24和图25所示，远离第二初始子金属层1320的第三初始子金属层1330形成第三子金属层133，远离第二初始子金属层1320的第一初始子金属层1310形成第一子金属层131。第三子金属层133比第一子金属层131靠近色转换层基板单元21。也就是说，第一子金属层131比第三子金属层133靠近子像素发光功能层12的出光侧G。
靠近第二初始子金属层1320的第三初始子金属层1330、第二初始子金属层1320以及靠近第二初始子金属层1320的第一初始子金属层1310形成第二子金属层132，第二子金属层132设置为连接第一子金属层131和第三子金属层133的共晶合金层。
在一些示例中，如图25所示，第一键合层13包括与第一子像素发光功能层12a对应的第一开口区K1、与第二子像素发光功能层12b(图中未示出) 对应的第二开口区和与第三子像素发光功能层12c(图中未示出)对应的第三开口区(图中未示出)。
其中，如图15b、图21b和图25所示，第一初始子金属层1310形成第一键合层13后，第一初始子金属层1310的第一子开口区K11、第二子开口区K21和第三子开口区K31分别对应成为第一子金属层131的第一子开口区K11、第二子开口区K21和第三子开口区K31；第三初始子金属层1330形成第一键合层13后，第三初始子金属层1330的第四子开口区K14、第五子开口区K25和第六子开口区K36，分别对应成为第三子金属层133的第四子开口区K14、第五子开口区K25和第六子开口区K36。第二初始子金属层1320与第一初始子金属层1310、第三初始子金属层1330形成共晶合金，在此过程中，第二初始子金属层1320对第一初始子金属层1310和第三初始子金属层1330的开口区没有影响。
也就是说，第一初始子金属层1310、第二初始子金属层1320和第三初始子金属层1330在形成第一键合层13后，第一子开口区K11和第四子开口区K14叠设形成第一键合层13的第一开口区K1，第二子开口区K21和第五子开口区K25叠设形成第一键合层13第二开口区，第三子开口区K31和第六子开口区K36叠设形成第一键合层13第三开口区。
M302：去除临时衬底20，结构如图26所示。
示例性的，通过防酸膜保护第一衬底31，将临时衬底20放入氢氟酸(HF)刻蚀槽进行部分刻蚀，然后采用干刻工艺去掉剩余的临时衬底20。
M303：如图27所示，形成第二绝缘层40，第二绝缘层40上设置有多个过孔。
示例性的，第二绝缘层40上的过孔包括第五过孔401、第六过孔、第七过孔和第八过孔404，第五过孔401与第一子像素发光功能层12a对应设置，第六过孔与第二子像素发光功能层12b对应设置，第七过孔与第三子像素发光功能层12c对应设置，第八过孔404与公共阴极层17对应设置。
M304：如图28所示，形成电极，其中，电极包括第一阳极124a、第二阳极、第三阳极和阴极电极17b。
其中，第一阳极124a、第二阳极和第三阳极称为阳极电极。
示例性的，通过构图工艺形成电极。其中，第一阳极124a与第一子像素发光功能层12a对应设置，第二阳极与第二子像素发光功能层12b对应设置，第三阳极与第三子像素发光功能层12c，阴极电极17b和阴极金属17a形成公共阴极层17。
M305：减薄第一衬底31。
示例性的，将第一衬底31的厚度减薄至60μm～200μm。减薄第一衬底31后形成的芯片结构10的形状接近正方体，使得芯片结构10放置更稳固，而且有利于后续工序的使用。在芯片结构10制备的过程中使用较厚的第一衬底31有利于芯片结构10的加工。
示例性的，通过在第一衬底31第一侧贴防酸膜，然后将第一衬底31的第二侧进行减薄，其中，多个子像素发光功能层12设置于在第一衬底31的第一侧。
M306：切割，得到单个芯片结构10。
在一些示例中，如图4所示，芯片晶圆单元11的第一子像素发光功能层12a包括沿第一方向X层叠设置的第一量子阱121a、第一p型氮化镓122a、第一反射部123a、第一键合部19a和第一阳极124a；第二子像素发光功能层12b(图中未示出)包括沿第一方向X层叠设置的第二量子阱、第二p型氮化镓、第二反射部123b、第二键合部和第二阳极；第三子像素发光功能层12c(图中未示出)包括沿第一方向X层叠设置的第三量子阱、第三p型氮化镓、第三反射部123c、第三键合部和第三阳极。公共阴极层17包括沿第一方向X层叠设置的阴极金属17a和阴极电极17b。其中，第一方向X为由色转换层基板单元2指向芯片晶圆单元1的方向。
第三子金属层133为连通第一n型氮化镓16a、第二n型氮化镓16b、第三n型氮化镓16c和第四n型氮化镓16d的导电层。也就是说，第三子金属层133具有连通第一子像素发光功能层12a、第二子像素发光功能层12b、第三子像素发光功能层12c和公共阴极层17的作用。
本实施例形成的芯片结构10的红光外量子效率提高至10％～20％。本实施例的芯片结构10通过第一键合层13的金属晶圆键合作用连接芯片晶圆单元11和色转换层基板单元21，第一键合层13采用金属材料，金属材料具有较高的折射率，可以防止子像素发光功能层12出射的光出现漏光和串色的作用，提高芯片结构10的出光效果。
以下介绍芯片结构10的制备方法的第二种实施例，根据该实施例形成的芯片结构10为图5所示的芯片结构10。
实施例2
如图29所示为初始芯片晶元单元110的制备步骤，包括T101～T107。
T101：如图8和图9a所示，在第二衬底14的一侧依次形成初始氮化镓缓冲层150、初始n型氮化镓层160、初始量子阱层1210和初始P型氮化镓 层1220，并图案化初始量子阱层1210和初始P型氮化镓层1220，形成初始芯片晶圆单元110的量子阱层121和P型氮化镓层122。
具体步骤可以参见步骤S101，此处不再赘述。
T102：如图9a和图9b所示，形成初步第一绝缘层18a，初步第一绝缘层18a上设置有多个过孔H。
具体步骤可以参见步骤S102，此处不再赘述。
T103：如图10所示，形成第二键合层19。
具体步骤可以参见步骤S103，此处不再赘述。
T104：去除第二衬底14。去除第二衬底14后的一个初始芯片晶圆单元110的结构如图13所示。
具体步骤可以参见步骤S104，此处不再赘述。
T105：如图30所示，形成图案化的氮化镓缓冲层15、n型氮化镓层16和第一绝缘层18。
示例性的，通过光刻工艺处理初始氮化镓缓冲层150、初始n型氮化镓层160、初步第一绝缘层18a形成图案化的氮化镓缓冲层15、n型氮化镓层16和第一绝缘层18。
T106：如图31a所示，在氮化镓缓冲层15远离临时衬底20的一侧形成图案化的第一初始子金属层1310和第二初始子金属层1320。
关于第一初始子金属层1310和第二初始子金属层1320的形成步骤可以参见步骤S106所述，此处不再赘述。
示例性的，如图31b所示，叠设的氮化镓缓冲层15和n型氮化镓层16栅该设置有第一子开口区K11、第二子开口区K21和第三子开口区K31。第一子开口区K11与第一子像素发光功能层12a对应设置，第二子开口区K21与第二子像素发光功能层12b对应设置，第三子开口区K31与第三子像素发光功能层12c对应设置。其中，图31a为图31b沿II截面线得到的截面图。
T107：如图32所示，将氮化镓缓冲层15表面进行粗化，形成初始芯片晶圆单元110。
示例性的，使用70℃～80℃的强碱使得氮化镓缓冲层15表面粗化，在暴露的氮化镓缓冲层15表面形成多个第一类微凸起结构15t。第一类微凸起结构15t可以使得光线易于出射，提高芯片结构10的出光效率。
其中，氮化镓缓冲层15对应第一子像素发光功能层12a、第二子像素发光功能层12b和第三子像素发光功能层12c的区域为第一区域S1，第一区域S1的表面也就是氮化镓缓冲层15在此步骤中暴露出来对应第一子开口区 K11、第二子开口区K21和第三子开口区K31的区域的表面。第一区域S1的表面均形成了多个第一类微凸起结构15t。氮化镓缓冲层15除去第一区域S1的剩余部分为第二区域S2，第一初始子金属层1310形成在氮化镓缓冲层15第二区域S2的表面。
初始色转换层基板单元210的制备步骤可以参见上述步骤R201～R205。此处不再赘述。
通过对盒工艺形成单个芯片结构10的，可以参见步骤M301～M306，此处不在赘述。
本实施例形成的芯片结构10如图5所示，芯片晶圆单元10还包括沿第二方向层叠设置的n型氮化镓层16和氮化镓缓冲层15，第二方向为由芯片晶圆单元11指向色转换层基板单元21的方向，可以理解的是，第二方向与出光侧G指向的方向平行。
如图5所示，n型氮化镓层16与第一量子阱121a、第二量子阱、第三量子阱及阴极金属17a连接，也就是说，n型氮化镓层16具有连通第一子像素发光功能层12a、第二子像素发光功能层12b、第三子像素发光功能层12c和公共阴极层17的作用。
本实施例形成的芯片结构10的红光外量子效率提高至10％～20％。本实施例的芯片结构10通过第一键合层13的金属晶圆键合作用连接芯片晶圆单元11和色转换层基板单元21，第一键合层13采用金属材料，金属材料具有较高的折射率，可以防止子像素发光功能层12出射的光出现漏光和串色的作用，提高芯片结构10的出光效果。并且，本实施例第一键合层13仅具有连接作用，采用n型氮化镓层16作为连通第一子像素发光功能层12a、第二子像素发光功能层12b、第三子像素发光功能层12c和公共阴极层17的导电层，可以减小电阻。
以下介绍芯片结构10的制备方法的第三种实施例，根据该实施例形成的芯片结构10为图6a所示的芯片结构10。
实施例3
如图33所示为初始芯片晶元单元110的制备步骤，包括N101～N109。
N101:如图8和图9a所示，在第二衬底14的一侧依次形成初始氮化镓缓冲层150、初始n型氮化镓层160、初始量子阱层1210和初始P型氮化镓层1220，并图案化初始量子阱层1210和初始P型氮化镓层1220，形成初始芯片晶圆单元110的量子阱层121和P型氮化镓层122。
具体步骤可以参见步骤S101，此处不再赘述。
N102:如图34所示，形成阴极金属17a。
示例性的，通过光刻防水制作图案化光刻胶，蒸镀形成阴极金属17a的材料，并图案化形成阴极金属17a。
示例性的，阴极金属17a的材料可以为钛、铝、镍和金中的任一种。
N103:如图35所示，形成初步第二绝缘层40a，初步第二绝缘层40a上设置有多个过孔。
具体步骤可以参见步骤M303的内容，此处不再赘述。
N104:如图36所示，形成电极，其中，电极包括第一阳极124a、第二阳极、第三阳极和阴极电极17b。
具体步骤可以参见步骤M304的内容，此处不再赘述。
N105:如图37所示，在电极远离第二衬底14的一侧键合临时衬底20。
示例性的，采用临时键合胶键合临时衬底20，临时键合胶可以采用丙烯酸酯类热塑性胶。
N106:如图38所示，去除第二衬底14。
具体步骤可以参见步骤S104，此处不再赘述。
N107:如图39所示，形成图案化的氮化镓缓冲层15、n型氮化镓层16和第二绝缘层40。
示例性的，通过光刻工艺处理初始氮化镓缓冲层150、初始n型氮化镓层160、初步第二绝缘层40a形成图案化的氮化镓缓冲层15、n型氮化镓层16和第二绝缘层40。
N108:如图40所示，在氮化镓缓冲层15远离临时衬底20的一侧形成图案化的第一初始子金属层1310和第二初始子金属层1320。
具体步骤可以参见步骤T106，此处不再赘述。
N109:如图41所示，将氮化镓缓冲层15表面进行粗化，形成初始芯片晶圆单元110。
具体步骤可以参见步骤T107，此处不再赘述。
初始色转换层基板单元210的制备步骤可以参见上述步骤R201～R205。此处不再赘述。
由上述步骤制备的初始芯片晶圆单元110和初始色转换层基板单元210形成芯片结构10的步骤，如图42所示，包括V301～V304。
V301：如图43所示，通过金属晶圆键合技术键合初始芯片晶圆单元110和初始色转换层基板单元210。
具体步骤可以参见步骤M301，此处不再赘述。
V302：去除临时衬底20。
示例性的，通过紫外激光照射，使得临时衬底20上的临时键合胶解键合，去除临时衬底20和临时键合胶。
V303：减薄第一衬底31。
具体步骤可以参见步骤M305，此处不再赘述。
V304：切割，得到芯片结构10。
具体步骤可以参见步骤M306，此处不再赘述。
本实施例形成的芯片结构10的红光外量子效率提高至10％～20％。本实施例的芯片结构10通过第一键合层13的金属晶圆键合作用连接芯片晶圆单元11和色转换层基板单元21，第一键合层13采用金属材料，金属材料具有较高的折射率，可以防止子像素发光功能层12出射的光出现漏光和串色的作用，提高芯片结构10的出光效果。并且，本实施例第一键合层13仅具有连接作用，采用n型氮化镓层16作为连通第一子像素发光功能层12a、第二子像素发光功能层12b、第三子像素发光功能层12c和公共阴极层17的导电层，采用钛、铝、镍和金中的任一种材料作为公共阴极层17的阴极金属17a，可以减小电阻。
在一些实施例中，如图6b所示，第一键合层13包括层叠设置的第一子键合层135和第二子键合层136。
示例性的，第一子键合层135和第二子键合层136的材料为氧化铟锌。
示例性的，第一子键合层135和第二子键合层136形成的第一键合层13的厚度d3范围为200nm～1200nm，例如，第一键合层13的厚度d3为200nm、400nm、600nm、800nm或1200nm等，此处并不设限。
本公开的一些实施例还提供一种显示基板100，如图1所示，显示基板100包括如上任一项实施例所述的多个芯片结构10。
在一些实施例中，显示基板100包括驱动背板，驱动背板包括线路层，多个芯片结构10设置于驱动背板上，线路层中例如包括多个焊盘组，每个焊盘组包括分离设置的多个焊盘，每个芯片结构10的阴极电极17b、第一阳极124a、第二阳极和第三阳极分别与多个焊盘中的一个焊盘对应电连接。
示例性地，多个芯片结构10通过巨量转移技术转移至驱动背板上。
本公开的一些实施例还提供一种显示装置1000，如图44所示，包括如上所述的所述的显示基板100。
示例性的，本公开实施例所提供的显示装置可以是显示不论运动(例如， 视频)还是固定(例如，静止图像)的且不论文字还是图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (28)

  1. 一种芯片结构，包括：芯片晶圆单元和设置于所述芯片晶圆单元出光侧的色转换层基板单元；其中，所述芯片晶圆单元包括多个子像素发光功能层；所述色转换层基板单元包括设置于所述芯片晶圆单元出光侧的色转换层；
    所述芯片晶圆单元还包括：第一键合层，设置于所述子像素发光功能层和所述色转换层之间，用于键合所述芯片晶圆单元和所述色转换层基板单元。
  2. 根据权利要求1所述的芯片结构，其中，所述第一键合层包括层叠设置的第一子金属层、第二子金属层和第三子金属层；
    所述第三子金属层比所述第一子金属层靠近所述色转换层基板单元，所述第二子金属层设置为连接所述第一子金属层和所述第三子金属层的共晶合金层；
    或，所述第一键合层包括层叠设置的第一子键合层和第二子键合层。
  3. 根据权利要求2所述的芯片结构，其中，所述第一子键合层和所述第二子键合层的材料为氧化铟锌。
  4. 根据权利要求2或3所述的芯片结构，其中，所述芯片晶圆单元包括第一子像素发光功能层、第二子像素发光功能层和第三子像素发光功能层；
    所述第一键合层包括与所述第一子像素发光功能层对应的第一开口区、与所述第二子像素发光功能层对应的第二开口区和与所述第三子像素发光功能层对应的第三开口区。
  5. 根据权利要求4所述的芯片结构，其中，所述芯片晶圆单元还包括公共阴极层；
    所述第一子像素发光功能层包括沿第一方向层叠设置的第一量子阱、第一p型氮化镓和第一阳极；
    所述第二子像素发光功能层包括沿第一方向层叠设置的第二量子阱、第二p型氮化镓和第二阳极；
    所述第三子像素发光功能层包括沿第一方向层叠设置的第三量子阱、第三p型氮化镓和第三阳极；
    所述公共阴极层包括沿第一方向层叠设置的阴极金属和阴极电极；
    其中，所述第一方向为由所述色转换层基板单元指向所述芯片晶圆单元的方向。
  6. 根据权利要求5所述的芯片结构，其中，所述公共阴极层的阴极金属材料包括钛、铝、镍和金中的任一种。
  7. 根据权利要求5所述的芯片结构，其中，所述芯片晶圆单元还包括第二键合层，所述第二键合层包括第一键合部、第二键合部、第三键合部和第 四键合部；
    所述第一键合部叠设于所述第一p型氮化镓和所述第一阳极之间；
    所述第二键合部叠设于所述第二p型氮化镓和所述第二阳极之间；
    所述第三键合部叠设于所述第三p型氮化镓和所述第三阳极之间；
    所述公共阴极层的阴极金属包括所述第四键合部。
  8. 根据权利要求7所述的芯片结构，其中，所述第二键合层包括层叠设置的第四子金属层、第五子金属层和第六子金属层；
    所述第六子金属层比所述第四子金属层远离所述色转换层基板，所述第五子金属层设置为连接所述第六子金属层和所述第四子金属层的共晶合金层。
  9. 根据权利要求1～8任一项所述的芯片结构，其中，所述芯片晶圆单元还包括第二键合层；
    所述第一键合层包括层叠设置的第一子金属层、第二子金属层和第三子金属层，所述第一键合层的最大厚度的厚度范围，等于所述第二键合层的厚度范围；
    或者，所述第一键合层包括层叠设置的第一子键合层和第二子键合层，所述第一键合层的厚度范围，小于所述第二键合层的厚度范围。
  10. 根据权利要求9所述的芯片结构，其中，
    所述第一键合层包括层叠设置的第一子金属层、第二子金属层和第三子金属层，所述第一键合层的最大厚度的厚度范围为3μm～6μm；或者，
    所述第一键合层包括层叠设置的第一子键合层和第二子键合层，所述第一键合层的厚度范围为200nm～1200nm；
    所述第二键合层的厚度范围为3μm～6μm。
  11. 根据权利要求1～10任一项所述的芯片结构，其中，所述第一键合层包括层叠设置的第一子金属层、第二子金属层和第三子金属层；
    所述第二子金属层为熔融温度小于240℃的共晶合金层。
  12. 根据权利要求6～10任一项所述的芯片结构，其中，所述芯片晶圆单元还包括沿第二方向层叠设置的n型氮化镓导电层和氮化镓缓冲层，所述第二方向为由所述芯片晶圆单元指向所述色转换层基板单元的方向；
    所述n型氮化镓导电层与所述第一量子阱、所述第二量子阱、所述第三量子阱及所述阴极金属连接；
    所述氮化镓缓冲层对应所述第一子像素发光功能层、所述第二子像素发光功能层和所述第三子像素发光功能层的区域为第一区域，所述第一区域朝 向所述色转换层基板的一侧设置有多个第一类微凸起结构；所述氮化镓缓冲层不包括所述第一区域的部分为第二区域，所述第一键合层位于所述第二区域的所述氮化镓缓冲层朝向所述色转换层基板的一侧。
  13. 根据权利要求7或8所述的芯片结构，其中，所述芯片晶圆单元还包括n型氮化镓导电层，所述n型氮化镓导电层包括第一n型氮化镓、第二n型氮化镓、第三n型氮化镓和第四n型氮化镓；
    所述第一n型氮化镓叠设于所述第一量子阱远离所述第一p型氮化镓的一侧；
    所述第二n型氮化镓叠设于所述第二量子阱远离所述第二p型氮化镓的一侧；
    所述第三n型氮化镓叠设于所述第三量子阱远离所述第三p型氮化镓的一侧；
    所述第四n型氮化镓叠设于所述第四键合区朝向所述色转换层基板的一侧；
    所述第一键合层设置于所述n型氮化镓导电层朝向所述色转换层基板单元的一侧。
  14. 根据权利要求13所述的芯片结构，其中，层叠设置的所述第一子金属层和所述第二子金属层包括设置有所述第一开口区的第一区、设置有所述第二开口区的第二区、设置有所述第三开口区的第三区和覆盖所述公共阴极层的第四区；
    所述第三子金属层覆盖所述第一区、所述第二区、所述第三区及所述第四区的所述第二子金属层，且所述第三子金属层被配置为连通所述第一n型氮化镓、所述第二n型氮化镓、所述第三n型氮化镓和所述第四n型氮化镓的导电层。
  15. 根据权利要求13或14所述的芯片结构，其中，所述n型氮化镓导电层对应所述第一子像素发光功能层、所述第二子像素发光功能层和所述第三子像素发光功能层的区域为第三区域，所述第三区域朝向所述色转换层基板单元的一侧设置有多个第二类微凸起结构。
  16. 根据权利要求5～8和12～15任一项所述的芯片结构，其中，所述芯片晶圆单元还包括反射金属层，所述反射金属层包括第一反射部、第二反射部和第三反射部；
    所述第一反射部叠设于所述第一p型氮化镓和所述第一阳极之间；
    所述第二反射部叠设于所述第二p型氮化镓和所述第二阳极之间；
    所述第三反射部叠设于所述第三p型氮化镓和所述第三阳极之间。
  17. 根据权利要求16所述的芯片结构，其中，所述芯片晶圆单元包括第二键合层，所述第二键合层包括第一键合部、第二键合部、第三键合部和第四键合部；
    所述第一反射部叠设于所述第一键合部朝向所述色转换层基板单元的一侧；
    所述第二反射部叠设于所述第二键合部朝向所述色转换层基板单元的一侧；
    所述第三反射部叠设于所述第三键合部朝向所述色转换层基板单元的一侧。
  18. 根据权利要求17所述的芯片结构，其中，所述第二键合层朝向所述色转换层基板单元的一侧设置有绝缘层，所述绝缘层上设置有第一过孔、第二过孔、第三过孔和第四过孔；
    所述第一键合部的第四子金属层填充所述第一过孔与所述第一反射部连接；
    所述第二键合部的第四子金属层填充所述第二过孔与所述第二反射部连接；
    所述第三键合部的第四子金属层填充所述第三过孔与所述第三反射部连接；
    所述第四键合部的第四子金属层填充所述第四过孔与所述n型氮化镓导电层连接。
  19. 根据权利要求1～18任一项所述的芯片结构，其中，所述芯片晶圆单元包括第一子像素发光功能层、第二子像素发光功能层和第三子像素发光功能层；
    所述色转换层包括限定坝层，以及由所述限定坝层限定的第四开口区、第五开口区和第六开口区；
    所述第四开口区设置有与所述第一子像素发光功能层对应的第一量子点转换部；
    所述第五开口区设置有与所述第二子像素发光功能层对应的散射粒子部；
    所述第六开口区设置有与所述第三子像素发光功能层对应的散射粒子部。
  20. 根据权利要求19所述的芯片结构，其中，
    所述第四开口区在所述色转换层基板单元的正投影覆盖所述第一子像素发光功能层在所述色转换层基板单元上的正投影；
    所述第五开口区在所述色转换层基板单元的正投影覆盖所述第二子像素发光功能层在所述色转换层基板单元上的正投影；
    所述第六开口区在所述色转换层基板单元的正投影覆盖所述第三子像素发光功能层在所述色转换层基板单元上的正投影。
  21. 根据权利要求19或20所述的芯片结构，其中，所述色转换层基板单元还包括聚光层，所述聚光层设置于所述色转换层靠近所述芯片晶圆单元的一侧；
    所述聚光层包括与所述第一量子点转换部对应的第一聚光部，与所述散射粒子部对应的第二聚光部，以及与所述第三量子点转换部对应的第三聚光部。
  22. 根据权利要求19～21任一项所述的芯片结构，其中，所述色转换层基板单元还包括衬底和彩膜层，所述衬底、所述彩膜层和所述色转换层沿第二方向层叠设置，所述第二方向为由所述芯片晶圆单元指向所述色转换层基板单元的方向；
    所述彩膜层包括黑矩阵，以及由所述黑矩阵限定的与第一量子点转换部对应的第一滤光膜、与散射粒子部对应的第二滤光膜和与散射粒子部对应的第三滤光膜。
  23. 一种显示基板，包括如权利要求1～22任一项所述的芯片结构。
  24. 一种芯片制备方法，包括：
    形成初始芯片晶圆单元，所述初始芯片晶圆单元包括层叠设置的临时衬底、多个子像素发光功能层、第一初始子金属层和第二初始子金属层，其中，所述第二初始子金属层包括多个第一类金属凸点；
    形成色转换层基板单元，所述色转换层基板单元包括层叠设置的色转换层和第一衬底；
    在所述色转换层远离所述第一衬底的一侧形成第三初始子金属层；
    键合所述第一初始子金属层、第二初始子金属层和所述第三初始子金属层，形成第一键合层；其中，所述第一键合层包括第一子金属层、第二子金属层和第三子金属层，所述第二子金属层为连接所述第一子金属层和所述第三子金属层的共晶合金层；
    剥离所述临时衬底，形成芯片晶圆单元，所述芯片晶圆单元和所述色转换层基板单元由所述第一键合层连接。
  25. 根据权利要求24所述的芯片制备方法，其中，所述形成初始芯片晶圆单元的步骤包括：
    提供第二衬底；
    在所述第二衬底的一侧形成所述初始芯片晶圆单元，所述初始芯片晶圆单元包括多个初始子像素发光功能层和初始公共阴极层；
    在所述初始芯片晶圆单元的所述多个初始子像素发光功能层和所述初始公共阴极层远离所述第二衬底的一侧形成所述临时衬底；
    剥离所述第二衬底。
  26. 根据权利要求25所述的芯片制备方法，其中，所述在所述第二衬底的一侧形成所述初始芯片晶圆单元，所述初始芯片晶圆单元包括多个初始子像素发光功能层和初始公共阴极层，在所述初始芯片晶圆单元的所述多个初始子像素发光功能层和所述初始公共阴极层远离所述第二衬底的一侧形成所述临时衬底的步骤包括：
    在所述第二衬底的一侧依次形成氮化镓缓冲层、n型氮化镓层、量子阱层和P型氮化镓层，并图案化所述量子阱层和P型氮化镓层，形成所述初始芯片晶圆单元的量子阱层和P型氮化镓层；
    在所述P型氮化镓层远离所述量子阱层的一侧形成第一绝缘层，所述第一绝缘层上设置有多个过孔；
    在所述第一绝缘层远离所述第二衬底的一侧形成第四子初始金属层和第五子初始金属层；第四子初始金属层填充所述第一绝缘层上设置的多个过孔；所述第五子初始金属层包括多个第二类金属凸点；
    提供临时衬底；
    在所述临时衬底的一侧形成所述初始芯片晶圆单元的第六子初始金属层；
    键合所述第六子初始金属层、第五子初始金属层和第四子初始金属层，形成第二键合层，所述第二键合层包括第四子金属层、第五子金属层和第六子金属层，所述第五子金属层设置为连接所述第六子金属层和所述第四子金属层的共晶合金层；
    所述剥离所述第二衬底的步骤之后还包括以下步骤：
    去除所述氮化镓缓冲层，图案化所述n型氮化镓层和所述第一绝缘层；
    在每一个所述初始芯片晶圆单元的所述n型氮化镓层远离所述临时衬底的一侧形成所述第一初始子金属层和所述第二初始子金属层，并将所述n型氮化镓层的表面粗化，形成所述初始芯片晶圆单元；
    或者，所述剥离所述第二衬底的步骤之后还包括以下步骤：
    图案化所述氮化镓缓冲层、n型氮化镓层和第一绝缘层；
    在所述初始芯片晶圆单元的所述氮化镓缓冲层上形成第一初始子金属层和所述第二初始子金属层，并将所述氮化镓缓冲层的表面粗化，形成所述初始芯片晶圆单元；
    所述剥离所述临时衬底，形成芯片晶圆单元的步骤包括：
    在每一个所述第二键合层远离所述色转换层基板单元的一侧形成第二绝缘层，所述第二绝缘层上设置有多个过孔；
    形成电极，所述电极包括阴极电极和阳极电极，所述阴极电极、所述阳极电极填充所述第二绝缘层上对应的所述多个过孔中的一个；
    将所述第一衬底减薄，形成所述芯片晶圆。
  27. 根据权利要求25所述的芯片制备方法，其中，所述在所述第二衬底的一侧形成所述初始芯片晶圆单元，所述初始芯片晶圆单元包括多个初始子像素发光功能层和初始公共阴极层，在所述初始芯片晶圆单元的所述多个初始子像素发光功能层和所述初始公共阴极层远离所述第二衬底的一侧形成所述临时衬底的步骤包括：
    在所述第二衬底的一侧依次形成氮化镓缓冲层、n型氮化镓层、量子阱层和P型氮化镓层，并图案化所述量子阱层和P型氮化镓层，形成所述初始芯片晶圆单元的量子阱层和P型氮化镓层；
    形成所述初始公共阴极层的阴极金属；
    在所述P型氮化镓层和所述阴极金属远离所述色转换层基板单元的一侧形成第二绝缘层，所述第二绝缘层上设置有多个过孔；
    形成电极，所述电极包括阴极电极和阳极电极，所述阴极电极、所述阳极电极填充所述第二绝缘层上对应的所述多个过孔中的一个；形成所述初始芯片晶圆单元的所述多个初始子像素发光功能层和初始公共阴极层；
    将所述多个子像素发光功能层和初始公共阴极层键合在临时衬底上；
    所述剥离所述第二衬底的步骤之后还包括以下步骤：
    图案化所述氮化镓缓冲层、n型氮化镓层和第二绝缘层，在所述氮化镓缓冲层上形成第一初始子金属层和所述第二初始子金属层，并将所述氮化镓缓冲层的表面粗化，形成所述初始芯片晶圆单元。
  28. 一种显示装置，包括如权利要求23所述的显示基板。
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CN113725249A (zh) * 2021-08-30 2021-11-30 京东方科技集团股份有限公司 一种芯片结构、制作方法和显示装置
CN114334923A (zh) * 2021-12-23 2022-04-12 厦门士兰明镓化合物半导体有限公司 显示屏、Micro-LED显示基板及其制备方法

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CN112234078A (zh) * 2019-06-30 2021-01-15 成都辰显光电有限公司 色彩转换组件及显示装置
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