WO2023236243A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2023236243A1
WO2023236243A1 PCT/CN2022/099412 CN2022099412W WO2023236243A1 WO 2023236243 A1 WO2023236243 A1 WO 2023236243A1 CN 2022099412 W CN2022099412 W CN 2022099412W WO 2023236243 A1 WO2023236243 A1 WO 2023236243A1
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gate
air gap
layer
substrate
sacrificial
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PCT/CN2022/099412
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English (en)
French (fr)
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申松梅
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长鑫存储技术有限公司
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Priority to KR1020237000717A priority Critical patent/KR20230169924A/ko
Priority to EP22790432.3A priority patent/EP4310889A4/en
Priority to US17/947,227 priority patent/US20230013859A1/en
Publication of WO2023236243A1 publication Critical patent/WO2023236243A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H01L29/4991—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Definitions

  • the present disclosure relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor structure and a manufacturing method thereof.
  • DRAM Dynamic Random Access Memory
  • the back end ofline (BEOL) process is used to establish several layers of wires, and the wires of different layers are connected by conductive holes.
  • BEOL back end ofline
  • most of the wires and conductive holes are made of metal, which easily causes parasitic capacitance between adjacent wires.
  • the parasitic capacitance between the aforementioned wires will continue to increase, resulting in an obvious resistance-capacitance delay (RC-Delay) effect in DRAM and easily reducing the service life of devices in DRAM.
  • RC-Delay resistance-capacitance delay
  • embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof.
  • the present disclosure provides a method for preparing a semiconductor structure, including: providing a substrate, forming a plurality of gate structures arranged at intervals on the substrate; Form sacrificial spacers with a preset thickness; form a first dielectric layer between the adjacent sacrificial spacers, and the top of the first dielectric layer is flush with the top of the gate structure and the top of the sacrificial spacers; remove The sacrificial sidewalls form an air gap structure on the side walls of the gate structure; a second dielectric layer is formed, and the second dielectric layer covers the top of the gate structure, the top opening of the air gap structure and the third A dielectric layer on top.
  • forming sacrificial spacers with a predetermined thickness on the sidewalls of the gate structure includes: forming an initial sacrificial layer with uniform thickness on the gate structure and the substrate surface; removing the sacrificial spacers located on the gate structure and the substrate surface; The initial sacrificial layer on the top of the gate structure and the surface of the substrate is retained to form the sacrificial spacers by retaining the initial sacrificial layer on the sidewalls of the gate structure.
  • the preparation method before forming sacrificial spacers of a predetermined thickness on the sidewalls of the gate structure, the preparation method further includes: forming a protective layer covering part of the sidewalls of the gate structure; Sacrificial sidewalls cover the outer surface of the protective layer.
  • the gate structure includes a metal layer.
  • the forming a plurality of spaced-apart gate structures on the substrate includes: forming a plurality of spaced-apart initial gate structures on the substrate, where the initial gate structure includes an initial metal layer; Part of the sidewall of the initial metal layer is oxidized to form the protective layer; the unoxidized initial metal layer forms the metal layer.
  • oxidizing part of the sidewall of the initial metal layer includes: treating with a liquid ozone solution.
  • the gate structure further includes a first barrier layer covering the top of the metal layer and the protective layer.
  • the preparation method further includes forming a sacrificial spacer between adjacent sacrificial spacers and above the gate structure.
  • a planarization process is used to remove part of the initial first dielectric layer to form the first dielectric layer; the top of the first dielectric layer is flush with the top of the first barrier layer.
  • the gate structure further includes a second barrier layer located between the substrate, the metal layer and the protective layer.
  • the plurality of gate structures include a plurality of first gate structures and a plurality of second gate structures; wherein there is a first spacing between adjacent first gate structures, and the adjacent first gate structures have a first spacing. There is a second spacing between the second gate structures, and the first spacing is smaller than the second spacing.
  • Forming a sacrificial spacer with a predetermined thickness on the sidewall of the gate structure and forming an air gap structure on the sidewall of the gate structure includes: forming a first sacrificial spacer on the sidewall of the first gate structure, The first sacrificial spacer is removed to form a first air gap structure; a second sacrificial spacer is formed on the side wall of the second gate structure, and the second sacrificial spacer is removed to form a second air gap structure.
  • the first sacrificial spacer and the second sacrificial spacer have the same thickness; the first air gap structure and the second air gap structure have the same width in a direction parallel to the substrate. .
  • the thickness of the first sacrificial spacer is less than the thickness of the second sacrificial spacer; the width of the first air gap structure in a direction parallel to the substrate is smaller than the width of the second air gap structure in a direction parallel to the substrate. width in the direction of the substrate.
  • removing the sacrificial sidewalls includes: treating with a low-temperature phosphoric acid solution to remove the sacrificial sidewalls; wherein the temperature of the low-temperature phosphoric acid solution is less than or equal to 120°C.
  • another aspect of the present disclosure provides a semiconductor structure formed by the method for preparing a semiconductor structure as described in some of the above embodiments.
  • the semiconductor structure includes: a substrate; a plurality of gate structures arranged at intervals on the substrate; an air gap structure located on the sidewall of the gate structure; a first dielectric layer located adjacent to the gate between the air gap structures on the sidewalls of the structure; and a second dielectric layer covering the top of the gate structure, the top opening of the air gap structure, and the top of the first dielectric layer.
  • the semiconductor structure further includes: a protective layer covering part of the sidewall of the gate structure; and the air gap structure is located between the protective layer and the first dielectric layer.
  • the gate structure includes: a metal layer and a first barrier layer located on a side of the metal layer away from the substrate; wherein the protective layer covers sidewalls of the metal layer, and the A first barrier layer covers the metal layer and the top of the protective layer.
  • the top of the first dielectric layer is flush with the top of the first barrier layer.
  • the plurality of gate structures include a plurality of first gate structures and a plurality of second gate structures; wherein there is a first spacing between adjacent first gate structures, and the adjacent first gate structures have a first spacing. There is a second spacing between the second gate structures, and the first spacing is smaller than the second spacing; wherein, the air gap structure located on the side wall of the first gate structure is a first air gap structure, The air gap structure located on the side wall of the second gate structure is a second air gap structure; the first air gap structure and the second air gap structure have the same width in a direction parallel to the substrate; Alternatively, the width of the first air gap structure in a direction parallel to the substrate is smaller than the width of the second air gap structure in a direction parallel to the substrate.
  • an air gap structure of a predetermined size can be formed after removing the sacrificial spacers to utilize air.
  • the gap structure effectively isolates the gate structure and effectively reduces the parasitic capacitance of the device where the gate structure is located.
  • embodiments of the present disclosure can also achieve balanced control of the corresponding parasitic capacitances of different devices, thereby effectively improving the device performance of the semiconductor structure. This can reduce the resistance-capacitance delay (RC-Delay) of the semiconductor structure.
  • RC-Delay resistance-capacitance delay
  • Figures 3 to 5 are respectively schematic cross-sectional views of the intermediate structure and the resulting structure corresponding to step S100 in an embodiment
  • Figures 9 to 10 are respectively schematic cross-sectional views of the intermediate structure and the resulting structure corresponding to step S300 in an embodiment
  • embodiments of the invention are described herein with reference to schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown may be anticipated due, for example, to manufacturing techniques and/or tolerances.
  • embodiments of the present disclosure should not be limited to the specific shapes of regions shown herein but are to include deviations in shapes due, for example, to manufacturing techniques.
  • the regions shown in the figures are schematic in nature and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.
  • the characteristic sizes of devices in integrated circuits are getting smaller and smaller.
  • the size of DRAM becomes smaller and smaller.
  • the size of each component in DRAM and the distance between adjacent components are getting smaller and smaller.
  • the back end ofline (BEOL) process is used to establish several layers of wires, and the wires of different layers are connected by conductive holes.
  • BEOL back end ofline
  • most of the wires and conductive holes are made of metal, which easily causes parasitic capacitance between adjacent wires.
  • the parasitic capacitance between the aforementioned wires will continue to increase, resulting in an obvious resistance-capacitance delay (RC-Delay) effect in DRAM and easily reducing the service life of devices in DRAM.
  • RC-Delay resistance-capacitance delay
  • some embodiments of the present disclosure provide a method of manufacturing a semiconductor structure.
  • the preparation method includes the following steps.
  • embodiments of the present disclosure can also achieve balanced control of the corresponding parasitic capacitances of different devices, thereby effectively improving the device performance of the semiconductor structure. This can reduce the resistance-capacitance delay (RC-Delay) of the semiconductor structure.
  • RC-Delay resistance-capacitance delay
  • the quiescent current of the transistor device in the semiconductor structure (ie: IDD current, which refers to the leakage current of the device when it is static) is proportional to the corresponding parasitic capacitance.
  • IDD current which refers to the leakage current of the device when it is static
  • an air gap structure is provided on the side wall of the gate structure, which can reduce the corresponding parasitic capacitance and reduce the leakage current of the device, thereby reducing the power consumption of the transistor device when it is turned off, thereby effectively improving the transistor device and semiconductor The service life of the structure.
  • the gate structure serves as a control element of the device and has a conductive function.
  • the gate structure includes a metal layer.
  • forming a plurality of spaced-apart gate structures on the substrate includes: forming a plurality of spaced-apart initial gate structures on the substrate, where the initial gate structure includes an initial metal layer; and oxidizing the initial metal layer. Part of the sidewall forms a protective layer; the initial metal layer that has not been oxidized forms a metal layer.
  • the protective layer can be formed directly based on the initial metal layer, which is beneficial to simplifying the process and ensuring that the execution of subsequent processes will not have an adverse effect on the metal layer of the gate structure, thereby ensuring the electrical performance of the gate structure.
  • oxidizing part of the sidewall of the initial metal layer includes: treating with a liquid ozone solution. In this way, a dense metal oxide can be formed as a protective layer on the surface of the initial metal layer.
  • forming sacrificial spacers with a preset thickness on the sidewalls of the gate structure in step S200 includes: forming an initial sacrificial spacer with a uniform thickness on the surface of the gate structure and the substrate. Sacrificial layer; remove the initial sacrificial layer located on the top of the gate structure and the surface of the substrate to retain the initial sacrificial layer located on the sidewalls of the gate structure to form sacrificial sidewalls.
  • the gate structure 2 includes a stacked first barrier layer 22 , a metal layer 21 and a second barrier layer 23 .
  • forming a plurality of gate structures 2 arranged at intervals on the substrate 1 includes the following steps.
  • a second barrier material layer 230 , a metal material layer 210 and a first barrier material layer 220 are sequentially stacked on the substrate 1 .
  • the materials of the second barrier material layer 230 and the first barrier material layer 220 may be the same or different.
  • the material of the second barrier material layer 230 and the first barrier material layer 220 is one of tantalum (Ta), tantalum nitride (TaN), copper (Cu) or titanium nitride (TiN) respectively.
  • the material of the metal material layer 210 is, for example, aluminum (Al).
  • photoresist PR is coated on top of the first barrier material layer 220, and a mask pattern is formed in the photoresist PR.
  • the mask pattern is used to define where the gate structure 2 is formed.
  • the protective layer 3 can be formed on the sidewalls of the gate structure 2 using a deposition process, or can be formed in other ways.
  • the protective layer 3 can be directly formed based on the initial metal layer 2A, which is conducive to simplifying the process and ensuring that the execution of subsequent processes will not have an adverse effect on the metal layer 21 of the gate structure 2, thereby ensuring the electrical performance of the gate structure 2 .
  • oxidizing part of the sidewall of the initial metal layer 2A includes: treatment with a liquid ozone solution.
  • a dense metal oxide can be formed as the protective layer 3 on the surface of the initial metal layer 2A.
  • liquid ozone solutions can be used with room temperature acidic solutions or chilled deionized water to effectively clean the wafer after the initial gate structure is formed without corrosive chemicals. This reduces production costs by reducing the use of chemicals.
  • the use of liquid ozone solution requires a smaller working space, and compared with the workbench operation of wet etching using chemical substances, it can have faster work efficiency to improve production efficiency.
  • the thickness of the protective layer 3 is no more than 1 nm. But it doesn't stop there.
  • step S200 referring to FIGS. 7 and 8 , sacrificial spacers 4 with a predetermined thickness are formed on the sidewalls of the gate structure 2 .
  • the sacrificial spacers 4 cover the outer surface of the protective layer 3 .
  • step S200 includes the following steps.
  • the initial sacrificial layer 4A is formed using a deposition process, and its thickness can be selected and set as needed.
  • the initial sacrificial layer 4A covers, for example, the outer surfaces of the first barrier layer 22 , the protective layer 3 and the second barrier layer 23 .
  • the initial sacrificial layer 4A located on the top of the gate structure 2 and the surface of the substrate 1 can be removed by dry etching.
  • the thickness of the initial sacrificial layer 4A is uniform, which can ensure that the sacrificial spacers 4 formed on the sidewalls of different gate structures 2 have the same thickness, thereby forming air gap structures G with the same width in the direction parallel to the substrate 1.
  • the top of the sacrificial spacer 4 is likely to be inclined due to the material loss caused by etching, that is, the top of the sacrificial spacer 4 and the sidewall of the first barrier layer 22 There is an included angle between them, and the included angle is an acute angle.
  • a planarization process is used to remove part of the initial first dielectric layer 5A to form the first dielectric layer 5 .
  • the planarization process is, for example, chemical mechanical polishing (CMP).
  • CMP chemical mechanical polishing
  • the first barrier layer 23 can directly serve as a polishing barrier layer for planarizing the initial first dielectric layer 5A. That is, in the process of removing part of the initial first dielectric layer 5A using a planarization process, the first barrier layer 23 can be directly formed on the surface without setting a mask. The first dielectric layer 5 between adjacent spacers 4 is sacrificed, and the top of the first dielectric layer 5 is flush with the top of the first barrier layer 23 , thereby simplifying the preparation process.
  • CMP chemical mechanical polishing
  • step S400 please refer to FIG. 11 , the sacrificial spacers 4 are removed, and the air gap structure G is formed on the sidewalls of the gate structure 2 .
  • the sacrificial spacers 4 are formed of silicon nitride material.
  • the sacrificial sidewall 4 can be removed using low-temperature phosphoric acid solution.
  • the temperature of the low-temperature phosphoric acid solution is less than or equal to 120°C.
  • high-temperature phosphoric acid solutions for example, the temperature is greater than 150° C.
  • low-temperature phosphoric acid solutions have a higher etching selectivity for nitrides and oxides.
  • Anhydrous pure phosphoric acid is a colorless crystal, hygroscopic, easily soluble in water and miscible with water in any ratio.
  • the low-temperature phosphoric acid solution in the embodiment of the present disclosure is a colorless and viscous liquid, in which the concentration of phosphoric acid accounts for, for example, 85% to 98%.
  • the reaction mechanism of the sacrificial sidewall 4 is removed by low-temperature phosphoric acid solution, which can be expressed as: Si 3 N 4 +4H 3 PO 4 +12H 2 O ⁇ 3Si(OH) 4 +4NH 4 H 4 PO 4 .
  • the second dielectric layer 6 may be formed by oxide deposition, such as silicon oxide.
  • the top of the air gap structure G is closed and has a smaller top opening. In this way, during the deposition of the second dielectric layer 6, the second dielectric layer 6 can easily close the top opening of the air gap structure G and simultaneously cover the gate structure 2 and the third dielectric layer 6.
  • the semiconductor structure generally has a unit array region R1 and a peripheral circuit region R2 located on at least one side of the unit array region R1.
  • the cell array region R1 refers to a region in a semiconductor structure for forming a cell array, for example, a region for forming a memory cell array.
  • any memory cell in the memory cell array includes a transistor and a storage capacitor.
  • the peripheral circuit region R2 is located on at least one side of the cell array region R1, such as the side or the peripheral side.
  • the peripheral circuit region R2 refers to a region in the semiconductor structure for forming peripheral circuits.
  • peripheral circuits can be connected by multiple transistors and other electronic components (such as capacitors, resistors, etc.) according to design requirements to achieve specific functions.
  • the distance between adjacent second gate structures 2B is relatively large. If only the first dielectric layer (such as oxide) is used to fill it, a small parasitic capacitance is easily generated, which reduces the peripheral transistor. The opening speed remains the same or decreases less. As a result, the read speed of both the unit transistor and the peripheral transistor cannot meet expectations due to the delay caused by the corresponding parasitic capacitance.
  • the first dielectric layer such as oxide
  • forming the sacrificial spacers 4 with a predetermined thickness on the sidewalls of the gate structure 2 and forming the air gap structure G on the sidewalls of the gate structure 2 includes: forming a first sacrificial sidewall on the sidewalls of the first gate structure 2A. Wall, remove the first sacrificial spacer to form the first air gap structure G1; form a second sacrificial spacer on the side wall of the second gate structure 2B, remove the second sacrificial spacer to form the second air gap structure G2.
  • first sacrificial spacers on the sidewalls of the first gate structure 2A and the second sacrificial spacers on the sidewalls of the second gate structure 2B can be formed simultaneously or in steps.
  • the thickness of the first sacrificial spacer and the second sacrificial spacer are the same; the first air gap structure G1 and the second air gap structure G2 are in a direction parallel to the substrate 1
  • the first sacrificial spacer and the second sacrificial spacer can be formed simultaneously, and the first air gap structure G1 and the second air gap structure G2 can be formed simultaneously to simplify the manufacturing process and ensure corresponding parasitic capacitances of the transistor devices in different areas.
  • the size remains consistent.
  • the thickness of the first sacrificial spacer is smaller than the thickness of the second sacrificial spacer.
  • the width W1 of the first air gap structure G1 in the direction parallel to the substrate 1 is smaller than the width W2 of the second air gap structure G2 in the direction parallel to the substrate 1 .
  • the first sacrificial sidewall and the second sacrificial sidewall can be formed in steps.
  • the first air gap structure G1 and the second air gap structure G2 can be formed simultaneously or step by step to control the first air gap structure G1 and the second air gap structure G2 to adopt different sizes respectively for transistor devices in different areas, thereby controlling The size of the corresponding parasitic capacitance.
  • first sacrificial sidewall and the second sacrificial sidewall are formed using a deposition process. Since the first spacing L1 between adjacent first gate structures 2A is smaller than the second spacing L2 between adjacent second gate structures 2B, in the same deposition process, the first spacing L1 between adjacent first gate structures 2A is deposited on the side of the first gate structure 2A. The thickness of the first sacrificial spacers on the wall is likely to be thicker, and the thickness of the second sacrificial spacers deposited on the sidewalls of the second gate structure 2B is likely to be thinner.
  • the first sacrificial sidewalls and the second sacrificial sidewalls are controlled by controlling the deposition rates of the first sacrificial sidewalls and the second sacrificial sidewalls respectively, the first sacrificial sidewalls and the second sacrificial sidewalls of the same thickness or a preset thickness can be formed correspondingly, thereby accurately controlling the first air gap structure.
  • the molding sizes of G1 and the second air gap structure G2 are used to balance the corresponding parasitic capacitances of the transistor devices in different areas by using the first air gap structure G1 and the second air gap structure G2.
  • the parasitic capacitances of the transistor devices in the unit array area R1 and the peripheral circuit area R2 can be balanced to make them consistent.
  • the transistor devices in the unit array area R1 and the peripheral circuit area R2 can be controlled to turn on according to a preset turn-on speed ratio, thereby avoiding problems affecting the performance of semiconductor structural devices due to inconsistent parasitic capacitance sizes.
  • some embodiments of the present disclosure provide a semiconductor structure formed by the method for preparing a semiconductor structure as described in some of the above embodiments.
  • the semiconductor structure includes: a substrate 1, a gate structure 2, an air gap structure G, a first dielectric layer 5 and a second dielectric layer 6.
  • the number of gate structures 2 is multiple, and the multiple gate structures 2 are spacedly arranged on the substrate 1 .
  • the air gap structure G is located on the side wall of the gate structure 2 .
  • the first dielectric layer 5 is located between the air gap structures G on the sidewalls of adjacent gate structures 2 .
  • the second dielectric layer 6 covers the top of the gate structure 2 , the top opening of the air gap structure G and the top of the first dielectric layer 5 .
  • the air gap structure G can be formed by forming sacrificial spacers of a predetermined thickness on the sidewalls of the gate structure 2 and removing the sacrificial spacers. In this way, the air gap structure G can be used to effectively isolate the gate structure 2 and effectively reduce the parasitic capacitance corresponding to the device where the gate structure 2 is located.
  • the semiconductor structure provided by the embodiments of the present disclosure has a simple manufacturing process, which facilitates implementation and reduces production costs.
  • the embodiments of the present disclosure can control the size of the air gap structure G in different devices to be preset sizes. In this way, balanced control of the parasitic capacitance corresponding to different devices can be achieved to effectively improve the device performance of the semiconductor structure. This can reduce the resistance-capacitance delay (RC-Delay) of the semiconductor structure.
  • the quiescent current of the transistor device in the semiconductor structure (ie: IDD current, which refers to the leakage current of the device when it is static) is proportional to the corresponding parasitic capacitance.
  • IDD current which refers to the leakage current of the device when it is static
  • an air gap structure G is provided on the side wall of the gate structure 2, which can reduce the corresponding parasitic capacitance and reduce the leakage current of the device, thereby reducing the power consumption of the transistor device when it is turned off, thereby effectively improving the transistor device. and the service life of semiconductor structures.
  • the substrate 1 is provided with a trench isolation structure (not shown in FIGS. 12 and 13 ), and the trench isolation structure can be used to divide multiple active regions in the substrate 1 to facilitate the integration of each transistor. formed in the corresponding active region. That is, the aforementioned gate structure 2, as a component of the transistor, can be disposed in the corresponding active area.
  • other components of the transistor can be implemented by referring to the implementation methods in the related art, which are not limited in the embodiments of the present disclosure.
  • the semiconductor structure further includes: a protective layer 3 covering part of the sidewall of the gate structure 2 .
  • the air gap structure G is located between the protective layer 3 and the first dielectric layer 5 .
  • the gate structure 2 includes: a metal layer 21 and a first barrier layer 22 located on the side of the metal layer 21 away from the substrate 1; wherein the protective layer 3 covers the metal layer 21 On the sidewalls, the first barrier layer 22 covers the metal layer 21 and the top of the protective layer 3 .
  • the first barrier layer 22 is one of a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a copper (Cu) layer, or a titanium nitride (TiN) layer.
  • the first barrier layer 22 is located on top of the metal layer 21 and the protective layer 3 and can protect the metal layer 21 from being damaged by etching during the preparation process of the semiconductor structure to ensure good electrical properties of the metal layer 21 .
  • the top of the first dielectric layer 5 is flush with the top of the first barrier layer 22 . That is to say, the first barrier layer 23 can directly serve as a grinding barrier layer during the formation of the first dielectric layer 5 , so that the first dielectric layer 5 between adjacent sacrificial spacers 4 can be directly formed without setting a mask. , to simplify the preparation process.
  • the gate structure 2 further includes a second barrier layer 23 .
  • the second barrier layer 23 is located between the substrate 1 and the metal layer 21 and the protective layer 3 .
  • the second barrier layer 23 is one of a tantalum (Ta) layer, a tantalum nitride (TaN) layer, a copper (Cu) layer, or a titanium nitride (TiN) layer.
  • the second barrier layer 23 is located between the metal layer 21 and the substrate 1 to prevent the metal layer 21 from contacting the oxide on the substrate 1 and being oxidized.
  • the semiconductor structure generally has a unit array region R1 and a peripheral circuit region R2 located on at least one side of the unit array region R1.
  • the cell array region R1 refers to a region in a semiconductor structure for forming a cell array, for example, a region for forming a memory cell array.
  • any memory cell in the memory cell array includes a transistor and a storage capacitor.
  • the peripheral circuit region R2 is located on at least one side of the cell array region R1, such as the side or the peripheral side.
  • the peripheral circuit region R2 refers to a region in the semiconductor structure for forming peripheral circuits.
  • peripheral circuits can be connected by multiple transistors and other electronic components (such as capacitors, resistors, etc.) according to design requirements to achieve specific functions.
  • W1 is the width of the first air gap structure G1 in the direction parallel to the substrate 1
  • W2 is the width of the second air gap structure G2 in the direction parallel to the substrate 1.
  • the first air gap structure G1 and the second air gap structure G2 can be formed simultaneously to simplify the manufacturing process and ensure that the corresponding parasitic capacitance sizes of the transistor devices in different regions remain consistent.
  • the distance between equivalent electrode plates refers to the distance in a direction parallel to the substrate 1 .
  • the dielectric constant ⁇ can be correspondingly controlled, thereby controlling the capacitance value of the parasitic capacitance.

Abstract

本公开涉及一种半导体结构及其制备方法。所述半导体结构的制备方法，包括：提供衬底，在衬底上形成间隔排布的多个栅极结构；在栅极结构的侧壁上形成预设厚度的牺牲侧墙；在相邻牺牲侧墙之间形成第一介质层，第一介质层顶部与栅极结构顶部及牺牲侧墙顶部平齐；去除牺牲侧墙，在栅极结构侧壁形成气隙结构；形成第二介质层，第二介质层覆盖栅极结构顶部、气隙结构顶部开口及第一介质层顶部。本公开提供的半导体结构及其制备方法，利于减小寄生电容并实现不同器件对应寄生电容大小的均衡控制，以有效提升半导体结构的器件性能。从而减小半导体结构的电阻电容延迟(RC-Delay)及提高半导体结构的使用寿命。

Description

半导体结构及其制备方法
相关申请的交叉引用
本公开要求于2022年06月07日提交中国专利局、申请号为202210634400.2、发明名称为“半导体结构及其制备方法”的中国专利的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体集成电路制造技术领域，特别是涉及一种半导体结构及其制备方法。
背景技术
随着半导体技术的发展，集成电路中器件的特征尺寸越来越小。在半导体工艺进入深亚微米阶段后，动态随机存储器(Dynamic Random Access Memory，简称DRAM)作为计算机等电子设备中常用的半导体结构，DRAM的尺寸越来越小。相应地，DRAM中各组成器件的尺寸及相邻器件之间的间距也越来越小。
目前，在DRAM的制备过程中，后道工序(Back end ofline，简称BEOL)用于建立若干层的导线，并使不同层的导线之间由导电孔相连。然而，导线及导电孔大多采用金属形成，容易使得相邻导线之间存在寄生电容。并且，随着器件特征尺寸的不断减小，前述导线之间的寄生电容会不断增大，导致DRAM中的电阻电容延迟(RC-Delay)效应明显，也容易降低DRAM中器件的使用寿命。
发明内容
根据本公开的各种实施例，本公开实施例提供了一种半导体结构及其制备方法。
根据一些实施例，本公开提供了一种半导体结构的制备方法，包括：提供衬底，在所述衬底上形成间隔排布的多个栅极结构；在所述栅极结构的侧壁上形成预设厚度的牺牲侧墙；在相邻所述牺牲侧墙之间形成第一介质层，所述第一介质层顶部与所述栅极结构顶部及所述牺牲侧墙顶部平齐；去除所述牺牲侧墙，在所述栅极结构侧壁形成气隙结构；形成第二介质层，所述第二介质层覆盖所述栅极结构顶部、所述气隙结构顶部开口及所述第一介质层顶部。
根据一些实施例，在所述栅极结构的侧壁上形成预设厚度的牺牲侧墙，包括：在所述 栅极结构和所述衬底表面形成厚度均匀的初始牺牲层；去除位于所述栅极结构顶部和所述衬底表面的初始牺牲层，以保留位于所述栅极结构侧壁上的初始牺牲层形成所述牺牲侧墙。
根据一些实施例，所述在所述栅极结构的侧壁上形成预设厚度的牺牲侧墙之前，所述制备方法还包括：形成覆盖所述栅极结构部分侧壁的保护层；所述牺牲侧墙覆盖所述保护层的外表面。
根据一些实施例，所述栅极结构包括金属层。所述在所述衬底上形成间隔排布的多个栅极结构，包括：在所述衬底上形成间隔排布的多个初始栅极结构，所述初始栅极结构包括初始金属层；氧化所述初始金属层的部分侧壁，形成所述保护层；未被氧化的初始金属层形成所述金属层。
根据一些实施例，氧化所述初始金属层的部分侧壁，包括：采用液态臭氧溶液处理。
根据一些实施例，所述栅极结构还包括第一阻挡层，所述第一阻挡层覆盖所述金属层和所述保护层的顶部。
根据一些实施例，在所述栅极结构的侧壁上形成预设厚度的牺牲侧墙之后，所述制备方法还包括，在相邻所述牺牲侧墙之间和所述栅极结构上方形成初始第一介质层，采用平坦化处理去除部分所述初始第一介质层，形成所述第一介质层；所述第一介质层顶部与所述第一阻挡层顶部平齐。
根据一些实施例，所述栅极结构还包括第二阻挡层，所述第二阻挡层位于所述衬底与所述金属层和所述保护层之间。
根据一些实施例，多个所述栅极结构包括多个第一栅极结构和多个第二栅极结构；其中，相邻所述第一栅极结构之间具有第一间距，相邻所述第二栅极结构之间具有第二间距，所述第一间距小于所述第二间距。在所述栅极结构的侧壁上形成预设厚度的牺牲侧墙及在所述栅极结构侧壁形成气隙结构包括：在所述第一栅极结构侧壁形成第一牺牲侧墙，去除所述第一牺牲侧墙形成第一气隙结构；在所述第二栅极结构侧壁形成第二牺牲侧墙，去除所述第二牺牲侧墙形成第二气隙结构。
根据一些实施例，所述第一牺牲侧墙和所述第二牺牲侧墙的厚度相同；所述第一气隙结构和所述第二气隙结构在平行于所述衬底方向的宽度相同。
根据一些实施例，所述第一牺牲侧墙的厚度小于第二牺牲侧墙的厚度；所述第一气隙结构在平行于所述衬底方向的宽度小于所述第二气隙结构在平行于所述衬底方向的宽度。
根据一些实施例，所述去除所述牺牲侧墙，包括：采用低温磷酸溶液处理，以去除所 述牺牲侧墙；其中，所述低温磷酸溶液的温度小于或等于120℃。
根据一些实施例，本公开另一方面提供了一种半导体结构，通过如上一些实施例所述的半导体结构的制备方法形成。所述半导体结构包括：衬底；多个栅极结构，间隔排布于所述衬底上；气隙结构，位于所述栅极结构侧壁；第一介质层，位于相邻所述栅极结构侧壁的气隙结构之间；以及，第二介质层，覆盖所述栅极结构顶部、所述气隙结构顶部开口及所述第一介质层的顶部。
根据一些实施例，所述半导体结构还包括：覆盖所述栅极结构部分侧壁的保护层；所述气隙结构位于所述保护层和所述第一介质层之间。
根据一些实施例，所述栅极结构包括：金属层以及位于所述金属层远离所述衬底一侧的第一阻挡层；其中，所述保护层覆盖所述金属层的侧壁，所述第一阻挡层覆盖所述金属层和所述保护层的顶部。
根据一些实施例，所述第一介质层顶部与所述第一阻挡层顶部平齐。
根据一些实施例，所述栅极结构还包括第二阻挡层，所述第二阻挡层位于所述衬底与所述金属层和所述保护层之间。
根据一些实施例，多个所述栅极结构包括多个第一栅极结构和多个第二栅极结构；其中，相邻所述第一栅极结构之间具有第一间距，相邻所述第二栅极结构之间具有第二间距，所述第一间距小于所述第二间距；其中，位于所述第一栅极结构侧壁的所述气隙结构为第一气隙结构，位于所述第二栅极结构侧壁的所述气隙结构为第二气隙结构；所述第一气隙结构和所述第二气隙结构在平行于所述衬底方向的宽度相同；或者，所述第一气隙结构在平行于所述衬底方向的宽度小于所述第二气隙结构在平行于所述衬底方向的宽度。
本公开实施例可以/至少具有以下优点：
在本公开实施例中，无需使用掩模版，通过在栅极结构侧壁上形成预设厚度的牺牲侧墙，便可以在去除该牺牲侧墙后形成预设尺寸的气隙结构，以利用气隙结构有效隔离栅极结构，并有效减小栅极结构所在器件的寄生电容。本公开实施例提供的前述方法工艺简单，也利于实施及降低生产成本。并且，本公开实施例通过控制不同器件中气隙结构的尺寸(例如气隙结构的高度及宽度)，还能够实现不同器件对应寄生电容大小的均衡控制，以有效提升半导体结构的器件性能。从而可以减小半导体结构的电阻电容延迟(RC-Delay)。
此外，半导体结构中晶体管器件的静态电流(即：IDD电流，是指器件静态时的漏电流)与对应寄生电容成正比。本公开实施例中在栅极结构的侧壁设置气隙结构，可以减小对应的寄生电容，并减小器件的漏电流，以降低晶体管器件关闭下的功耗，从而有效提高 晶体管器件及半导体结构的使用寿命。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中提供的一种半导体结构的制备方法的流程示意图；
图2为一实施例中提供的另一种半导体结构的制备方法的流程示意图；
图3～图5分别为一实施例中步骤S100对应中间结构及所得结构的剖面示意图；
图6为一实施例中步骤S150对应所得结构的剖面示意图；
图7～图8分别为一实施例中步骤S200对应中间结构及所得结构的剖面示意图；
图9～图10分别为一实施例中步骤S300对应中间结构及所得结构的剖面示意图；
图11为一实施例中步骤S400对应所得结构的剖面示意图；
图12为一实施例中步骤S500对应所得结构的剖面示意图；并且，图12亦为一实施例中一种半导体结构的结构示意图；
图13为一实施例中另一种半导体结构的结构示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上 面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
在此使用时，“沉积”工艺包括但不限于物理气相沉积(Physical Vapor Deposition，简称PVD)、化学气相沉积(Chemical Vapor Deposition，简称CVD)或原子层沉积(Atomic Layer Deposition，简称ALD)。
此外，这里参考作为本公开的理想实施例(和中间结构)的示意图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本公开的范围。
随着半导体技术的发展，集成电路中器件的特征尺寸越来越小。在半导体工艺进入深亚微米阶段后，DRAM的尺寸越来越小。相应的，DRAM中各组成元件的尺寸及相邻元件之间的间距也越来越小。
目前，在DRAM的制备过程中，后道工序(Back end ofline，简称BEOL)用于建立若干层的导线，并使不同层的导线之间由导电孔相连。然而，导线及导电孔大多采用金属形成，容易使得相邻导线之间存在寄生电容。并且，随着器件特征尺寸的不断减小，前述导线之间的寄生电容会不断增大，导致DRAM中的电阻电容延迟(RC-Delay)效应明显，也容易降低DRAM中器件的使用寿命。
基于此，本公开实施例提供了一种半导体结构及其制备方法，利于减小寄生电容并实现不同器件对应寄生电容大小的均衡控制，以有效提升半导体结构的器件性能。从而减小半导体结构的电阻电容延迟(RC-Delay)及提高半导体结构的使用寿命。
请参阅图1，本公开一些实施例提供了一种半导体结构的制备方法。所述制备方法包括步骤如下。
S100，提供衬底，在衬底上形成间隔排布的多个栅极结构。
S200，在栅极结构的侧壁上形成预设厚度的牺牲侧墙。
S300，在相邻牺牲侧墙之间形成第一介质层，第一介质层顶部与栅极结构顶部及牺牲侧墙顶部平齐。
S400，去除牺牲侧墙，在栅极结构侧壁形成气隙结构。
S500，形成第二介质层，第二介质层覆盖栅极结构顶部、气隙结构顶部开口及第一介质层顶部。
在本公开实施例中，无需使用掩模版，通过在栅极结构侧壁上形成预设厚度的牺牲侧墙，便可以在去除该牺牲侧墙后形成预设尺寸的气隙结构，以利用气隙结构有效隔离栅极结构，并有效减小栅极结构所在器件对应的寄生电容。本公开实施例提供的前述方法工艺简单，也利于实施及降低生产成本。并且，本公开实施例通过控制不同器件中气隙结构的尺寸(例如气隙结构的高度及宽度)，还能够实现不同器件对应寄生电容大小的均衡控制，以有效提升半导体结构的器件性能。从而可以减小半导体结构的电阻电容延迟(RC-Delay)。
此外，半导体结构中晶体管器件的静态电流(即：IDD电流，是指器件静态时的漏电流)与对应寄生电容成正比。本公开实施例中在栅极结构的侧壁设置气隙结构，可以减小对应的寄生电容，并减小器件的漏电流，以降低晶体管器件关闭下的功耗，从而有效提高晶体管器件及半导体结构的使用寿命。
请参阅图2，在本公开一些实施例中，在步骤S200于栅极结构的侧壁上形成预设厚度的牺牲侧墙之前，所述制备方法还包括：S150，形成覆盖栅极结构部分侧壁的保护层；牺牲侧墙覆盖保护层的外表面。
需要说明的是，栅极结构作为器件的控制元件，具备导电功能。在本公开一些实施例中，栅极结构包括金属层。在步骤S100中于衬底上形成间隔排布的多个栅极结构，包括：在衬底上形成间隔排布的多个初始栅极结构，初始栅极结构包括初始金属层；氧化初始金属层的部分侧壁，形成保护层；未被氧化的初始金属层形成金属层。如此，保护层可以基于初始金属层直接形成，有利于简化工艺，并确保后续工艺的执行不会对栅极结构的金属层产生不良影响，从而确保栅极结构的电学性能。
结合初始金属层的材料，在本公开一些实施例中，氧化初始金属层的部分侧壁，包括： 采用液态臭氧溶液处理。如此，可以在初始金属层的表面形成致密的金属氧化物作为保护层。
此外，在本公开一些实施例中，栅极结构还包括第一阻挡层，第一阻挡层覆盖金属层和保护层的顶部。在本公开一些实施例中，栅极结构还包括第二阻挡层，第二阻挡层位于衬底与金属层和保护层之间。由上，栅极结构可以有多种不同的实施方式，例如采用单层结构或多层结构，具体可以根据实际需求选择设置。
值得一提的是，在本公开一些实施例中，在步骤S200中于栅极结构的侧壁上形成预设厚度的牺牲侧墙，包括：在栅极结构和衬底表面形成厚度均匀的初始牺牲层；去除位于栅极结构顶部和衬底表面的初始牺牲层，以保留位于栅极结构的侧壁的初始牺牲层形成牺牲侧墙。
此处，初始牺牲层采用沉积工艺形成，其厚度可以根据需要选择设置。初始牺牲层的厚度均匀，可以确保后续形成于不同栅极结构侧壁上的牺牲侧墙具有相同厚度，进而可以形成在平行于衬底方向上具有相同宽度的气隙结构，以准确控制不同器件对应寄生电容的大小保持均衡。
在本公开一些实施例中，在步骤S200于栅极结构的侧壁上形成预设厚度的牺牲侧墙之后，所述制备方法还包括，在相邻牺牲侧墙之间和栅极结构上方形成初始第一介质层，采用平坦化处理去除部分初始第一介质层，形成第一介质层；第一介质层顶部与第一阻挡层顶部平齐。如此，可以利用第一阻挡层直接作为初始第一介质层平坦化的研磨阻挡层，也即，在采用平坦化处理去除部分初始第一介质层的过程中，无需设置掩模版也可以直接形成位于相邻牺牲侧墙之间的第一介质层，并确保第一介质层的顶部与第一阻挡层的顶部平齐，从而利于简化制备工艺。
为了更清楚地说明上述一些实施例中半导体结构的制备方法，请结合图3～图12理解，以下一些实施例以栅极结构包括层叠设置的第一阻挡层、金属层和第二阻挡层为例对该制备方法进行了详述。
在步骤S100中，请参阅图3～图5，提供衬底1，在衬底1上形成间隔排布的多个栅极结构2。
在一些实施例中，衬底1可以采用半导体材料、绝缘材料、导体材料或者它们的任意组合构成。衬底1可以为单层结构，也可以为多层结构。例如，衬底1可以是诸如硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导 体衬底。或者，还例如，衬底1可以是包括诸如Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗的层状衬底。
示例地，衬底1内设置有沟槽隔离结构(图3～图5中未示出)，可以利用在沟槽隔离结构在衬底1内划分出多个有源区，以便于将各晶体管形成于对应的有源区内。也即，前述的栅极结构2作为晶体管的组成部分，可以设置于对应的有源区。此外，晶体管的其他组成部分可以参见相关技术中的实施方式实施，本公开实施例对此不作限定。
在一些实施例中，栅极结构2包括层叠设置的第一阻挡层22、金属层21和第二阻挡层23。相应的，在衬底1上形成间隔排布的多个栅极结构2包括步骤如下。
如图3中所示，按照待形成的栅极结构2，在衬底1上依次层叠形成第二阻挡材料层230、金属材料层210和第一阻挡材料层220。其中，第二阻挡材料层230和第一阻挡材料层220的材料可以相同或不同。示例地，第二阻挡材料层230和第一阻挡材料层220的材料分别为钽(Ta)、氮化钽(TaN)、铜(Cu)或氮化钛(TiN)中的一种。金属材料层210的材料例如为铝(Al)。第二阻挡材料层230位于金属材料层210和衬底1之间，可以避免金属材料层210与衬底1上的氧化物接触而被氧化。第一阻挡材料层220位于金属材料层210顶部，可以保护金属材料层210不被刻蚀损伤，以确保金属材料层210的电学性能良好。
如图4中所示，在第一阻挡材料层220顶部涂覆光刻胶PR，并在光刻胶PR中形成掩模图案。掩模图案用于定义栅极结构2的形成位置。
如图5中所示，基于光刻胶PR中的掩模图案，刻蚀第一阻挡材料层220、金属材料层210和第二阻挡材料层230，可以分别形成第一阻挡层22、初始金属层21A和第二阻挡层23，以由第一阻挡层22、初始金属层21A和第二阻挡层23共同构成初始栅极结构。
此处，可以理解，金属材料层210在刻蚀后也可以直接形成金属层21。如此，第一阻挡层22、金属层21A和第二阻挡层23可以共同构成栅极结构2。也即，直接完成栅极结构2的制备。
本实施例中，金属材料层210在刻蚀后形成初始金属层21A，方便后续利用初始金属层21A的表面直接形成保护层3。
在步骤S150中，请参阅图6，形成覆盖栅极结构2部分侧壁的保护层3。
此处，保护层3可以采用沉积工艺形成于栅极结构2侧壁上，也可以采用其他方式形成。
示例地，在衬底1上形成间隔排布的多个初始栅极结构后，氧化初始金属层2A的部 分侧壁，形成保护层3。这样未被氧化的初始金属层2A形成金属层21。如此，保护层3可以基于初始金属层2A直接形成，有利于简化工艺，并确保后续工艺的执行不会对栅极结构2的金属层21产生不良影响，从而能够确保栅极结构2的电学性能。
示例地，氧化初始金属层2A的部分侧壁，包括：采用液态臭氧溶液处理。如此，可以在初始金属层2A的表面形成致密的金属氧化物作为保护层3。
此处，采用液态臭氧溶液处理，可以表现为：采用液态臭氧溶液清洗形成初始栅极结构后的晶圆，这样既能去除晶圆表面的微颗粒，也可以使得初始金属层21A暴露于空气中的侧壁被氧化而形成致密氧化物，例如在铝金属层的表面形成氧化铝薄膜作为保护层3。
此外，液态臭氧溶液可以与室温酸性溶液或冷冻去离子水一起使用，以有效清洁形成初始栅极结构后的晶圆而不含腐蚀性化学物质。这样可以因减少化学物质的使用而降低生产成本。并且，采用液态臭氧溶液处理所需工作空间较小，相比于采用化学物质进行湿法刻蚀的工作台操作，可以具有更快的工作效率，以提升生产效率。
示例地，保护层3的厚度不大于1nm。但并不仅限于此。
在步骤S200中，请参阅图7和图8，在栅极结构2的侧壁上形成预设厚度的牺牲侧墙4。
在半导体结构包括保护层3的示例中，牺牲侧墙4覆盖保护层3的外表面。
此处，牺牲侧墙4可以采用氮化物材料形成，例如氮化硅。牺牲侧墙4的厚度可以根据相邻栅极结构2之间的间距及待形成气隙结构G的相关尺寸设计确定。
示例地，步骤S200包括步骤如下。
如图7所示，在栅极结构2和衬底1表面形成厚度均匀的初始牺牲层4A。
此处，初始牺牲层4A采用沉积工艺形成，其厚度可以根据需要选择设置。在半导体结构还包括保护层3的示例中，初始牺牲层4A例如覆盖第一阻挡层22、保护层3及第二阻挡层23的外表面。
如图8所示，去除位于栅极结构2顶部和衬底1表面的初始牺牲层4A，以保留位于栅极结构2侧壁上的初始牺牲层4A形成牺牲侧墙4。
此处，位于栅极结构2顶部和衬底1表面的初始牺牲层4A可以采用干法刻蚀去除。这样初始牺牲层4A的厚度均匀，可以确保形成于不同栅极结构2侧壁上的牺牲侧墙4具有相同厚度，进而可以形成在平行于衬底1方向上具有相同宽度的气隙结构G，以准确控制不同器件对应寄生电容的大小保持均衡。
此外，可以理解，在干法刻蚀初始牺牲层4A后，基于刻蚀造成的材料损失，牺牲侧 墙4的顶部容易呈斜面，也即，牺牲侧墙4顶部与第一阻挡层22侧壁之间具有夹角，且该夹角呈锐角。
在步骤S300中，请参阅图9和图10，在相邻牺牲侧墙4之间形成第一介质层5，第一介质层5顶部与栅极结构2顶部及牺牲侧墙4顶部平齐。
示例地，步骤S300具体可以包括以下步骤。
如图9中所示，在相邻牺牲侧墙4之间和栅极结构2上方形成初始第一介质层5A。初始第一介质层5A的材料与牺牲侧墙4的材料不同，初始第一介质层5A可以采用氧化物沉积形成，例如氧化硅。初始第一介质层5A填充相邻牺牲侧墙4之间的间隔，并覆盖牺牲侧墙4和栅极结构2的顶部。
如图10中所示，采用平坦化处理去除部分初始第一介质层5A，形成第一介质层5。
此处，平坦化处理例如为化学机械研磨(Chemical Mechanical Polishing，简称CMP)。第一阻挡层23可以直接作为初始第一介质层5A平坦化的研磨阻挡层，也即，在采用平坦化处理去除部分初始第一介质层5A的过程中，无需设置掩模版也可以直接形成位于相邻牺牲侧墙4之间的第一介质层5，并确保第一介质层5的顶部与第一阻挡层23的顶部平齐，从而利于简化制备工艺。
在步骤S400中，请参阅图11，去除牺牲侧墙4，在栅极结构2侧壁形成气隙结构G。
在本公开一些实施例中，牺牲侧墙4采用氮化硅材料形成。牺牲侧墙4可以采用低温磷酸溶液去除。其中，低温磷酸溶液的温度小于或等于120℃。相较于高温磷酸溶液(例如温度大于150℃)，低温磷酸溶液对于氮化物和氧化物的刻蚀选择比更高。
无水纯净的磷酸是无色晶体，有吸湿性，易溶于水且可与水任意比互溶。本公开实施例中的低温磷酸溶液为无色粘稠的液体，其中磷酸的浓度占比例如为85％～98％。牺牲侧墙4采用低温磷酸溶液去除的反应机理，可以表现为：Si 3N 4+4H 3PO 4+12H 2O→3Si(OH) 4+4NH 4H 4PO 4。
结合前述一些实施例可知，牺牲侧墙4顶部与第一阻挡层22侧壁之间具有夹角，且该夹角呈锐角。这样在去除牺牲侧墙4以形成气隙结构G之后，气隙结构G的顶部容易收口且具有较小的顶部开口。
在步骤S500中，请参阅图12，形成第二介质层6，第二介质层6覆盖栅极结构2顶部、气隙结构G顶部开口及第一介质层5顶部。
此处，第二介质层6可以采用氧化物沉积形成，例如氧化硅。气隙结构G的顶部收口且具有较小的顶部开口，这样在沉积第二介质层6的过程中，第二介质层6容易封闭气隙 结构G的顶部开口并同步覆盖栅极结构2及第一介质层5的顶部。
值得一提的是，请参阅图13，在本公开一些实施例中，多个栅极结构2包括多个第一栅极结构2A和多个第二栅极结构2B；其中，相邻第一栅极结构2A之间具有第一间距L1，相邻第二栅极结构2B之间具有第二间距L2，所述第一间距L1小于所述第二间距L2。
此处，可以理解，半导体结构通常具有单元阵列区域R1以及位于单元阵列区域R1至少一侧的外围电路区域R2。此处，单元阵列区域R1是指：半导体结构中用于形成单元阵列的区域，例如形成存储单元阵列的区域。在DRAM中，存储单元阵列中的任一存储单元均包括晶体管及存储电容。外围电路区域R2位于单元阵列区域R1的至少一侧，例如旁侧或周侧。外围电路区域R2是指：半导体结构中用于形成外围电路的区域。在DRAM中，外围电路通过可以由多个晶体管以及其他电子元件(例如电容、电阻等)按照设计要求连接起来，以实现特定的功能。
为了方便描述，可以将位于单元阵列区域R1内的晶体管定义为单元晶体管，将位于外围电路区域R2的晶体管定义为外围晶体管，其中，相较于外围晶体管，单元晶体管可以具有更高的开启速度。相应的，前述第一栅极结构2A可以为单元晶体管的栅极结构，第二栅极结构2B可以为外围晶体管的栅极结构。这样在单元阵列区域R1内，相邻第一栅极结构2A之间的间距较小，如果仅采用第一介质层(例如氧化物)填充，容易产生较大的寄生电容，使得单元晶体管的开启速度降低很多。并且，在外围电路区域R2内，相邻第二栅极结构2B之间的间距较大，如果仅采用第一介质层(例如氧化物)填充，容易产生较小的寄生电容，使外围晶体管的开启速度保持不变或降低较少。从而导致单元晶体管和外围晶体管的读取速度均会因对应寄生电容造成的延迟而无法达到预期。
基于此，在栅极结构2的侧壁上形成预设厚度的牺牲侧墙4及在栅极结构2侧壁形成气隙结构G包括：在第一栅极结构2A侧壁形成第一牺牲侧墙，去除第一牺牲侧墙形成第一气隙结构G1；在第二栅极结构2B侧壁形成第二牺牲侧墙，去除第二牺牲侧墙形成第二气隙结构G2。
此处，可以理解，第一栅极结构2A侧壁上的第一牺牲侧墙以及第二栅极结构2B侧壁上的第二牺牲侧墙，可以同步形成，也可以分步形成。
请结合图13理解，在本公开一些实施例中，第一牺牲侧墙和第二牺牲侧墙的厚度相同；第一气隙结构G1和第二气隙结构G2在平行于衬底1方向的宽度相同。即，W1＝W2，其中，W1为第一气隙结构G1在平行于衬底1方向的宽度，W2为第二气隙结构G2在平行于衬底1方向的宽度。如此，第一牺牲侧墙和第二牺牲侧墙可以同步形成，第一气隙结 构G1和第二气隙结构G2可以同步形成，以简化制备工艺，同时确保不同区域内晶体管器件对应的寄生电容大小保持一致。
请结合图13理解，在本公开一些实施例中，第一牺牲侧墙的厚度小于第二牺牲侧墙的厚度。第一气隙结构G1在平行于衬底1方向的宽度W1小于第二气隙结构G2在平行于衬底1方向的宽度W2。如此，第一牺牲侧墙和第二牺牲侧墙可以分步形成。第一气隙结构G1和第二气隙结构G2可以同步或分步形成，以针对不同区域内的晶体管器件，控制第一气隙结构G1和第二气隙结构G2分别采用不同尺寸，进而控制相应寄生电容的大小。
需要补充的是，第一牺牲侧墙和第二牺牲侧墙采用沉积工艺形成。由于相邻第一栅极结构2A之间的第一间距L1小于相邻第二栅极结构2B之间的第二间距L2，因此，在同一沉积过程中，沉积于第一栅极结构2A侧壁上的第一牺牲侧墙厚度容易厚一点，沉积于第二栅极结构2B侧壁上的第二牺牲侧墙厚度容易薄一点。基于此，分别控制第一牺牲侧墙和第二牺牲侧墙的沉积速率，可以对应形成相同厚度或预设厚度的第一牺牲侧墙和第二牺牲侧墙，进而精确控制第一气隙结构G1和第二气隙结构G2的成型尺寸，以利用第一气隙结构G1和第二气隙结构G2均衡不同区域内晶体管器件对应的寄生电容。
例如，寄生电容电容值C的计算公式为：C＝∈S/d，其中，∈为介电常数，S为等效电极板之间的相对面积，d为等效电极板之间的距离。这样结合栅极结构2的设置位置，在栅极结构2等效为电极板的情况下，等效电极板之间的距离是指其在平行于衬底1方向上的距离。本公开实施例中，通过控制第一气隙结构G1及第二气隙结构G2在平行于衬底1方向的宽度，可以对应控制介电常数∈，进而实现对寄生电容电容值大小的控制。如此，可以均衡单元阵列区域R1和外围电路区域R2内晶体管器件的寄生电容，以使二者趋于一致。从而能够控制单元阵列区域R1和外围电路区域R2内晶体管器件按照预设的开启速度比进行开启，避免出现因寄生电容大小不一致而影响半导体结构器件性能的问题。
请参阅图12和图13，本公开一些实施例提供了一种半导体结构，通过如上一些实施例所述的半导体结构的制备方法形成。所述半导体结构包括：衬底1、栅极结构2、气隙结构G、第一介质层5和第二介质层6。栅极结构2的数量为多个，且多个栅极结构2间隔排布于衬底1上。气隙结构G位于栅极结构2侧壁。第一介质层5位于相邻栅极结构2侧壁的气隙结构G之间。第二介质层6覆盖栅极结构2顶部、气隙结构G顶部开口及第一介质层5的顶部。
在本公开实施例中，无需使用掩模版，气隙结构G可以通过在栅极结构2侧壁上形成 预设厚度的牺牲侧墙，并去除牺牲侧墙的方式形成。这样不仅可以利用气隙结构G有效隔离栅极结构2，并有效减小栅极结构2所在器件对应的寄生电容。本公开实施例提供的半导体结构制备工艺简单，利于实施及降低生产成本。并且，本公开实施例通过控制牺牲侧墙的形成厚度，可以控制不同器件中气隙结构G的尺寸为预设尺寸。这样能够实现不同器件对应寄生电容大小的均衡控制，以有效提升半导体结构的器件性能。从而可以减小半导体结构的电阻电容延迟(RC-Delay)。
此外，半导体结构中晶体管器件的静态电流(即：IDD电流，是指器件静态时的漏电流)与对应寄生电容成正比。本公开实施例中在栅极结构2的侧壁设置气隙结构G，可以减小对应的寄生电容，并减小器件的漏电流，以降低晶体管器件关闭下的功耗，从而有效提高晶体管器件及半导体结构的使用寿命。
在一些实施例中，衬底1可以采用半导体材料、绝缘材料、导体材料或者它们的任意组合构成。衬底1可以为单层结构，也可以为多层结构。例如，衬底1可以是诸如硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导体衬底。或者，还例如，衬底1可以是包括诸如Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗的层状衬底。
示例地，衬底1内设置有沟槽隔离结构(图12～图13中未示出)，可以利用在沟槽隔离结构在衬底1内划分出多个有源区，以便于将各晶体管形成于对应的有源区内。也即，前述的栅极结构2作为晶体管的组成部分，可以设置于对应的有源区。此外，晶体管的其他组成部分可以参见相关技术中的实施方式实施，本公开实施例对此不作限定。
需要补充的是，前述的气隙结构G可以不仅形成于栅极结构2的侧壁上，也可以延伸或应用至与栅极结构2相连的导线侧壁上，以进一步降低寄生电容及实现不同晶体管器件对应寄生电容大小的均衡控制，从而有效提升半导体结构的器件性能。
请继续参阅图12，在本公开一些实施例中，所述半导体结构还包括：覆盖栅极结构2部分侧壁的保护层3。气隙结构G位于保护层3和第一介质层5之间。
请继续参阅图12，在本公开一些实施例中，栅极结构2包括：金属层21以及位于金属层21远离衬底1一侧的第一阻挡层22；其中，保护层3覆盖金属层21的侧壁，第一阻挡层22覆盖金属层21和保护层3的顶部。
示例地，保护层3为金属氧化层，例如采用与金属层21相同的金属材料氧化形成。
示例地，第一阻挡层22为钽(Ta)层、氮化钽(TaN)层、铜(Cu)层或氮化钛(TiN) 层中的一种。第一阻挡层22位于金属层21及保护层3的顶部，可以保护金属层21在半导体结构的制备过程中不被刻蚀损伤，以确保金属层21的电学性能良好。
请继续参阅图12，在本公开一些实施例中，第一介质层5顶部与第一阻挡层22顶部平齐。这也就是说，第一阻挡层23可以直接作为第一介质层5形成过程中的研磨阻挡层，从而无需设置掩模版也可以直接形成位于相邻牺牲侧墙4之间的第一介质层5，以简化制备工艺。
请继续参阅图12，在本公开一些实施例中，栅极结构2还包括第二阻挡层23。第二阻挡层23位于衬底1与金属层21和保护层3之间。
示例地，第二阻挡层23为钽(Ta)层、氮化钽(TaN)层、铜(Cu)层或氮化钛(TiN)层中的一种。第二阻挡层23位于金属层21和衬底1之间，可以避免金属层21与衬底1上的氧化物接触而被氧化。
请参阅图13，在本公开一些实施例中，多个栅极结构2包括多个第一栅极结构2A和多个第二栅极结构2B；其中，相邻第一栅极结构2A之间具有第一间距L1，相邻第二栅极结构2B之间具有第二间距L2，所述第一间距L1小于所述第二间距L2；其中，位于第一栅极结构2A侧壁的气隙结构G为第一气隙结构G1，位于第二栅极结构2B侧壁的气隙结构G为第二气隙结构G2。
可以理解的是，半导体结构通常具有单元阵列区域R1以及位于单元阵列区域R1至少一侧的外围电路区域R2。此处，单元阵列区域R1是指：半导体结构中用于形成单元阵列的区域，例如形成存储单元阵列的区域。在DRAM中，存储单元阵列中的任一存储单元均包括晶体管及存储电容。外围电路区域R2位于单元阵列区域R1的至少一侧，例如旁侧或周侧。外围电路区域R2是指：半导体结构中用于形成外围电路的区域。在DRAM中，外围电路通过可以由多个晶体管以及其他电子元件(例如电容、电阻等)按照设计要求连接起来，以实现特定的功能。
为了方便描述，可以将位于单元阵列区域R1内的晶体管定义为单元晶体管，将位于外围电路区域R2的晶体管定义为外围晶体管。相应的，前述第一栅极结构2A可以为单元晶体管的栅极结构，第二栅极结构2B可以为外围晶体管的栅极结构。
请继续参阅图13，在一些示例中，第一气隙结构G1和第二气隙结构G2在平行于衬底1方向的宽度相同。即，W1＝W2，其中，W1为第一气隙结构G1在平行于衬底1方向的宽度，W2为第二气隙结构G2在平行于衬底1方向的宽度。如此，第一气隙结构G1和第二气隙结构G2可以同步形成，以简化制备工艺，同时确保不同区域内晶体管器件对 应的寄生电容大小保持一致。
请继续参阅图13，在另一些示例中，第一气隙结构G1在平行于衬底1方向的宽度W1小于第二气隙结构G2在平行于衬底1方向的宽度W2。如此，第一气隙结构G1和第二气隙结构G2可以同步或分步形成，以针对不同区域内的晶体管器件，控制第一气隙结构G1和第二气隙结构G2分别采用不同尺寸，进而控制相应寄生电容的大小。
例如，寄生电容电容值C的计算公式为：C＝∈S/d，其中，∈为介电常数，S为等效电极板之间的相对面积，d为等效电极板之间的距离。这样结合栅极结构2的设置位置，在栅极结构2等效为电极板的情况下，等效电极板之间的距离是指其在平行于衬底1方向上的距离。本公开实施例中，通过控制第一气隙结构G1及第二气隙结构G2在平行于衬底1方向的宽度，可以对应控制介电常数∈，进而实现对寄生电容电容值大小的控制。如此，可以均衡单元阵列区域R1和外围电路区域R2内晶体管器件的寄生电容，以使二者趋于一致。从而能够控制单元阵列区域R1和外围电路区域R2内晶体管器件按照预设的开启速度比进行开启，避免出现因寄生电容大小不一致而影响半导体结构器件性能的问题。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种半导体结构的制备方法，包括：
    提供衬底，在所述衬底上形成间隔排布的多个栅极结构；
    在所述栅极结构的侧壁上形成预设厚度的牺牲侧墙；
    在相邻所述牺牲侧墙之间形成第一介质层，所述第一介质层顶部与所述栅极结构顶部及所述牺牲侧墙顶部平齐；
    去除所述牺牲侧墙，在所述栅极结构侧壁形成气隙结构；
    形成第二介质层，所述第二介质层覆盖所述栅极结构顶部、所述气隙结构顶部开口及所述第一介质层顶部。
  2. 根据权利要求1所述的半导体结构的制备方法，其中，在所述栅极结构的侧壁上形成预设厚度的牺牲侧墙，包括：
    在所述栅极结构和所述衬底表面形成厚度均匀的初始牺牲层；
    去除位于所述栅极结构顶部和所述衬底表面的初始牺牲层，以保留位于所述栅极结构侧壁上的初始牺牲层形成所述牺牲侧墙。
  3. 根据权利要求1所述的半导体结构的制备方法，其中，
    所述在所述栅极结构的侧壁上形成预设厚度的牺牲侧墙之前，所述制备方法还包括：形成覆盖所述栅极结构部分侧壁的保护层；
    所述牺牲侧墙覆盖所述保护层的外表面。
  4. 根据权利要求3所述的半导体结构的制备方法，其中，所述栅极结构包括金属层；所述在所述衬底上形成间隔排布的多个栅极结构，包括：
    在所述衬底上形成间隔排布的多个初始栅极结构，所述初始栅极结构包括初始金属层；
    氧化所述初始金属层的部分侧壁，形成所述保护层；
    未被氧化的初始金属层形成所述金属层。
  5. 根据权利要求4所述的半导体结构的制备方法，其中，氧化所述初始金属层的部分侧壁，包括：采用液态臭氧溶液处理。
  6. 根据权利要求4所述的半导体结构的制备方法，其中，所述栅极结构还包括第一阻挡层，所述第一阻挡层覆盖所述金属层和所述保护层的顶部。
  7. 根据权利要求6所述的半导体结构的制备方法，其中，在所述栅极结构的侧壁上形成预设厚度的牺牲侧墙之后，所述制备方法还包括，
    在相邻所述牺牲侧墙之间和所述栅极结构上方形成初始第一介质层，采用平坦化处理去除部分所述初始第一介质层，形成所述第一介质层；所述第一介质层顶部与所述第一阻挡层顶部平齐。
  8. 根据权利要求4所述的半导体结构的制备方法，其中，所述栅极结构还包括第二阻挡层，所述第二阻挡层位于所述衬底与所述金属层和所述保护层之间。
  9. 根据权利要求1所述的半导体结构的制备方法，其中，
    多个所述栅极结构包括多个第一栅极结构和多个第二栅极结构；其中，相邻所述第一栅极结构之间具有第一间距，相邻所述第二栅极结构之间具有第二间距，所述第一间距小于所述第二间距；
    在所述栅极结构的侧壁上形成预设厚度的牺牲侧墙及在所述栅极结构侧壁形成气隙结构包括：在所述第一栅极结构侧壁形成第一牺牲侧墙，去除所述第一牺牲侧墙形成第一气隙结构；在所述第二栅极结构侧壁形成第二牺牲侧墙，去除所述第二牺牲侧墙形成第二气隙结构。
  10. 根据权利要求9所述的半导体结构的制备方法，其中，
    所述第一牺牲侧墙和所述第二牺牲侧墙的厚度相同；所述第一气隙结构和所述第二气隙结构在平行于所述衬底方向的宽度相同。
  11. 根据权利要求9所述的半导体结构的制备方法，其中，
    所述第一牺牲侧墙的厚度小于第二牺牲侧墙的厚度；所述第一气隙结构在平行于所述衬底方向的宽度小于所述第二气隙结构在平行于所述衬底方向的宽度。
  12. 根据权利要求1～11中任一项所述的半导体结构的制备方法，其中，所述去除所述牺牲侧墙，包括：采用低温磷酸溶液处理，以去除所述牺牲侧墙；
    其中，所述低温磷酸溶液的温度小于或等于120℃。
  13. 一种半导体结构，通过所述权利要求1-12任一项所述的半导体结构的制备方法形成，所述半导体结构包括：
    衬底；
    多个栅极结构，间隔排布于所述衬底上；
    气隙结构，位于所述栅极结构侧壁；
    第一介质层，位于相邻所述栅极结构侧壁的气隙结构之间；
    以及，第二介质层，覆盖所述栅极结构顶部、所述气隙结构顶部开口及所述第一介质层的顶部。
  14. 根据权利要求13所述的半导体结构，其中，所述半导体结构还包括：覆盖所述栅极结构部分侧壁的保护层；所述气隙结构位于所述保护层和所述第一介质层之间。
  15. 根据权利要求13所述的半导体结构，其中，所述栅极结构包括：金属层以及位于所述金属层远离所述衬底一侧的第一阻挡层；
    其中，所述保护层覆盖所述金属层的侧壁，所述第一阻挡层覆盖所述金属层和所述保护层的顶部。
  16. 根据权利要求15所述的半导体结构，其中，所述第一介质层顶部与所述第一阻挡层顶部平齐。
  17. 根据权利要求15所述的半导体结构，其中，所述栅极结构还包括第二阻挡层，所述第二阻挡层位于所述衬底与所述金属层和所述保护层之间。
  18. 根据权利要求15所述的半导体结构，其中，多个所述栅极结构包括多个第一栅极结构和多个第二栅极结构；
    其中，相邻所述第一栅极结构之间具有第一间距，相邻所述第二栅极结构之间具有第二间距，所述第一间距小于所述第二间距；
    其中，位于所述第一栅极结构侧壁的所述气隙结构为第一气隙结构，位于所述第二栅极结构侧壁的所述气隙结构为第二气隙结构；所述第一气隙结构和所述第二气隙结构在平行于所述衬底方向的宽度相同；或者，所述第一气隙结构在平行于所述衬底方向的宽度小于所述第二气隙结构在平行于所述衬底方向的宽度。
PCT/CN2022/099412 2022-06-07 2022-06-17 半导体结构及其制备方法 WO2023236243A1 (zh)

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WO2013166632A1 (zh) * 2012-05-08 2013-11-14 中国科学院微电子研究所 半导体器件及其制造方法
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