US20070096202A1 - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

Info

Publication number
US20070096202A1
US20070096202A1 US11551680 US55168006A US2007096202A1 US 20070096202 A1 US20070096202 A1 US 20070096202A1 US 11551680 US11551680 US 11551680 US 55168006 A US55168006 A US 55168006A US 2007096202 A1 US2007096202 A1 US 2007096202A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
layer
gate
gate structures
insulation layer
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11551680
Inventor
Dae-Woong Kang
Sung-nam Chang
Jin-Joo Kim
Kyong-Joo LEE
Eun-Jung Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/764Air gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11521Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11521Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region
    • H01L27/11524Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the memory core region with cell select transistors, e.g. NAND
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11568Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region

Abstract

Methods for forming semiconductor memory structures including air gaps between adjacent gate structures are provided. The volume of the air gaps is maximized and the width thereof made uniform in order to minimize the parasitic capacitance and any variance therein between the gate structures. The methods include forming an insulation layer between adjacent gate structures and subsequently etching the insulation layer to leave an air gap. Devices fabricated in accordance with the methods are also provided.

Description

  • This U.S. non-provisional application claims benefit of priority under 35 U.S.C.§119 from Korean Patent Application No. 2005-0103107, filed on Oct. 31, 2005, the entire contents of which are incorporated herein by reference.
  • BACKGROUND
  • 1. Technical Field
  • This disclosure generally relates to semiconductor devices and, more particularly, to semiconductor devices such as memory devices having an air gap defined between adjacent gate structures and methods of fabricating the same.
  • 2. Description of the Related Art
  • Among semiconductor devices, non-volatile memory devices are commonly used in consumer electronic devices because information can be retained in the device even when no power is supplied. Advances in consumer electronics cause demand for ever higher density memory devices. Efforts to manufacture devices meeting this demand often involve scaling down the sizes of gate structures and minimizing the space between adjacent gate structures.
  • Unfortunately, these efforts often result in increased parasitic capacitance between adjacent structures in the memory cell regions. Such increases in parasitic capacitance reduce the speed of the memory devices. Also, variation in parasitic capacitance between gate structures causes a variation in the threshold voltage for each gate structure, thereby degrading the reliability of memory devices.
  • FIG. 1 a is a circuit diagram of a typical NAND flash memory array, which is a popular type of non-volatile memory device. As shown in FIG. 1 a, the NAND flash memory array includes a string select line SSL, a ground select line GSL, a common source line CSL, a plurality of word lines W/L#0-31, and a plurality of bit lines BL crossing across the other lines. FIG. 1 b is a schematic plan view of a typical NAND flash memory array corresponding to FIG. 1 a. In FIG. 1 b, active regions 16 and bit line contacts 146 are illustrated together with floating gates 22. FIG. 1 c is a cross-sectional view of a NAND flash memory structure of FIG. 1 b taken along the wordline direction. In the wordline direction, a cell gate structure includes a control gate 24, an inter-gate dielectric layer 23, a floating gate 22, a tunnel oxide 21, and isolation regions 15 formed on a semiconductor substrate 10. FIG. 1 d is a cross-sectional view of the NAND flash memory structure of FIG. 1 b taken along the bitline direction. As shown in FIG. 1 d, in the bitline direction a cell gate structure includes the control gate 24, the inter-gate dielectric layer 23, the floating gate 22, the tunnel oxide 21, and impurity regions 16 formed on the semiconductor substrate 10.
  • FIG. 2 is a perspective view of a portion of a NAND memory cell array. The capacitances between various portions of the memory cell array and the voltages on some of the floating gates are identified in FIG. 2. For example, Vfg is a voltage at a central floating gate and Vcg is a voltage at a central control gate. Further, V1 and V2 are voltages between adjacent floating gates in the x-direction; and V3 and V4 are voltages between adjacent floating gates in the y direction. Furthermore, V5 and V6 are voltages between . . . In addition, C stands for parasitic overlap capacitance. Using the relationship Q=CV as applied to the structure in FIG. 2, Equation 1 and 2 are developed. Equation 1 describes the variation of the floating gate voltage (ΔVfg) in one of the NAND memory cells of FIG. 2 as a function of the surrounding capacitances and voltages. Δ V fg = C fgy ( Δ V 3 + Δ V 4 ) C ono + C tun + 2 C fgx + 2 C fgy + 2 C fgcg ( Equation 1 )
    As shown in Equation 1, decreasing Cfgy, the capacitance between adjacent floating gates 22 in the bitline direction, results in a decrease in the variation of the floating gate voltage (ΔVfg). Therefore, a low Cfgy improves the threshold voltage distribution among the cell gates in the memory cell array.
  • Equation 2 describes the floating gate voltage (Vfg) of one of the memory cells of FIG. 2 as a function of the surrounding voltages and capacitances. V fg = C ono * V cg + C fgx ( V 1 + V 2 ) + C fgy ( V 3 + V 4 ) + C fgcg ( V 5 + V 6 ) C ono + C tun + 2 C fgx + 2 C fgy + 2 C fgcg ( Equation 2 )
    As shown in Equation 2, decreasing Cfgy, results in an increase in Vfg. Consequently, the coupling ratio can be increased and the speed performance of the device can be improved.
  • From the analysis above, one method to improve device performance as device density is increased is to reduce the parasitic capacitance between adjacent floating gates. Typically, the spaces between adjacent floating gates are filled by an insulating layer whose dielectric constant is a primary factor in determining the capacitance between the adjacent floating gates. An insulating layer formed from a material having a higher dielectric constant will cause increased parasitic capacitance between adjacent gate structures. Consequently, it is desirable to form the dielectric layer from the lowest dielectric constant material possible.
  • Table 1 is a list of the approximate dielectric constants of several materials. Typical dielectric layers are formed from silicon oxide or silicon nitride materials. As shown in Table 1, these materials have dielectric constants of approximately 3.9 and 7.8, respectively. Air, on the other hand, has an approximate dielectric constant of 1.005. Consequently, a substantial reduction in the parasitic capacitance between adjacent gate structures can be achieved by replacing the silicon oxide or nitride dielectric material commonly used in semiconductor, e.g., memory structures with air. Further, it is desired to fill as much of the space between adjacent gates as possible with air, as opposed to another dielectric material, to minimize the parasitic capacitance.
    TABLE 1
    Material Dielectric Constant
    Vacuum 1
    (By definition)
    Air 1.005
    Polyethylene 2.25
    Paper 3
    Silicon oxide 3.9
    Silicon nitride 7.8
    Rubber 7
    Silicon 11.68
    Methyl alcohol 30
    Water 80
    Barium Titanate 1200
  • One approach to reduce parasitic capacitance between adjacent gate structures is disclosed in U.S. Published Patent Application No. 20050023597 to Kutsukake et al. (hereinafter referred to as “Kutsukake”). In Kutsukake, air gaps are formed between gate structures simultaneously with gate sidewall spacers due to the conformal dielectric layer deposition process. Another approach is disclosed in Korean Published Patent Application 2002-0081926, in which air gaps are formed by depositing a thicker spacer layer on an upper portion of gate sidewalls than on a bottom portion thereof. One disadvantage of these approaches is that the area between adjacent gates is largely filled with an oxide dielectric layer with a relatively small air pocket. Therefore, the parasitic capacitance between the gates is not reduced as much as it would be if substantially the entire area were filled by an air gap or pocket.
  • This disclosure overcomes this and other disadvantages of previous approaches to minimizing the parasitic capacitance between adjacent gate structures.
  • SUMMARY
  • This disclosure is directed to methods of forming air gaps between adjacent gate structures that maximizes the volume filled by the air gap in order to minimize the parasitic capacitance between the gate structures, as well as devices fabricated in accordance with the methods.
  • In one embodiment, a semiconductor device comprises at least two adjacent gate structures disposed on a semiconductor substrate; and an air gap extending between the gate structures, wherein the air gap is substantially rectangular in cross-section.
  • In another embodiment, a semiconductor device comprises at least two adjacent cell gate structures disposed on a semiconductor substrate, the cell gate structures adapted to store a charge; and a protection layer disposed on opposing sidewalls of the at least two adjacent gate structures, the protection layer defining an air gap between the at least two adjacent cell gate structures, the protection layer having opposing vertical portions, each disposed between the air gap and the opposing sidewalls of the at least two adjacent gate structure, and a horizontal portion, disposed between the air gap and the semiconductor substrate, the vertical portions each having a substantially uniform thickness.
  • As a result, the volume of the air gaps is maximized and the width thereof made uniform in order to minimize the parasitic capacitance and any variance therein between the gate structures.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing and other features and advantages of the disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the following drawings.
  • FIG. 1 a is a circuit diagram of a typical NAND flash memory array.
  • FIG. 1 b is a plan view of a typical NAND flash memory array corresponding to the schematic view of FIG. 1 a.
  • FIG. 1 c is a cross-sectional view of a NAND flash memory structure of FIG. 1 taken along the wordline direction.
  • FIG. 1 d is a cross-sectional view of a NAND flash memory structure of FIG. 1 taken along the bitline direction.
  • FIG. 2 is a perspective view of a NAND flash memory structure showing various voltages and capacitances associated with the structure.
  • FIG. 3 is a cross-sectional view of a non-volatile memory structure in accordance with an embodiment of the present invention.
  • FIGS. 4 through 10 are cross-sectional views illustrating a method of manufacturing a non-volatile memory structure in accordance with some embodiments.
  • FIG. 11 is a graph showing experimental results of programming speed for devices fabricated according to some embodiments.
  • FIG. 12 is a plot of endurance characteristics for various dielectric materials.
  • FIG. 13 is a plot of experimental results showing the threshold voltage distribution in a NAND flash memory for various dielectric materials.
  • DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
  • Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the spirit and teachings of this disclosure and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.
  • Example embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments may not be construed as limited to the particular shapes of regions illustrated herein but may be to include deviations in shapes that result, for example, from manufacturing.
  • FIG. 3 is a partial cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.
  • Referring to FIG. 3, a semiconductor device includes a plurality of gate structures, e.g., a ground select gate structure 127, a plurality of cell gate structures 126, a string select gate structure 128, and a high voltage gate structure 129. The gate structures may be fabricated on a semiconductor substrate 100 with the ground select, cell, and string select gate structures (127, 126, and 128, respectively) formed in a cell region A of the substrate 100, and the high voltage gate structure 129 formed in a peripheral region B of the substrate 100. Although not shown, a low voltage gate structure may also be formed in the peripheral region B. Each gate structure may include a tunneling dielectric pattern 121, a charge-storage layer 122, an inter-gate dielectric layer 123, a control gate 124, and a hard mask 125 sequentially stacked on the substrate 100. The cell gate structures 126 include the charge-storage layer 122 to store a charge therein for programming. The charge-storage layer 122 may be a polysilicon floating gate or a known charge-trap dielectric layer formed of a material such as silicon nitride or HfAlO. The charge-storage layer 122 may also be formed of a material including silicon nano-crystals. The ground select gate structure 127 and string select gate structure 128 each have a butting contact 141 to allow direct electrical contact through the gate structures to the charge-storage layer 122.
  • A protection layer 130 (refer briefly to FIG. 5) may cover the gate structures (126, 127, 128, and 129) and the substrate 100. Alternatively, the protection layer 130 may be omitted depending on applications, which will be explained further below.
  • A second insulation layer pattern 137 is disposed between adjacent cell gate structures 126, between the ground select gate structure 127 and a cell gate structure 126, and between the string select gate structure 128 and a cell gate structure 126. The second insulation layer pattern 137 and the protection layer 130, if formed, may collectively define a plurality of air gaps 134 between the adjacent gate structures. The air gaps 134 may be substantially rectangular in cross-section, as will be explained further below. The air gaps 134 may be formed self-aligned with opposing sidewalls of the at least two adjacent gate structures.
  • An upper insulation layer 138 covers the gate structures and the air gaps 134. The upper insulation layer 138 may seal the air gaps 134. A bottom portion of the upper insulation layer 138 may overlie the top of the air gaps 134.
  • Thus, in accordance with one embodiment of the invention, and as may be seen well in the cross-sectional view of FIG. 3, the air gaps 134 are substantially rectangular in cross-section, featuring preferably right-rectilinear sides and sharp, about ninety-degree corners. Moreover, the widths of rectangular air gaps 134 are highly uniform over their height. As will be seen by reference to FIG. 11, the performance of devices, especially the illustrated NAND flash memory, made in accordance with some embodiments of the invention exhibit significantly higher operating speeds than with prior art devices including those without an air gap of substantially rectangular shape and uniform width between adjacent gate structures.
  • Impurity regions 110 for forming source/drain regions are disposed between the gate structures and below the air gaps 134. The high voltage gate structure 129 may have associated impurity regions 113 including lightly doped drains (LDD) 111 and highly doped regions 112.
  • According to one aspect of the invention, a top of the cell gate structure 126 may be higher than a top of the air gaps 134.
  • According to another embodiment, other combinations of materials for forming the cell gate structures 126 and the substrate 100 are also possible within the spirit and scope of the present invention. For example, the cell gate structure 126 may be a SONOS cell gate structure that includes a silicon oxide tunneling dielectric pattern on a silicon substrate, a nitride (such as silicon nitride) charge-trap layer on the tunneling dielectric pattern, a silicon oxide inter-gate dielectric layer on the charge-trap layer, and a polysilicon control gate on the inter-gate dielectric layer. As another example, the cell gate structure 126 may be a SANOS cell gate structure that includes a silicon oxide tunneling dielectric pattern on a silicon substrate, a nitride (such as silicon nitride) charge-trap layer on the tunneling dielectric pattern, an aluminum oxide (Al2O3) inter-gate dielectric layer on the charge-trap layer, and a polysilicon control gate on the inter-gate dielectric layer. Yet another example would be a TANOS cell gate structure, which comprises a silicon oxide tunneling dielectric pattern on a silicon substrate, a silicon nitride charge-trap layer on the tunneling dielectric pattern, an aluminum oxide (Al2O3) inter-gate dielectric layer on the charge-trap layer, and a tantalum nitride (TaN) control gate on the inter-gate dielectric layer.
  • According to some embodiments, a gate group comprises a ground select gate structure 127, a string select gate structure 128, and a plurality of cell gate structures 126 disposed between the ground select gate structure 127 and the string select gate structure 128. In addition, a common source line 147 is formed adjacent the ground select gate structure 127.
  • In accordance with some embodiments, the ground select gate structure 127 and the string select gate structure 128 each have a first sidewall facing the cell gate structures 126 and a second sidewall opposite the first sidewall. The second insulation layer pattern 137, the protection layer 130, or both may be formed on the first sidewalls, but may not be placed on some or all of the second sidewalls.
  • With no protection layer 130 and/or the second insulation layer pattern 137 disposed on the second sidewall of the string select gate structure 128 facing (adjacent) a bit line contact 146 in a direct contact (DC) region, voids leading to shorts in the DC region, particularly between the bit line contacts 146 can be avoided. Further, when there is no protection layer 130 and/or second insulation layer pattern 137 disposed on the second sidewall of the ground select gate structure 127 facing the common source line 147, the devices can be further scaled down without reducing the width of the common source line 147. This prevents resistance from being increased in the area of the common source line 147.
  • Also, the second insulation layer pattern 137 may be or may not be placed on either sidewall of the high voltage gate structure 129 depending on applications.
  • As discussed in the background, it is desirable to maximize the volume of the air gaps 134 between adjacent charge-storage layers 122 in order to minimize the parasitic capacitances. To accomplish this, the air gap 134 may be substantially rectangular in cross-section. Also, the air gap 134 may have a substantially uniform width along most if not all of their height. The width of each air gap 134 may be measured from one sidewall of the air gap 134 to the opposite sidewall of the air gap 134 along the direction parallel to the plane of the substrate 100. In order to have a substantially uniform width, the air gaps 134 may have substantially vertical sidewalls with respect to the substrate 100. The air gaps 134 may also have substantially horizontal tops and bottoms. The air gaps 134 may extend along substantially the entire sidewalls of the charge-storage layer patterns 122. In other words, the air gaps 134 may extend vertically from the substrate 100 to an extent greater than or equal to the vertical extent of the charge-storage layers 122. However, the air gaps 134 may not need to extend along the entire sidewalls of the charge-storage layer patterns 122 depending on applications.
  • Those of skill in the art will appreciate that the substantially uniform width of the air gaps 134 in accordance with one embodiment of the invention, while minimizing parasitic capacitance due to greater air gap volume, also minimizes any variation in parasitic capacitance over most if not all of the height of the air gap. This is due to the verticality of the sidewalls and due to the uniformity of width of the air gaps that produces the substantially rectangular cross-section of the air gaps 134. Unlike with prior art devices featuring curved or tapered sidewalls of variable width that produce air gaps of inversely variable width, the invented devices have air gaps 134 the dielectric value of which is substantially the same over the substantial height of the air gaps 134. This minimizes variation in parasitic capacitance at various heights or near various irregular features of the air gaps 134 and their surrounding sidewalls that undesirably produce more parasitic capacitance near the tops and bottoms of the air gaps than near the middles of the air gaps as typified by the prior art teardrop-shaped or oval air gaps). Thus, with features of the present invention, the reliability of the semiconductor devices can be substantially improved.
  • According to some embodiments the protection layer 130 may be formed conformally on the sidewalls of the gate structures, e.g., 126 and on the substrate 100 so as to form the sidewalls and bottoms of the air gaps 134. Vertical portions of the protection layer 130, disposed on opposing sidewalls of adjacent gate structures thereby defining the sidewalls of the air gaps 134, may have a substantially uniform thickness throughout the vertical extent of the air gaps 134. Horizontal portions of the protection layer 130, defining the bottoms of the air gaps 134, may have a substantially uniform thickness as well.
  • According to some other aspects of the present invention, the thickness of the vertical portions and the horizontal portions may be substantially the same. The inner sidewall of the vertical portions may form an approximately 90 degree angle with a top surface of the horizontal portions. The vertical portions of the protection layer 130 may be said to have an inner sidewall and an outer sidewall, the outer sidewall adjoining the sidewalls of the gate structures, and the inner sidewall may be substantially parallel with the sidewalls of the gate structures.
  • In accordance with some embodiments, the second insulation layer pattern 137 and the protection layer 130 may form a spacer layer pattern on the sidewalls of the gate structures, e.g., 126. In this case, the spacer layer pattern may include an upper portion and a lower portion. And the lower portion may have a substantially uniform thickness along substantially the entire sidewalls of the gate structures. If the protection layer 130 is not used, the second insulation layer pattern 137 alone forms the spacer layer pattern on an upper portion of the sidewalls of the gate structures. In this case, the spacer layer pattern may not be formed between the air gaps 134 and the sidewalls of the gate structures. In other words, the sidewalls of the gate structures may directly define the sidewalls of the air gaps 134. Thus, if the protection layer 130 is not formed, the air gaps 134 may be primarily defined by the opposing sidewalls of the gate structure, e.g. 126 and the second insulation layer pattern 137.
  • Further, if the protection layer 130 is not used to form the air gaps 134, the inter-gate dielectric layer 123 has an etch selectivity with respect to the first insulation layer 132 as will be further explained below in conjunction with FIGS. 5-6.
  • The spacer layer pattern may overhang a portion of the tops of the air gaps 134. The upper insulation layer 138 may cover the remaining portion of the tops of the air gaps 134. The protection layer pattern 130 may also not be formed between bottoms of the air gaps 134 and the substrate 100. In other words, the substrate 100 may directly define the bottoms of the air gaps 134.
  • FIGS. 4 through 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with some embodiments of the present invention.
  • Referring to FIG. 4, manufacturing a semiconductor device, e.g., a flash memory structure includes forming a ground select gate structure 127, a string select gate structure 128, and a plurality of cell gate structures 126, between the ground select gate structure 127 and the string select gate structure 128, on a cell region A of a semiconductor substrate 100, and forming a high voltage gate structure 129 or a low voltage gate structure (not shown) on a peripheral region B of the substrate 100. The gate structures each may include a tunneling dielectric pattern 121, a charge-storage layer 122, an inter-gate dielectric layer 123, a control gate 124, and a hard mask 125, which are sequentially stacked. The hard mask 125 may comprise high-temperature oxide (HTO), nitride or other suitable material. The gate structures are then used as implantation masks for self-aligned formation of source/drain regions 110 in the cell region A and LDD regions 111 in the peripheral region B.
  • Referring to FIG. 5, a protection layer 130 may be conformally formed over the gate structures and the substrate 100, thereby covering the top and the sidewalls of the gate structures. Then, a first insulation layer 132 may be formed over the protection layer 130. The protection layer 130 may act as an etch stop layer during subsequent etch processes. The protection layer 130 may have an etch selectivity with respect to the first insulation layer 132. As an example, the protection layer 130 may be, but not limited to, a silicon nitride layer and the first insulation layer 132 may be a silicon oxide layer, for example. Specifically, the first insulation layer 132 may be a medium temperature oxide (MTO) layer deposited by a low pressure chemical vapor deposition (LPCVD) process, for instance. Also, the protection layer 130 may comprise any material having an etch selectivity with the first insulation layer 132.
  • According to some embodiments though, the protection layer 130 may not be formed, in which case, the first insulation layer 132 be directly formed on the top and the sidewalls of the gate structures. In this case, the inter-gate dielectric layer 123 may have an etch selectivity with the first insulation layer 132.
  • Referring to FIG. 6, a portion of the first insulation layer 132 is then removed, e.g., etched to form a first insulation layer pattern 133. The etching of the first insulation layer 132 may expose a region of the sidewalls of the gate structures. The first insulation layer pattern 133 is thus formed on the sidewalls of the gate structures and above the source/drain regions 110. In other words, the first insulation layer pattern 133 extends between the adjacent gate structures. If the protection layer 130 is used, it remains on the tops and sidewalls of the gate structures and on the substrate 100 after the etching of the first insulation layer 132 as shown.
  • Referring to FIG. 7, a photoresist pattern 135 may be formed covering the cell region A. Impurity regions 113 are then formed around the high voltage gate structure 129 by forming highly-doped regions 112 in addition to the already-formed LDD regions 111 in the peripheral region B. The highly-doped regions 112 may be formed by ion implantation using the high voltage gate structure 129 and the first insulation layer pattern 133 as an implantation mask.
  • Referring to FIGS. 8 and 9, the photoresist pattern 135 is removed using conventional techniques such as ashing. Then, a second insulation layer 136 is formed over the protection layer 130 (if used) and the first insulation layer pattern 133. The second insulation layer 136 is partially etched or etched back to form the second insulation layer pattern 137. The second insulation layer pattern 137 has an opening 131 to expose an upper surface of the first insulation layer pattern 133. If the protection layer 130 is used, the etching of the second insulation layer 136 may include an etching of a portion of the protection layer 130, thereby exposing the top and a portion of the sidewalls of the hard mask 125.
  • Referring to FIG. 10, the first insulation layer pattern 133 is then selectively removed by, for example, etching through the opening 131 defined by the second insulation layer pattern 137, to form the air gaps 134. The air gaps 134 are substantially rectangular in cross-section to maximize the size of the air gap 134 and to minimize the adverse effect of parasitic capacitance between adjacent gate structures (and, as indicated above, further to minimize variances in any parasitic capacitance, i.e. to render uniform the parasitic capacitance, therebetween over the substantial height of the air gap 134).
  • If the protection layer 130 is used, the protection layer 130 may define the sidewalls and bottoms of the air gaps 134. In this case, the air gaps 134 may be substantially surrounded by the protection layer 130 and the second insulation layer pattern 137. If the protection layer 130 is not used, the gate structures may directly define the sidewalls of the air gaps 134 and the substrate 100 may directly define the bottoms of the air gaps 134 as discussed above.
  • Wet etching may be used to remove the first insulation layer pattern 133. For example, hydrofluoric acid may be used to etch the first insulation layer pattern 133. The second insulation layer pattern 137 and/or the protection layer 130 may act as an etch stop during the process for removing the first insulation layer pattern 133.
  • Once the first insulation layer pattern 133 has been removed, a portion of the second insulation layer pattern 137 may form an overhang over the tops of the air gaps 134. If the protection layer 130 is used, it will prevent the gate structure, particularly the inter-gate dielectric layer 123 from being etched while the first insulation layer pattern 133 is removed, e.g., etched. If the protection layer 130 is not used, it is desirable that the inter-gate dielectric layer 123 have an etch selectivity with respect to the first insulation layer pattern 133 to protect itself from the etchant, as discussed above.
  • According to one aspect of the invention, any remaining portions of the second insulation layer pattern 137 and/or the protection layer 130 may be removed from one sidewall of the string select gate structure 128 and one sidewall of the ground select gate structure 127 as discussed above with reference to FIG. 3 although not illustrated. For example, in the cell region A, a region between adjacent string select gate structures 128, i.e., a DC region in which the bit line contact 146 is formed, may be opened while other regions are covered by, for example, a photoresist pattern. Then, the spacer layer pattern, i.e., the protection layer 130 and/or the second insulation layer pattern 137 may be selectively removed from one of the sidewalls of the string select gate structures 128 in the DC region by, for example, wet etching using phosphoric acid or dry etching. As a result, the spacer layer pattern is formed selectively not to extend along one of the sidewalls of the string select gate 128 adjacent the bit line contact 146.
  • In addition, the spacer layer pattern, i.e., the protection layer 130 and/or the second insulation layer pattern 137, may be selectively removed from one of the sidewalls of the ground select gate structure 127 near the common source line 147, using the immediately-above described method. As a result, the spacer layer pattern is formed selectively not to extend along one of the sidewalls of the ground select gate structure 127 facing the common source line 147.
  • Also, in the peripheral region B, the spacer layer pattern may also be selectively removed from the high voltage gate structure 129 or the low voltage structure using the above method described to remove the spacer layer pattern in the cell region A. However, the spacer layer pattern may remain in the peripheral region B.
  • Referring again to FIG. 3, an interlayer insulation layer 138 is then formed to cover the gate structures and the air gaps 134. Therefore, a bottom portion of the interlayer insulation layer directly overlies a top of the air gaps 134.
  • Afterwards, although not shown, a bit line is formed on the resulting structure to be coupled to one of the plurality of impurity regions 110 via the bit line contact 146 adjacent the string select gate structure 128 from which the spacer layer pattern is removed
  • FIG. 11 is a graph showing experimental results of programming speed for devices fabricated according to some embodiments of the present invention.
  • Referring to FIG. 11, NAND flash structures were formed and tested using various dielectric materials between adjacent gate structures. The program voltage was estimated to be about 20V. The experimental results show that higher programming speed was achieved for the device structures having an air gap according to some embodiments, than either of the conventional silicon oxide or nitride materials without such an air gap between gate structures.
  • FIG. 12 is a plot of endurance characteristics for various dielectric materials.
  • Referring to FIG. 12, the plot compares the endurance characteristics of a 1 Gbit NAND flash memory cell having a rectangular air gap defined between adjacent gate structures to cells using silicon nitride (SiN) or oxide filled between the gate structures without such an air gap. The plot shows that after extensive program/erase (P/E) cycling, negligible difference in the Vth distribution between the device fabricated according to some embodiments of the present invention and the cells having silicon nitride (SiN) or oxide filled between the gate structures without such an air gap is observed. Therefore, the endurance characteristics of the cell are not degraded by having an air gap as discussed above as opposed to the conventional structures.
  • FIG. 13 is a plot of experimental results showing the threshold voltage distribution in a 1 Gbit NAND flash memory for various dielectric materials.
  • Referring to FIG. 13, the plot compares the cell threshold voltage (Vth) distribution of a 1 Gbit NAND flash memory cell using a single pulse program. The plot shows that the Vth distribution is dramatically improved with the cells formed according to some embodiments of the present invention as opposed to the cells formed using prior art methods having oxide or silicon nitride (SiN) filled between gate structures without air gaps. This improvement in Vth distribution is believed to be due to the improved floating gate voltage shift with the air gap.
  • Semiconductor devices, e.g., non-volatile memory devices formed according to some of the embodiments described herein can be used in various electronic systems such as cellular phones, digital cameras, digital televisions, and video game systems. Additionally, the memory devices can be used in various types of memory cards such as Compact Flash, Memory Stick, xD Picture Card, Smart Media, and other multimedia card types. Further, non-volatile memory devices may be operatively coupled with other types of semiconductor devices, such as dynamic random access memory (DRAM) devices and/or microprocessors, in the foregoing applications. In some cases, a non-volatile memory such as a NAND flash memory device and a DRAM device may be incorporated together in a single integrated circuit (IC) package, also known as a ND chip.
  • The foregoing description is illustrative and is not to be construed as limiting of the disclosure. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the disclosure. For example, the embodiments have been described with respect to NAND flash memory applications, but the inventive principles could also be applied to other types of memory devices, such as NOR-type flash memories. Accordingly, all such modifications are intended to be included within the scope of the disclosure as defined in the claims.

Claims (46)

  1. 1. A semiconductor device comprising:
    at least two adjacent gate structures disposed on a semiconductor substrate, the at least two adjacent gate structures having an air gap defined therebetween, the air gap being substantially rectangular in cross-section.
  2. 2. The device of claim 1, wherein the air gap is formed self-aligned with opposing sidewalls of the at least two gate structures.
  3. 3. A semiconductor device comprising:
    at least two adjacent cell gate structures disposed on a semiconductor substrate, the cell gate structures adapted to store a charge; and
    a protection layer disposed on opposing sidewalls of the at least two adjacent gate structures, the protection layer defining an air gap between the at least two adjacent cell gate structures, the protection layer having opposing vertical portions, each disposed between the air gap and the opposing sidewalls of the at least two adjacent gate structures, and a horizontal portion, disposed between the air gap and the semiconductor substrate, the vertical portion having a substantially uniform thickness.
  4. 4. The device of claim 3, wherein the horizontal portion of the protection layer is formed conformally on the semiconductor substrate so as to have a substantially uniform thickness.
  5. 5. The device of claim 3, wherein the vertical portion of the protection layer has an inner sidewall and an outer sidewall opposite the inner sidewall, the outer sidewall adjoining the sidewalls of the gate structures, the inner sidewall being substantially parallel with the sidewalls of the gate structures.
  6. 6. The device of claim 3, wherein the thickness of the vertical portion is substantially equal to the thickness of the horizontal portion.
  7. 7. The device of claim 3, wherein the gate structures each comprise a tunneling dielectric pattern, a charge-storage layer, an inter-gate dielectric, a control gate, which are sequentially stacked, the air gap extending between adjacent charge-storage layers.
  8. 8. The device of claim 7, wherein the charge-storage layer is a charge-trap dielectric layer or a polysilicon floating gate.
  9. 9. The device of claim 3, wherein the gate structures include a tunnel oxide layer, a nitride layer, another oxide layer, and a polysilicon layer, which are sequentially formed, to form a SONOS cell gate structure.
  10. 10. The device of claim 3, wherein the gate structures include a tunnel oxide layer, a nitride layer, an Al2O3 layer, and a TaN layer, which are sequentially formed, to form a TANOS cell gate structure.
  11. 11. The device of claim 3, wherein the gate structures include a tunnel oxide layer, a nitride layer, an Al2O3 layer, and a polysilicon layer, which are sequentially formed, to form a SANOS cell gate structure.
  12. 12. The device of claim 3, further comprising an interlayer insulation layer sealing the air gap.
  13. 13. The device of claim 12, wherein a bottom portion of the interlayer insulation layer directly overlies a top of the air gap.
  14. 14. The device of claim 2, wherein an inner sidewall of the vertical portion and a top surface of the horizontal portion form an approximately 90 degree angle.
  15. 15. A semiconductor device comprising:
    at least two adjacent memory cell gate structures disposed on a semiconductor substrate, the at least two adjacent memory cell gate structures having an air gap disposed therebetween, the air gap having a substantially uniform width over its height.
  16. 16. The semiconductor device of claim 15, wherein the cell gate structures each include:
    a tunneling dielectric pattern;
    a charge-storage layer disposed on the tunneling dielectric pattern;
    an inter-gate dielectric layer disposed on the charge-storage layer; and
    a control gate disposed on the inter-gate dielectric layer,
    wherein the air gap extends along at least a substantially entire sidewall of the charge-storage layer.
  17. 17. The semiconductor device of claim 16, wherein the charge-storage layer comprises a material chosen from nitride, polysilicon, and silicon nano-crystals.
  18. 18. The device of claim 16, wherein a top of the cell gate structure is higher than a top of the air gap.
  19. 19. A non-volatile semiconductor memory device comprising:
    a semiconductor substrate comprising:
    a cell region; and
    a peripheral region;
    a plurality of gate structures formed on the cell region, the plurality of gate structures including:
    a ground select gate and a string select gate disposed on the cell region, the ground select gate and the string select gate spaced apart from each other; and
    a plurality of cell gate structures disposed between the ground select gate and the string select gate, wherein each cell gate structure comprises:
    a tunneling dielectric pattern on the semiconductor substrate;
    a charge-storage layer disposed on the tunneling dielectric pattern;
    an inter-gate dielectric layer disposed on the charge-storage layer; and
    a control gate disposed on the inter-gate dielectric layer;
    a spacer layer pattern disposed on opposing sidewalls of the plurality of gate structures, the spacer layer pattern defining a plurality of air gaps between adjacent gate structures, wherein the air gaps are substantially rectangular in cross-section;
    an interlayer insulation layer disposed so as to cover the ground select gate, the string select gate, the plurality of cell gate structures, and the plurality of air gaps; and
    a plurality of impurity regions disposed below the air gaps and between the gate structures; and
    a bit line overlying the interlayer insulation layer, the bit line coupled to one of the plurality of impurity regions via a bit line contact.
  20. 20. The device of claim 19, wherein the spacer layer pattern is formed selectively not to extend along one of the sidewalls of the string select gate adjacent the bit line contact.
  21. 21. The device of claim 20, further comprising a common source line disposed adjacent the ground select gate, wherein the spacer layer pattern is formed selectively not to extend along one of the sidewalls of the ground select gate facing the common source line.
  22. 22. The device of claim 19, wherein the spacer layer pattern comprises an upper portion and a lower portion, the lower portion having a substantially uniform thickness along substantially the entire sidewalls of the gate structures.
  23. 23. The device of claim 22, wherein the upper portion of the spacer layer pattern overhangs the tops of the air gaps and the interlayer insulation layer covers the remaining portion of the tops of the air gaps.
  24. 24. A method comprising:
    forming at least two adjacent gate structures on a semiconductor substrate;
    forming a first insulation layer pattern covering a portion of opposing sidewalls of the at least two adjacent gate structures, the first insulation layer pattern extending between the at least two adjacent gate structures;
    forming a second insulation layer pattern over a portion of the first insulation layer pattern between the at least two adjacent gate structures, wherein the second insulation layer pattern having an opening to expose a top surface of the first insulation layer pattern; and
    removing the first insulation layer pattern, thereby forming an air gap between the at least two adjacent gate structures.
  25. 25. The method of claim 24, wherein forming a first insulation layer pattern comprises:
    forming a first insulation layer covering the top and the sidewalls of the gate structures; and
    etching a portion of the first insulation layer so as to expose the portion of the sidewalls of the gate structures.
  26. 26. The method of claim 24, wherein the gate structure comprises a charge-storage layer, an inter-gate dielectric layer, and a control gate, the first insulation layer having an etch selectivity with respect to the inter-gate dielectric layer.
  27. 27. The method of claim 24, wherein forming a second insulation layer pattern comprises:
    forming a second insulation layer over the first insulation layer pattern; and
    partially etching the second insulation layer to expose the top surface of the first insulation layer.
  28. 28. The method of claim 24, which further comprises forming a protection layer on a top and the sidewalls of the at least two adjacent gate structures before forming the first insulation layer pattern.
  29. 29. The method of claim 28, wherein the protection layer has an etch selectivity with respect to the first insulation layer pattern.
  30. 30. The method of claim 24, which further comprises forming an interlayer insulation layer directly overlying the air gap.
  31. 31. A method of manufacturing a semiconductor device comprising:
    forming at least two adjacent cell gate structures on a semiconductor substrate;
    forming a protection layer covering a top and sidewalls of the at least two cell gate structures;
    forming a first insulation layer overlying the protection layer;
    etching a portion of the first insulation layer to form the first insulation layer pattern that exposes a portion of the sidewalls of the gate structures;
    forming a second insulation layer over the first insulation layer and the exposed sidewalls of the gate structures;
    etching a portion of the second insulation layer to form a second insulation layer pattern having an opening that exposes an upper surface of the first insulation layer; and
    removing the first insulation layer pattern, using the second insulation layer pattern and the protection layer as a mask, thereby forming an air gap between the sidewalls of the at least two adjacent gate structures.
  32. 32. The method of claim 31, wherein the air gap is substantially rectangular in cross-section.
  33. 33. The method of claim 31, wherein each gate structure comprises a tunneling dielectric layer, a charge-storage layer, an inter-gate dielectric layer, and a control gate, which are sequentially formed on the semiconductor substrate, the air gap extending along substantially the entire sidewalls of the charge-storage layer.
  34. 34. The method of claim 31, wherein the first insulation layer has an etch selectivity with respect to both the protection layer and the second insulation layer pattern.
  35. 35. The method of claim 31, wherein the first insulation layer comprises silicon oxide, and wherein the protection layer and the second insulation layer pattern each comprise silicon nitride such that the air gap is substantially surrounded by the protection layer and the second insulation layer pattern.
  36. 36. The method of claim 31, wherein removing the first insulation layer pattern comprises a wet etching process.
  37. 37. The method of claim 36, wherein the wet etching process comprises hydrofluoric acid.
  38. 38. A method of manufacturing a semiconductor memory device, the method comprising:
    forming a tunneling dielectric pattern on a semiconductor substrate having a cell region and a peripheral region;
    forming a plurality of gate structures formed on the cell region, the plurality of gate structures including:
    a ground select gate and a string select gate disposed on the cell region, the ground select gate and the string select gate spaced apart from each other; and
    a plurality of cell gate structures disposed between the ground select gate and the string select gate, wherein each cell gate structure comprises:
    a tunneling dielectric pattern on the semiconductor substrate;
    a charge-storage layer disposed on the tunneling dielectric pattern;
    an inter-gate dielectric layer disposed on the charge-storage layer; and
    a control gate disposed on the inter-gate dielectric layer;
    forming spacer layer patterns on opposing sidewalls of the plurality of gate structures, the spacer layer patterns defining a plurality of air gaps between adjacent gate structures, wherein the air gaps are substantially rectangular in cross-section;
    forming an interlayer insulation layer to cover the ground select gate, the string select gate, the plurality of cell gate structures, and the plurality of air gaps; and
    forming a bit line coupled to one of the plurality of impurity regions via a bit line contact adjacent the string select gate where one of the spacer layer patterns is removed.
  39. 39. The method of claim 38, which further comprises selectively removing one of the spacer layer patterns from one sidewall of the string select gate opposite another sidewall facing the cell gate structure;
  40. 40. The method of claim 39, wherein selectively removing comprises using a wet etching process or dry etching.
  41. 41. The method of claim 40, wherein the wet etching uses a phosphoric acid.
  42. 42. The method of claim 39, which further comprises:
    forming a common source line adjacent the ground select gate; and
    selectively removing one of the spacer layer patterns from one sidewall of the ground select gate opposite another sidewall facing the common source line;
  43. 43. A system comprising:
    a dynamic random access memory (DRAM) device; and
    a non-volatile memory device, the non-volatile memory device comprising:
    a plurality of cell gate structures; and
    an air gap disposed between adjacent cell gate structures in the plurality of cell gate structures, wherein the air gap is substantially rectangular in cross-section.
  44. 44. The system of claim 43, further comprising a microprocessor operatively coupled to the DRAM device and the non-volatile memory device.
  45. 45. The system of claim 43, wherein the DRAM device and the non-volatile memory device are disposed in a single integrated circuit (IC) package.
  46. 46. The system of claim 43, wherein the air gap has a substantially uniform width over its height.
US11551680 2005-10-31 2006-10-20 Semiconductor device and method for fabricating the same Abandoned US20070096202A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR2005-0103107 2005-10-31
KR20050103107A KR100784860B1 (en) 2005-10-31 2005-10-31 Nonvalitile memory device and method for fabricating the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12847351 US8362542B2 (en) 2005-10-31 2010-07-30 Semiconductor devices comprising a plurality of gate structures
US13050335 US8436410B2 (en) 2005-10-31 2011-03-17 Semiconductor devices comprising a plurality of gate structures
US13751679 US8809146B2 (en) 2005-10-31 2013-01-28 Semiconductor devices comprising a plurality of gate structures

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12847351 Continuation US8362542B2 (en) 2005-10-31 2010-07-30 Semiconductor devices comprising a plurality of gate structures

Publications (1)

Publication Number Publication Date
US20070096202A1 true true US20070096202A1 (en) 2007-05-03

Family

ID=37995127

Family Applications (3)

Application Number Title Priority Date Filing Date
US11551680 Abandoned US20070096202A1 (en) 2005-10-31 2006-10-20 Semiconductor device and method for fabricating the same
US12847351 Active 2027-10-11 US8362542B2 (en) 2005-10-31 2010-07-30 Semiconductor devices comprising a plurality of gate structures
US13751679 Active US8809146B2 (en) 2005-10-31 2013-01-28 Semiconductor devices comprising a plurality of gate structures

Family Applications After (2)

Application Number Title Priority Date Filing Date
US12847351 Active 2027-10-11 US8362542B2 (en) 2005-10-31 2010-07-30 Semiconductor devices comprising a plurality of gate structures
US13751679 Active US8809146B2 (en) 2005-10-31 2013-01-28 Semiconductor devices comprising a plurality of gate structures

Country Status (2)

Country Link
US (3) US20070096202A1 (en)
KR (1) KR100784860B1 (en)

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080087942A1 (en) * 2006-10-11 2008-04-17 Macronix International Co., Ltd. Vertical channel memory and manufacturing method thereof and operating method using the same
US20080087946A1 (en) * 2006-10-11 2008-04-17 Macronix International Co., Ltd. Vertical channel transistor structure and manufacturing method thereof
US20080150003A1 (en) * 2006-12-20 2008-06-26 Jian Chen Electron blocking layers for electronic devices
US20080150004A1 (en) * 2006-12-20 2008-06-26 Nanosys, Inc. Electron Blocking Layers for Electronic Devices
US20080283898A1 (en) * 2007-05-14 2008-11-20 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and method of manufacturing the same
US20090078986A1 (en) * 2007-09-20 2009-03-26 Lars Bach Manufacturing method for an integrated circuit including different types of gate stacks, corresponding intermediate integrated circuit structure and corresponding integrated circuit
DE102007045058A1 (en) * 2007-09-20 2009-04-09 Qimonda Ag Integrated circuit for use in flash memory i.e. NAND-type flash memory, of cellular telephone, has gate stacks coupled to other gate stacks, where each gate stack is provided with control electrode that includes layer
US20090180324A1 (en) * 2008-01-15 2009-07-16 Ramaswamy D V Nirmal Semiconductor Constructions, NAND Unit Cells, Methods Of Forming Semiconductor Constructions, And Methods Of Forming NAND Unit Cells
US20090212352A1 (en) * 2008-02-26 2009-08-27 Kenji Aoyama Semiconductor memory device and method for manufacturing the same
US20090212351A1 (en) * 2006-12-20 2009-08-27 Nanosys, Inc. Electron blocking layers for electronic devices
US20090267131A1 (en) * 2008-02-15 2009-10-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US20090294895A1 (en) * 2008-05-28 2009-12-03 Qimonda Ag Integrated circuit with conductive structures
US20090302367A1 (en) * 2008-06-10 2009-12-10 Kabushiki Kaisha Toshiba Method of fabricating semiconductor device and semiconductor device fabricated by the method
KR100971208B1 (en) 2007-11-22 2010-07-20 주식회사 동부하이텍 Flash memory and method for the same
US20100237398A1 (en) * 2009-03-23 2010-09-23 Kabushiki Kaisha Toshiba Semiconductor storage device and method for manufacturing the same
US7847341B2 (en) 2006-12-20 2010-12-07 Nanosys, Inc. Electron blocking layers for electronic devices
US20100330804A1 (en) * 2009-06-30 2010-12-30 Hynix Semiconductor Inc. Method for Fabricating Bitline in Semiconductor Device
US7868376B2 (en) 2008-03-03 2011-01-11 Kabushiki Kaisha Toshiba Semiconductor storage device and method for manufacturing the same
US20110318914A1 (en) * 2010-06-25 2011-12-29 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US20120032245A1 (en) * 2010-08-03 2012-02-09 Samsung Electronics Co., Ltd. Vertical Structure Non-Volatile Memory Device
US8153491B2 (en) 2005-08-04 2012-04-10 Macronix International Co., Ltd. Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer
US20120104485A1 (en) * 2010-10-27 2012-05-03 Samsung Electronics Co., Ltd. Nonvolatile Memory Devices And Methods Of Manufacturing The Same
US20120126306A1 (en) * 2010-11-18 2012-05-24 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and manufacturing method of nonvolatile semiconductor memory device
US20120126302A1 (en) * 2010-11-18 2012-05-24 Mitsuhiko Noda Nonvolatile semiconductor memory device and manufacturing method of the same
US20120132985A1 (en) * 2010-11-30 2012-05-31 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and method of manufacturing non-volatile semiconductor memory device
CN102651369A (en) * 2011-02-25 2012-08-29 株式会社东芝 Nonvolatile semiconductor memory device and method for manufacturing the same
US20120231599A1 (en) * 2011-03-09 2012-09-13 Hynix Semiconductor Inc. Method of manufacturing semiconductor devices
CN102683263A (en) * 2012-05-28 2012-09-19 上海华力微电子有限公司 Manufacturing method of grid isolating structure, grid isolating structure and semiconductor device
US20130164926A1 (en) * 2011-12-22 2013-06-27 SK Hynix Inc. Method of manufacturing semiconductor device
CN103579253A (en) * 2012-08-08 2014-02-12 爱思开海力士有限公司 Semiconductor memory device and method of manufacturing the same
US9041122B2 (en) 2013-08-27 2015-05-26 Samsung Electronics Co., Ltd. Semiconductor devices having metal silicide layers and methods of manufacturing such semiconductor devices
US9184091B2 (en) 2013-02-19 2015-11-10 Samsung Electronics Co., Ltd. Semiconductor device and method of forming the same
US9293547B2 (en) 2010-11-18 2016-03-22 Kabushiki Kaisha Toshiba NAND EEPROM with perpendicular sets of air gaps and method for manufacturing NAND EEPROM with perpendicular sets of air gaps
US9343355B2 (en) 2013-03-14 2016-05-17 Samsung Electronics Co., Ltd. Wiring structures including spacers and an airgap defined thereby, and methods of manufacturing the same
US9368589B2 (en) 2013-04-01 2016-06-14 Samsung Electronics Co., Ltd. Semiconductor device and semiconductor module
US9865693B1 (en) * 2016-08-04 2018-01-09 United Microelectronics Corporation Semiconductor memory cell, semiconductor memory device, and method of manufacturing semiconductor memory device

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101356695B1 (en) * 2007-08-06 2014-01-29 삼성전자주식회사 Method of fabricating semiconductor device
KR101038603B1 (en) 2008-05-26 2011-06-03 주식회사 하이닉스반도체 Semiconductor device and method for manufacturing the same
US8546239B2 (en) 2010-06-11 2013-10-01 Sandisk Technologies Inc. Methods of fabricating non-volatile memory with air gaps
US8603890B2 (en) 2010-06-19 2013-12-10 Sandisk Technologies Inc. Air gap isolation in non-volatile memory
US8946048B2 (en) 2010-06-19 2015-02-03 Sandisk Technologies Inc. Method of fabricating non-volatile memory with flat cell structures and air gap isolation
US8492224B2 (en) * 2010-06-20 2013-07-23 Sandisk Technologies Inc. Metal control gate structures and air gap isolation in non-volatile memory
US8421159B2 (en) * 2010-08-02 2013-04-16 International Business Machines Corporation Raised source/drain field effect transistor
US8450789B2 (en) 2010-08-24 2013-05-28 Micron Technology, Inc. Memory array with an air gap between memory cells and the formation thereof
KR20120026313A (en) 2010-09-09 2012-03-19 삼성전자주식회사 Non-volatile memory device and method of fabricating the same
KR101692403B1 (en) * 2010-12-16 2017-01-04 삼성전자주식회사 Methods of manufacturing a semiconductor device
US8778749B2 (en) 2011-01-12 2014-07-15 Sandisk Technologies Inc. Air isolation in high density non-volatile memory
KR101760662B1 (en) * 2011-02-09 2017-07-25 삼성전자 주식회사 Fabricating method of non volatile memory device and non volatile memory device thereby
KR20120121727A (en) * 2011-04-27 2012-11-06 에스케이하이닉스 주식회사 Semiconductor cell and method for forming the same, cell array, semiconductor device, semiconductor module, semiconductor system, electronic unit and electronic system
KR20120124706A (en) * 2011-05-04 2012-11-14 에스케이하이닉스 주식회사 Semiconductor device and method of manufacturing the same
US8575000B2 (en) * 2011-07-19 2013-11-05 SanDisk Technologies, Inc. Copper interconnects separated by air gaps and method of making thereof
US8569130B2 (en) 2011-07-28 2013-10-29 Micron Technology, Inc. Forming air gaps in memory arrays and memory arrays with air gaps thus formed
US9136128B2 (en) 2011-08-31 2015-09-15 Micron Technology, Inc. Methods and apparatuses including memory cells with air gaps and other low dielectric constant materials
US8586527B2 (en) 2011-10-20 2013-11-19 Jaipal Singh Cerivastatin to treat pulmonary disorders
US8766348B2 (en) * 2011-12-21 2014-07-01 Samsung Electronics Co., Ltd. Semiconductor device with selectively located air gaps and method of fabrication
US9123714B2 (en) 2012-02-16 2015-09-01 Sandisk Technologies Inc. Metal layer air gap formation
JP5791798B2 (en) * 2012-06-08 2015-10-07 三菱電機株式会社 Power converter internal motor, an air conditioner with a built-in motor, water heater, and ventilation blow devices
US8890254B2 (en) 2012-09-14 2014-11-18 Macronix International Co., Ltd. Airgap structure and method of manufacturing thereof
US9129854B2 (en) * 2012-10-04 2015-09-08 Sandisk Technologies Inc. Full metal gate replacement process for NAND flash memory
US20140159132A1 (en) * 2012-12-06 2014-06-12 Micron Technology, Inc. Memory arrays with air gaps between conductors and the formation thereof
US9123577B2 (en) 2012-12-12 2015-09-01 Sandisk Technologies Inc. Air gap isolation in non-volatile memory using sacrificial films
US9349740B2 (en) 2014-01-24 2016-05-24 Sandisk Technologies Inc. Non-volatile storage element with suspended charge storage region
US9177853B1 (en) 2014-05-14 2015-11-03 Sandisk Technologies Inc. Barrier layer stack for bit line air gap formation
US9478461B2 (en) 2014-09-24 2016-10-25 Sandisk Technologies Llc Conductive line structure with openings
US9524904B2 (en) 2014-10-21 2016-12-20 Sandisk Technologies Llc Early bit line air gap formation
US9401305B2 (en) 2014-11-05 2016-07-26 Sandisk Technologies Llc Air gaps structures for damascene metal patterning
US9847249B2 (en) 2014-11-05 2017-12-19 Sandisk Technologies Llc Buried etch stop layer for damascene bit line formation
KR20160107784A (en) 2015-03-05 2016-09-19 삼성전자주식회사 Non volatile memory devices and methods of manufacturing the same
US9524973B1 (en) 2015-06-30 2016-12-20 Sandisk Technologies Llc Shallow trench air gaps and their formation
US9524974B1 (en) 2015-07-22 2016-12-20 Sandisk Technologies Llc Alternating sidewall assisted patterning
US9391081B1 (en) 2015-09-08 2016-07-12 Sandisk Technologies Llc Metal indentation to increase inter-metal breakdown voltage
US9607997B1 (en) 2015-09-08 2017-03-28 Sandisk Technologies Inc. Metal line with increased inter-metal breakdown voltage
US9583581B1 (en) * 2015-10-27 2017-02-28 Broadcom Corporation Discontinuities in a semiconductor device to accommodate for manufacturing variations and/or misalignment tolerances
CN108573926A (en) * 2017-03-09 2018-09-25 联华电子股份有限公司 The semiconductor memory device and manufacturing method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532594A (en) * 1981-07-13 1985-07-30 Nissan Motor Company, Limited Multiple microcomputer system with comonitoring/back-up for an automotive vehicle
US6468877B1 (en) * 2001-07-19 2002-10-22 Chartered Semiconductor Manufacturing Ltd. Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner
US20030151069A1 (en) * 2001-12-25 2003-08-14 Kikuko Sugimae Semiconductor device and manufacturing method
US20040004863A1 (en) * 2002-07-05 2004-01-08 Chih-Hsin Wang Nonvolatile electrically alterable memory device and array made thereby
US20040038489A1 (en) * 2002-08-21 2004-02-26 Clevenger Lawrence A. Method to improve performance of microelectronic circuits
US20040232496A1 (en) * 2003-05-21 2004-11-25 Jian Chen Use of voids between elements in semiconductor structures for isolation
US20050023597A1 (en) * 2003-06-23 2005-02-03 Hiroyuki Kutsukake Nonvolatile semiconductor memory device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4493182B2 (en) 2000-08-23 2010-06-30 株式会社ルネサステクノロジ Semiconductor device
KR100706225B1 (en) * 2001-04-20 2007-04-11 삼성전자주식회사 Structure for Gate Insulation and Method of Forming The Same
US7042095B2 (en) * 2002-03-29 2006-05-09 Renesas Technology Corp. Semiconductor device including an interconnect having copper as a main component

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532594A (en) * 1981-07-13 1985-07-30 Nissan Motor Company, Limited Multiple microcomputer system with comonitoring/back-up for an automotive vehicle
US6468877B1 (en) * 2001-07-19 2002-10-22 Chartered Semiconductor Manufacturing Ltd. Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner
US20030151069A1 (en) * 2001-12-25 2003-08-14 Kikuko Sugimae Semiconductor device and manufacturing method
US6894341B2 (en) * 2001-12-25 2005-05-17 Kabushiki Kaisha Toshiba Semiconductor device and manufacturing method
US20040004863A1 (en) * 2002-07-05 2004-01-08 Chih-Hsin Wang Nonvolatile electrically alterable memory device and array made thereby
US20040038489A1 (en) * 2002-08-21 2004-02-26 Clevenger Lawrence A. Method to improve performance of microelectronic circuits
US20040232496A1 (en) * 2003-05-21 2004-11-25 Jian Chen Use of voids between elements in semiconductor structures for isolation
US20050023597A1 (en) * 2003-06-23 2005-02-03 Hiroyuki Kutsukake Nonvolatile semiconductor memory device

Cited By (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8153491B2 (en) 2005-08-04 2012-04-10 Macronix International Co., Ltd. Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer
US9246015B2 (en) 2006-10-11 2016-01-26 Macronix International Co., Ltd. Vertical channel transistor structure and manufacturing method thereof
US20080087942A1 (en) * 2006-10-11 2008-04-17 Macronix International Co., Ltd. Vertical channel memory and manufacturing method thereof and operating method using the same
US7811890B2 (en) 2006-10-11 2010-10-12 Macronix International Co., Ltd. Vertical channel transistor structure and manufacturing method thereof
US8772858B2 (en) 2006-10-11 2014-07-08 Macronix International Co., Ltd. Vertical channel memory and manufacturing method thereof and operating method using the same
US20080087946A1 (en) * 2006-10-11 2008-04-17 Macronix International Co., Ltd. Vertical channel transistor structure and manufacturing method thereof
US20080150004A1 (en) * 2006-12-20 2008-06-26 Nanosys, Inc. Electron Blocking Layers for Electronic Devices
US9214525B2 (en) 2006-12-20 2015-12-15 Sandisk Corporation Gate stack having electron blocking layers on charge storage layers for electronic devices
US20080150003A1 (en) * 2006-12-20 2008-06-26 Jian Chen Electron blocking layers for electronic devices
US20090212351A1 (en) * 2006-12-20 2009-08-27 Nanosys, Inc. Electron blocking layers for electronic devices
US7847341B2 (en) 2006-12-20 2010-12-07 Nanosys, Inc. Electron blocking layers for electronic devices
US8686490B2 (en) 2006-12-20 2014-04-01 Sandisk Corporation Electron blocking layers for electronic devices
US8399322B2 (en) 2007-05-14 2013-03-19 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and method of manufacturing the same
US8008149B2 (en) 2007-05-14 2011-08-30 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and method of manufacturing the same
US20080283898A1 (en) * 2007-05-14 2008-11-20 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and method of manufacturing the same
US8575017B2 (en) 2007-05-14 2013-11-05 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and method of manufacturing the same
DE102007045058A1 (en) * 2007-09-20 2009-04-09 Qimonda Ag Integrated circuit for use in flash memory i.e. NAND-type flash memory, of cellular telephone, has gate stacks coupled to other gate stacks, where each gate stack is provided with control electrode that includes layer
DE102007045058B4 (en) * 2007-09-20 2015-07-02 Qimonda Ag A method of fabricating an integrated circuit including various types of gate stacks in said first and second regions
US20090078986A1 (en) * 2007-09-20 2009-03-26 Lars Bach Manufacturing method for an integrated circuit including different types of gate stacks, corresponding intermediate integrated circuit structure and corresponding integrated circuit
US8072072B2 (en) * 2007-09-20 2011-12-06 Qimonda Ag Integrated circuit including different types of gate stacks, corresponding intermediate integrated circuit structure and corresponding integrated circuit
KR100971208B1 (en) 2007-11-22 2010-07-20 주식회사 동부하이텍 Flash memory and method for the same
US8610193B2 (en) 2008-01-15 2013-12-17 Micron Technology Inc. Semiconductor constructions, NAND unit cells, methods of forming semiconductor constructions, and methods of forming NAND unit cells
US9230978B2 (en) 2008-01-15 2016-01-05 Micron Technology, Inc. Semiconductor constructions and NAND unit cells
US8394683B2 (en) 2008-01-15 2013-03-12 Micron Technology, Inc. Methods of forming semiconductor constructions, and methods of forming NAND unit cells
US9431422B2 (en) 2008-01-15 2016-08-30 Micron Technology, Inc. Semiconductor constructions and NAND unit cells
US20090180324A1 (en) * 2008-01-15 2009-07-16 Ramaswamy D V Nirmal Semiconductor Constructions, NAND Unit Cells, Methods Of Forming Semiconductor Constructions, And Methods Of Forming NAND Unit Cells
US10079244B2 (en) 2008-01-15 2018-09-18 Micron Technology, Inc. Semiconductor constructions and NAND unit cells
US8008704B2 (en) * 2008-02-15 2011-08-30 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US8349686B2 (en) 2008-02-15 2013-01-08 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US20090267131A1 (en) * 2008-02-15 2009-10-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method of manufacturing the same
US20110147822A1 (en) * 2008-02-26 2011-06-23 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing the same
US7915156B2 (en) 2008-02-26 2011-03-29 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing the same
US20090212352A1 (en) * 2008-02-26 2009-08-27 Kenji Aoyama Semiconductor memory device and method for manufacturing the same
US20110097887A1 (en) * 2008-03-03 2011-04-28 Kabushiki Kaisha Toshiba Semiconductor storage device and method for manufacturing the same
US8071449B2 (en) 2008-03-03 2011-12-06 Kabushiki Kaisha Toshiba Semiconductor storage device and method for manufacturing the same
US7868376B2 (en) 2008-03-03 2011-01-11 Kabushiki Kaisha Toshiba Semiconductor storage device and method for manufacturing the same
US20090294895A1 (en) * 2008-05-28 2009-12-03 Qimonda Ag Integrated circuit with conductive structures
US7893519B2 (en) 2008-05-28 2011-02-22 Qimonda Ag Integrated circuit with conductive structures
US7884415B2 (en) 2008-06-10 2011-02-08 Kabushiki Kaisha Toshiba Semiconductor memory device having multiple air gaps in interelectrode insulating film
US20110104883A1 (en) * 2008-06-10 2011-05-05 Kabushiki Kaisha Toshiba Method of fabricating semiconductor device
US20090302367A1 (en) * 2008-06-10 2009-12-10 Kabushiki Kaisha Toshiba Method of fabricating semiconductor device and semiconductor device fabricated by the method
US20100237398A1 (en) * 2009-03-23 2010-09-23 Kabushiki Kaisha Toshiba Semiconductor storage device and method for manufacturing the same
JP2010225786A (en) * 2009-03-23 2010-10-07 Toshiba Corp Semiconductor storage device, and method for manufacturing semiconductor storage device
US8253188B2 (en) 2009-03-23 2012-08-28 Kabushiki Kaisha Toshiba Semiconductor storage device and method for manufacturing the same
US7932168B2 (en) 2009-06-30 2011-04-26 Hynix Semiconductor Inc. Method for fabricating bitline in semiconductor device
US20100330804A1 (en) * 2009-06-30 2010-12-30 Hynix Semiconductor Inc. Method for Fabricating Bitline in Semiconductor Device
US8765572B2 (en) * 2010-06-25 2014-07-01 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US20110318914A1 (en) * 2010-06-25 2011-12-29 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device
US9070587B2 (en) * 2010-08-03 2015-06-30 Samsung Electronics Co., Ltd. Vertical structure non-volatile memory device having insulating regions that are formed as air gaps between selection transistors of adjacent memory cell strings
US9406688B2 (en) 2010-08-03 2016-08-02 Samsung Electronics Co., Ltd. Vertical structure non-volatile memory device having insulating regions that are formed as air gaps
US20120032245A1 (en) * 2010-08-03 2012-02-09 Samsung Electronics Co., Ltd. Vertical Structure Non-Volatile Memory Device
US20120104485A1 (en) * 2010-10-27 2012-05-03 Samsung Electronics Co., Ltd. Nonvolatile Memory Devices And Methods Of Manufacturing The Same
US20120126302A1 (en) * 2010-11-18 2012-05-24 Mitsuhiko Noda Nonvolatile semiconductor memory device and manufacturing method of the same
US8294194B2 (en) * 2010-11-18 2012-10-23 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and manufacturing method of the same
US20120126306A1 (en) * 2010-11-18 2012-05-24 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and manufacturing method of nonvolatile semiconductor memory device
US9293547B2 (en) 2010-11-18 2016-03-22 Kabushiki Kaisha Toshiba NAND EEPROM with perpendicular sets of air gaps and method for manufacturing NAND EEPROM with perpendicular sets of air gaps
US20120132985A1 (en) * 2010-11-30 2012-05-31 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and method of manufacturing non-volatile semiconductor memory device
US9006815B2 (en) * 2011-02-25 2015-04-14 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method for manufacturing the same
US20120217568A1 (en) * 2011-02-25 2012-08-30 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method for manufacturing the same
CN102651369A (en) * 2011-02-25 2012-08-29 株式会社东芝 Nonvolatile semiconductor memory device and method for manufacturing the same
US20120231599A1 (en) * 2011-03-09 2012-09-13 Hynix Semiconductor Inc. Method of manufacturing semiconductor devices
US8956950B2 (en) * 2011-03-09 2015-02-17 SK Hynix Inc. Method of manufacturing semiconductor devices
US8865562B2 (en) * 2011-12-22 2014-10-21 SK Hynix Inc. Method of manufacturing semiconductor device
US20130164926A1 (en) * 2011-12-22 2013-06-27 SK Hynix Inc. Method of manufacturing semiconductor device
CN102683263A (en) * 2012-05-28 2012-09-19 上海华力微电子有限公司 Manufacturing method of grid isolating structure, grid isolating structure and semiconductor device
CN103579253A (en) * 2012-08-08 2014-02-12 爱思开海力士有限公司 Semiconductor memory device and method of manufacturing the same
US9184091B2 (en) 2013-02-19 2015-11-10 Samsung Electronics Co., Ltd. Semiconductor device and method of forming the same
US9343355B2 (en) 2013-03-14 2016-05-17 Samsung Electronics Co., Ltd. Wiring structures including spacers and an airgap defined thereby, and methods of manufacturing the same
US9368589B2 (en) 2013-04-01 2016-06-14 Samsung Electronics Co., Ltd. Semiconductor device and semiconductor module
US9041122B2 (en) 2013-08-27 2015-05-26 Samsung Electronics Co., Ltd. Semiconductor devices having metal silicide layers and methods of manufacturing such semiconductor devices
US9865693B1 (en) * 2016-08-04 2018-01-09 United Microelectronics Corporation Semiconductor memory cell, semiconductor memory device, and method of manufacturing semiconductor memory device

Also Published As

Publication number Publication date Type
US20100295113A1 (en) 2010-11-25 application
KR20070046412A (en) 2007-05-03 application
US8809146B2 (en) 2014-08-19 grant
US8362542B2 (en) 2013-01-29 grant
KR100784860B1 (en) 2007-12-14 grant
US20130178044A1 (en) 2013-07-11 application

Similar Documents

Publication Publication Date Title
US6541815B1 (en) High-density dual-cell flash memory structure
US7208794B2 (en) High-density NROM-FINFET
US6894339B2 (en) Flash memory with trench select gate and fabrication process
US6153494A (en) Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash
US6894341B2 (en) Semiconductor device and manufacturing method
US6566196B1 (en) Sidewall protection in fabrication of integrated circuits
US20050093047A1 (en) Semiconductor memory device and method of manufacturing the same
US20020020890A1 (en) Memory cell and production method
US20120052674A1 (en) Semiconductor devices and methods of fabricating the same
US20060141706A1 (en) Methods of forming non-volatile semiconductor memory devices using prominences and trenches, and devices so formed
US20030025147A1 (en) Semiconductor device and method of producing the same
US6885044B2 (en) Arrays of nonvolatile memory cells wherein each cell has two conductive floating gates
US6069382A (en) Non-volatile memory cell having a high coupling ratio
US7018895B2 (en) Nonvolatile memory cell with multiple floating gates formed after the select gate
US6630384B1 (en) Method of fabricating double densed core gates in sonos flash memory
US6562681B2 (en) Nonvolatile memories with floating gate spacers, and methods of fabrication
US6768161B2 (en) Semiconductor device having floating gate and method of producing the same
US7071061B1 (en) Method for fabricating non-volatile memory
US20100019311A1 (en) Semiconductor memory device and manufacturing method thereof
US20070047304A1 (en) Non-volatile semiconductor memory device and method of manufacturing the same
US20020033501A1 (en) Nonvolatile semiconductor memory and method of fabricating the same
US6875660B2 (en) Method of manufacturing high coupling ratio flash memory having sidewall spacer floating gate electrode
US20050287741A1 (en) Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer
US20060141710A1 (en) NOR-type flash memory device of twin bit cell structure and method of fabricating the same
US20050062091A1 (en) Nonvolatile memory cell with multiple floating gates formed after the select gate and having upward protrusions

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KANG, DAE-WOONG;CHANG, SUNG-NAM;KIM, JIN-JOO;AND OTHERS;REEL/FRAME:018419/0110

Effective date: 20061017