WO2023221198A1 - 阵列基板、阵列基板的制备方法、显示面板和显示装置 - Google Patents

阵列基板、阵列基板的制备方法、显示面板和显示装置 Download PDF

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Publication number
WO2023221198A1
WO2023221198A1 PCT/CN2022/097640 CN2022097640W WO2023221198A1 WO 2023221198 A1 WO2023221198 A1 WO 2023221198A1 CN 2022097640 W CN2022097640 W CN 2022097640W WO 2023221198 A1 WO2023221198 A1 WO 2023221198A1
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conductive layer
layer
substrate
disposed
source
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PCT/CN2022/097640
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English (en)
French (fr)
Inventor
罗成志
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武汉华星光电技术有限公司
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Priority to US17/794,454 priority Critical patent/US20230411400A1/en
Publication of WO2023221198A1 publication Critical patent/WO2023221198A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G02F1/133555—Transflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present application belongs to the field of display technology, and in particular relates to an array substrate, a preparation method of the array substrate, a display panel and a display device.
  • liquid crystal displays Liquid Crystal displays
  • TFT Thin Film Transistor
  • LCD switching devices Display
  • TFT-LCD is a passive display panel that requires a backlight module for image display.
  • the ratio of the light intensity before and after the backlight emitted by the backlight module passes through the TFT-LCD display panel is called light efficiency.
  • the array substrate of the TFT-LCD display panel includes a light-transmitting area and a reflective area.
  • the reflective area reflects the light emitted by the backlight source and then reflects the backlight to the light-transmitting area, thus improving the light efficiency of the TFT-LCD display panel. Therefore, how to improve the reflectivity of the reflective area in the array substrate is an urgent problem that needs to be solved.
  • Embodiments of the present application provide a method for preparing a column substrate, an array substrate, a display panel and a display device, which improve the reflectivity of the array substrate on the basis of ensuring the electrical connection between the source and drain electrodes and the active layer.
  • an array substrate including:
  • An active layer is provided on one side of the substrate, the active layer includes a source and drain overlap region;
  • Source and drain electrodes are disposed on a side of the active layer away from the substrate, and are electrically connected to the active layer in the source and drain overlap regions;
  • the source and drain electrodes include a first conductive layer disposed close to the active layer, a third conductive layer disposed on a side of the first conductive layer away from the active layer, and a third conductive layer disposed on the side of the first conductive layer away from the active layer.
  • a second conductive layer between a conductive layer and the third conductive layer, the light reflectivity of the second conductive layer is greater than the light reflectance of the first conductive layer, and the light reflection of the second conductive layer
  • the light reflectivity is greater than the light reflectance of the third conductive layer, and the orthographic projection area of the first conductive layer on the substrate is smaller than the orthographic projection area of the second conductive layer on the substrate.
  • embodiments of the present application also provide a method for preparing an array substrate, including:
  • the active layer including a source-drain connecting region
  • a source-drain electrode is formed on the side of the active layer away from the substrate, and the source-drain electrode is electrically connected to the active layer in the source-drain overlap region;
  • the source and drain electrodes include a first conductive layer disposed close to the active layer, a third conductive layer disposed on a side of the first conductive layer away from the active layer, and a third conductive layer disposed on the side of the first conductive layer away from the active layer.
  • a second conductive layer between a conductive layer and the third conductive layer, the light reflectivity of the second conductive layer is greater than the light reflectance of the first conductive layer, and the light reflection of the second conductive layer
  • the light reflectivity is greater than the light reflectance of the third conductive layer, and the orthographic projection area of the first conductive layer on the substrate is smaller than the orthographic projection area of the second conductive layer on the substrate.
  • the array substrate provided by the embodiment of the present application includes a substrate; an active layer is disposed on one side of the substrate, and the active layer includes a source and drain overlapping area; and a source and drain electrode is disposed on a side of the active layer away from the substrate. side, and is electrically connected to the active layer in the source-drain overlap region; wherein, the source-drain electrode includes a first conductive layer disposed close to the active layer, and a third conductive layer disposed on a side of the first conductive layer away from the active layer.
  • the light reflectance of the second conductive layer is greater than the light reflectance of the first conductive layer
  • the light reflectance of the second conductive layer It is greater than the light reflectivity of the third conductive layer
  • the orthographic projection area of the first conductive layer on the substrate is smaller than the orthographic projection area of the second conductive layer on the substrate.
  • FIG. 1 is a schematic structural diagram of an array substrate in the prior art provided by an embodiment of the present application.
  • FIG. 2 is a first structural schematic diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 3 is a second structural schematic diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for preparing an array substrate according to an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of an array substrate in the prior art provided by an embodiment of the present application.
  • the array substrate 100 may include a substrate 101, a first conductive layer 102, a first buffer layer 103, a second buffer layer 104, an active layer 105, a gate insulation layer 106, a gate layer 107, and a first interlayer insulation. layer 108, the second interlayer insulating layer 109, the planarization layer 110, the second conductive layer 111, the third conductive layer 112 and the fourth conductive layer 113.
  • the above-mentioned plurality of film layers 102-113 are all arranged in the reflective area of the array substrate 100.
  • the first conductive layer 102 can be made of metal materials such as molybdenum, titanium, and aluminum.
  • the reflectivity of molybdenum metal is about 52%, that of titanium metal is about 60%, and that of aluminum metal is about 97%. %. If molybdenum or titanium is selected as the material of the first conductive layer 102, the reflectivity will be low, which will affect the reflection rate of the array substrate 100.
  • aluminum is better used as the material of the first conductive layer 102, but the high temperature The manufacturing process will cause the resistance of the aluminum material to increase sharply, and the volume of the aluminum material will expand at high temperatures. Since the existence of the substrate 101 will limit the expansion, the compressive stress generated by limiting the expansion will be released through atomic diffusion along the grains. The boundaries spread to form hillocks.
  • the second conductive layer 111 , the third conductive layer 112 and the fourth conductive layer 113 overlap with the source and drain connecting areas of the active layer 105 through via holes to achieve electrical connection.
  • the second conductive layer 111 and the fourth conductive layer 113 can both be made of metal materials such as molybdenum or titanium, and the third conductive layer 112 can be made of aluminum material.
  • the second conductive layer 111 , the third conductive layer 112 and the fourth conductive layer 113 Form a three-layer structure. It should be noted that direct contact between the aluminum material and the active layer 105 will produce a large resistance. Therefore, the second conductive layer 111 needs to be provided between the third conductive layer 112 and the active layer 105 to prevent short circuit caused by excessive resistance. .
  • the first conductive layer 102 of the array substrate 100 cannot use an aluminum material with a high reflectivity to improve the reflection rate of the array substrate 100, and the third conductive layer 112 using an aluminum material requires Contact with the active layer 105 is achieved via the second conductive layer 111 as a spacer.
  • embodiments of the present application provide an array substrate, a preparation method of the array substrate, a display panel, and a display device. Please refer to Figures 2 and 3.
  • Figure 2 is a first structural schematic diagram of an array substrate provided by an embodiment of the present application
  • Figure 3 is a second structural schematic diagram of an array substrate provided by an embodiment of the present application.
  • the array substrate 200 may include a substrate 201 and a light-transmitting area 202 and a light-reflecting area 203 provided on the light exit side of the substrate.
  • the light-transmitting area 202 may include a plurality of sub-light-transmitting areas 2021
  • the reflective area 203 may include a plurality of sub-light-reflecting areas 2031.
  • a plurality of sub-light-transmitting areas 2021 and a plurality of sub-light-reflecting areas 2031 are arranged adjacent to each other in sequence, that is, the plurality of sub-light-transmitting areas 2021 are arranged in sequence and the plurality of sub-light-reflecting areas 2031 are arranged in sequence and each sub-light-transmitting area 2021 is arranged in two adjacent areas.
  • the sub-reflective areas 2031 are arranged adjacent to each other or any sub-transmissive area 2021 is adjacent to at least one sub-reflective area 2031 .
  • the orthographic projection area of each sub-light-transmitting area 2021 on the substrate 201 can be set to be larger than the orthographic projection area of each sub-reflective area 2031 on the substrate 201, thereby increasing the size of the sub-light-transmitting area 2021 and improving the performance of the array substrate 200. Transmittance.
  • the array substrate 200 may include a substrate 201, an active layer 31 and a source and drain electrode.
  • the active layer 31 is disposed on one side of the substrate, and the active layer includes a source and drain overlapping area; the source and drain electrodes are disposed on The side of the source layer 31 away from the substrate 201 is electrically connected to the active layer 31 in the source-drain overlap region.
  • the active layer 31 and the source and drain electrodes are both disposed in the reflective area 203 .
  • the source and drain electrodes may include a first conductive layer 34, a second conductive layer 35, and a third conductive layer 36, wherein the first conductive layer 34 is disposed close to the active layer 31, and the third conductive layer 36 is disposed on the first conductive layer 36.
  • the layer 34 is on a side away from the active layer 31 , and the second conductive layer 35 is disposed between the first conductive layer 34 and the third conductive layer 36 .
  • the light reflectance of the second conductive layer 35 is greater than the light reflectance of the first conductive layer 34 , the light reflectance of the second conductive layer 35 is greater than the light reflectance of the third conductive layer 36 , and the first conductive layer 34 is on the substrate 201
  • the orthographic projection area on the substrate 201 is smaller than the orthographic projection area of the second conductive layer 35 on the substrate 201 .
  • the active layer 31 may include a source-drain connecting area for connecting the source-drain wiring, thereby achieving electrical connection with the source-drain electrode through the source-drain wiring.
  • the reflective area 203 may also include via holes 32, an interlayer insulating layer 33 and a gate insulating layer 41.
  • the gate insulating layer 41 covers the active layer 31, and the interlayer insulating layer 33 is disposed away from the gate insulating layer 41 and away from the active layer 31. layer 31 side, and the interlayer insulating layer 33 is disposed between the first conductive layer 34 and the active layer 31 .
  • the via hole 32 penetrates the gate insulating layer 41 and the interlayer insulating layer 33 and is located between the source and drain electrodes and the active layer 31 . That is, the via hole 32 may extend from the upper surface of the interlayer insulating layer 33 to the source-drain overlap area in the active layer 31 , and the via hole 32 may form a groove 50 with the source-drain overlap area.
  • the source and drain electrodes may include source electrodes and drain electrodes
  • the source and drain overlap areas may include source overlap areas and drain overlap areas
  • the via holes 32 may include first via holes 321 and second via holes 322
  • the first via hole 321 can extend from the upper surface of the interlayer insulating layer 33 to the source overlap area, that is, the first via hole 321 is provided between the source electrode and the source overlap area, and the first via hole 321 can be connected to the source electrode.
  • the source overlap area forms the first groove 51, a part of the first conductive layer 34 can be disposed on the groove wall and bottom of the first groove 51, and a part of the second conductive layer 35 can be disposed in the first groove 51 and in conjunction with the disposed
  • the first conductive layer 34 in the first groove 51 contacts, thereby achieving electrical connection between the source electrode and the source connecting area.
  • the second via hole 322 may extend from the upper surface of the interlayer insulating layer 33 to the drain overlap area. That is, the second via hole 322 is disposed between the drain electrode and the drain overlap area. The second via hole 322 may be connected to the drain electrode overlap area.
  • the extremely overlapping area forms the second groove 52, a portion of the first conductive layer 34 can be disposed on the groove wall and bottom of the second groove 52, and a portion of the second conductive layer 35 can be disposed in the second groove 52 and is disposed in the second groove 52.
  • the first conductive layer 34 in the second groove 52 is in contact, thereby achieving electrical connection between the drain electrode and the drain connecting area.
  • the second conductive layer 35 may be disposed on the interlayer insulating layer 33 , and another part of the second conductive layer 35 may be disposed in the groove 50 and in contact with the first conductive layer 34 .
  • the second conductive layer 35 can be made of aluminum material with high reflectivity
  • the first conductive layer 34 can be made of metal materials such as titanium or molybdenum, so that the second conductive layer made of aluminum material can be blocked by the first conductive layer 34 35 is in direct contact with the source-drain overlap area of the active layer 31 to avoid short circuit caused by excessive resistance.
  • the second conductive layer 111 in the prior art is not only provided in the via hole extending to the surface of the active layer 105, but also The portion disposed on the second interlayer insulating layer 109 and disposed on the second interlayer insulating layer 109 completely blocks the third conductive layer 112, so that light cannot directly enter the third conductive layer 112. Since the second conductive layer 111 is a titanium or molybdenum material with low reflectivity, resulting in a poor reflected light return rate of the array substrate 100 .
  • a part of the first conductive layer 34 is disposed in the groove 50, and the other part of the first conductive layer 34 is disposed on the interlayer insulating layer 33. Since the first conductive layer 34 is positioned directly on the substrate 201, The projection area is smaller than the orthographic projection area of the second conductive layer 35 on the substrate 201, so that the first conductive layer 34 disposed on the interlayer insulating layer 33 will only block a part of the light incident on the second conductive layer 35. Most of the area on the light incident side of the second conductive layer 35 can directly receive light. Since the second conductive layer 35 is made of aluminum material with high reflectivity, the reflected light return rate of the array substrate 200 can be improved.
  • the first part of the second conductive layer 35 is disposed on the interlayer insulating layer 33
  • the second part of the second conductive layer 35 is disposed in the groove 50
  • the second conductive layer 35 is disposed on the interlayer insulating layer 33 .
  • the connection position between the first part and the second part of 35 is at the notch of the groove 50.
  • a part of the first conductive layer 34 can be provided near the notch of the groove 50.
  • the first conductive layer 34 may be disposed on the interlayer insulating layer, and at least part of the first conductive layer 34 may be connected to the first conductive layer 34 disposed in the groove 50 , so that in the groove of the groove 50 The second conductive layer 35 is blocked at the opening position.
  • the orthographic projection area of the first conductive layer 34 disposed at the notch position of the groove 50 on the substrate 201 needs to be located in the orthographic projection area of the first part of the second conductive layer 35 on the substrate 201, thereby avoiding at least part of the
  • the first conductive layer 34 greatly blocks the incident light in the first part of the second conductive layer 35 and affects the reflected light return rate of the array substrate 200 .
  • the third conductive layer 36 can be disposed on the first part of the second conductive layer 35, and since the second conductive layer 35 is made of aluminum material, in order to avoid the high temperature causing the aluminum material to form hills, the third conductive layer 36 can be To suppress the second conductive layer 35 , the orthographic projection area of the second conductive layer 35 on the substrate 201 needs to be located within the orthographic projection area of the third conductive layer 36 on the substrate 201 .
  • the first conductive layer 34 and the third conductive layer 36 can be made of the same material, such as titanium or molybdenum and other metal materials.
  • the reflectivity of the second conductive layer 35 can be made greater than that of the first conductive layer 34.
  • the reflectivity of the conductive layer 34 and the third conductive layer 36, that is, the second conductive layer 35 is made of aluminum material.
  • the second conductive layer 35 is made of an aluminum material with high reflectivity, and the first conductive layer 34 is only provided in the groove 50 but not on the interlayer insulating layer 33 .
  • the incident light of the two conductive layers 35 affects the reflected light return rate of the array substrate 200 .
  • the third conductive layer 36 by arranging the third conductive layer 36 on the second conductive layer 35, the second conductive layer 35 made of aluminum material is suppressed from forming hills, thereby improving the stability of the array substrate 200.
  • the array substrate 200 provided in this embodiment may also include a first buffer layer 37, a second buffer layer 38, a fourth conductive layer 39 and a fifth conductive layer 40.
  • the layer 37 , the second buffer layer 38 , the fourth conductive layer 39 and the fifth conductive layer 40 are all disposed in the reflective area 203 .
  • the first buffer layer 37 is provided on the substrate 201
  • the second buffer layer 38 is provided on the first buffer layer 37
  • the fourth conductive layer 39 is disposed on the substrate 201
  • the fifth conductive layer 40 is disposed on the fourth conductive layer 39.
  • the fourth conductive layer 39 and the fifth conductive layer 40 define patterns through a patterning process, so that the fourth conductive layer 39 and the fifth conductive layer 40 covers the first buffer layer 37, the fourth conductive layer 39 and the fifth conductive layer 40 are disposed between the substrate 201 and the active layer 31, the fifth conductive layer 40 is disposed in the fourth conductive layer 39 is away from the side of the substrate 201 , and the light reflectance of the fourth conductive layer 39 is greater than the light reflectance of the fifth conductive layer 40 .
  • the fourth conductive layer 39 can be made of aluminum material. However, since the aluminum material will form hills at high temperatures, the fourth conductive layer 39 is suppressed by the fifth conductive layer 40 , therefore, it is required that the orthographic projection area of the fourth conductive layer 39 on the substrate 201 is located within the orthographic projection area of the fifth conductive layer 40 on the substrate 201 .
  • the fifth conductive layer 40 can be made of metal materials such as titanium or molybdenum, and the reflectivity of the fourth conductive layer 39 is greater than the reflectance of the fifth conductive layer 40 , that is, the reflectivity of aluminum is greater than the reflectance of titanium or molybdenum.
  • the array substrate 200 may also include a gate insulating layer 41 and a gate layer 42, wherein the gate insulating layer 41 is disposed on the second buffer layer 38; the active layer 31 is also disposed on the second buffer layer 38, and The pattern is defined through a patterning process, and the active layer 31 covers the gate insulating layer 41 .
  • the interlayer insulating layer 33 may include a first interlayer insulating layer 331 and a second interlayer insulating layer 332.
  • the first interlayer insulating layer 331 is disposed on the gate insulating layer 41, and the second interlayer insulating layer 332 is disposed on the first interlayer insulating layer 331.
  • the gate layer 42 is disposed on the gate insulating layer 41, and the gate layer 42 covers the first interlayer insulating layer 331.
  • the orthographic projection area of the gate layer 42 on the substrate 201 is located at The source layer 31 is within the orthographic projection area on the substrate 201, so that the gate layer 42 serves as the gate of the thin film transistor in the array substrate 200; the fourth conductive layer 39 and the fifth conductive layer 40 can serve as the light shielding layer of the array substrate 200, Therefore, the orthographic projection area of the fourth conductive layer 39 and the fifth conductive layer 40 on the substrate 201 can be disposed within the active layer 31 , so that the pair of the fourth conductive layer 39 and the fifth conductive layer 40 is composed of the active layer 31
  • the thin film transistor plays a light-shielding role.
  • the array substrate 200 may also include a flat layer 43 disposed on the second interlayer insulating layer 332, a part of the second conductive layer 35 and the third conductive layer 36 covering the flat layer 43, the second conductive layer
  • the contact surface between a part of 35 and the second interlayer insulating layer 332 is the light incident side of a part of the second conductive layer 35, so that the reflection rate of the array substrate 200 is improved by using the second conductive layer 35 of aluminum material.
  • the second conductive layer 35 is made of aluminum material with high reflectivity, but also a part of the first conductive layer 34 provided on the interlayer insulating layer 33 is placed directly on the substrate 201
  • the projection area is set smaller than the orthographic projection area of the second conductive layer 35 on the substrate 201, so that the first conductive layer 34 will not affect the incident light of the second conductive layer 35, thereby improving the reflection rate of the array substrate 200.
  • the fourth conductive layer 39 is made of an aluminum material with a high reflectivity, thereby further improving the reflected light return rate of the array substrate 200 .
  • the second conductive layer 35 using aluminum material is suppressed from forming hillocks, and by providing the fifth conductive layer 40 on the fourth conductive layer 39, the use of aluminum is suppressed.
  • the fourth conductive layer 39 of material forms hillocks to improve the stability of the array substrate 200 .
  • FIG. 4 is a flowchart of a method of preparing an array substrate provided by an embodiment of the present application. Schematic diagram. The preparation method of the array substrate may include the following steps:
  • the substrate 201 provided in this embodiment can be a glass substrate or the like.
  • a first buffer layer 37 and a second buffer layer 38 are also formed on the substrate 201 .
  • the first buffer layer 37 is provided on the substrate 201
  • the second buffer layer 38 is provided on the first buffer layer 37 .
  • the fourth conductive layer 39 is provided on the substrate 201 .
  • the fifth conductive layer 40 is disposed on the fourth conductive layer 39.
  • the fourth conductive layer 39 and the fifth conductive layer 40 define patterns through a patterning process, so that the fourth conductive layer 39 and the fifth conductive layer 40 cover the first buffer layer.
  • the fourth conductive layer 39 and the fifth conductive layer 40 are disposed between the substrate 201 and the active layer 31
  • the fifth conductive layer 40 is disposed on the side of the fourth conductive layer 39 away from the substrate 201
  • the fourth conductive layer 39 is disposed between the substrate 201 and the active layer 31.
  • the light reflectance of layer 39 is greater than that of fifth conductive layer 40 .
  • the fourth conductive layer 39 can be made of aluminum material. However, since the aluminum material will form hills at high temperatures, the fourth conductive layer 39 is suppressed by the fifth conductive layer 40 , therefore, it is required that the orthographic projection area of the fourth conductive layer 39 on the substrate 201 is located within the orthographic projection area of the fifth conductive layer 40 on the substrate 201 .
  • the fifth conductive layer 40 can be made of metal materials such as titanium or molybdenum, and the reflectivity of the fourth conductive layer 39 is greater than the reflectance of the fifth conductive layer 40 , that is, the reflectivity of aluminum is greater than the reflectance of titanium or molybdenum.
  • the fourth conductive layer 39 and the fifth conductive layer 40 are located between the substrate 201 and the active layer 31 .
  • Source and drain electrodes on the side of the active layer away from the substrate, and the source and drain electrodes are electrically connected to the active layer in the source and drain overlap areas.
  • the active layer 31 is disposed on one side of the substrate, and the active layer includes a source-drain overlap region; the source-drain electrode is disposed on a side of the active layer 31 away from the substrate 201, and in the source-drain overlap region electrically connected to the active layer 31 .
  • the source and drain electrodes may include a first conductive layer 34, a second conductive layer 35, and a third conductive layer 36, wherein the first conductive layer 34 is disposed close to the active layer 31, and the third conductive layer 36 is disposed on the first conductive layer 36.
  • the layer 34 is on a side away from the active layer 31 , and the second conductive layer 35 is disposed between the first conductive layer 34 and the third conductive layer 36 .
  • the light reflectance of the second conductive layer 35 is greater than the light reflectance of the first conductive layer 34 , the light reflectance of the second conductive layer 35 is greater than the light reflectance of the third conductive layer 36 , and the first conductive layer 34 is on the substrate 201
  • the orthographic projection area on the substrate 201 is smaller than the orthographic projection area of the second conductive layer 35 on the substrate 201 .
  • the active layer 31 may include a source-drain connecting area for connecting the source-drain wiring, thereby achieving electrical connection with the source-drain electrode through the source-drain wiring.
  • the reflective area 203 may also include via holes 32, an interlayer insulating layer 33 and a gate insulating layer 41.
  • the gate insulating layer 41 covers the active layer 31, and the interlayer insulating layer 33 is disposed away from the gate insulating layer 41 and away from the active layer 31. layer 31 side, and the interlayer insulating layer 33 is disposed between the first conductive layer 34 and the active layer 31 .
  • the via hole 32 penetrates the gate insulating layer 41 and the interlayer insulating layer 33 and is located between the source and drain electrodes and the active layer 31 . That is, the via hole 32 may extend from the upper surface of the interlayer insulating layer 33 to the source-drain overlap area in the active layer 31 , and the via hole 32 may form a groove 50 with the source-drain overlap area.
  • the source and drain electrodes may include source electrodes and drain electrodes
  • the source and drain overlap areas may include source overlap areas and drain overlap areas
  • the via holes 32 may include first via holes 321 and second via holes 322
  • the first via hole 321 can extend from the upper surface of the interlayer insulating layer 33 to the source overlap area, that is, the first via hole 321 is provided between the source electrode and the source overlap area, and the first via hole 321 can be connected to the source electrode.
  • the source overlap area forms the first groove 51, a part of the first conductive layer 34 can be disposed on the groove wall and bottom of the first groove 51, and a part of the second conductive layer 35 can be disposed in the first groove 51 and in conjunction with the disposed
  • the first conductive layer 34 in the first groove 51 contacts, thereby achieving electrical connection between the source electrode and the source connecting area.
  • the second via hole 322 may extend from the upper surface of the interlayer insulating layer 33 to the drain overlap area. That is, the second via hole 322 is disposed between the drain electrode and the drain overlap area. The second via hole 322 may be connected to the drain electrode overlap area.
  • the extremely overlapping area forms the second groove 52, a portion of the first conductive layer 34 can be disposed on the groove wall and bottom of the second groove 52, and a portion of the second conductive layer 35 can be disposed in the second groove 52 and is disposed in the second groove 52.
  • the first conductive layer 34 in the second groove 52 is in contact, thereby achieving electrical connection between the drain electrode and the drain connecting area.
  • the second conductive layer 35 may be disposed on the interlayer insulating layer 33 , and another part of the second conductive layer 35 may be disposed in the groove 50 and in contact with the first conductive layer 34 .
  • the second conductive layer 35 can be made of aluminum material with high reflectivity
  • the first conductive layer 34 can be made of metal materials such as titanium or molybdenum, so that the second conductive layer made of aluminum material can be blocked by the first conductive layer 34 35 is in direct contact with the source-drain overlap area of the active layer 31 to avoid short circuit caused by excessive resistance.
  • the second conductive layer 111 in the prior art is not only provided in the via hole extending to the surface of the active layer 105, but also The portion disposed on the second interlayer insulating layer 109 and disposed on the second interlayer insulating layer 109 completely blocks the third conductive layer 112, so that light cannot directly enter the third conductive layer 112. Since the second conductive layer 111 is a titanium or molybdenum material with low reflectivity, resulting in a poor reflected light return rate of the array substrate 100 .
  • a part of the first conductive layer 34 is disposed in the groove 50, and the other part of the first conductive layer 34 is disposed on the interlayer insulating layer 33. Since the first conductive layer 34 is positioned directly on the substrate 201, The projection area is smaller than the orthographic projection area of the second conductive layer 35 on the substrate 201, so that the first conductive layer 34 disposed on the interlayer insulating layer 33 will only block a part of the light incident on the second conductive layer 35. Most of the area on the light incident side of the second conductive layer 35 can directly receive light. Since the second conductive layer 35 is made of aluminum material with high reflectivity, the reflected light return rate of the array substrate 200 can be improved.
  • the first part of the second conductive layer 35 is disposed on the interlayer insulating layer 33
  • the second part of the second conductive layer 35 is disposed in the groove 50
  • the second conductive layer 35 is disposed on the interlayer insulating layer 33 .
  • the connection position between the first part and the second part of 35 is at the notch of the groove 50.
  • a part of the first conductive layer 34 can be provided near the notch of the groove 50.
  • the first conductive layer 34 may be disposed on the interlayer insulating layer, and at least part of the first conductive layer 34 may be connected to the first conductive layer 34 disposed in the groove 50 , so that in the groove of the groove 50 The second conductive layer 35 is blocked at the opening position.
  • the orthographic projection area of the first conductive layer 34 disposed at the notch position of the groove 50 on the substrate 201 needs to be located in the orthographic projection area of the first part of the second conductive layer 35 on the substrate 201, thereby avoiding at least part of the
  • the first conductive layer 34 greatly blocks the incident light in the first part of the second conductive layer 35 and affects the reflected light return rate of the array substrate 200 .
  • the third conductive layer 36 can be disposed on the first part of the second conductive layer 35, and since the second conductive layer 35 is made of aluminum material, in order to avoid the high temperature causing the aluminum material to form hills, the third conductive layer 36 can be To suppress the second conductive layer 35 , the orthographic projection area of the second conductive layer 35 on the substrate 201 needs to be located within the orthographic projection area of the third conductive layer 36 on the substrate 201 .
  • the first conductive layer 34 and the third conductive layer 36 can be made of the same material, such as titanium or molybdenum and other metal materials.
  • the reflectivity of the second conductive layer 35 can be made greater than that of the first conductive layer 34.
  • the reflectivity of the conductive layer 34 and the third conductive layer 36, that is, the second conductive layer 35 is made of aluminum material.
  • a substrate is provided, a fourth conductive layer is formed on the substrate, a fifth conductive layer is formed on the side of the fourth conductive layer away from the substrate, and an active layer is formed on the substrate.
  • the layer includes a source-drain overlap area, a source-drain electrode is formed on the side of the active layer away from the substrate, and the source-drain electrode is electrically connected to the active layer in the source-drain overlap area.
  • the second conductive layer 35 is an aluminum material with high reflectivity, but also by configuring the orthographic projection area of a portion of the first conductive layer 34 disposed on the interlayer insulating layer 33 on the substrate 201 to be smaller than that of the second conductive layer.
  • the fourth conductive layer 39 is made of an aluminum material with a high reflectivity, thereby further improving the reflected light return rate of the array substrate 200 .
  • the second conductive layer 35 using aluminum material is suppressed from forming hillocks, and by providing the fifth conductive layer 40 on the fourth conductive layer 39, the use of aluminum is suppressed.
  • the fourth conductive layer 39 of material forms hillocks to improve the stability of the array substrate 200 .
  • An embodiment of the present application also provides a display panel.
  • the display panel includes the array substrate 200 provided in the above embodiment, a color filter substrate and a liquid crystal layer.
  • the array substrate 200 and the color filter substrate are arranged opposite to each other, and the liquid crystal layer is arranged between the array substrate 200 and the color filter substrate. between color filter substrates.
  • An embodiment of the present application also provides a display device, which may include the display panel provided in the above embodiment.
  • the display device may be a full-screen display device.
  • the display device may be a wearable device such as a watch or a bracelet, or the display device may be an electronic device such as a mobile phone or a tablet computer.
  • the display device includes the display panel provided in the above embodiment and a backlight module disposed on the light incident side of the display panel. The backlight module is used to provide illumination for the display panel.

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Abstract

本申请公开了一种阵列基板、阵列基板的制备方法、显示面板和显示装置，阵列基板包括：靠近有源层的第一导电层、第一导电层远离有源层一侧的第三导电层、以及两导电层之间的第二导电层，第二导电层的光反射率大于第一导电层以及第三导电层的光反射率，第一导电层在衬底上的正投影区域小于第二导电层在衬底上的正投影区域。

Description

阵列基板、阵列基板的制备方法、显示面板和显示装置 技术领域
本申请属于显示技术领域，尤其涉及一种阵列基板、阵列基板的制备方法、显示面板和显示装置。
 背景技术
随着显示技术的不断进步和发展，使用薄膜晶体管(Thin Film Transistor，TFT)作为开关器件的液晶显示屏(Liquid Crystal Display，LCD)具有低成本、高分辨率、使用寿命长等优势受到人们青睐。
然而，TFT-LCD是一种被动式显示面板，需要配合背光模组进行图像显示，背光模组所发出的背光源透过TFT-LCD显示面板前后的光强之比被称为光效。
 技术问题
目前，TFT-LCD显示面板被有效利用的光效只有3-10%。TFT-LCD显示面板的阵列基板包括透光区和反光区，反光区将背光源发出的光线反射再由背光反射至透光区，由此提高TFT-LCD显示面板的光效。因此，如何提高阵列基板中反光区的反射率是目前亟需解决的问题。
 技术解决方案
本申请实施例提供一种列基板、阵列基板的制备方法、显示面板和显示装置，在保证源漏电极与有源层电连接关系的基础上，提高阵列基板的反光率。
第一方面，本申请实施例提供一种阵列基板，包括：
衬底；
有源层，设置于所述衬底的一侧，所述有源层包括源漏极搭接区；
源漏电极，设置于所述有源层的远离所述衬底的一侧，且在所述源漏极搭接区与所述有源层电连接；
其中，所述源漏电极包括靠近所述有源层设置的第一导电层、设置于所述第一导电层的远离所述有源层一侧的第三导电层、以及设置于所述第一导电层与所述第三导电层之间的第二导电层，所述第二导电层的光反射率大于所述第一导电层的光反射率，且所述第二导电层的光反射率大于所述第三导电层的光反射率，所述第一导电层在所述衬底上的正投影区域小于所述第二导电层在所述衬底上的正投影区域。
第二方面，本申请实施例还提供一种阵列基板的制备方法，包括：
提供一衬底；
在所述衬底上形成有源层，所述有源层包括源漏极搭接区；
在所述有源层远离所述衬底一侧形成源漏电极，所述源漏电极在所述源漏极搭接区与所述有源层电连接；
其中，所述源漏电极包括靠近所述有源层设置的第一导电层、设置于所述第一导电层的远离所述有源层一侧的第三导电层、以及设置于所述第一导电层与所述第三导电层之间的第二导电层，所述第二导电层的光反射率大于所述第一导电层的光反射率，且所述第二导电层的光反射率大于所述第三导电层的光反射率，所述第一导电层在所述衬底上的正投影区域小于所述第二导电层在所述衬底上的正投影区域。
 有益效果
本申请实施例提供的阵列基板包括衬底；有源层，设置于衬底的一侧，有源层包括源漏极搭接区；源漏电极，设置于有源层的远离衬底的一侧，且在源漏极搭接区与有源层电连接；其中，源漏电极包括靠近有源层设置的第一导电层、设置于第一导电层的远离有源层一侧的第三导电层、以及设置于第一导电层与第三导电层之间的第二导电层，第二导电层的光反射率大于第一导电层的光反射率，且第二导电层的光反射率大于第三导电层的光反射率，第一导电层在衬底上的正投影区域小于第二导电层在衬底上的正投影区域。本申请在保证源漏电极与有源层电连接关系的基础上，提高阵列基板的反光率。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其有益效果显而易见。
图1为本申请实施例提供的现有技术中阵列基板的结构示意图。
图2为本申请实施例提供的阵列基板的第一种结构示意图。
图3为本申请实施例提供的阵列基板的第二种结构示意图。
图4为本申请实施例提供的阵列基板的制备方法的流程示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其它元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
请参阅图1，图1为本申请实施例提供的现有技术中阵列基板的结构示意图。其中，阵列基板100可以包括衬底101、第一导电层102、第一缓冲层103、第二缓冲层104、有源层105、栅极绝缘层106、栅极层107、第一层间绝缘层108、第二层间绝缘层109、平坦层110、第二导电层111、第三导电层112以及第四导电层113。上述多个膜层102-113均设置在阵列基板100的反光区。
其中，第一导电层102可以为钼、钛、铝等金属材料制成，其中，金属钼的反射率约为52%，金属钛的反射率约为60%，金属铝的反射率约为97%。如果选用钼或钛作为第一导电层102的材料，则反射率较低从而影响阵列基板100的反射回光率，相比之下，选用铝作为第一导电层102的材料更好，但是高温制程会使得铝材料的电阻急剧增加，并且铝材料在高温下体积会发生膨胀，而由于衬底101的存在会限制膨胀，限制膨胀产生的压缩应力会通过原子扩散的方式释放，沿着晶粒边界扩散形成会小丘。
另外，第二导电层111、第三导电层112以及第四导电层113通过过孔与有源层105的源漏极搭接区搭接，实现电连接。其中，第二导电层111和第四导电层113可以均采用钼或钛等金属材料，第三导电层112可以采用铝材料，第二导电层111、第三导电层112以及第四导电层113形成三层结构。需要说明的是，铝材料与有源层105直接接触会产生较大的电阻，因此，需要在第三导电层112与有源层105之间设置第二导电层111来防止电阻过大造成短路。
由上可知，现有技术中提供的阵列基板100的第一导电层102无法采用反射率较高的铝材料来提高阵列基板100的反射回光率，且采用铝材料的第三导电层112需要通过第二导电层111作为间隔与有源层105实现接触。
为解决现有技术中存在的问题，本申请实施例提供一种阵列基板、阵列基板的制备方法、显示面板和显示装置。请参阅图2和图3，图2为本申请实施例提供的阵列基板的第一种结构示意图，图3为本申请实施例提供的阵列基板的第二种结构示意图。
其中，该阵列基板200可以包括衬底201和设置在衬底出光侧上的透光区202和反光区203。透光区202可以包括多个子透光区2021，反光区203可以包括多个子反光区2031。多个子透光区2021与多个子反光区2031依次相邻设置，即多个子透光区2021依次间隔设置，多个子反光区2031依次间隔设置，任一子透光区2021设置在相邻的两个子反光区2031之间或者任一子透光区2021与至少一个子反光区2031相邻设置。可以将每一子透光区2021在衬底201上正投影区域设置大于每一子反光区2031在衬底201上正投影区域，从而增大子透光区2021的尺寸，提高阵列基板200的透光率。
其中，阵列基板200可以包括衬底201、有源层31和源漏电极，有源层31设置于衬底的一侧，且有源层包括源漏极搭接区；源漏电极设置于有源层31的远离衬底201的一侧，且在源漏极搭接区与有源层31电连接。有源层31和源漏电极均设置在反光区203。
源漏电极可以包括第一导电层34、第二导电层35以及第三导电层36，其中，第一导电层34设置在靠近有源层31一侧，第三导电层36设置在第一导电层34远离有源层31一侧，以及第二导电层35设置在第一导电层34与第三导电层36之间。第二导电层35的光反射率大于第一导电层34的光反射率，第二导电层35的光反射率大于第三导电层36的光反射率，且第一导电层34在衬底201上的正投影区域小于第二导电层35在衬底201上的正投影区域。
有源层31可以包括源漏极搭接区，用于连接源漏极走线，从而通过源漏极走线实现与源漏电极的电连接。
反光区203还可以包括过孔32、层间绝缘层33和栅极绝缘层41，栅极绝缘层41覆盖在有源层31上，层间绝缘层33设置在栅极绝缘层41远离有源层31一侧，且层间绝缘层33设置在第一导电层34与有源层31之间。过孔32贯穿栅极绝缘层41和层间绝缘层33且位于源漏电极与有源层31之间。即过孔32可以从层间绝缘层33的上表面延伸至有源层31中的源漏极搭接区，过孔32可以与源漏极搭接区形成凹槽50。
具体地，源漏电极可以包括源电极和漏电极，源漏极搭接区可以包括源极搭接区和漏极搭接区，过孔32可以包括第一过孔321和第二过孔322，第一过孔321可以从层间绝缘层33的上表面延伸至源极搭接区，即第一过孔321设置在源电极与源极搭接区之间，第一过孔321可以与源极搭接区形成第一凹槽51，一部分第一导电层34可以设置在第一凹槽51的槽壁和底部，一部分第二导电层35可以设置在第一凹槽51内且与设置在第一凹槽51内的第一导电层34接触，从而实现源电极与源极搭接区的电连接。
第二过孔322可以从层间绝缘层33的上表面延伸至漏极搭接区，即第二过孔322设置在漏电极与漏极搭接区之间，第二过孔322可以与漏极搭接区形成第二凹槽52，一部分第一导电层34可以设置在第二凹槽52的槽壁和底部，一部分第二导电层35可以设置在第二凹槽52内且与设置在第二凹槽52内的第一导电层34接触，从而实现漏电极与漏极搭接区的电连接。
可以理解的是，一部分第二导电层35可以设置在层间绝缘层33上，另一部分第二导电层35可以设置在凹槽50内，并且与第一导电层34接触。其中，第二导电层35可以选用反射率较高的铝材料，第一导电层34可以选用钛或钼等金属材料，从而通过第一导电层34来阻隔由铝材料制成的第二导电层35与有源层31的源漏极搭接区直接接触，避免电阻过大造成的短路现象。
需要说明的是，对比图1和图3可知，本实施例与现有技术的区别在于：现有技术中的第二导电层111不仅设置在延伸至有源层105表面的过孔内，还设置在第二层间绝缘层109上，且设置在第二层间绝缘层109的部分对第三导电层112完全遮挡，从而使得光线无法直接入射至第三导电层112，由于第二导电层111为钛或钼材料，反射率较低，从而导致阵列基板100的反射回光率较差。而本实施例中的第一导电层34的一部分设置在凹槽50内，第一导电层34的另一部分设置在层间绝缘层33上，由于第一导电层34在衬底201上的正投影区域小于第二导电层35在衬底201上的正投影区域，从而使得设置在层间绝缘层33上的第一导电层34只会对入射至第二导电层35的一部分光线进行遮挡，而第二导电层35的入光侧的大部分区域可以直接接收光线，由于第二导电层35采用反射率较高的铝材料，从而可以提高阵列基板200的反射回光率。
还需要说明的是，如图3所示，第二导电层35的第一部分设置在层间绝缘层33上、第二导电层35的第二部分设置在凹槽50内，而第二导电层35第一部分与第二部分的连接位置处于凹槽50的槽口，为了防止第二导电层35由于槽口的刚性发生断裂，可以在凹槽50的槽口附近设置部分第一导电层34。具体地，可以将至少部分第一导电层34设置在层间绝缘层上，且至少部分第一导电层34与设置在凹槽50内的第一导电层34连接，从而在凹槽50的槽口位置对第二导电层35进行阻挡。
但是，在凹槽50的槽口位置设置的至少部分第一导电层34在衬底201上正投影区域需要位于第二导电层35的第一部分在衬底201上正投影区域，从而避免至少部分第一导电层34对第二导电层35的第一部分的入射光线产生较大的阻挡而影响阵列基板200的反射回光率。
另外，第三导电层36可以设置在第二导电层35的第一部分上，且由于第二导电层35采用的是铝材料，为了避免高温使得铝材料形成小丘，可以通过第三导电层36对第二导电层35进行抑制，因此需要将第二导电层35在衬底201上正投影区域位于第三导电层36在衬底201上正投影区域内。其中，第一导电层34和第三导电层36可以采用相同材料，如钛或钼等金属材料，为提高阵列基板200的反射回光率，可以使第二导电层35的反射率大于第一导电层34和第三导电层36的反射率，即第二导电层35采用铝材料。
由上可知，本实施例通过将第二导电层35设置为反射率较高的铝材料，并将第一导电层34仅设置在凹槽50内而未设置在层间绝缘层33上对第二导电层35的入射光线产生影响，提高阵列基板200的反射回光率。另外，通过在第二导电层35上设置第三导电层36来抑制采用铝材料的第二导电层35形成小丘，提高阵列基板200的稳定性。
为了进一步提高阵列基板200的反射回光率，本实施例提供的阵列基板200还可以包括第一缓冲层37、第二缓冲层38、第四导电层39和第五导电层40，第一缓冲层37、第二缓冲层38、第四导电层39和第五导电层40均设置在反光区203。
其中，第一缓冲层37设置在衬底201上，第二缓冲层38设置在第一缓冲层37上。第四导电层39设置在衬底201上，第五导电层40设置在第四导电层39上，第四导电层39和第五导电层40通过构图工艺定义出图形，使得第四导电层39和第五导电层40覆盖在第一缓冲层37内，第四导电层39和第五导电层40设置在衬底201与有源层31之间，第五导电层40设置在第四导电层39远离衬底201一侧，且第四导电层39的光反射率大于第五导电层40的光反射率。
其中，为提高阵列基板的反射回光率，可以将第四导电层39采用铝材料，但是由于铝材料会在高温形成小丘，因此，通过第五导电层40对第四导电层39进行抑制，因此，需要第四导电层39在衬底201上的正投影区域位于第五导电层40在衬底201上正投影区域内。第五导电层40可以采用钛或钼等金属材料，且第四导电层39的反射率大于第五导电层40的反射率，即铝的反射率大于钛或钼的反射率。
另外，阵列基板200还可以包括栅极绝缘层41和栅极层42，其中，栅极绝缘层41设置在第二缓冲层38上；有源层31也设置在第二缓冲层38上，且通过构图工艺定义出图形，有源层31覆盖在栅极绝缘层41内。
层间绝缘层33可以包括第一层间绝缘层331和第二层间绝缘层332，第一层间绝缘层331设置在栅极绝缘层41上，第二层间绝缘层332设置在第一层间绝缘层331上；栅极层42设置在栅极绝缘层41上，且栅极层42覆盖在第一层间绝缘层331内，栅极层42在衬底201上正投影区域位于有源层31在衬底201上正投影区域内，从而使得栅极层42作为阵列基板200中薄膜晶体管的栅极；第四导电层39和第五导电层40可以作为阵列基板200的遮光层，从而可以将第四导电层39和第五导电层40在衬底201上的正投影区域设置在有源层31内，使得第四导电层39和第五导电层40对由有源层31组成的薄膜晶体管起到遮光作用。
另外，阵列基板200还可以包括平坦层43，平坦层43设置在第二层间绝缘层332上，第二导电层35的一部分和第三导电层36覆盖在平坦层43内，第二导电层35的一部分与第二层间绝缘层332的接触面为第二导电层35的一部分的入光侧，从而通过采用铝材料的第二导电层35提高阵列基板200的反射回光率。
由上可知，本实施例中不仅通过将第二导电层35设置为反射率较高的铝材料，并将设置在层间绝缘层33上的一部分第一导电层34在衬底201上的正投影区域设置小于第二导电层35在衬底201上的正投影区域，从而使得第一导电层34不会对第二导电层35的入射光线产生影响，进而提高阵列基板200的反射回光率。另外还通过将第四导电层39设置为反射率较高的铝材料，进一步提高阵列基板200的反射回光率。
另外，通过在第二导电层35上设置第三导电层36来抑制采用铝材料的第二导电层35形成小丘，以及通过在第四导电层39上设置第五导电层40来抑制采用铝材料的第四导电层39形成小丘，提高阵列基板200的稳定性。
为进一步对提高阵列基板200的反射回光率的说明，本申请实施例还提供一种阵列基板的制备方法，请参阅图4，图4为本申请实施例提供的阵列基板的制备方法的流程示意图。该阵列基板的制备方法可以包括以下步骤：
601，提供一衬底。
请继续参阅图2和图3，本实施例提供的衬底201可以为玻璃衬底等。
602，在衬底上形成第四导电层。
在衬底201上还形成有第一缓冲层37和第二缓冲层38。第一缓冲层37设置在衬底201上，第二缓冲层38设置在第一缓冲层37上。第四导电层39设置在衬底201上。
603，在第四导电层远离衬底一侧形成第五导电层。
第五导电层40设置在第四导电层39上，第四导电层39和第五导电层40通过构图工艺定义出图形，使得第四导电层39和第五导电层40覆盖在第一缓冲层37内，第四导电层39和第五导电层40设置在衬底201与有源层31之间，第五导电层40设置在第四导电层39远离衬底201一侧，且第四导电层39的光反射率大于第五导电层40的光反射率。
其中，为提高阵列基板的反射回光率，可以将第四导电层39采用铝材料，但是由于铝材料会在高温形成小丘，因此，通过第五导电层40对第四导电层39进行抑制，因此，需要第四导电层39在衬底201上的正投影区域位于第五导电层40在衬底201上正投影区域内。第五导电层40可以采用钛或钼等金属材料，且第四导电层39的反射率大于第五导电层40的反射率，即铝的反射率大于钛或钼的反射率。
604，在衬底上形成有源层，有源层包括源漏极搭接区。
需要说明的是，第四导电层39和第五导电层40位于衬底201与有源层31之间。
605，在有源层远离衬底一侧形成源漏电极，源漏电极在源漏极搭接区与有源层电连接。
有源层31设置于衬底的一侧，且有源层包括源漏极搭接区；源漏电极设置于有源层31的远离衬底201的一侧，且在源漏极搭接区与有源层31电连接。
源漏电极可以包括第一导电层34、第二导电层35以及第三导电层36，其中，第一导电层34设置在靠近有源层31一侧，第三导电层36设置在第一导电层34远离有源层31一侧，以及第二导电层35设置在第一导电层34与第三导电层36之间。第二导电层35的光反射率大于第一导电层34的光反射率，第二导电层35的光反射率大于第三导电层36的光反射率，且第一导电层34在衬底201上的正投影区域小于第二导电层35在衬底201上的正投影区域。
有源层31可以包括源漏极搭接区，用于连接源漏极走线，从而通过源漏极走线实现与源漏电极的电连接。
反光区203还可以包括过孔32、层间绝缘层33和栅极绝缘层41，栅极绝缘层41覆盖在有源层31上，层间绝缘层33设置在栅极绝缘层41远离有源层31一侧，且层间绝缘层33设置在第一导电层34与有源层31之间。过孔32贯穿栅极绝缘层41和层间绝缘层33且位于源漏电极与有源层31之间。即过孔32可以从层间绝缘层33的上表面延伸至有源层31中的源漏极搭接区，过孔32可以与源漏极搭接区形成凹槽50。
具体地，源漏电极可以包括源电极和漏电极，源漏极搭接区可以包括源极搭接区和漏极搭接区，过孔32可以包括第一过孔321和第二过孔322，第一过孔321可以从层间绝缘层33的上表面延伸至源极搭接区，即第一过孔321设置在源电极与源极搭接区之间，第一过孔321可以与源极搭接区形成第一凹槽51，一部分第一导电层34可以设置在第一凹槽51的槽壁和底部，一部分第二导电层35可以设置在第一凹槽51内且与设置在第一凹槽51内的第一导电层34接触，从而实现源电极与源极搭接区的电连接。
第二过孔322可以从层间绝缘层33的上表面延伸至漏极搭接区，即第二过孔322设置在漏电极与漏极搭接区之间，第二过孔322可以与漏极搭接区形成第二凹槽52，一部分第一导电层34可以设置在第二凹槽52的槽壁和底部，一部分第二导电层35可以设置在第二凹槽52内且与设置在第二凹槽52内的第一导电层34接触，从而实现漏电极与漏极搭接区的电连接。
可以理解的是，一部分第二导电层35可以设置在层间绝缘层33上，另一部分第二导电层35可以设置在凹槽50内，并且与第一导电层34接触。其中，第二导电层35可以选用反射率较高的铝材料，第一导电层34可以选用钛或钼等金属材料，从而通过第一导电层34来阻隔由铝材料制成的第二导电层35与有源层31的源漏极搭接区直接接触，避免电阻过大造成的短路现象。
需要说明的是，对比图1和图3可知，本实施例与现有技术的区别在于：现有技术中的第二导电层111不仅设置在延伸至有源层105表面的过孔内，还设置在第二层间绝缘层109上，且设置在第二层间绝缘层109的部分对第三导电层112完全遮挡，从而使得光线无法直接入射至第三导电层112，由于第二导电层111为钛或钼材料，反射率较低，从而导致阵列基板100的反射回光率较差。而本实施例中的第一导电层34的一部分设置在凹槽50内，第一导电层34的另一部分设置在层间绝缘层33上，由于第一导电层34在衬底201上的正投影区域小于第二导电层35在衬底201上的正投影区域，从而使得设置在层间绝缘层33上的第一导电层34只会对入射至第二导电层35的一部分光线进行遮挡，而第二导电层35的入光侧的大部分区域可以直接接收光线，由于第二导电层35采用反射率较高的铝材料，从而可以提高阵列基板200的反射回光率。
还需要说明的是，如图3所示，第二导电层35的第一部分设置在层间绝缘层33上、第二导电层35的第二部分设置在凹槽50内，而第二导电层35第一部分与第二部分的连接位置处于凹槽50的槽口，为了防止第二导电层35由于槽口的刚性发生断裂，可以在凹槽50的槽口附近设置部分第一导电层34。具体地，可以将至少部分第一导电层34设置在层间绝缘层上，且至少部分第一导电层34与设置在凹槽50内的第一导电层34连接，从而在凹槽50的槽口位置对第二导电层35进行阻挡。
但是，在凹槽50的槽口位置设置的至少部分第一导电层34在衬底201上正投影区域需要位于第二导电层35的第一部分在衬底201上正投影区域，从而避免至少部分第一导电层34对第二导电层35的第一部分的入射光线产生较大的阻挡而影响阵列基板200的反射回光率。
另外，第三导电层36可以设置在第二导电层35的第一部分上，且由于第二导电层35采用的是铝材料，为了避免高温使得铝材料形成小丘，可以通过第三导电层36对第二导电层35进行抑制，因此需要将第二导电层35在衬底201上正投影区域位于第三导电层36在衬底201上正投影区域内。其中，第一导电层34和第三导电层36可以采用相同材料，如钛或钼等金属材料，为提高阵列基板200的反射回光率，可以使第二导电层35的反射率大于第一导电层34和第三导电层36的反射率，即第二导电层35采用铝材料。
由上可知，本实施例通过提供一衬底，在衬底上形成第四导电层，在第四导电层远离衬底一侧形成第五导电层，在衬底上形成有源层，有源层包括源漏极搭接区，在有源层远离衬底一侧形成源漏电极，源漏电极在源漏极搭接区与有源层电连接。不仅通过将第二导电层35设置为反射率较高的铝材料，并将设置在层间绝缘层33上的一部分第一导电层34在衬底201上的正投影区域设置小于第二导电层35在衬底201上的正投影区域，从而使得第一导电层34不会对第二导电层35的入射光线产生影响，进而提高阵列基板200的反射回光率。另外还通过将第四导电层39设置为反射率较高的铝材料，进一步提高阵列基板200的反射回光率。
另外，通过在第二导电层35上设置第三导电层36来抑制采用铝材料的第二导电层35形成小丘，以及通过在第四导电层39上设置第五导电层40来抑制采用铝材料的第四导电层39形成小丘，提高阵列基板200的稳定性。
本申请实施例还提供了一种显示面板，该显示面板包括上述实施例提供的阵列基板200、彩膜基板和液晶层，阵列基板200与彩膜基板相对设置，液晶层设置在阵列基板200与彩膜基板之间。
本申请实施例还提供了一种显示装置，该显示装置可包括上述实施例提供的显示面板。该显示装置可以为全面屏显示装置，例如，该显示装置可以为手表、手环等可穿戴设备，或者，该显示装置可以为手机或平板电脑等电子设备等。该显示装置包括如上实施例提供的显示面板和设置于显示面板入光侧的背光模组，背光模组用于为显示面板提供光照。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的阵列基板、阵列基板的制备方法、显示面板和显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其中，包括：
    衬底；
    有源层，设置于所述衬底的一侧，所述有源层包括源漏极搭接区；
    源漏电极，设置于所述有源层的远离所述衬底的一侧，且在所述源漏极搭接区与所述有源层电连接；
    其中，所述源漏电极包括靠近所述有源层设置的第一导电层、设置于所述第一导电层的远离所述有源层一侧的第三导电层、以及设置于所述第一导电层与所述第三导电层之间的第二导电层，所述第二导电层的光反射率大于所述第一导电层的光反射率，且所述第二导电层的光反射率大于所述第三导电层的光反射率，所述第一导电层在所述衬底上的正投影区域小于所述第二导电层在所述衬底上的正投影区域。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括栅极绝缘层和层间绝缘层，所述栅极绝缘层覆盖在所述有源层上，所述层间绝缘层设置在所述栅极绝缘层远离所述有源层一侧，且所述层间绝缘层设置在所述第一导电层与所述有源层之间，所述源漏电极与所述有源层之间设置有贯穿所述栅极绝缘层和所述层间绝缘层的过孔，所述过孔与所述源漏极搭接区形成凹槽。
  3. 根据权利要求2所述的阵列基板，其中，所述源漏电极包括源电极和漏电极，所述源漏极搭接区包括源极搭接区和漏极搭接区，所述过孔包括第一过孔和第二过孔，所述第一过孔设置在所述源电极与所述源极搭接区之间，所述第一过孔与所述源极搭接区形成第一凹槽，一部分所述第一导电层设置在所述第一凹槽的槽壁和底部，一部分所述第二导电层设置在所述第一凹槽内且与设置在所述第一凹槽内的所述第一导电层接触。
  4. 根据权利要求3所述的阵列基板，其中，所述第二过孔设置在所述漏电极与所述漏极搭接区之间，所述第二过孔与所述漏极搭接区形成第二凹槽，一部分所述第一导电层设置在所述第二凹槽的槽壁和底部，一部分所述第二导电层设置在所述第二凹槽内且与设置在所述第二凹槽内的所述第一导电层接触。
  5. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括设置在所述衬底与所述有源层之间的第四导电层和第五导电层，所述第五导电层设置在所述第四导电层远离所述衬底一侧，所述第四导电层的光反射率大于所述第五导电层的光反射率。
  6. 根据权利要求5所述的阵列基板，其中，所述第四导电层在所述衬底上的正投影区域位于所述有源层在所述衬底上的正投影区域内，所述第四导电层在所述衬底上的正投影区域位于所述第五导电层在所述衬底上的正投影区域内。
  7. 根据权利要求1所述的阵列基板，其中，所述第一导电层和所述第三导电层的材料相同。
  8. 根据权利要求1所述的阵列基板，其中，所述第一导电层和所述第三导电层的材料为钛或钼金属材料，所述第二导电层的材料为铝金属材料。
  9. 一种阵列基板的制备方法，其中，包括：
    提供一衬底；
    在所述衬底上形成有源层，所述有源层包括源漏极搭接区；
    在所述有源层远离所述衬底一侧形成源漏电极，所述源漏电极在所述源漏极搭接区与所述有源层电连接；
    其中，所述源漏电极包括靠近所述有源层设置的第一导电层、设置于所述第一导电层的远离所述有源层一侧的第三导电层、以及设置于所述第一导电层与所述第三导电层之间的第二导电层，所述第二导电层的光反射率大于所述第一导电层的光反射率，且所述第二导电层的光反射率大于所述第三导电层的光反射率，所述第一导电层在所述衬底上的正投影区域小于所述第二导电层在所述衬底上的正投影区域。
  10. 根据权利要求9所述的阵列基板的制备方法，其中，在所述衬底上形成有源层之前，所述方法还包括：
    在所述衬底上形成第四导电层；
    在所述第四导电层远离所述衬底一侧形成第五导电层，其中，所述第四导电层的光反射率大于所述第五导电层的光反射率，所述第四导电层在所述衬底上的正投影区域位于所述第五导电层在所述衬底上的正投影区域内。
  11. 一种显示面板，其中，包括：
    阵列基板；
    彩膜基板，与所述阵列基板相对设置；和
    液晶层，设置在所述阵列基板与所述彩膜基板之间。
  12. 根据权利要求11所述的显示面板，其中，所述阵列基板包括：
    衬底；
    有源层，设置于所述衬底的一侧，所述有源层包括源漏极搭接区；
    源漏电极，设置于所述有源层的远离所述衬底的一侧，且在所述源漏极搭接区与所述有源层电连接；
    其中，所述源漏电极包括靠近所述有源层设置的第一导电层、设置于所述第一导电层的远离所述有源层一侧的第三导电层、以及设置于所述第一导电层与所述第三导电层之间的第二导电层，所述第二导电层的光反射率大于所述第一导电层的光反射率，且所述第二导电层的光反射率大于所述第三导电层的光反射率，所述第一导电层在所述衬底上的正投影区域小于所述第二导电层在所述衬底上的正投影区域。
  13. 根据权利要求12所述的显示面板，其中，所述阵列基板还包括栅极绝缘层和层间绝缘层，所述栅极绝缘层覆盖在所述有源层上，所述层间绝缘层设置在所述栅极绝缘层远离所述有源层一侧，且所述层间绝缘层设置在所述第一导电层与所述有源层之间，所述源漏电极与所述有源层之间设置有贯穿所述栅极绝缘层和所述层间绝缘层的过孔，所述过孔与所述源漏极搭接区形成凹槽。
  14. 根据权利要求13所述的显示面板，其中，所述源漏电极包括源电极和漏电极，所述源漏极搭接区包括源极搭接区和漏极搭接区，所述过孔包括第一过孔和第二过孔，所述第一过孔设置在所述源电极与所述源极搭接区之间，所述第一过孔与所述源极搭接区形成第一凹槽，一部分所述第一导电层设置在所述第一凹槽的槽壁和底部，一部分所述第二导电层设置在所述第一凹槽内且与设置在所述第一凹槽内的所述第一导电层接触。
  15. 根据权利要求14所述的显示面板，其中，所述第二过孔设置在所述漏电极与所述漏极搭接区之间，所述第二过孔与所述漏极搭接区形成第二凹槽，一部分所述第一导电层设置在所述第二凹槽的槽壁和底部，一部分所述第二导电层设置在所述第二凹槽内且与设置在所述第二凹槽内的所述第一导电层接触。
  16. 根据权利要求12所述的显示面板，其中，所述阵列基板还包括设置在所述衬底与所述有源层之间的第四导电层和第五导电层，所述第五导电层设置在所述第四导电层远离所述衬底一侧，所述第四导电层的光反射率大于所述第五导电层的光反射率。
  17. 根据权利要求16所述的显示面板，其中，所述第四导电层在所述衬底上的正投影区域位于所述有源层在所述衬底上的正投影区域内，所述第四导电层在所述衬底上的正投影区域位于所述第五导电层在所述衬底上的正投影区域内。
  18. 根据权利要求12所述的显示面板，其中，所述第一导电层和所述第三导电层的材料相同。
  19. 根据权利要求12所述的显示面板，其中，所述第一导电层和所述第三导电层的材料为钛或钼金属材料，所述第二导电层的材料为铝金属材料。
  20. 一种显示装置，其中，包括：
    显示面板，所述显示面板为权利要求11-19任一项所述的显示面板；
    背光模组，设置于所述显示面板的入光侧。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101840100A (zh) * 2009-03-18 2010-09-22 北京京东方光电科技有限公司 液晶显示装置及其彩膜基板的制造方法
CN106531768A (zh) * 2016-12-07 2017-03-22 厦门天马微电子有限公司 一种有机电致发光显示面板及其制备方法
CN108346622A (zh) * 2017-01-25 2018-07-31 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板
CN109037297A (zh) * 2018-08-09 2018-12-18 京东方科技集团股份有限公司 一种有机发光显示基板及其制作方法
CN110911424A (zh) * 2019-12-11 2020-03-24 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN114093893A (zh) * 2021-11-18 2022-02-25 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101840100A (zh) * 2009-03-18 2010-09-22 北京京东方光电科技有限公司 液晶显示装置及其彩膜基板的制造方法
CN106531768A (zh) * 2016-12-07 2017-03-22 厦门天马微电子有限公司 一种有机电致发光显示面板及其制备方法
CN108346622A (zh) * 2017-01-25 2018-07-31 京东方科技集团股份有限公司 阵列基板及其制备方法、显示面板
CN109037297A (zh) * 2018-08-09 2018-12-18 京东方科技集团股份有限公司 一种有机发光显示基板及其制作方法
CN110911424A (zh) * 2019-12-11 2020-03-24 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板
CN114093893A (zh) * 2021-11-18 2022-02-25 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板

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