WO2023216239A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023216239A1
WO2023216239A1 PCT/CN2022/092727 CN2022092727W WO2023216239A1 WO 2023216239 A1 WO2023216239 A1 WO 2023216239A1 CN 2022092727 W CN2022092727 W CN 2022092727W WO 2023216239 A1 WO2023216239 A1 WO 2023216239A1
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WIPO (PCT)
Prior art keywords
width
channel
sub
gate
transistor
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Ceased
Application number
PCT/CN2022/092727
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English (en)
French (fr)
Inventor
鲁凯
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US17/781,008 priority Critical patent/US12165582B2/en
Publication of WO2023216239A1 publication Critical patent/WO2023216239A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • OLED display devices are widely used due to their advantages of self-luminescence and flexibility.
  • Existing OLED display devices use drive circuits based on LTPS (Low Temperature Poly-silicon) technology to drive pixels.
  • LTPS Low Temperature Poly-silicon
  • the transistor connected to the gate of the drive transistor is a double-gate design.
  • Transistors, the semiconductor pattern located between the double-gate structure is susceptible to coupling from other signals, resulting in a higher potential and leakage to the drive transistor during the light-emitting phase.
  • the existing display panel has a problem of display flickering caused by the imbalance of leakage effects of different transistors on the gates of the driving transistors.
  • Embodiments of the present application provide a display panel to alleviate the problem of display flicker caused by the unbalanced leakage influence of different transistors on the gates of driving transistors in existing display panels.
  • An embodiment of the present application provides a display panel, which includes a plurality of light-emitting devices arranged in an array and a pixel driving circuit that drives the light-emitting devices.
  • the pixel driving circuit includes:
  • the first initialization transistor is connected to the first initialization signal line and is used to input the first initialization signal to the first node under the control of the first scan signal;
  • a switching transistor used to input a data signal to the second node under the control of the second scan signal
  • a driving transistor electrically connected to the first node and the second node, for driving the light-emitting device to emit light under the control of the potential of the first node and the second node;
  • a compensation transistor connected to the driving transistor through the first node and the third node, for compensating the threshold voltage of the driving transistor under the control of the third scan signal
  • the compensation transistor includes at least two sub-channels, and a width-to-length ratio of a sub-channel of the compensation transistor close to the driving transistor is smaller than a width-to-length ratio of a channel of the first initialization transistor.
  • the first initialization transistor includes at least two sub-channels, and a width-to-length ratio of a sub-channel of the compensation transistor close to the drive transistor is smaller than that of a sub-channel of the first initialization transistor close to the drive transistor. The width-to-length ratio of the sub-channel.
  • the compensation transistor includes a first channel
  • the first initialization transistor includes a second channel
  • the first channel includes at least a first sub-channel and a second sub-channel
  • the The second channel at least includes a third sub-channel and a fourth sub-channel.
  • the first sub-channel is located on a side of the second sub-channel close to the driving transistor.
  • the third sub-channel is located on The fourth sub-channel is close to a side of the driving transistor
  • the width-to-length ratio of the first sub-channel is smaller than the width-to-length ratio of the third sub-channel
  • the width-to-length ratio of the first channel is The ratio is smaller than the width-to-length ratio of the second channel of the first initialization transistor.
  • the width-to-length ratio of the first sub-channel is smaller than the width-to-length ratio of the second sub-channel, and the width-to-length ratio of the third sub-channel is larger than that of the fourth sub-channel. Width to length ratio.
  • the width-to-length ratio of the second sub-channel is equal to the width-to-length ratio of the fourth sub-channel, or the width-to-length ratio of the second sub-channel is smaller than the fourth sub-channel.
  • the width to length ratio is equal to the width-to-length ratio of the fourth sub-channel, or the width-to-length ratio of the second sub-channel is smaller than the fourth sub-channel.
  • the width-to-length ratio of the first sub-channel is smaller than the width-to-length ratio of the second sub-channel, and the width-to-length ratio of the third sub-channel is equal to the width-to-length ratio of the fourth sub-channel.
  • the width-to-length ratio of the second sub-channel is equal to the width-to-length ratio of the fourth sub-channel.
  • the width-to-length ratio of the third sub-channel is greater than the width-to-length ratio of the fourth sub-channel, and the width-to-length ratio of the first sub-channel is equal to that of the second sub-channel.
  • the width-to-length ratio of the first sub-channel is equal to the width-to-length ratio of the fourth sub-channel.
  • the width-to-length ratio of the first sub-channel is equal to the width-to-length ratio of the second sub-channel
  • the width-to-length ratio of the third sub-channel is equal to the width-to-length ratio of the fourth sub-channel. Width to length ratio.
  • the compensation transistor includes a connected first gate and a second gate, and a first active pattern
  • the first initialization transistor includes a connected third gate and a fourth gate
  • a second The active pattern has a first overlapping area in the first sub-channel, the first active pattern and the first gate, and in the second sub-channel, the first active pattern and the first gate electrode have a first overlapping area.
  • the second gate electrode has a second overlapping area, and in the third sub-channel, the second active pattern and the third gate electrode have a third overlapping area, and in the fourth sub-channel, There is a fourth overlapping area between the second active pattern and the fourth gate;
  • the ratio of the width of the first active pattern located in the first overlapping area to the width of the first gate electrode is equal to the width of the first active pattern located in the second overlapping area and the width of the second gate electrode.
  • the ratio of the width of the second active pattern located in the third overlapping area to the width of the third gate electrode is equal to the width of the second active pattern located in the fourth overlapping area and the width of the third gate electrode.
  • the ratio of the width of the fourth gate electrode, and the ratio of the width of the first active pattern located in the first overlapping area to the width of the first gate electrode is smaller than that of the second active pattern located in the third overlapping area.
  • the ratio of the width of the pattern to the width of the third gate is equal to the width of the first active pattern located in the second overlapping area and the width of the second gate electrode.
  • the width of the first gate located in the first overlapping area is equal to the width of the second gate located in the second overlapping area
  • the width of the third gate located in the third overlapping area is equal to the width of the second gate located in the second overlapping area.
  • the width is equal to the width of the fourth gate located in the fourth overlapping region, and the width of the first gate located in the first overlapping region is greater than the width of the third gate located in the third overlapping region.
  • the width of the first active pattern located in the first overlapping area is equal to the width of the first active pattern located in the second overlapping area
  • the width of the second active pattern located in the third overlapping area is equal to the width of the first active pattern located in the second overlapping area.
  • the width of the source pattern is equal to the width of the second active pattern located in the fourth overlapping area
  • the width of the first active pattern located in the first overlapping area is equal to the width of the second active pattern located in the third overlapping area. The width of the source pattern.
  • the width of the first active pattern located in the first overlapping area is equal to the width of the first active pattern located in the second overlapping area
  • the width of the second active pattern located in the third overlapping area is equal to the width of the first active pattern located in the second overlapping area.
  • the width of the source pattern is equal to the width of the second active pattern located in the fourth overlapping area, and the width of the first active pattern located in the first overlapping area is smaller than the width of the second active pattern located in the third overlapping area. The width of the source pattern.
  • the width of the first gate located in the first overlapping area is equal to the width of the second gate located in the second overlapping area
  • the width of the third gate located in the third overlapping area is equal to the width of the second gate located in the second overlapping area.
  • the width is equal to the width of the fourth gate located in the fourth overlapping area
  • the width of the first gate located in the first overlapping area is equal to or greater than the width of the third gate located in the third overlapping area.
  • the first initialization transistor is a low-temperature polysilicon thin film transistor
  • the compensation transistor is a low-temperature polysilicon thin film transistor
  • the compensation transistor includes a first gate and a second gate
  • the first initialization transistor includes The third gate electrode and the fourth gate electrode, the projections of the first gate electrode and the second gate electrode on the first active pattern have a spacing, the third gate electrode and the fourth gate electrode There is a spacing in the projection onto the second active pattern.
  • adjacent pixel driving circuits arranged laterally are arranged symmetrically, the first initialization transistors in the adjacent pixel driving circuits are connected to the same initialization signal line, and the compensation transistors in the adjacent pixel driving circuits are connected to the same scan line.
  • the pixel driving circuit further includes a second initialization transistor, the second initialization transistor is connected to a second initialization signal line, and is used to input an anode to the light-emitting device under the control of a fourth scan signal. second initialization signal;
  • the first light-emitting control transistor is connected to the driving transistor through the second node, and is used to conduct current from the high-potential signal line of the power supply to the driving transistor under the control of the light-emitting control signal;
  • the second light-emitting control transistor is connected to the driving transistor through a third node, and is used to conduct the current flowing from the driving transistor to the anode of the light-emitting device under the control of the light-emitting control signal.
  • the pixel driving circuit further includes a storage capacitor, one end of the storage capacitor is connected to the power high potential signal line, and the other end of the storage capacitor is connected to the first node.
  • the display panel includes:
  • the pixel driving circuit layer includes multiple pixel driving circuits
  • the pixel driving circuit includes a semiconductor layer, a first metal layer, a second metal layer and a third metal layer that are sequentially stacked on the substrate, and the semiconductor layer includes the first active pattern and the In the second active pattern, the first metal layer includes a first gate, a second gate, a third gate and a fourth gate.
  • the second metal layer forms a plate of a storage capacitor.
  • the third metal layer forms a source electrode and a drain electrode.
  • the present application provides a display panel; the display panel includes a plurality of light-emitting devices arranged in an array and a pixel driving circuit for driving the light-emitting devices.
  • the pixel driving circuit includes a first initialization transistor, a switching transistor, a driving transistor and a compensation transistor.
  • the first initialization transistor Connected to the first initialization signal line, used to input the first initialization signal to the first node under the control of the first scan signal, and the switching transistor is used to input the data signal to the second node under the control of the second scan signal,
  • the driving transistor is electrically connected to the first node and the second node, and is used to drive the light-emitting device to emit light under the control of the potential of the first node and the second node.
  • the compensation transistor is connected to the driving transistor through the first node and the third node, and is used to Under the control of the third scan signal, the threshold voltage of the driving transistor is compensated; wherein the compensation transistor includes at least two sub-channels, and the width-to-length ratio of the sub-channel close to the driving transistor in the compensation transistor is smaller than that of the channel of the first initialization transistor. Width to length ratio.
  • the width-to-length ratio of the sub-channel of the compensation transistor close to the driving transistor smaller than the width-to-length ratio of the channel of the first initialization transistor, the impact of the leakage of the compensation transistor on the gate of the driving transistor can be reduced or the first initialization transistor can be increased.
  • the influence of the leakage of the initializing transistor on the gate of the driving transistor cancels out the influence of the leakage of the compensation transistor on the potential of the gate of the driving transistor and the influence of the first initializing transistor on the lowering of the potential of the gate of the driving transistor. This prevents the leakage of each transistor from causing changes in the gate potential of the driving transistor and improves the problem of display flicker.
  • FIG. 1 is a circuit diagram of a display panel provided by an embodiment of the present application.
  • Figure 2 is a first perspective view of a display panel provided by an embodiment of the present application.
  • FIG. 3 is an exploded view of the semiconductor layer of the display panel in FIG. 2 .
  • FIG. 4 is an exploded view of the first metal layer of the display panel in FIG. 2 .
  • FIG. 5 is an exploded view of the second metal layer of the display panel in FIG. 2 .
  • FIG. 6 is an exploded view of the third metal layer of the display panel in FIG. 2 .
  • FIG. 7 is a schematic diagram of gate electrodes and active patterns in the display panel in FIG. 2 .
  • FIG. 8 is a second perspective view of the display panel provided by the embodiment of the present application.
  • Figure 9 is a third perspective view of a display panel provided by an embodiment of the present application.
  • Figure 10 is a third perspective view of a display panel provided by an embodiment of the present application.
  • Embodiments of the present application address the problem of display flicker in existing display panels caused by the unbalanced leakage effects of different transistors on the gates of driving transistors, and provide a display panel and a display device to alleviate the above technical problems.
  • embodiments of the present application provide a display panel, which includes a plurality of light-emitting devices LEDs arranged in an array and a pixel driving circuit that drives the light-emitting device LEDs.
  • the pixel driving circuit Circuit includes:
  • the first initialization transistor T4 is connected to the first initialization signal line VI-1 and is used to input the first initialization signal to the first node Q under the control of the first scan signal;
  • the switching transistor T2 is used to input a data signal to the second node A under the control of the second scan signal;
  • the drive transistor Drive TFT is connected to the first node Q and the second node A, and is used to drive the light-emitting device LED to emit light under the control of the potential of the first node Q and the second node A;
  • the compensation transistor T3 is connected to the drive transistor Drive TFT through the first node Q and the third node B, and is used to compensate the threshold voltage of the drive transistor Drive TFT under the control of the third scan signal;
  • the compensation transistor T3 includes at least one sub-channel, and the width-to-length ratio of the sub-channel of the compensation transistor T3 close to the driving transistor Drive TFT is smaller than the width-to-length ratio of the channel of the first initialization transistor T4. .
  • Embodiments of the present application provide a display panel that can reduce the leakage of the compensation transistor to the driving transistor by making the width-to-length ratio of the sub-channel of the compensation transistor close to the driving transistor smaller than the width-to-length ratio of the channel of the first initialization transistor.
  • the influence of the gate of the transistor or the influence of the leakage of the first initialization transistor on the gate of the driving transistor is increased, thereby causing the leakage of the compensation transistor to raise the potential of the gate of the driving transistor and the first initialization transistor's effect on the driving transistor.
  • the effect of lowering the potential of the gate is offset, thereby preventing the leakage of each transistor from causing changes in the gate potential of the driving transistor, and improving the problem of display flicker.
  • the first initialization transistor includes at least two sub-channels, and a width-to-length ratio of a sub-channel of the compensation transistor close to the drive transistor is smaller than a width-to-length ratio of a sub-channel of the first initialization transistor close to the drive transistor. The width-to-length ratio of the sub-channel.
  • the width-to-length ratio of the sub-channel of the compensation transistor connected to the driving transistor is made smaller than the first initialization
  • the width-to-length ratio of the sub-channel of the transistor offsets the effects of the two on the potential of the gate of the driving transistor, thereby improving the problem of display flicker.
  • the compensation transistor T3 includes a first channel 21
  • the first initialization transistor T4 includes a second channel 22
  • the first channel 21 at least Including a first sub-channel 111 and a second sub-channel 112
  • the second channel 22 at least includes a third sub-channel 113 and a fourth sub-channel 114
  • the first sub-channel 111 is located in the The second sub-channel 112 is close to the drive transistor Drive
  • the third sub-channel 113 is located in the fourth sub-channel 114 close to the drive transistor Drive.
  • the width-to-length ratio of the first sub-channel 111 is smaller than the width-to-length ratio of the third sub-channel 113 (for example, W1/L1 can be smaller than W3/L3 in Figure 7), and the first The width-to-length ratio of the channel 21 is smaller than the width-to-length ratio of the second channel 22 (for example, in FIG. 7 , W1/L1+W2/L2 can be smaller than W3/L3+W4/L4).
  • width-to-length ratio of the first sub-channel smaller than the width-to-length ratio of the third sub-channel, and making the width-to-length ratio of the first channel smaller than the width-to-length ratio of the second channel, further reducing the leakage of the compensation transistor to the driving transistor.
  • the effect of raising the potential of the gate is similar or even the same as the effect of the first initialization transistor lowering the potential of the gate of the driving transistor, thereby improving the problem of display flicker.
  • the width-to-length ratio of the first sub-channel is smaller than the width-to-length ratio of the second sub-channel, and the width-to-length ratio of the third sub-channel is larger than that of the fourth sub-channel.
  • the width to length ratio By making the width-to-length ratio of the first sub-channel smaller than the width-to-length ratio of the second sub-channel, the leakage current of the first sub-channel of the compensation transistor is reduced, thereby reducing the leakage impact of the compensation transistor on the gate of the driving transistor.
  • the width-to-length ratio of the third sub-channel greater than the width-to-length ratio of the fourth sub-channel, the leakage of the third sub-channel of the first initialization transistor is increased, thereby causing the first initialization transistor to have a negative impact on the driving transistor.
  • the influence of gate leakage increases, so that the influence of the compensation transistor on raising the gate potential of the driving transistor and the influence of the first initialization transistor on lowering the gate potential of the driving transistor are balanced, thereby preventing the potential of the gate of the driving transistor from being affected. Improve the display flickering problem.
  • the width-to-length ratio of the first sub-channel can be reduced by increasing the width of the first gate, and the width-to-length ratio of the third sub-channel can be increased by reducing the width of the third gate.
  • the width-to-length ratio so that the width-to-length ratio of the first sub-channel is smaller than the width-to-length ratio of the second sub-channel, and the width-to-length ratio of the third sub-channel is larger than the width-to-length ratio of the fourth sub-channel, so that the compensation transistor pair
  • the effect of raising the gate potential of the driving transistor is balanced with the lowering effect of the first initialization transistor on the gate potential of the driving transistor, thereby preventing the gate potential of the driving transistor from being affected by leakage and causing display flickering, and due to the first sub-channel
  • the width-to-length ratio is reduced, and the width-to-length ratio of the third sub-channel is increased, so that the impact of the compensation transistor and the first initialization transistor on the gate of the driving transistor is close to or
  • the width-to-length ratio of the second sub-channel is equal to the width-to-length ratio of the fourth sub-channel, or the width-to-length ratio of the second sub-channel is smaller than the fourth sub-channel.
  • the ratio of width to length of the road is equal to the width-to-length ratio of the fourth sub-channel, or the width-to-length ratio of the second sub-channel is smaller than the fourth sub-channel.
  • width-to-length ratio of the second sub-channel By setting the width-to-length ratio of the second sub-channel equal to the width-to-length ratio of the fourth sub-channel, there is no need to change the design of the second sub-channel and the fourth sub-channel; by making the width-to-length ratio of the second sub-channel The ratio is smaller than the width-to-length ratio of the fourth sub-channel, and further increases the difference between the width-to-length ratio of the first channel of the compensation transistor and the width-to-length ratio of the second channel of the first initialization transistor, so that the compensation transistor has a negative impact on the driving transistor.
  • the leakage effect of the gate potential of the first initialization transistor and the leakage effect of the first initialization transistor on the gate potential of the driving transistor are balanced, thereby improving the problem of display flicker.
  • the width-to-length ratio of the first sub-channel is smaller than the width-to-length ratio of the second sub-channel, and the width-to-length ratio of the third sub-channel is equal to the fourth sub-channel.
  • the width-to-length ratio of the second sub-channel is equal to the width-to-length ratio of the fourth sub-channel.
  • the width-to-length ratio of the first sub-channel smaller than the width-to-length ratio of the second sub-channel, only the design of the first sub-channel of the compensation transistor needs to be changed, without changing the design of the first initialization transistor, so that the compensation transistor can The influence of the gate potential of the driving transistor is reduced, so that the raising influence of the compensation transistor on the gate potential of the driving transistor and the lowering influence of the first initialization transistor on the gate potential of the driving transistor are offset, thereby improving the problem of display flicker.
  • the width of the first gate can be increased and the width-to-length ratio of the first sub-channel can be reduced, so that the influence of the compensation transistor on raising the gate potential of the driving transistor can be reduced, thereby improving the display. Flashing problem.
  • the width-to-length ratio of the third sub-channel is greater than the width-to-length ratio of the fourth sub-channel, and the width-to-length ratio of the first sub-channel is equal to the second sub-channel.
  • the width-to-length ratio of the first sub-channel is equal to the width-to-length ratio of the fourth sub-channel.
  • the first The influence of the initialization transistor on the gate of the driving transistor balances the lowering influence of the first initialization transistor on the gate potential of the driving transistor with the raising influence of the compensation transistor on the gate potential of the driving transistor, thereby improving the problem of display flicker.
  • the width-to-length ratio of the first sub-channel is equal to the width-to-length ratio of the second sub-channel
  • the width-to-length ratio of the third sub-channel is equal to the fourth sub-channel. The width to length ratio.
  • the first sub-channel can be reduced and the width-to-length ratio of the second sub-channel, thereby reducing the width-to-length ratio of the first channel, and/or increasing the width-to-length ratio of the third sub-channel and the fourth sub-channel, thereby increasing the width-to-length ratio of the second channel.
  • the width-to-length ratio of the channel reduces the effect of the compensation transistor on pulling up the gate potential of the driving transistor, and/or the first initialization transistor increases the effect of pulling down the gate potential of the driving transistor, causing the compensation transistor and the first initialization transistor to have a lower effect on the gate potential of the driving transistor.
  • the effect of the transistor on the gate potential of the driving transistor is offset, thereby improving the problem of display flicker.
  • the compensation transistor T3 includes a connected first gate 131 and a second gate 132 and a first active pattern 11 .
  • the first initialization transistor T4 It includes the connected third gate 133 and the fourth gate 134 and the second active pattern 12.
  • the first active pattern 11 and the first gate 131 have a third An overlapping region 121.
  • the second sub-channel 112 the first active pattern 11 and the second gate 132 have a second overlapping region 122.
  • the third sub-channel 113 the There is a third overlapping region 123 between the second active pattern 12 and the third gate electrode 133 .
  • the fourth sub-channel 114 there is a third overlapping area 123 between the second active pattern 12 and the fourth gate electrode 134 .
  • the ratio W1/L1 of the width W1 of the first active pattern 11 located in the first overlapping area 121 to the width L1 of the first gate electrode 131 is equal to the width W1 of the first active pattern 11 located in the second overlapping area 122.
  • the ratio W2/L2 of the width W2 of the pattern 11 to the width L2 of the second gate electrode 132, the width W3 of the second active pattern 12 located in the third overlapping region 123 and the width L3 of the third gate electrode 133 The ratio W3/L3 is equal to the ratio W4/L4 of the width W4 of the second active pattern 12 located in the fourth overlapping area 124 and the width L4 of the fourth gate electrode 134, and is located in the first overlapping area 121
  • the ratio W1/L1 of the width W1 of the first active pattern 11 to the width L1 of the first gate 131 is smaller than the width W3 of the second active pattern 12 and the third gate located in the third overlapping region 123.
  • the ratio of the width L3 of pole 133 is W3/L3.
  • the compensation transistor is The width-to-length ratio of the first channel of the first initialization transistor is smaller than the width-to-length ratio of the second channel of the first initialization transistor, so that the influence of the compensation transistor on the gate potential of the driving transistor can be compared with that of the first initialization transistor on the gate potential of the driving transistor.
  • the influence of the electrode potential is reduced, so that the influence of the compensation transistor and the first initialization transistor on the gate potential of the driving transistor is balanced, thereby improving the problem of display flicker.
  • T3-1 and T3-2 respectively represent the parts of the compensation transistor T3 corresponding to the first gate and the second gate
  • T4-1 and T4-2 respectively represent the third gate of the compensation transistor T3.
  • An initialization transistor T4 corresponds to portions of the third gate and the fourth gate
  • the compensation transistor and the first initialization transistor are illustrated by showing their gates and active patterns. Detailed description is as described in the following examples.
  • the two gates of the compensation transistor T3 are connected. Therefore, in Figures 1 and 2, the first gate and the second gate are actually one gate. Take Figure 2 as an example.
  • the first gate and the second gate are two parts of the gate that are perpendicular to each other. Therefore, the first gate and the second gate are not specifically marked.
  • the third gate electrode and the fourth gate electrode of the first initialization transistor T4 are also two parts of the gate electrode that are perpendicular to each other. Therefore, in order to specifically describe the first gate electrode, the second gate electrode, the third gate electrode and the fourth gate electrode Corresponding parts are represented by reference numerals 131, 132, 133 and 134 in FIG. 7 as the first gate, the second gate, the third gate and the fourth gate respectively.
  • the width of each part of the first active pattern located in the horizontal direction shown in FIG. The widths are equal, the widths of the second active patterns located in the longitudinal direction are equal, and the widths of each part of the first gate are equal, the widths of each part of the second gate are equal, the widths of each part of the third gate are equal, and the width of each part of the third gate is equal.
  • the width of each part of the quad gate is equal.
  • the embodiments of the present application are not limited thereto.
  • the width of the gate electrode located in the overlapping area may be different from the width of the gate electrode located in the non-overlapping area.
  • the width of the first gate electrode located in the first overlapping area may be different from the width of the gate electrode located in the first overlapping area.
  • the widths of the outer first gates are not equal.
  • the widths of various parts of the gates are different, since the gates are formed by etching, only the shape of the mask needs to be changed without adding process steps. And the change of the width of the gate can be set according to the needs. For example, if it is necessary to increase the width of the first gate in the first overlapping area, the overall width of the first gate can be increased to reduce the width of the first gate. For example, if you need to reduce the width of the third gate in the third overlapping area, you can only reduce the width of the third gate located in the third overlapping area, and leave it unchanged or increase the width outside the third overlapping area. the width of the third gate to avoid increasing the impedance of the third gate. In the same way, the second gate and the fourth gate can also be designed in a similar manner as described above, which will not be described again here.
  • the width L1 of the first gate 131 located in the first overlapping region 121 is equal to the width L2 of the second gate 132 located in the second overlapping region 122 .
  • the width L3 of the third gate 133 in the third overlapping region 123 is equal to the width L4 of the fourth gate 134 located in the fourth overlapping region 124 , and the width L3 of the first gate 134 located in the first overlapping region 121
  • the width L1 of 131 is greater than the width L3 of the third gate 133 located in the third overlapping region 123 .
  • the driving of the compensation transistor and/or the first initialization transistor can be adjusted.
  • the influence of the gate of the transistor offsets the influence of the compensation transistor and the first initialization transistor on the gate potential of the driving transistor, thereby improving the flicker problem of the display panel.
  • the width of the first gate located in the first overlapping region can be increased and the width of the second gate located in the second overlapping region can be increased, so that the width of the first gate located in the first overlapping region is greater than The width of the third gate located in the third overlapping region, and because the widths of the first gate and the second gate are increased, the resistance of the first gate and the second gate can be reduced.
  • the width of the third gate located in the third overlapping area and the width of the fourth gate located in the fourth overlapping area can also be reduced, so that the width of the first gate located in the first overlapping area is reduced.
  • the width is greater than the width of the third gate located in the third overlapping region.
  • the width W1 of the first active pattern 11 located in the first overlapping area 121 is equal to the width W2 of the first active pattern 11 located in the second overlapping area 122
  • the width W3 of the second active pattern 12 located in the third overlapping area 123 is equal to the width W4 of the second active pattern 12 located in the fourth overlapping area 124
  • the width W3 located in the first overlapping area 121 The width W1 of the first active pattern 11 is equal to the width W3 of the second active pattern 12 located in the third overlapping area 123 .
  • the width of the first active pattern and the second active pattern equal, when designing the pixel driving circuit, there is no need to change the design of the first active pattern and the second active pattern, and the first trench can be changed by the width of the gate electrode.
  • the width-to-length ratio of the channel and the second channel balances the influence of the compensation transistor and the first initialization transistor on the gate potential of the driving transistor, thereby improving the problem of display flicker without changing the mask of the active pattern.
  • the width of the first active pattern located in the first overlapping area is equal to the width of the first active pattern located in the second overlapping area
  • the width of the second active pattern located in the third overlapping area is equal to the width of the first active pattern located in the second overlapping area.
  • the width of the active pattern is equal to the width of the second active pattern located in the fourth overlapping area, and the width of the first active pattern located in the first overlapping area is smaller than the width of the second active pattern located in the third overlapping area. The width of the active pattern.
  • the width of the first active pattern located in the first overlapping area smaller than the width of the second active pattern located in the third overlapping area, the impact of the compensation transistor on the gate potential of the driving transistor is compared with that of the first initialization transistor. If the influence on the gate potential of the driving transistor is reduced, the raising influence of the compensation transistor on the gate potential of the driving transistor and the lowering influence of the first initialization transistor on the gate potential of the driving transistor are balanced, thereby improving the problem of display flicker.
  • the width-to-length ratio of the first channel of the compensation transistor is less than The width-to-length ratio of the second channel of the first initialization transistor. It is also possible to increase the width of the second active pattern located in the third overlapping area and increase the width of the second active pattern located in the fourth overlapping area, so that the width-to-length ratio of the first channel of the compensation transistor is smaller than that of the third overlapping area. Initialize the width-to-length ratio of the second channel of the transistor.
  • the width of the first active pattern located in the first overlapping area and the width of the first active pattern located in the second overlapping area reduce the width of the second active pattern located in the third overlapping area.
  • the width-to-length ratio of the first channel of the compensation transistor can be reduced, and the width-to-length ratio of the second channel of the first initialization transistor can be increased.
  • the width of the first gate located in the first overlapping area is equal to the width of the second gate located in the second overlapping area
  • the width of the third gate located in the third overlapping area is equal to the width of the second gate located in the second overlapping area.
  • the width is equal to the width of the fourth gate located in the fourth overlapping area
  • the width of the first gate located in the first overlapping area is equal to or greater than the width of the third gate located in the third overlapping area. width.
  • the width of the first gate located in the first overlapping area is equal to the width of the third gate located in the third overlapping area, there is no need to change the design of the gate electrode, and there is no need to change the mask of the gate electrode, while the width of the first gate electrode located in the first overlapping area is
  • the width of the first active pattern is smaller than the width of the second active pattern located in the third overlapping area, so that the width-to-length ratio of the first channel of the compensation transistor can be smaller than the width-to-length ratio of the second channel of the first initialization transistor.
  • the influence of the compensation transistor on the gate potential of the driving transistor can be reduced compared to the influence of the first initialization transistor on the gate potential of the driving transistor, so that the influence of the compensation transistor and the first initialization transistor on the gate potential of the driving transistor can be reduced.
  • the impact is balanced, thereby improving the display flicker problem.
  • the width-to-length ratio of the first channel of the compensation transistor can be compared with that of the third gate electrode located in the third overlapping region.
  • the width-to-length ratio of the second channel of an initialization transistor is smaller, further reducing or eliminating the influence of the compensation transistor and the first initialization transistor on the gate of the driving transistor, thereby improving the problem of display flicker.
  • the width-to-length ratio of the first sub-channel is equal to the width-to-length ratio of the second sub-channel
  • the width-to-length ratio of the third sub-channel is equal to the width-to-length ratio of the fourth sub-channel.
  • the design of the gate and the active pattern is described in detail as an example, but the embodiment of the present application is not limited thereto.
  • the gate electrode and the active pattern can also be designed in a manner similar to the above embodiment.
  • the first initialization transistor is a low-temperature polysilicon thin film transistor
  • the compensation transistor is a low-temperature polysilicon thin film transistor
  • the compensation transistor includes a first gate and a second gate
  • the first initialization transistor It includes a third gate and a fourth gate
  • the projections of the first gate and the second gate on the first active pattern are spaced
  • the third gate and the fourth gate are The projection of the poles onto the second active pattern is spaced.
  • adjacent pixel drive circuits arranged laterally are arranged symmetrically, the first initialization transistor in the adjacent pixel drive circuit is connected to the same initialization signal line, and the compensation transistor in the adjacent pixel drive circuit is connected to the same scan line. .
  • the pixel driving circuit further includes a second initialization transistor T7, and the second initialization transistor T7 is connected to the second initialization signal line VI-2 for use in Under the control of the fourth scan signal, input a second initialization signal to the LED anode of the light-emitting device;
  • the first light-emitting control transistor T5 is connected to the drive transistor Drive TFT through the second node A, and is used to conduct the current of the power high-potential signal line VDD to the drive transistor Drive TFT under the control of the light-emitting control signal;
  • the second light emission control transistor T6 is connected to the drive transistor Drive TFT through the third node B, and is used to conduct the current flowing from the drive transistor Drive TFT to the anode of the light emitting device LED under the control of the light emission control signal.
  • the display panel includes:
  • the pixel driving circuit layer includes multiple pixel driving circuits
  • the pixel driving circuit includes a semiconductor layer, a first metal layer, a second metal layer and a third metal layer that are sequentially stacked on the substrate, and the semiconductor layer includes the first active pattern and the In the second active pattern, the first metal layer includes a first gate, a second gate, a third gate and a fourth gate.
  • the second metal layer forms a plate of a storage capacitor.
  • the third metal layer forms a source electrode and a drain electrode.
  • Figure 3 is a perspective view of the semiconductor layer in Figure 2
  • Figure 4 is a perspective view of the first metal layer in Figure 2
  • Figure 5 is a perspective view of the second metal layer in Figure 2
  • Figure 6 is a perspective view of the third metal layer in Figure 2.
  • the pixel driving circuit further includes a storage capacitor Cst.
  • One end of the storage capacitor Cst is connected to the power high potential signal line VDD, and the other end of the storage capacitor Cst is connected to the power supply high potential signal line VDD.
  • the first node Q connection is not limited to the storage capacitor Cst.
  • the data line Data transmits data signals
  • the first initialization signal line VI-1 transmits the first initialization signal
  • the second initialization signal line VI-2 transmits the second Initialization signal
  • the first scanning signal line Scan2(n-1) transmits the first scanning signal
  • the second scanning signal line Scan1(n-1) transmits the second scanning signal
  • the third scanning signal line Scan2(n) transmits the third scanning signal
  • the fourth scanning signal line Scan1(n) transmits the fourth scanning signal
  • the luminescence control signal line EM(n) transmits the luminescence control signal
  • the power supply low potential signal line VSS transmits low potential.
  • Scan1 and Scan2 represent two sets of scan lines, and Scan(n-1) and Scan(n) represent two levels of scan lines.
  • the pixel driving circuit in two sub-pixels is used to show the arrangement and connection relationship of each component, and in order to facilitate viewing of the design of the compensation transistor and the first initialization transistor, some components and wiring are not shown.
  • the first initialization signal line VI-1 is not shown in FIG. 2 .
  • Drive TFT, T2, T3, T4, T5, T6, and T7 respectively represent the arrangement positions of the active patterns of each transistor, and you can see the first active pattern and the second active pattern.
  • the pattern has a bent structure; as shown in Figure 4, the gates of each transistor are represented by Drive TFT, T2, T3, T4, T5, T6, and T7 respectively.
  • the first gate of the compensation transistor T3 and the second gate are two parts perpendicular to each other, and the third gate and the fourth gate of the first initialization transistor T4 are two parts perpendicular to each other; as shown in Figure 5 and Figure 6, the wiring of each trace is shown.
  • the above embodiments describe in detail the arrangement of the compensation transistor and the first initialization transistor using the pixel driving circuit shown in Figure 1 and the perspective view in Figure 2, but the embodiments of the present application are not limited thereto, for example
  • the pixel drive circuit adopts other design methods.
  • the display panel shown in Figures 8, 9 and 10 is only structurally different from the display panel in Figure 2 in terms of the compensation transistor and the first initialization transistor. As shown in Figures 8, 9 and 10 The exploded view of the display panel can be determined by analogy with the exploded view of the display panel in Figure 2, and will not be described again here.
  • embodiments of the present application provide a display device, which includes the display panel and electronic components described in any of the above embodiments.
  • Embodiments of the present application provide a display panel and a display device; the display panel includes a plurality of light-emitting devices arranged in an array and a pixel driving circuit for driving the light-emitting devices.
  • the pixel driving circuit includes a first initialization transistor, a switching transistor, a driving transistor and a compensation transistor. , the first initialization transistor is connected to the first initialization signal line and is used to input the first initialization signal to the first node under the control of the first scan signal, and the switching transistor is used to input the first initialization signal to the second node under the control of the second scan signal.
  • the node inputs the data signal
  • the driving transistor is used to drive the light-emitting device to emit light under the control of the potential of the first node and the second node
  • the compensation transistor is connected to the driving transistor through the first node and the third node, and is used to control the third scanning signal.
  • the threshold voltage of the driving transistor is compensated; wherein the compensation transistor includes a connected first gate and a second gate, a first active pattern, and the first initialization transistor includes a connected third gate and a fourth gate, In the second active pattern, the width-to-length ratio of the first channel of the compensation transistor is smaller than the width-to-length ratio of the second channel of the first initialization transistor.
  • the first channel includes a first sub-channel and a second sub-channel.
  • the second channel includes a third sub-channel and a fourth sub-channel.
  • the first sub-channel is located on a side of the second sub-channel close to the driving transistor.
  • the third sub-channel is located on a side of the fourth sub-channel close to the driving transistor. side, the width-to-length ratio of the first sub-channel is smaller than the width-to-length ratio of the third sub-channel.
  • the present application can reduce the The effect of the leakage of the compensating transistor on the gate of the driving transistor or the effect of the leakage of the first initial transistor on the gate of the driving transistor is increased, so that the effect of the leakage of the compensating transistor on the potential of the gate of the driving transistor is increased and the first The effect of the initialization transistor on lowering the gate potential of the driving transistor is offset, thereby preventing the leakage of each transistor from causing changes in the gate potential of the driving transistor, and improving the problem of display flicker.

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Abstract

一种显示面板，使补偿晶体管（T3）靠近驱动晶体管（Drive TFT）的子沟道（111）的宽长比小于第一初始化晶体管（T4）的沟道（22）的宽长比，使补偿晶体管（T3）漏电对驱动晶体管（Drive TFT）的栅极的电位的拉升影响和第一初始化晶体管（T4）对驱动晶体管（Drive TFT）的栅极的电位的拉低影响抵消，避免各晶体管的漏电导致驱动晶体管（Drive TFT）的栅极电位变化，改善显示闪烁的问题。

Description

显示面板 技术领域
本申请涉及显示技术领域，尤其是涉及一种显示面板。
 背景技术
OLED（Organic Light-Emitting Diode，有机发光二极管）显示器件由于自发光、可实现柔性等优点被广泛应用。现有OLED显示器件会采用基于LTPS（Low Temperature Poly-silicon，低温多晶硅）技术的驱动电路对像素进行驱动，但在实际使用过程中，由于与驱动晶体管的栅极连接的晶体管为双栅设计的晶体管，位于双栅结构之间的半导体图案容易受到其他信号的耦合，导致电位较高，在发光阶段向驱动晶体管漏电，且在实际过程中，存在部分晶体管的向驱动晶体管的栅极漏电导致驱动晶体管的栅极电位提高，部分晶体管向驱动晶体管的栅极漏电导致驱动晶体管的栅极电位降低，总体会导致驱动晶体管的栅极电位升高，从而一帧内显示亮度变化，且在低频显示时出现明显的闪烁现象。
所以，现有显示面板存在不同晶体管对驱动晶体管的栅极的漏电影响不平衡所导致的显示闪烁的问题。
 技术问题
本申请实施例提供一种显示面板，用以缓解现有显示面板存在不同晶体管对驱动晶体管的栅极的漏电影响不平衡所导致的显示闪烁的问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，该显示面板包括阵列设置的多个发光器件和驱动所述发光器件的像素驱动电路，所述像素驱动电路包括：
第一初始化晶体管，与第一初始化信号线连接，用于在第一扫描信号的控制下，向第一节点输入第一初始化信号；
开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
驱动晶体管，与第一节点和第二节点电连接，用于在第一节点和第二节点电位的控制下，驱动所述发光器件发光；
补偿晶体管，通过所述第一节点和第三节点与所述驱动晶体管相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压；
其中，所述补偿晶体管包括至少两个子沟道，所述补偿晶体管中靠近所述驱动晶体管的子沟道的宽长比小于所述第一初始化晶体管的沟道的宽长比。
在一些实施例中，所述第一初始化晶体管包括至少两个子沟道，所述补偿晶体管中靠近所述驱动晶体管的子沟道的宽长比小于所述第一初始化晶体管中靠近所述驱动晶体管的子沟道的宽长比。
在一些实施例中，所述补偿晶体管包括第一沟道，所述第一初始化晶体管包括第二沟道，所述第一沟道至少包括第一子沟道和第二子沟道，所述第二沟道至少包括第三子沟道和第四子沟道，所述第一子沟道位于所述第二子沟道靠近所述驱动晶体管的一侧，所述第三子沟道位于所述第四子沟道靠近所述驱动晶体管的一侧，所述第一子沟道的宽长比小于所述第三子沟道的宽长比，且所述第一沟道的宽长比小于所述第一初始化晶体管的第二沟道的宽长比。
在一些实施例中，所述第一子沟道的宽长比小于所述第二子沟道的宽长比，所述第三子沟道的宽长比大于所述第四子沟道的宽长比。
在一些实施例中，所述第二子沟道的宽长比等于所述第四子沟道的宽长比，或者所述第二子沟道的宽长比小于所述第四子沟道的宽长比。
在一些实施例中，所述第一子沟道的宽长比小于所述第二子沟道的宽长比，所述第三子沟道的宽长比等于所述第四子沟道的宽长比，且所述第二子沟道的宽长比等于所述第四子沟道的宽长比。
在一些实施例中，所述第三子沟道的宽长比大于所述第四子沟道的宽长比，所述第一子沟道的宽长比等于所述第二子沟道的宽长比，且所述第一子沟道的宽长比等于所述第四子沟道的宽长比。
在一些实施例中，所述第一子沟道的宽长比等于所述第二子沟道的宽长比，所述第三子沟道的宽长比等于所述第四子沟道的宽长比。
在一些实施例中，所述补偿晶体管包括相连的第一栅极和第二栅极、第一有源图案，所述第一初始化晶体管包括相连的第三栅极和第四栅极、第二有源图案，在所述第一子沟道，所述第一有源图案所述第一栅极存在第一重合区域，在所述第二子沟道，所述第一有源图案与所述第二栅极存在第二重合区域，在所述第三子沟道，所述第二有源图案与所述第三栅极存在第三重合区域，在所述第四子沟道，所述第二有源图案与所述第四栅极存在第四重合区域；
其中，位于所述第一重合区域的第一有源图案的宽度与所述第一栅极的宽度的比值等于位于所述第二重合区域的第一有源图案的宽度与第二栅极的宽度的比值，位于所述第三重合区域的第二有源图案的宽度与所述第三栅极的宽度的比值等于位于所述第四重合区域的第二有源图案的宽度与所述第四栅极的宽度的比值，且位于所述第一重合区域的第一有源图案的宽度与所述第一栅极的宽度的比值小于位于所述第三重合区域的第二有源图案的宽度与第三栅极的宽度的比值。
在一些实施例中，位于所述第一重合区域的第一栅极的宽度等于位于所述第二重合区域的第二栅极的宽度，位于所述第三重合区域的第三栅极的宽度等于位于所述第四重合区域的第四栅极的宽度，且位于所述第一重合区域的第一栅极的宽度大于位于所述第三重合区域的第三栅极的宽度。
在一些实施例中，位于所述第一重合区域的第一有源图案的宽度等于位于所述第二重合区域的第一有源图案的宽度，位于所述第三重合区域的第二有源图案的宽度等于位于所述第四重合区域的第二有源图案的宽度，且位于所述第一重合区域的第一有源图案的宽度等于位于所述第三重合区域的第二有源图案的宽度。
在一些实施例中，位于所述第一重合区域的第一有源图案的宽度等于位于所述第二重合区域的第一有源图案的宽度，位于所述第三重合区域的第二有源图案的宽度等于位于所述第四重合区域的第二有源图案的宽度，且位于所述第一重合区域的第一有源图案的宽度小于位于所述第三重合区域的第二有源图案的宽度。
在一些实施例中，位于所述第一重合区域的第一栅极的宽度等于位于所述第二重合区域的第二栅极的宽度，位于所述第三重合区域的第三栅极的宽度等于位于所述第四重合区域的第四栅极的宽度，且位于所述第一重合区域的第一栅极的宽度等于或者大于位于所述第三重合区域的第三栅极的宽度。
在一些实施例中，所述第一初始化晶体管为低温多晶硅薄膜晶体管，所述补偿晶体管为低温多晶硅薄膜晶体管，所述补偿晶体管包括第一栅极和第二栅极，所述第一初始化晶体管包括第三栅极和第四栅极，所述第一栅极和所述第二栅极在所述第一有源图案上的投影存在间距，所述第三栅极和所述第四栅极在所述第二有源图案上的投影存在间距。
在一些实施例中，横向设置的相邻像素驱动电路对称设置，相邻像素驱动电路中的第一初始化晶体管连接至同一初始化信号线，相邻像素驱动电路中的补偿晶体管连接至同一扫描线。
在一些实施例中，所述像素驱动电路还包括第二初始化晶体管，所述第二初始化晶体管与第二初始化信号线连接，用于在第四扫描信号的控制下，向所述发光器件阳极输入第二初始化信号；
第一发光控制晶体管，通过第二节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线向所述驱动晶体管的电流；
第二发光控制晶体管，通过第三节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通所述驱动晶体管流向所述发光器件阳极的电流。
在一些实施例中，所述像素驱动电路还包括存储电容，所述存储电容一端与所述电源高电位信号线连接，所述存储电容另一端与所述第一节点连接。
在一些实施例中，所述显示面板包括：
衬底；
像素驱动电路层，包括多个像素驱动电路；
其中，所述像素驱动电路包括依次层叠设置在所述衬底上的半导体层、第一金属层、第二金属层和第三金属层，所述半导体层包括所述第一有源图案和所述第二有源图案，所述第一金属层包括第一栅极、第二栅极、第三栅极和第四栅极。
在一些实施例中，所述第二金属层形成有存储电容的极板。
在一些实施例中，所述第三金属层形成有源极和漏极。
 有益效果
本申请提供一种显示面板；该显示面板包括阵列设置的多个发光器件和驱动发光器件的像素驱动电路，像素驱动电路包括第一初始化晶体管、开关晶体管、驱动晶体管和补偿晶体管，第一初始化晶体管与第一初始化信号线连接，用于在第一扫描信号的控制下，向第一节点输入第一初始化信号，开关晶体管用于在第二扫描信号的控制下，向第二节点输入数据信号，驱动晶体管与第一节点和第二节点电连接，用于在第一节点和第二节点电位的控制下，驱动发光器件发光，补偿晶体管通过第一节点和第三节点与驱动晶体管相连，用于在第三扫描信号的控制下，补偿驱动晶体管的阈值电压；其中，补偿晶体管包括至少两个子沟道，补偿晶体管中靠近驱动晶体管的子沟道的宽长比小于第一初始化晶体管的沟道的宽长比。本申请通过使补偿晶体管靠近驱动晶体管的子沟道的宽长比小于第一初始化晶体管的沟道的宽长比，可以减小补偿晶体管的漏电对驱动晶体管的栅极的影响或者增大第一初始晶体管的漏电对驱动晶体管的栅极的影响，从而使补偿晶体管漏电对驱动晶体管的栅极的电位的拉升影响和第一初始化晶体管对驱动晶体管的栅极的电位的拉低影响抵消，从而避免各晶体管的漏电导致驱动晶体管的栅极电位变化，改善显示闪烁的问题。
 附图说明
图1为本申请实施例提供的显示面板的电路图。
图2为本申请实施例提供的显示面板的第一种透视图。
图3为图2中的显示面板的半导体层的分解图。
图4为图2中的显示面板的第一金属层的分解图。
图5为图2中的显示面板的第二金属层的分解图。
图6为图2中的显示面板的第三金属层的分解图。
图7为图2中的显示面板中栅极和有源图案的示意图。
图8为本申请实施例提供的显示面板的第二种透视图。
图9为本申请实施例提供的显示面板的第三种透视图。
图10为本申请实施例提供的显示面板的第三种透视图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例针对现有显示面板存在不同晶体管对驱动晶体管的栅极的漏电影响不平衡所导致的显示闪烁的问题，提供一种显示面板和显示装置，用以缓解上述技术问题。
如图1、图2、图7所示，本申请实施例提供一种显示面板，该显示面板包括阵列设置的多个发光器件LED和驱动所述发光器件LED的像素驱动电路，所述像素驱动电路包括：
第一初始化晶体管T4，与第一初始化信号线VI-1连接，用于在第一扫描信号的控制下，向第一节点Q输入第一初始化信号；
开关晶体管T2，用于在第二扫描信号的控制下，向第二节点A输入数据信号；
驱动晶体管Drive TFT，与第一节点Q和第二节点A连接，用于在第一节点Q和第二节点A电位的控制下，驱动所述发光器件LED发光；
补偿晶体管T3，通过所述第一节点Q和第三节点B与所述驱动晶体管Drive TFT相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管Drive TFT的阈值电压；
其中，所述补偿晶体管T3包括至少一个子沟道，所述补偿晶体管T3中靠近所述驱动晶体管Drive TFT的子沟道的宽长比小于所述第一初始化晶体管T4的沟道的宽长比。
本申请实施例提供一种显示面板，该显示面板通过使补偿晶体管靠近驱动晶体管的子沟道的宽长比小于第一初始化晶体管的沟道的宽长比，可以减小补偿晶体管的漏电对驱动晶体管的栅极的影响或者增大第一初始晶体管的漏电对驱动晶体管的栅极的影响，从而使补偿晶体管漏电对驱动晶体管的栅极的电位的拉升影响和第一初始化晶体管对驱动晶体管的栅极的电位的拉低影响抵消，从而避免各晶体管的漏电导致驱动晶体管的栅极电位变化，改善显示闪烁的问题。
在一种实施例中，所述第一初始化晶体管包括至少两个子沟道，所述补偿晶体管中靠近所述驱动晶体管的子沟道的宽长比小于第一初始化晶体管中靠近所述驱动晶体管的子沟道的宽长比。由于向驱动晶体管漏电和驱动晶体管向外漏电时，主要与直接连接驱动晶体管的薄膜晶体管的子沟道有关，因此，使与驱动晶体管连接的补偿晶体管的子沟道的宽长比小于第一初始化晶体管的子沟道的宽长比，使两者对驱动晶体管的栅极的电位的作用抵消，改善显示闪烁的问题。
在一种实施例中，如图1至图7所示，所述补偿晶体管T3包括第一沟道21，所述第一初始化晶体管T4包括第二沟道22，所述第一沟道21至少包括第一子沟道111和第二子沟道112，所述第二沟道22至少包括第三子沟道113和第四子沟道114，所述第一子沟道111位于所述第二子沟道112靠近所述驱动晶体管Drive TFT的一侧，所述第三子沟道113位于所述第四子沟道114靠近所述驱动晶体管Drive TFT的一侧，所述第一子沟道111的宽长比小于所述第三子沟道113的宽长比（例如图7中可以使W1/L1小于W3/L3），所述第一沟道21的宽长比小于所述第二沟道22的宽长比（例如图7中可以使W1/L1+W2/L2小于W3/L3+W4/L4）。通过使第一子沟道的宽长比小于第三子沟道的宽长比，使第一沟道的宽长比小于第二沟道的宽长比，进一步使补偿晶体管漏电对驱动晶体管的栅极的电位的拉升影响和第一初始化晶体管对驱动晶体管的栅极的电位的拉低影响相近甚至相同，改善显示闪烁的问题。
针对补偿晶体管和第一初始化晶体管的漏电不平衡导致驱动晶体管的栅极电位变化的问题。在一种实施例中，所述第一子沟道的宽长比小于所述第二子沟道的宽长比，所述第三子沟道的宽长比大于所述第四子沟道的宽长比。通过使第一子沟道的宽长比小于第二子沟道的宽长比，使得补偿晶体管的第一子沟道的漏电减小，从而使补偿晶体管对驱动晶体管的栅极的漏电影响减小；通过使第三子沟道的宽长比大于第四子沟道的宽长比，使第一初始化晶体管的第三子沟道的漏电增大，从而使第一初始化晶体管对驱动晶体管的栅极的漏电影响增大，使得补偿晶体管对驱动晶体管的栅极电位拉升影响和第一初始化晶体管对驱动晶体管的栅极电位拉低影响平衡，从而避免驱动晶体管的栅极的电位受到影响，改善显示闪烁的问题。
具体的，如图8所示，可以通过增大第一栅极的宽度，减小第一子沟道的宽长比，通过减小第三栅极的宽度，增大第三子沟道的宽长比，从而使得第一子沟道的宽长比小于第二子沟道的宽长比，第三子沟道的宽长比大于第四子沟道的宽长比，使补偿晶体管对驱动晶体管的栅极电位的拉升影响与第一初始化晶体管对驱动晶体管的栅极电位的拉低影响达到平衡，避免驱动晶体管的栅极电位受到漏电影响导致显示闪烁，且由于第一子沟道的宽长比减小，第三子沟道的宽长比增大，使得补偿晶体管和第一初始化晶体管对驱动晶体管的栅极的影响效果接近甚至相同，改善显示闪烁的问题。
在一种实施例中，所述第二子沟道的宽长比等于所述第四子沟道的宽长比，或者所述第二子沟道的宽长比小于所述第四子沟道的宽长比。通过将第二子沟道的宽长比设置为等于第四子沟道的宽长比，无需改变第二子沟道和第四子沟道的设计；通过使第二子沟道的宽长比小于第四子沟道的宽长比，进一步增大补偿晶体管的第一沟道的宽长比与第一初始化晶体管的第二沟道的宽长比的差值，使补偿晶体管对驱动晶体管的栅极电位的漏电影响和第一初始化晶体管对驱动晶体管的栅极电位的漏电影响达到平衡，改善显示闪烁的问题。
针对补偿晶体管和第一初始化晶体管的漏电不平衡导致驱动晶体管的栅极电位变化的问题。在一种实施例中，所述第一子沟道的宽长比小于所述第二子沟道的宽长比，所述第三子沟道的宽长比等于所述第四子沟道的宽长比，且所述第二子沟道的宽长比等于所述第四子沟道的宽长比。通过使第一子沟道的宽长比小于第二子沟道的宽长比，则仅需要改变补偿晶体管的第一子沟道的设计，无需改变第一初始化晶体管的设计，使补偿晶体管对驱动晶体管的栅极电位的影响降低，使补偿晶体管对驱动晶体管的栅极电位的拉升影响和第一初始化晶体管对驱动晶体管的栅极电位的拉低影响抵消，改善显示闪烁的问题。
具体的，如图9所示，可以增大第一栅极的宽度，减小第一子沟道的宽长比，使补偿晶体管对驱动晶体管的栅极电位的拉升影响降低，从而改善显示闪烁的问题。
针对补偿晶体管和第一初始化晶体管的漏电不平衡导致驱动晶体管的栅极电位变化的问题。在一种实施例中，所述第三子沟道的宽长比大于所述第四子沟道的宽长比，所述第一子沟道的宽长比等于所述第二子沟道的宽长比，且所述第一子沟道的宽长比等于所述第四子沟道的宽长比。通过使第三子沟道的宽长比大于第四子沟道的宽长比，增大第三子沟道的宽长比，则可以增大第一初始化晶体管对驱动晶体管的栅极电位的影响，使补偿晶体管对驱动晶体管的栅极电位的拉升影响和第一初始化晶体管对驱动晶体管的栅极电位的拉低影响抵消，改善显示闪烁的问题。
具体的，如图10所示，通过增大与驱动晶体管栅极直接连接的T4-1的第三栅极的宽度，使第三子沟道的宽长比增大，则可以增大第一初始化晶体管对驱动晶体管的栅极的影响，使第一初始化晶体管对驱动晶体管的栅极电位的拉低影响与补偿晶体管对驱动晶体管的栅极电位的拉升影响平衡，改善显示闪烁的问题。
针对补偿晶体管和第一初始化晶体管的漏电不平衡导致驱动晶体管的栅极电位变化的问题。在一种实施例中，所述第一子沟道的宽长比等于所述第二子沟道的宽长比，所述第三子沟道的宽长比等于所述第四子沟道的宽长比。通过使第一子沟道的宽长比等于第二子沟道的宽长比，第三子沟道的宽长比等于第四子沟道的宽长比，可以减小第一子沟道和第二子沟道的宽长比，从而减小第一沟道的宽长比，和/或增大第三子沟道和第四子沟道的宽长比，从而增大第二沟道的宽长比，使补偿晶体管对驱动晶体管的栅极电位的拉升影响降低，和/或第一初始化晶体管对驱动晶体管的栅极电位的拉低影响增大，使补偿晶体管和第一初始化晶体管对驱动晶体管的栅极电位的影响抵消，改善显示闪烁的问题。
在一种实施例中，如图1至图7所示，所述补偿晶体管T3包括相连的第一栅极131和第二栅极132、第一有源图案11，所述第一初始化晶体管T4包括相连的第三栅极133和第四栅极134、第二有源图案12，在所述第一子沟道111，所述第一有源图案11与所述第一栅极131存在第一重合区域121，在所述第二子沟道112，所述第一有源图案11与所述第二栅极132存在第二重合区域122，在所述第三子沟道113，所述第二有源图案12与所述第三栅极133存在第三重合区域123，在所述第四子沟道114，所述第二有源图案12与所述第四栅极134存在第四重合区域124；
其中，位于所述第一重合区域121的第一有源图案11的宽度W1与所述第一栅极131的宽度L1的比值W1/L1等于位于所述第二重合区域122的第一有源图案11的宽度W2与第二栅极132的宽度L2的比值W2/L2，位于所述第三重合区域123的第二有源图案12的宽度W3与所述第三栅极133的宽度L3的比值W3/L3等于位于所述第四重合区域124的第二有源图案12的宽度W4与所述第四栅极134的宽度L4的比值W4/L4，且位于所述第一重合区域121的第一有源图案11的宽度W1与所述第一栅极131的宽度L1的比值W1/L1小于位于所述第三重合区域123的第二有源图案12的宽度W3与第三栅极133的宽度L3的比值W3/L3。通过使得第一重合区域的第一有源图案的宽度与第一栅极的宽度的比值小于第三重合区域的第二有源图案的宽度与第三栅极的宽度的比值，使补偿晶体管的第一沟道的宽长比小于第一初始化晶体管的第二沟道的宽长比，则可以使补偿晶体管对驱动晶体管的栅极电位的影响相较于第一初始化晶体管对驱动晶体管的栅极电位的影响降低，使补偿晶体管和第一初始化晶体管对驱动晶体管的栅极电位的影响达到平衡，从而改善显示闪烁的问题。
需要说明的是，在图1至图6中，以T3-1和T3-2分别表示补偿晶体管T3对应第一栅极和第二栅极的部分，以T4-1和T4-2分别表示第一初始化晶体管T4对应第三栅极和第四栅极的部分，且在图7中，通过示出补偿晶体管和第一初始化晶体管的栅极和有源图案以对补偿晶体管和第一初始化晶体管进行详细说明，具体如下述实施例所述。
需要说明的是，从图1、图2均可以看到，补偿晶体管T3的两个栅极会连接，因此，在图1、图2中第一栅极和第二栅极实际是一个栅极的两个部分，以图2为例，第一栅极和第二栅极是栅极中相互垂直的两个部分，因此，未具体标注第一栅极和第二栅极，同理可知，第一初始化晶体管T4的第三栅极和第四栅极也是栅极中相互垂直的两个部分，因此，为了具体说明第一栅极、第二栅极、第三栅极和第四栅极对应的部分，在图7中以标号131、标号132、标号133和标号134分别表示第一栅极、第二栅极、第三栅极和第四栅极。
需要说明的是，在图7中示出的位于横向的第一有源图案的各部分宽度相等，位于横向的第一有源图案的各部分的宽度相等，位于纵向的第一有源图案的宽度相等，位于纵向的第二有源图案的宽度相等，且第一栅极中各部分的宽度相等、第二栅极中各部分的宽度相等、第三栅极中各部分的宽度相等、第四栅极中各部分的宽度相等。但本申请实施例不限于此，例如位于重合区域的栅极的宽度与位于不重合区域的栅极的宽度可以不等，例如第一重合区域的第一栅极的宽度与位于第一重合区域外的第一栅极的宽度不相等。
具体的，在各栅极的各部分的宽度不等时，由于栅极形成时通过刻蚀形成，使得仅需要改变掩模版的形状，无需增加工艺步骤。且对于栅极的宽度的变化，可以根据需求设定，例如需要增加第一重合区域的第一栅极的宽度，则可以使得第一栅极的整体宽度增大，以减小第一栅极的宽度，例如需要减小第三重合区域的第三栅极的宽度，则可以仅减小位于第三重合区域的第三栅极的宽度，不改变或者增加位于第三重合区域外的第三栅极的宽度，避免增大第三栅极的阻抗。同理，对于第二栅极、第四栅极的设计也可以采用上述类同方式，在此不再赘述。
在一种实施例中，如图7所示，位于所述第一重合区域121的第一栅极131的宽度L1等于位于所述第二重合区域122的第二栅极132的宽度L2，位于所述第三重合区域123的第三栅极133的宽度L3等于位于所述第四重合区域124的第四栅极134的宽度L4，且位于所述第一重合区域121的第一栅极131的宽度L1大于位于所述第三重合区域123的第三栅极133的宽度L3。通过改变补偿晶体管和/或第一初始化晶体管的栅极的宽度，使得补偿晶体管和/或第一初始化晶体管的沟道的宽长比变化，则可以调节补偿晶体管和/或第一初始化晶体管对驱动晶体管的栅极的影响，使补偿晶体管和第一初始化晶体管对驱动晶体管的栅极电位的影响抵消，改善显示面板的闪烁问题。
具体的，可以通过增大位于第一重合区域的第一栅极的宽度和增大位于第二重合区域的第二栅极的宽度，以使位于第一重合区域的第一栅极的宽度大于位于第三重合区域的第三栅极的宽度，且由于第一栅极和第二栅极的宽度增大，可以减小第一栅极和第二栅极的阻抗。
具体的，还可以通过减小位于第三重合区域的第三栅极的宽度和减小位于第四重合区域的第四栅极的宽度，以使位于第一重合区域的第一栅极的宽度大于位于第三重合区域的第三栅极的宽度。
具体的，还可以通过同时增大位于第一重合区域的第一栅极的宽度和增大位于第二重合区域的第二栅极的宽度，减小位于第三重合区域的第三栅极的宽度和减小位于第四重合区域的第四栅极的宽度，通过减小补偿晶体管的第一沟道的宽长比，同时增大第一初始化晶体管的第二沟道的宽长比，使第一初始化晶体管的第二沟道的宽长比增大，则可以减小补偿晶体管对驱动晶体管的栅极电位的影响，增大第一初始化晶体管对驱动晶体管的栅极电位的影响，从而使补偿晶体管和第一初始化晶体管对驱动晶体管的栅极电位的影响平衡，改善显示闪烁的问题。
在一种实施例中，如图7所示，位于所述第一重合区域121的第一有源图案11的宽度W1等于位于所述第二重合区域122的第一有源图案11的宽度W2，位于所述第三重合区域123的第二有源图案12的宽度W3等于位于所述第四重合区域124的第二有源图案12的宽度W4，且位于所述第一重合区域121的第一有源图案11的宽度W1等于位于所述第三重合区域123的第二有源图案12的宽度W3。通过使第一有源图案和第二有源图案的宽度相等，在设计像素驱动电路时，无需改变第一有源图案和第二有源图案的设计，可以通过栅极的宽度改变第一沟道和第二沟道的宽长比，从而使补偿晶体管和第一初始化晶体管对驱动晶体管的栅极电位的影响平衡，改善显示闪烁的问题的同时，可以不改变有源图案的掩模版。
针对补偿晶体管和第一初始化晶体管的漏电不平衡导致驱动晶体管的栅极电位变化的问题。在一种实施例中，位于所述第一重合区域的第一有源图案的宽度等于位于所述第二重合区域的第一有源图案的宽度，位于所述第三重合区域的第二有源图案的宽度等于位于所述第四重合区域的第二有源图案的宽度，且位于所述第一重合区域的第一有源图案的宽度小于位于所述第三重合区域的第二有源图案的宽度。通过使位于第一重合区域的第一有源图案的宽度小于位于第三重合区域的第二有源图案的宽度，使补偿晶体管对驱动晶体管的栅极电位的影响相较于第一初始化晶体管对驱动晶体管的栅极电位的影响降低，则补偿晶体管对驱动晶体管的栅极电位的拉升影响和第一初始化晶体管对驱动晶体管的栅极电位的拉低影响达到平衡，改善显示闪烁的问题。
具体的，可以通过减小位于第一重合区域的第一有源图案的宽度和减小位于第二重合区域的第一有源图案的宽度，使得补偿晶体管的第一沟道的宽长比小于第一初始化晶体管的第二沟道的宽长比。还可以通过增大位于第三重合区域的第二有源图案的宽度和增大位于第四重合区域的第二有源图案的宽度，使得补偿晶体管的第一沟道的宽长比小于第一初始化晶体管的第二沟道的宽长比。还可以通过减小位于第一重合区域的第一有源图案的宽度和减小位于第二重合区域的第一有源图案的宽度，同时，减小位于第三重合区域的第二有源图案的宽度和减小位于第四重合区域的第二有源图案的宽度，可以减小补偿晶体管的第一沟道的宽长比，增大第一初始化晶体管的第二沟道的宽长比，降低补偿晶体管对驱动晶体管的栅极电位的影响，提高第一初始化晶体管对驱动晶体管的栅极电位的影响，使补偿晶体管和第一初始化晶体管对驱动晶体管的栅极电位的影响抵消，改善显示闪烁的问题。
在一种实施例中，位于所述第一重合区域的第一栅极的宽度等于位于所述第二重合区域的第二栅极的宽度，位于所述第三重合区域的第三栅极的宽度等于位于所述第四重合区域的第四栅极的宽度，且位于所述第一重合区域的第一栅极的宽度等于或者大于位于所述第三重合区域的第三栅极的宽度。通过使位于第一重合区域的第一栅极的宽度等于位于第三重合区域的第三栅极的宽度，无需改变栅极的设计，无需更改栅极的掩模版，而位于第一重合区域的第一有源图案的宽度小于位于第三重合区域的第二有源图案的宽度，可以使补偿晶体管的第一沟道的宽长比小于第一初始化晶体管的第二沟道的宽长比，则可以使补偿晶体管对驱动晶体管的栅极电位的影响相较于第一初始化晶体管对驱动晶体管的栅极电位的影响降低，使补偿晶体管和第一初始化晶体管对驱动晶体管的栅极电位的影响达到平衡，从而改善显示闪烁的问题。
通过使位于所述第一重合区域的第一栅极的宽度大于位于所述第三重合区域的第三栅极的宽度，可以使补偿晶体管的第一沟道的宽长比相较于第一初始化晶体管的第二沟道的宽长比更小，进一步缩小或者消除补偿晶体管和第一初始化晶体管对驱动晶体管的栅极的影响，改善显示闪烁的问题。
需要说明的是，上述实施例以第一子沟道的宽长比等于所述第二子沟道的宽长比，第三子沟道的宽长比等于第四子沟道的宽长比为例对栅极和有源图案的设计进行了详细说明，但本申请实施例不限于此，例如在第一子沟道的宽长比小于第二子沟道的宽长比，第三子沟道的宽长比大于第四子沟道的宽长比时，也可以采用与上述实施例类同的方式对栅极和有源图案进行设计。
在一种实施例中，所述第一初始化晶体管为低温多晶硅薄膜晶体管，所述补偿晶体管为低温多晶硅薄膜晶体管，所述补偿晶体管包括第一栅极和第二栅极，所述第一初始化晶体管包括第三栅极和第四栅极，所述第一栅极和所述第二栅极在所述第一有源图案上的投影存在间距，所述第三栅极和所述第四栅极在所述第二有源图案上的投影存在间距。本申请针对低温多晶硅薄膜晶体管会采用双栅设计，双栅之间的半导体图案容易受到其他信号的耦合，导致电位较高，在发光阶段向驱动晶体管漏电，通过设置屏蔽金属，减小对驱动晶体管的栅极的漏电，改善显示闪烁。
在一种实施例中，横向设置的相邻像素驱动电路对称设置，相邻像素驱动电路中的第一初始化晶体管连接至同一初始化信号线，相邻像素驱动电路中的补偿晶体管连接至同一扫描线。通过将相邻像素驱动电路中的第一初始化晶体管连接至同一初始化信号线，使相邻像素驱动电路中的补偿晶体管连接至同一扫描线，减小子像素的占用空间，可以提高显示面板的开口率，且由于无需将两个子像素之间的部分走线断开，降低了工艺难度，提高了显示面板的良率。
在一种实施例中，如图1、图2所示，所述像素驱动电路还包括第二初始化晶体管T7，所述第二初始化晶体管T7与第二初始化信号线VI-2连接，用于在第四扫描信号的控制下，向所述发光器件LED阳极输入第二初始化信号；
第一发光控制晶体管T5，通过第二节点A与所述驱动晶体管Drive TFT相连，用于在发光控制信号的控制下，导通电源高电位信号线VDD向所述驱动晶体管Drive TFT的电流；
第二发光控制晶体管T6，通过第三节点B与所述驱动晶体管Drive TFT相连，用于在发光控制信号的控制下，导通所述驱动晶体管Drive TFT流向所述发光器件LED阳极的电流。
在一种实施例中，所述显示面板包括：
衬底；
像素驱动电路层，包括多个像素驱动电路；
其中，所述像素驱动电路包括依次层叠设置在所述衬底上的半导体层、第一金属层、第二金属层和第三金属层，所述半导体层包括所述第一有源图案和所述第二有源图案，所述第一金属层包括第一栅极、第二栅极、第三栅极和第四栅极。
在一种实施例中，所述第二金属层形成有存储电容的极板。
在一种实施例中，所述第三金属层形成有源极和漏极。
如图3至图6所示，图3为图2中半导体层的透视图，图4为图2中的第一金属层的透视图，图5为图2中的第二金属层的透视图，图6为图2中的第三金属层透视图。
在一种实施例中，如图1所示，所述像素驱动电路还包括存储电容Cst，所述存储电容Cst一端与所述电源高电位信号线VDD连接，所述存储电容Cst另一端与所述第一节点Q连接。
可以理解的是，在本申请实施例中，如图1所示，数据线Data传输数据信号，第一初始化信号线VI-1传输第一初始化信号、第二初始化信号线VI-2传输第二初始化信号，第一扫描信号线Scan2（n-1）传输第一扫描信号，第二扫描信号线Scan1（n-1）传输第二扫描信号，第三扫描信号线Scan2（n）传输第三扫描信号，第四扫描信号线Scan1（n）传输第四扫描信号，发光控制信号线EM（n）传输发光控制信号，电源低电位信号线VSS传输低电位。
需要说明的是，Scan1和Scan2表示两组扫描线，Scan（n-1）和Scan（n）表示两级扫描线。
需要说明的是，图2中以两个子像素中的像素驱动电路示出各元件的设置以及连接关系，且为了便于查看补偿晶体管和第一初始化晶体管的设计，未示出部分元件和走线，例如图2中未示出第一初始化信号线VI-1。
具体的，如图3所示，分别以Drive TFT、T2、T3、T4、T5、T6、T7表示各晶体管的有源图案的设置位置，且可以看到第一有源图案和第二有源图案具有弯折结构；如图4所示，分别以Drive TFT、T2、T3、T4、T5、T6、T7表示各晶体管的栅极，从图4可以看到，补偿晶体管T3的第一栅极和第二栅极为相互垂直的两个部分，第一初始化晶体管T4的第三栅极和第四栅极为相互垂直的两个部分；如图5、图6所示，示出了各走线的结构以及设置位置，且从图5和图6可以看到，在图2中，位于不同膜层的元件可以通过过孔并通过对应膜层的金属连接，因此，图5、图6中存在未标示的部分，该未标示的部分标示此处存在过孔连接，此走线可以作为连接走线。
需要说明的是，上述实施例以图1所示的像素驱动电路和图2中的透视图对补偿晶体管和第一初始化晶体管的设置方式进行了详细说明，但本申请实施例不限于此，例如像素驱动电路采用其他设计方式，例如还有其他双栅设计的晶体管连接至驱动晶体管，也可以对其他双栅设计的晶体管的沟道进行设计，改善显示闪烁。
需要说明的是，图8、图9、图10中示出的显示面板与图2中的显示面板仅存在补偿晶体管和第一初始化晶体管的结构区别，图8、图9、图10中示出的显示面板的分解图可以类比图2中的显示面板的分解图确定，在此不再赘述。
同时，本申请实施例提供一种显示装置，该显示装置包括上述实施例任一所述的显示面板和电子元件。
根据上述实施例可知：
本申请实施例提供一种显示面板和显示装置；该显示面板包括阵列设置的多个发光器件和驱动发光器件的像素驱动电路，像素驱动电路包括第一初始化晶体管、开关晶体管、驱动晶体管和补偿晶体管，第一初始化晶体管与第一初始化信号线连接，用于在第一扫描信号的控制下，向第一节点输入第一初始化信号，开关晶体管用于在第二扫描信号的控制下，向第二节点输入数据信号，驱动晶体管用于在第一节点和第二节点电位的控制下，驱动发光器件发光，补偿晶体管通过第一节点和第三节点与驱动晶体管相连，用于在第三扫描信号的控制下，补偿驱动晶体管的阈值电压；其中，补偿晶体管包括相连的第一栅极和第二栅极、第一有源图案，第一初始化晶体管包括相连的第三栅极和第四栅极、第二有源图案，补偿晶体管的第一沟道的宽长比小于第一初始化晶体管的第二沟道的宽长比，第一沟道包括第一子沟道和第二子沟道，第二沟道包括第三子沟道和第四子沟道，第一子沟道位于第二子沟道靠近驱动晶体管的一侧，第三子沟道位于第四子沟道靠近驱动晶体管的一侧，第一子沟道的宽长比小于第三子沟道的宽长比。本申请通过使补偿晶体管的第一沟道的宽长比小于第一初始化晶体管的宽长比，并使第一子沟道的宽长比小于第三子沟道的宽长比，可以减小补偿晶体管的漏电对驱动晶体管的栅极的影响或者增大第一初始晶体管的漏电对驱动晶体管的栅极的影响，从而使补偿晶体管漏电对驱动晶体管的栅极的电位的拉升影响和第一初始化晶体管对驱动晶体管的栅极的电位的拉低影响抵消，从而避免各晶体管的漏电导致驱动晶体管的栅极电位变化，改善显示闪烁的问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种显示面板和显示装置进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其中，所述显示面板包括阵列设置的多个发光器件和驱动所述发光器件的像素驱动电路，所述像素驱动电路包括：
    第一初始化晶体管，与第一初始化信号线连接，用于在第一扫描信号的控制下，向第一节点输入第一初始化信号；
    开关晶体管，用于在第二扫描信号的控制下，向第二节点输入数据信号；
    驱动晶体管，与第一节点和第二节点电连接，用于在第一节点和第二节点电位的控制下，驱动所述发光器件发光；
    补偿晶体管，通过所述第一节点和第三节点与所述驱动晶体管相连，用于在第三扫描信号的控制下，补偿所述驱动晶体管的阈值电压；
    其中，所述补偿晶体管包括至少两个子沟道，所述补偿晶体管中靠近所述驱动晶体管的子沟道的宽长比小于所述第一初始化晶体管的沟道的宽长比。
  2. 如权利要求1所述的显示面板，其中，所述第一初始化晶体管包括至少两个子沟道，所述补偿晶体管中靠近所述驱动晶体管的子沟道的宽长比小于所述第一初始化晶体管中靠近所述驱动晶体管的子沟道的宽长比。
  3. 如权利要求2所述的显示面板，其中，所述补偿晶体管包括第一沟道，所述第一初始化晶体管包括第二沟道，所述第一沟道至少包括第一子沟道和第二子沟道，所述第二沟道至少包括第三子沟道和第四子沟道，所述第一子沟道位于所述第二子沟道靠近所述驱动晶体管的一侧，所述第三子沟道位于所述第四子沟道靠近所述驱动晶体管的一侧，所述第一子沟道的宽长比小于所述第三子沟道的宽长比，且所述第一沟道的宽长比小于所述第一初始化晶体管的第二沟道的宽长比。
  4. 如权利要求3所述的显示面板，其中，所述第一子沟道的宽长比小于所述第二子沟道的宽长比，所述第三子沟道的宽长比大于所述第四子沟道的宽长比。
  5. 如权利要求4所述的显示面板，其中，所述第二子沟道的宽长比等于所述第四子沟道的宽长比，或者所述第二子沟道的宽长比小于所述第四子沟道的宽长比。
  6. 如权利要求3所述的显示面板，其中，所述第一子沟道的宽长比小于所述第二子沟道的宽长比，所述第三子沟道的宽长比等于所述第四子沟道的宽长比，且所述第二子沟道的宽长比等于所述第四子沟道的宽长比。
  7. 如权利要求3所述的显示面板，其中，所述第三子沟道的宽长比大于所述第四子沟道的宽长比，所述第一子沟道的宽长比等于所述第二子沟道的宽长比，且所述第一子沟道的宽长比等于所述第四子沟道的宽长比。
  8. 如权利要求3所述的显示面板，其中，所述第一子沟道的宽长比等于所述第二子沟道的宽长比，所述第三子沟道的宽长比等于所述第四子沟道的宽长比。
  9. 如权利要求8所述的显示面板，其中，所述补偿晶体管包括相连的第一栅极和第二栅极、第一有源图案，所述第一初始化晶体管包括相连的第三栅极和第四栅极、第二有源图案，在所述第一子沟道，所述第一有源图案所述第一栅极存在第一重合区域，在所述第二子沟道，所述第一有源图案与所述第二栅极存在第二重合区域，在所述第三子沟道，所述第二有源图案与所述第三栅极存在第三重合区域，在所述第四子沟道，所述第二有源图案与所述第四栅极存在第四重合区域；
    其中，位于所述第一重合区域的第一有源图案的宽度与所述第一栅极的宽度的比值等于位于所述第二重合区域的第一有源图案的宽度与第二栅极的宽度的比值，位于所述第三重合区域的第二有源图案的宽度与所述第三栅极的宽度的比值等于位于所述第四重合区域的第二有源图案的宽度与所述第四栅极的宽度的比值，且位于所述第一重合区域的第一有源图案的宽度与所述第一栅极的宽度的比值小于位于所述第三重合区域的第二有源图案的宽度与第三栅极的宽度的比值。
  10. 如权利要求9所述的显示面板，其中，位于所述第一重合区域的第一栅极的宽度等于位于所述第二重合区域的第二栅极的宽度，位于所述第三重合区域的第三栅极的宽度等于位于所述第四重合区域的第四栅极的宽度，且位于所述第一重合区域的第一栅极的宽度大于位于所述第三重合区域的第三栅极的宽度。
  11. 如权利要求10所述的显示面板，其中，位于所述第一重合区域的第一有源图案的宽度等于位于所述第二重合区域的第一有源图案的宽度，位于所述第三重合区域的第二有源图案的宽度等于位于所述第四重合区域的第二有源图案的宽度，且位于所述第一重合区域的第一有源图案的宽度等于位于所述第三重合区域的第二有源图案的宽度。
  12. 如权利要求9所述的显示面板，其中，位于所述第一重合区域的第一有源图案的宽度等于位于所述第二重合区域的第一有源图案的宽度，位于所述第三重合区域的第二有源图案的宽度等于位于所述第四重合区域的第二有源图案的宽度，且位于所述第一重合区域的第一有源图案的宽度小于位于所述第三重合区域的第二有源图案的宽度。
  13. 如权利要求12所述的显示面板，其中，位于所述第一重合区域的第一栅极的宽度等于位于所述第二重合区域的第二栅极的宽度，位于所述第三重合区域的第三栅极的宽度等于位于所述第四重合区域的第四栅极的宽度，且位于所述第一重合区域的第一栅极的宽度等于或者大于位于所述第三重合区域的第三栅极的宽度。
  14. 如权利要求1所述的显示面板，其中，所述第一初始化晶体管为低温多晶硅薄膜晶体管，所述补偿晶体管为低温多晶硅薄膜晶体管，所述补偿晶体管包括第一栅极和第二栅极，所述第一初始化晶体管包括第三栅极和第四栅极，所述第一栅极和所述第二栅极在所述第一有源图案上的投影存在间距，所述第三栅极和所述第四栅极在所述第二有源图案上的投影存在间距。
  15. 如权利要求1所述的显示面板，其中，横向设置的相邻像素驱动电路对称设置，相邻像素驱动电路中的第一初始化晶体管连接至同一初始化信号线，相邻像素驱动电路中的补偿晶体管连接至同一扫描线。
  16. 如权利要求1所述的显示面板，其中，所述像素驱动电路还包括第二初始化晶体管，所述第二初始化晶体管与第二初始化信号线连接，用于在第四扫描信号的控制下，向所述发光器件阳极输入第二初始化信号；
    第一发光控制晶体管，通过第二节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通电源高电位信号线向所述驱动晶体管的电流；
    第二发光控制晶体管，通过第三节点与所述驱动晶体管相连，用于在发光控制信号的控制下，导通所述驱动晶体管流向所述发光器件阳极的电流。
  17. 如权利要求16所述的显示面板，其中，所述像素驱动电路还包括存储电容，所述存储电容一端与所述电源高电位信号线连接，所述存储电容另一端与所述第一节点连接。
  18. 如权利要求1所述的显示面板，其中，所述显示面板包括：
    衬底；
    像素驱动电路层，包括多个像素驱动电路；
    其中，所述像素驱动电路包括依次层叠设置在所述衬底上的半导体层、第一金属层、第二金属层和第三金属层，所述半导体层包括所述第一有源图案和所述第二有源图案，所述第一金属层包括第一栅极、第二栅极、第三栅极和第四栅极。
  19. 如权利要求18所述的显示面板，其中，所述第二金属层形成有存储电容的极板。
  20. 如权利要求18所述的显示面板，其中，所述第三金属层形成有源极和漏极。
PCT/CN2022/092727 2022-05-07 2022-05-13 显示面板 Ceased WO2023216239A1 (zh)

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