WO2023148799A1 - 半導体素子を用いたメモリ装置 - Google Patents

半導体素子を用いたメモリ装置 Download PDF

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Publication number
WO2023148799A1
WO2023148799A1 PCT/JP2022/003747 JP2022003747W WO2023148799A1 WO 2023148799 A1 WO2023148799 A1 WO 2023148799A1 JP 2022003747 W JP2022003747 W JP 2022003747W WO 2023148799 A1 WO2023148799 A1 WO 2023148799A1
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layer
semiconductor
impurity
conductor layer
gate
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English (en)
French (fr)
Japanese (ja)
Inventor
正一 各務
康司 作井
望 原田
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Unisantis Electronics Singapore Pte Ltd
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Unisantis Electronics Singapore Pte Ltd
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Priority to JP2023522527A priority Critical patent/JP7705670B2/ja
Priority to PCT/JP2022/003747 priority patent/WO2023148799A1/ja
Priority to US18/162,446 priority patent/US20230247820A1/en
Priority to TW112103500A priority patent/TWI846299B/zh
Publication of WO2023148799A1 publication Critical patent/WO2023148799A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies

Definitions

  • the present invention relates to a memory device using semiconductor elements.
  • the channel In a normal planar MOS transistor, the channel extends horizontally along the upper surface of the semiconductor substrate. In contrast, the SGT channel extends in a direction perpendicular to the upper surface of the semiconductor substrate (see Patent Document 1 and Non-Patent Document 1, for example). For this reason, the SGT enables a higher density semiconductor device compared to a planar MOS transistor.
  • a DRAM Dynamic Random Access Memory
  • PCM Phase Change Memory
  • RRAM Resistive Random Access Memory
  • MRAM Magnetic-resistive Random Access Memory
  • Non-Patent Document 6 a DRAM memory cell having no capacitor and composed of a single MOS transistor, and a DRAM memory cell having two gate electrodes and trenches for storing carriers (see Non-Patent Document 8). See), etc.
  • a DRAM without a capacitor has a problem that a sufficient voltage margin cannot be obtained because it is greatly affected by the coupling of the gate electrode from the word line of the floating body. Further, when the substrate is completely depleted, the harmful effects are increased.
  • the present application relates to a memory device using semiconductor elements, which does not have a variable resistance element or a capacitor and can be configured only with MOS transistors.
  • a memory device using a semiconductor element includes: a substrate; a first semiconductor layer overlying the substrate; a first impurity layer, at least part of which is columnar, on the surface of part of the first semiconductor layer; a second semiconductor layer extending vertically in contact with the columnar portion of the first impurity layer; a first insulating layer covering part of the first semiconductor layer and part of the first impurity layer; a first gate insulating layer in contact with the first insulating layer and surrounding the first impurity layer and the second semiconductor layer; a first gate conductor layer in contact with the first insulating layer and the first gate insulating layer; a second insulating layer formed in contact with the first gate conductor layer and the first gate insulating layer; a third semiconductor layer in contact with the second semiconductor layer; a second gate insulating layer surrounding part or all of the upper portion of the third semiconductor layer; a second gate conductor layer covering part or all of the top of the second gate insulating layer;
  • the first wiring conductor layer connected to the second impurity layer is a source line
  • the second wiring conductor layer connected to the third impurity layer is a bit line
  • the third wiring conductor layer connected to the second gate conductor layer is a word line
  • the fourth wiring conductor layer connected to the first gate conductor layer is a plate line
  • a source line A voltage is applied to each of the bit line, plate line and word line to write and erase the memory (second invention).
  • the first invention is characterized in that the first gate conductor layer and the second gate conductor layer have different work functions (third invention).
  • the majority carriers in the first impurity layer are electrons
  • the majority carriers in the second semiconductor layer are holes
  • the work function of the first gate conductor layer is the second is larger than the work function of the gate conductor layer of (fourth invention).
  • the majority carriers in the first impurity layer are holes
  • the majority carriers in the second semiconductor layer are holes
  • the work function of the first gate conductor layer is the first 2 (fifth invention).
  • the first invention is characterized in that majority carriers in the first impurity layer are different from majority carriers in the first semiconductor layer (sixth invention).
  • the majority carriers in the second semiconductor layer are the same as the majority carriers in the first semiconductor layer (seventh invention).
  • the first invention is characterized in that majority carriers in the second impurity layer and the third impurity layer are the same as majority carriers in the first impurity layer (eighth invention).
  • the concentration of the first impurity layer is lower than that of the second impurity layer and the third impurity layer (ninth invention).
  • the vertical distance from the bottom of the third semiconductor layer to the top of the first impurity layer is the distance from the bottom of the third semiconductor layer to the bottom of the first gate conductor layer. It is characterized by being shorter than the vertical distance (10th invention).
  • a source line contact hole for connecting the source line and the second impurity layer, and the first wiring conductor layer are shared by adjacent cells (the first wiring conductor layer). 11 invention).
  • bit line contact hole for connecting the bit line and the third impurity layer and the second wiring conductor layer are shared by adjacent cells (the second wiring conductor layer). 12 Invention).
  • the first gate conductor layer is separated by a fourth insulating layer in contact with the first gate conductor layer and connected to the first plate line and the second plate line, respectively. , and independent voltages are applied (a thirteenth invention).
  • the bottom of the first impurity layer is located deeper than the bottom of the first insulating layer, and the first impurity layer is shared by a plurality of cells.
  • a fifth wiring conductor layer connected to the first impurity layer is provided, and the fifth wiring conductor layer is a control line to which a desired voltage can be applied. (16th invention).
  • FIG. 4 is a diagram for explaining a write operation of the memory device using the semiconductor element according to the first embodiment, accumulation of carriers immediately after the operation, and cell current;
  • FIG. 4 is a diagram for explaining accumulation of hole carriers, erase operation, and cell current immediately after write operation of the memory device using the semiconductor element according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the memory device according to the first embodiment;
  • FIG. 4 is a diagram for explaining the method of manufacturing the memory device according to the first embodiment;
  • It is a cross-sectional structure of a memory device using a semiconductor element according to a second embodiment.
  • FIG. 10 is a diagram for explaining the manufacturing process of the memory device according to the second embodiment; . It is a cross-sectional structure of a memory device using a semiconductor element according to a third embodiment.
  • FIG. 1 shows a vertical cross-sectional structure of a memory using a semiconductor device according to the first embodiment of the present invention.
  • There is a columnar p-layer 4 (which is an example of the "second semiconductor layer” in the claims).
  • a first insulating layer 2 covering part of the p-layer 1 and the n-layer 3 (which is an example of a "first insulating layer” in the claims) and a first gate insulating layer covering part of the p-layer 4
  • a layer 5 (which is an example of a "first gate insulating layer” in the claims).
  • the first gate conductor layer 22 (which is an example of the “first gate conductor layer” in the claims) is in contact with the first insulating layer 2 and the first gate insulating layer 5 .
  • There is a second insulating layer 6 (which is an example of the “second insulating layer” in the claims) in contact with the gate insulating layer 5 and the gate conductor layer 22 .
  • a p-layer 8 containing acceptor impurities (which is an example of a "third semiconductor layer” in the claims).
  • n+ layer 7a an example of a "second impurity layer” in the scope of claims
  • n+ layer 7b On one side opposite to the n+ layer 7a is an n+ layer 7b (which is an example of a "third impurity layer” in the claims).
  • a second gate insulating layer 9 (which is an example of the "second gate insulating layer” in the claims) is provided on the upper surface of the p-layer 8 . Gate insulating layer 9 is in contact with or close to n+ layers 7a and 7b, respectively. A second gate conductor layer 10 having a work function lower than that of the first gate conductor layer 22 is provided on the opposite side of the semiconductor layer 8 in contact with the gate insulating layer 9 ("second is an example of the "gate conductor layer of
  • n+ layer 7a is connected to the source line SL (an example of the "source line” in the scope of claims) which is the first wiring conductive layer
  • n+ layer 7b is connected to the bit line BL (which is the second wiring conductive layer).
  • the gate conductor layer 10 is an example of the "bit line” in the claims), the word line WL (which is an example of the "word line” in the claims), the gate conductor layer 10 is the third wiring conductive layer.
  • Each conductor layer 22 is connected to a plate line PL (an example of a "plate line” in the scope of claims), which is a fourth wiring conductive layer.
  • the memory is operated by manipulating the potentials of the source line, bit line, plate line, and word line. This memory device is hereinafter referred to as dynamic flash memory.
  • one or a plurality of dynamic flash memory cells described above are arranged two-dimensionally on the substrate 20 .
  • the impurity concentration may have a profile.
  • the impurity concentrations of the n-layer 3, the p-layer 4, and the p-layer 8 may have profiles. Further, the impurity concentration and profile may be set independently for the p-layer 4 and the p-layer 8 .
  • n+ layer 7a and the n+ layer 7b are formed of a p+ layer in which holes are majority carriers (hereinafter, a semiconductor region containing a high concentration of acceptor impurities is referred to as a "p+ layer")
  • Write carriers are electrons. Dynac flash memory operation is performed.
  • the first semiconductor layer 1 is a p-type semiconductor. Even if memory cells are arranged, the operation of the dynamic flash memory is performed.
  • the insulating layer 2 and the gate insulating layer 5 are shown separately in FIG. 1, they may be formed integrally.
  • the insulating layer 2 and the gate insulating layer 5 are collectively referred to as the gate insulating layer 5 .
  • third semiconductor layer 8 is a p-type semiconductor in FIG.
  • third semiconductor layer 8 can be of p-type, n-type or i-type.
  • FIG. 1 the bottom of the p layer 8 and the upper surface of the insulating layer 6 are shown to coincide with each other.
  • the interface between p-layer 4 and p-layer 8 does not have to coincide with the upper surface of insulating layer 6 as long as it is deeper than the bottom of insulating layer 6 .
  • any material can be used for the substrate 20 as long as it can support the p-layer 1, whether it is an insulator, a semiconductor, or a conductor.
  • the gate conductor layer 22 can change the potential of a part of the memory cell through the insulating layer 2 or the gate insulating layer 5, and if the gate conductor layer 10 has a work function different from that of the gate conductor layer 10, a high concentration It may be a semiconducting layer doped with , or a conducting layer.
  • first to fourth wiring conductive layers may be formed in multiple layers if they are not in contact with each other.
  • the bottom of the n-layer 3 and the bottom of the gate insulating layer 2 are shown to be aligned, but the n-layer 3 may be in contact with both the p-layer 1 and the gate insulating layer 2. You don't have to.
  • the majority carriers in the n+ layer 7a and the n+ layer 7b are electrons, and for example, p+poly (hereinafter, poly-Si containing a high concentration of acceptor impurities is referred to as "p+poly”) is used for the gate conductor layer 22 connected to PL. do.
  • p+poly poly-Si containing a high concentration of acceptor impurities
  • n+poly poly-Si containing a high concentration of acceptor impurities
  • the MOSFET in this memory cell includes an n+ layer 7a serving as a source, an n+ layer 7b serving as a drain, a gate insulating layer 9, a gate conductor layer 10 serving as a gate, and a p layer serving as a substrate.
  • Layer 8 acts as a component. For example, 0 V is applied to the p-layer 1, 0 V is input to the n+ layer 7a connected to the source line SL, 3 V is input to the n+ layer 7b connected to the bit line BL, and 3 V is input to the plate line PL. 0 V is applied to the gate conductor layer 22, and 1.5 V, for example, is applied to the gate conductor layer 10 connected to the word line WL.
  • a partial inversion layer 12 is formed immediately below the gate insulating layer 9 under the gate conductor layer 10, and a pinch-off point 13 exists.
  • a MOSFET with gate conductor layer 10 therefore operates in the saturation region.
  • the electric field becomes maximum between the pinch-off point 13 and the boundary region between the n+ layer 7b in the MOSFET having the gate conductor layer 10, and the impact ionization phenomenon occurs in this region. Due to this impact ionization phenomenon, electrons accelerated from the n+ layer 7a connected to the source line SL toward the n+ layer 7b connected to the bit line BL collide with the Si lattice, and the kinetic energy of the electrons/holes A pair is generated. The generated holes diffuse toward the lower hole concentration due to the concentration gradient. Some of the generated electrons flow into the gate conductor layer 10, but most of them flow into the n+ layer 7b connected to the bit line BL.
  • a gate-induced drain leakage (GIDL) current may be passed to generate hole groups (see, for example, Non-Patent Document 7).
  • FIG. 2(b) shows the hole groups 11 in the p-layers 4 and 8 when all the electrodes WL, BL, PL, and SL are at 0 V immediately after writing.
  • the generated hole groups 11 are the majority carriers of the p-layer 4 and the p-layer 8, but the concentration of the generated holes temporarily becomes high in the region of the p-layer 8, and the concentration gradient causes the concentration of the holes in the p-layer 4 moves by diffusion. Furthermore, since p+poly, which has a higher work function than n+poly, is used for the first gate conductor layer 22 , the p-layer 4 is accumulated in a higher concentration near the first gate insulating layer 5 .
  • the hole concentration in p layer 4 is higher than the hole concentration in p layer 8 .
  • P-layer 8 which is substantially the substrate of the MOSFET with gate conductor layer 10, is charged to a positive bias because p-layer 4 and p-layer 8 are electrically connected. Holes in the depletion layer move toward the SL side, the BL side, or the n layer 3 and gradually recombine with electrons. 4 and p-layer 8 are lowered by positive substrate bias effects due to the temporary accumulation of holes. As a result, as shown in FIG. 2(c), the threshold voltage of the MOSFET having the gate conductor layer 10 connected to the word line WL is lowered. This write state is assigned to logical storage data "1".
  • bit lines BL, source lines SL, word lines WL, and plate lines PL are examples for performing the write operation, and other voltage conditions that allow the write operation may be used.
  • FIG. 2 shows a combination of p+ poly (work function 5.15 eV) and n+ poly (work function 4.05 eV) as an example of the combination of the gate conductor layer 22 and the gate conductor layer 10, but this is Ni (work function function 5.2 eV) and n+poly, Ni and W (work function 4.52 eV), Ni and TaN (work function 4.0 eV)/W/TiN (work function 4.7 eV), metals, metal nitrides, or An alloy thereof (including silicide) or a laminated structure may be used.
  • the generated holes can be accumulated.
  • the capacitance can be freely changed by adjusting the volume of p-layer 4 .
  • the depth of the p-layer 4 should be increased in order to lengthen the retention time. Therefore, the bottom of p layer 4 is required to be deeper than the bottom of p layer 8 .
  • the n layer 3, the n + layer 7a, and the n + layer 7b involved in recombination with electrons are in contact with each other, compared to the volume of the p layers 4 and 8 where the hole carriers are accumulated.
  • FIG. 3(a) shows the state immediately after the hole groups 11 generated by impact ionization in the previous cycle are stored in the p-layers 4 and 8 and all the biases become 0 V before the erasing operation. ing.
  • the voltage of the source line SL is set to the negative voltage VERA during the erase operation.
  • the voltage of PL is set to 2V.
  • VERA is, for example, -0.5V.
  • the structure of the present embodiment it is possible to effectively increase the recombination area of electrons and holes when erasing data compared to when storing data. Therefore, a stable state of logic information data "0" can be provided in a short time, and the operating speed of this dynamic flash memory device is improved.
  • the voltage conditions applied to the bit lines BL, source lines SL, word lines WL, and plate lines PL are examples for performing the erase operation, and other voltage conditions that enable the erase operation may be used.
  • the gate conductor layer 22 is biased to 2 V is described above.
  • An inversion layer in which electrons are majority carriers can be formed at the interface between the layer 8 and the gate insulating layer 9 and the interface between the p-layer 4 and the gate insulating layer 2, and the recombination area of electrons and holes can be increased.
  • the erasing time can be shortened more positively by passing a current having electrons as majority carriers between BL and SL.
  • the inversion layer 14 will cause the n+ layer 7a or 7b to and the n-layer 3 can be connected, and the data erasing time can be shortened.
  • the p-layer 8 which is one of the constituent elements of the MOSFET for reading and writing information, is electrically connected to the p-layer 1, the n-layer 3, and the p-layer 4. Additionally, a voltage can be applied to the gate conductor layer 22 . Therefore, in both the write operation and the erase operation, for example, the substrate bias becomes unstable in the floating state during the MOSFET operation like the SOI structure, and the semiconductor portion under the gate insulating layer 9 is completely depleted. I have nothing to do. For this reason, the threshold value, drive current, etc. of the MOSFET are less likely to be affected by the operating conditions.
  • the characteristics of the MOSFET are the thickness of the p-layer 8, the type of impurity, the impurity concentration and profile, the impurity concentration and profile of the p-layer 4, the thickness and material of the gate insulating layer 9, and the work functions of the gate conductor layers 10 and 22. , can be adjusted to set a wide range of voltages for desired memory operations.
  • the depletion layer is not completely depleted under the MOSFET and spreads in the depth direction of the p-layer 4, the coupling of the gate electrode from the word line of the floating body, which is a drawback of the DRAM which does not have a capacitor, is eliminated. Almost unaffected.
  • the structure is resistant to disturbance failure of the memory.
  • the holes of the pairs of holes and electrons generated in the depletion layer in the cell during holding are accumulated in the p-layer 8, and the data changes from "0" to "1".
  • holes are accumulated in a higher concentration in the p-layer 4, so that the change in the hole concentration in the p-layer 8 immediately below the MOSFET is not greatly affected. Therefore, "0" data information can be held stably.
  • the above state can be achieved by applying 0 V to BL, WL, and SL and ⁇ 0.5 V to PL. It is within the scope of the present invention. However, considering the difficulty of generating a negative voltage inside and controlling it in a timely manner, it is better to use materials having different work functions for the first gate conductor layer and the second gate conductor layer. This is a simple method from the viewpoint of electrode potential control.
  • the element structure consisting of the p layer 8, the n+ layers 7a and 7b, the gate insulating layer 9, and the gate conductor layer 10 is applicable not only to this memory cell but also to other general devices. It can be formed in common with MOS circuits including CMOS structures. Therefore, this memory cell can be easily combined with a conventional CMOS circuit.
  • 4A to 4I show a method of manufacturing a dynamic flash memory according to this embodiment.
  • (a) is a plan view
  • (b) is a vertical cross-sectional view along the XX' line of (a)
  • (c) is a vertical cross-sectional view along the YY' line of (a). indicates Identical or similar components to those shown in FIG. 1 are given the same reference numerals.
  • p-layer 1, n-layer 3, p-layer 4, insulating layer 41, and mask material layer 42 are formed on substrate 20 from the bottom.
  • the substrate may be a semiconductor or an insulating film.
  • the p layer 1 and the n layer 3 may be well layers.
  • the insulating layer 41 can be a silicon oxide film
  • the mask material layer 42 can be a silicon nitride film.
  • the insulating layer 41, the p-layer 4 and the n-layer 3 are etched by RIE (Reactive Ion Etching) in a region that will become a memory cell in the future. do.
  • RIE Reactive Ion Etching
  • the bottom of the etched groove is drawn to match the bottom of the n layer 3, but the bottom of the groove should be deeper than the top of the n layer 3.
  • an insulating film 2 is selectively formed by oxidation on the sidewalls and bottoms of the p-layer 4 and n-layer 3 left by etching.
  • the gate insulating layer 5 and the insulating film 2 are described separately, but they are collectively described as a gate insulating layer 25 hereinafter.
  • an oxide film may be formed on the entire surface using, for example, ALD (Atomic Layer Deposition) technology.
  • the gate insulating layer 25 is also formed around the mask material layer 42 .
  • polycrystalline silicon heavily doped with boron is deposited as a gate conductor layer 22 on the entire surface by, for example, CVD, and then etched back by selective RIE to form a gate conductor layer.
  • the upper surface of 22 is etched to be lower than the upper surface of p layer 4 .
  • an insulating layer 6 is formed on the entire surface by, for example, CVD.
  • the insulating layer 6 is polished by a CMP (Chemical Mechanical Polishing) technique until the surfaces of the mask materials 42a to 42d are exposed, and then the mask materials 42a to 42d are selectively removed. Furthermore, the insulating layer 6 is etched back until the surface of the p-layer 4 appears, and the insulating layer 41 is etched at the same time.
  • CMP Chemical Mechanical Polishing
  • a semiconductor layer 8 is grown by, for example, a CVD method under conditions such that it is continuous as a crystal layer from the p-layer 4, and then a portion other than the portion necessary for operating as a MOSFET in the memory cell is grown. is removed.
  • a gate insulating layer 9 is formed, and a gate conductor layer 10 is formed of n+poly whose work function is lower than that of the gate conductor layer 22 so as to serve as the gate electrode of the MOSFET in each memory cell. process.
  • these are shown as gate insulating layers 9a, 9b, 9c and gate conductor layers 10a, 10c. Thereafter, n+ layers 7a and n+7b are formed in a self-aligned manner.
  • contact holes 33a to 33d are formed in the respective memory cells. After that, wiring conductor layers 35 and 36 are formed. The wiring conductor layer 35 is connected to the source line SL. Next, after forming an insulating film 38, second contact holes 37c and 37d are formed and a wiring conductor layer 39 is formed. It is connected to the bit line BL.
  • FIG. 4I(a) In the plan view of FIG. 4I(a), there are actually only the second wiring conductor layer 39 and the insulating film 38 in the upper part, but for the sake of understanding, the p-layers 4a to 4d and the gate conductors in the main lower layers are shown. Layers 10a, 10c and contact holes 33a, 33b, 33c, 33d, 37c, 37d are shown. Focusing on the memory cell at the intersection of XX' and YY' in FIG. (FIG.
  • the impurity layer 4 is p-type
  • the gate conductor layer 22 is p+poly
  • the gate conductor layer 10 is n+poly.
  • the gate conductor layers 10 and 22 may be a semiconductor, a metal, or a compound thereof.
  • FIGS. 4A to 4J the shape of the groove has been described using a rectangular vertical cross section, but it may be trapezoidal.
  • the impurity layers 3 and 4 are shown as columns having square bottoms, but they may be columns having other polygonal or circular bottoms.
  • the n-layer 3 may exist in a portion where a memory cell will be present in the future. Therefore, although the n layer 3 is formed on the entire surface of the p layer 1 in FIG. 4A, the n layer 3 may be formed only on a selected region on the p layer 1.
  • Any material may be used for the mask material layers 42a to 42d and the gate insulating layer 25 as long as a selectivity can be obtained during etching.
  • the mask material layers 42a to 42d are used as the CMP endpoint materials, but the gate insulating layer 25, the insulating layer 6, the p-layer 4, etc. can also be used.
  • any insulating film used in a normal MOS process such as a SiO2 film, a SiON film, an HfSiON film, or a laminated film of SiO2/SiN, can be used. It is possible.
  • the wiring conductor layers 36 and 39 and the contact hole 33c can be formed by using the damascene method or the like.
  • 37c can be formed in a single process.
  • the gate conductor layer 10, the semiconductor layer 8, and all the wiring conductor layers are illustrated so as to extend in parallel or perpendicular to the XX' axis or the YY' axis. They may extend obliquely.
  • the MOS circuit portion including the peripheral circuits other than the memory cells is not shown, but the same mask as the p-layer 8 portion of FIG. 4G is used for that portion, and the respective impurity concentrations are controlled. Then, it is clear that MOSFETs for circuits other than memory cells can be formed in the same process after the MOSFETs are formed.
  • the substrate region where the channel of the MOSFET is formed is composed of the p-layer 4 and the p-layer 8 surrounded by the insulating layer 2, the gate insulating layer 5 and the n-layer 3. be done. Due to this structure, the majority carriers generated when logic data "1" is written can be accumulated in the p-layers 8 and 4, and their number can be increased. Furthermore, since a material having a larger work function than that of the gate conductor layer 10 is used for the gate conductor layer 22, the holes generated during writing can be accumulated near the interface of the p-layer 4 near the gate conductor layer 22, thereby providing information. longer retention time.
  • a positive voltage is applied to the gate conductor layer 22 to form an inversion layer and effectively increase the recombination area between holes and electrons, thereby increasing the recombination area with electrons and erasing data. is short.
  • the erase operation is accelerated by the thyristor structure of the n+ layer 7a, p-layer 8, p-layer 4, n-layer 3, and p-layer 1. can also Therefore, the operating margin of the memory can be expanded, the power consumption can be reduced, and the memory can operate at high speed.
  • the p-layer 8 which is one of the components of the MOSFET in the dynamic flash memory according to the first embodiment of the present invention, is connected to the p-layer 4, the n-layer 3, and the p-layer 1, and the gate conductor layer
  • p-layer 8 and p-layer 4 below gate insulating layer 9 are not completely depleted.
  • the threshold voltage, drive current, etc. of the MOSFET are less likely to be affected by the operating conditions of the memory.
  • the bottom of the MOSFET is not completely depleted, the coupling of the gate electrode from the floating body word line, which is a drawback of DRAMs without capacitors, is not greatly affected. That is, according to the present invention, it is possible to design a wide operating voltage margin as a dynamic flash memory.
  • the p-layer 8 which is one of the constituent elements of the MOSFET in the dynamic flash memory according to the first embodiment of the present invention, is connected to the p-layer 4, and is used for writing information data "1".
  • the amount of storage can be increased, for example, by ten times or more compared to conventional zero-capacitor DRAMs (Non-Patent Documents 6 and 9). Therefore, even if a disturbance factor occurs in the voltage applied to the memory cell for purposes other than reading and writing, the written information data "1" is less likely to disappear.
  • the present invention provides a memory cell structure that is resistant to disturb defects.
  • Adjacent cells share the n+ layer 7a, the wiring conductor layer 35 connected to the source line SL, and the contact hole 33a of the dynamic flash memory cell shown in FIG. 4I. Adjacent cells share the n+ layer 7c, the wiring conductor layers 36 and 39 connected to the bit lines BL, and the contact holes 33c and 37c. Therefore, the cell area of the dynamic flash memory according to the present invention is determined by the lines and spaces of the p-layers 8a, 8b and the gate conductors 10a, 10c, respectively, or the lines and spaces of the wiring conductor layers 35 and 36. FIG. Therefore, the cell area is 4F 2 where F is the minimum dimension for manufacturing, and a fine memory cell can be provided.
  • FIG. 5 A dynamic flash memory according to a second embodiment of the present invention will be described with reference to FIG.
  • components identical or similar to those in FIGS. 1 and 4 are denoted by the same reference numerals.
  • FIG. 5A(a) is a plan view thereof, and FIG.
  • the dynamic flash memory can operate by applying voltages to the source line SL, the plate lines PL-1 and PL-2, the word line WL, and the bit line BL, as in the first embodiment. .
  • FIG. 5B An example of the manufacturing method is shown using FIG. 5B.
  • a portion of the gate conductor layer 22 is etched by commonly used lithography and etching techniques to form a groove, and the insulating film 32 is formed in the groove.
  • the cell structure of FIG. 5A can be created by proceeding in the same manner as in the processes of FIGS. 4E to 4I.
  • Fig. 5B shows a cross-sectional view and a plan view during the manufacturing process.
  • a groove is formed in a portion of the gate conductor layer 22 by lithography and etching techniques commonly used between the gate conductor layers 22-1 and 22-2, and the insulating layer 32 is formed in the groove.
  • the process proceeds directly to step 4E, and the trench is filled at the same time as the insulating layer 6 is formed.
  • FIG. 5A shows an example in which the gate conductor layer 22 is divided into two by the insulating layer 32, the division location can be set arbitrarily, and a desired number of memory cells can be formed in the same gate conductor layer. can be placed.
  • any insulating film used in a normal MOS process can be used for the insulating film 32, such as a SiO2 film, a SiON film, an HfSiON film, or a laminated film of SiO2/SiN.
  • Embodiments of the invention have the following features.
  • feature 1 As in the first embodiment, voltages are applied to the source line SL, the word line WL, and the bit line BL, and independent voltages are applied to the two plate lines PL-1 and PL-2 to operate the dynamic flash memory. can be done.
  • the gate conductor layer 22-1 connected to PL1 in which the memory cell is placed and the gate conductor layer 22-2 connected to PL2 are electrically separated, and voltages are set independently. be able to. Therefore, by changing the voltage applied to the PL electrode in contact with the memory from which data information is read and written and the voltage applied to the other PL electrodes, it is possible to further reduce the disturb defect described in the first embodiment. can.
  • feature 2 In the dynamic flash memory according to the second embodiment of the present invention, each PL electrode can be divided and operated, so that power consumption can be reduced. Furthermore, it is also possible to reuse the power generated during charging and discharging in the integrated circuit.
  • FIG. 6 A dynamic flash memory according to a third embodiment of the present invention will be described with reference to FIG.
  • components identical or similar to those in FIG. 1 are denoted by the same reference numerals.
  • the bottom of the n layer 3 in FIG. 1 is located deeper than the gate insulating layer 2, and the n layer 3 is shared by a plurality of cells. Other than that, it is the same as FIG. In this case, gate insulating layer 2 may or may not be in contact with p layer 1 .
  • the dynamic flash memory can operate by applying voltages to the source line SL, the plate line PL, the word line WL, and the bit line BL, as in the first embodiment.
  • n layer 3 is shared by a plurality of cells as shown in FIG.
  • Multiple memory operations can also be operated simultaneously by connecting and applying voltages.
  • the dynamic flash memory can operate by applying voltages to the source line SL, plate line PL, word line WL, and bit line BL. It is possible to widen the operation margin for writing "1" and erasing "0" of information data and perform high-speed memory operation.
  • first semiconductor layer 2 first insulating layers 3, 3a, 3b, 3c first impurity layers 4, 4a, 4b, 4c, 4d second semiconductor layer 5, first gate insulating layer 6.
  • Substrate 22, 22-1, 22-2 First gate conductor layer 25 Insulating layer (collective name for 2 and 5) SL source line PL PL1, PL2 plate lines WL, WL1, WL2 word line BL bit line 31 third insulating layer 32 fourth insulating layer 33a, 33b, 33c, 33d contact holes 35, 36 first wiring conductor layer 37c , 37d contact hole 39 second wiring conductor layer 41 insulating layers 42, 42a, 42b, 42c, 42d mask material

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Dram (AREA)
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PCT/JP2022/003747 WO2023148799A1 (ja) 2022-02-01 2022-02-01 半導体素子を用いたメモリ装置
US18/162,446 US20230247820A1 (en) 2022-02-01 2023-01-31 Semiconductor-element-including memory device
TW112103500A TWI846299B (zh) 2022-02-01 2023-02-01 使用半導體元件的記憶裝置

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