JP7705670B2 - 半導体素子を用いたメモリ装置 - Google Patents

半導体素子を用いたメモリ装置 Download PDF

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Publication number
JP7705670B2
JP7705670B2 JP2023522527A JP2023522527A JP7705670B2 JP 7705670 B2 JP7705670 B2 JP 7705670B2 JP 2023522527 A JP2023522527 A JP 2023522527A JP 2023522527 A JP2023522527 A JP 2023522527A JP 7705670 B2 JP7705670 B2 JP 7705670B2
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layer
semiconductor
conductor layer
impurity
gate
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Japanese (ja)
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JPWO2023148799A1 (https=
Inventor
正一 各務
康司 作井
望 原田
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Unisantis Electronics Singapore Pte Ltd
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Unisantis Electronics Singapore Pte Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Dram (AREA)
JP2023522527A 2022-02-01 2022-02-01 半導体素子を用いたメモリ装置 Active JP7705670B2 (ja)

Applications Claiming Priority (1)

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PCT/JP2022/003747 WO2023148799A1 (ja) 2022-02-01 2022-02-01 半導体素子を用いたメモリ装置

Publications (2)

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JPWO2023148799A1 JPWO2023148799A1 (https=) 2023-08-10
JP7705670B2 true JP7705670B2 (ja) 2025-07-10

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JP2023522527A Active JP7705670B2 (ja) 2022-02-01 2022-02-01 半導体素子を用いたメモリ装置

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US (1) US20230247820A1 (https=)
JP (1) JP7705670B2 (https=)
TW (1) TWI846299B (https=)
WO (1) WO2023148799A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022269890A1 (ja) * 2021-06-25 2022-12-29 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置の製造方法
WO2023281728A1 (ja) * 2021-07-09 2023-01-12 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置
WO2024214180A1 (ja) * 2023-04-11 2024-10-17 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置
JP7762991B1 (ja) 2024-06-03 2025-10-31 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体素子を用いたメモリ装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003188279A (ja) 2001-12-14 2003-07-04 Toshiba Corp 半導体メモリ装置およびその製造方法
US20030190766A1 (en) 2002-04-08 2003-10-09 Micron Technology, Inc. Process for making a silicon-on-insulator ledge and structures achieved thereby
US20050280113A1 (en) 2004-06-21 2005-12-22 Kim Yil W Semiconductor device capable of threshold voltage adjustment by applying an external voltage
JP2008147514A (ja) 2006-12-12 2008-06-26 Renesas Technology Corp 半導体記憶装置
JP2010519770A (ja) 2007-02-26 2010-06-03 マイクロン テクノロジー， インク． パストランジスタと、垂直読み出し／書き込み有効化トランジスタを含む、キャパシタレスフローティングボディ揮発性メモリセル、およびその製造法とプログラミング法
US20130256774A1 (en) 2012-03-28 2013-10-03 Namho Jeon Semiconductor memory devices
US20200135863A1 (en) 2015-04-29 2020-04-30 Zeno Semiconductor, Inc. MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5340754A (en) * 1992-09-02 1994-08-23 Motorla, Inc. Method for forming a transistor having a dynamic connection between a substrate and a channel region
JPH09321296A (ja) * 1996-05-27 1997-12-12 Toyota Central Res & Dev Lab Inc 半導体装置およびその製造方法
US6621725B2 (en) * 2000-08-17 2003-09-16 Kabushiki Kaisha Toshiba Semiconductor memory device with floating storage bulk region and method of manufacturing the same
KR100945511B1 (ko) * 2008-04-10 2010-03-09 주식회사 하이닉스반도체 반도체 소자 및 그의 제조방법
JP7109928B2 (ja) * 2018-01-31 2022-08-01 キオクシア株式会社 トランジスタ及び半導体記憶装置並びにトランジスタの製造方法
KR102059896B1 (ko) * 2018-10-24 2019-12-27 가천대학교 산학협력단 양자우물 구조를 갖는 1t 디램 셀 소자
TWI747465B (zh) * 2020-08-28 2021-11-21 旺宏電子股份有限公司 記憶體結構

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003188279A (ja) 2001-12-14 2003-07-04 Toshiba Corp 半導体メモリ装置およびその製造方法
US20030190766A1 (en) 2002-04-08 2003-10-09 Micron Technology, Inc. Process for making a silicon-on-insulator ledge and structures achieved thereby
US20050280113A1 (en) 2004-06-21 2005-12-22 Kim Yil W Semiconductor device capable of threshold voltage adjustment by applying an external voltage
JP2008147514A (ja) 2006-12-12 2008-06-26 Renesas Technology Corp 半導体記憶装置
JP2010519770A (ja) 2007-02-26 2010-06-03 マイクロン テクノロジー， インク． パストランジスタと、垂直読み出し／書き込み有効化トランジスタを含む、キャパシタレスフローティングボディ揮発性メモリセル、およびその製造法とプログラミング法
US20130256774A1 (en) 2012-03-28 2013-10-03 Namho Jeon Semiconductor memory devices
US20200135863A1 (en) 2015-04-29 2020-04-30 Zeno Semiconductor, Inc. MOSFET and Memory Cell Having Improved Drain Current Through Back Bias Application

Also Published As

Publication number Publication date
WO2023148799A1 (ja) 2023-08-10
TW202341424A (zh) 2023-10-16
US20230247820A1 (en) 2023-08-03
JPWO2023148799A1 (https=) 2023-08-10
TWI846299B (zh) 2024-06-21

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