WO2023145592A1 - 配線基板 - Google Patents

配線基板 Download PDF

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Publication number
WO2023145592A1
WO2023145592A1 PCT/JP2023/001462 JP2023001462W WO2023145592A1 WO 2023145592 A1 WO2023145592 A1 WO 2023145592A1 JP 2023001462 W JP2023001462 W JP 2023001462W WO 2023145592 A1 WO2023145592 A1 WO 2023145592A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
metal
wiring board
metal portion
board according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/001462
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
一起 早野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to CN202380019237.1A priority Critical patent/CN118613908A/zh
Priority to KR1020247025171A priority patent/KR20240131389A/ko
Priority to EP23746805.3A priority patent/EP4475178A1/en
Priority to JP2023576844A priority patent/JPWO2023145592A1/ja
Publication of WO2023145592A1 publication Critical patent/WO2023145592A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/244—Finish plating of conductors, especially of copper conductors, e.g. for pads or lands
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present disclosure relates to wiring boards.
  • connection terminals for electrically connecting to a semiconductor element or the like.
  • the pads are formed of a plurality of metal layers, as shown in US Pat. In such a pad, the contact surface with the insulating layer is easily peeled off, and the connection reliability may be poor.
  • a wiring board includes an insulating layer having a first surface and a second surface located opposite to the first surface, and pads located on the first surface.
  • the first surface includes a first area including a plane along the second surface, and a second area located around the first area and including an inclined surface inclined from the first area toward the second surface. have.
  • the surface of the second region has a plurality of recesses and protrusions, and the arithmetic mean roughness of the surface of the second region is greater than the arithmetic mean roughness of the surface of the first region.
  • a central portion of the pad is located in the first region, and a peripheral portion of the pad is located in the second region.
  • FIG. 4 is an explanatory diagram for explaining an example of pads included in the wiring board according to the embodiment of the present disclosure
  • 2 is an electron micrograph showing an example of a region X shown in FIG. 1
  • FIG. 4 is an explanatory diagram for explaining an example of a process of forming pads included in the wiring board according to the embodiment of the present disclosure
  • FIG. 4 is an explanatory diagram for explaining another example of pads included in the wiring board according to the embodiment of the present disclosure
  • the pads formed of multiple metal layers can easily come off at the contact surface with the insulating layer, resulting in poor connection reliability. Therefore, there is a demand for a wiring board that reduces the peeling between the insulating layer and the pad and has excellent connection reliability.
  • the wiring board according to the present disclosure has the second region including the inclined surface inclined from the first region toward the second surface, and the surface of the second region has a plurality of concave portions and convex portions. and the arithmetic mean roughness of the surface of the second region is greater than the arithmetic mean roughness of the surface of the first region.
  • FIG. 1 is an explanatory diagram for explaining an example of pads included in a wiring board according to an embodiment of the present disclosure.
  • FIG. 2 is an electron micrograph showing an example of the region X shown in FIG.
  • the wiring board according to one embodiment has a structure in which at least one insulating layer 1 and at least one conductive layer 3 are alternately laminated.
  • FIG. 1 shows the vicinity of a pad 2 formed on an insulating layer 1 located on the outermost layer of a wiring board.
  • the insulating layer 1 is specifically a core insulating layer and a build-up insulating layer.
  • the insulating layer 1 is made of resin such as epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether resin, and liquid crystal polymer. These resins may be used alone or in combination of two or more. Insulating particles may be dispersed in the insulating layer 1 as shown in FIG. Insulating particles are shown as circles in FIG.
  • the insulating particles are not limited, and examples thereof include inorganic insulating fillers such as silica, alumina, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide. When there are two or more insulating layers 1, they may be made of the same resin or different resins.
  • the core insulating layer 1 When the insulating layer 1 is a core insulating layer, the core insulating layer has a thickness of, for example, 0.04 mm or more and 3.0 mm or less.
  • the core insulating layer has through-hole conductors for electrically connecting the conductor layers 3 located on the upper and lower surfaces of the core insulating layer.
  • the through-hole conductors are located in through-holes penetrating through the upper and lower surfaces of the core insulating layer.
  • the through-hole conductors are made of conductors plated with metal such as copper plating. Through-hole conductors are connected to conductor layers 3 on both sides of the core insulating layer.
  • the through-hole conductor may be formed only on the inner wall surface of the through-hole, or may be filled in the through-hole.
  • the build-up insulating layer When the insulating layer 1 is a build-up insulating layer, the build-up insulating layer has a thickness of, for example, 2 ⁇ m or more and 200 ⁇ m or less.
  • the build-up insulating layers may be made of the same resin or different resins.
  • the buildup insulating layer has via-hole conductors 5 for electrically connecting the conductor layers 3 positioned above and below via the buildup insulating layer.
  • the via-hole conductor 5 is obtained by depositing, for example, copper plating on the via-hole penetrating the upper and lower surfaces of the build-up insulating layer.
  • the via-hole conductor 5 may be positioned in a state of filling the inside of the via-hole as shown in FIG. may be filled.
  • the conductor layer 3 is located on the main surface of the insulating layer 1, that is, on the main surface of the core insulating layer and the main surface of the build-up insulating layer.
  • the conductor layer 3 is made of copper such as copper foil or copper plating.
  • the thickness of the conductor layer 3 is not particularly limited, and is, for example, 2 ⁇ m or more and 70 ⁇ m or less.
  • pads 2 are located on the insulating layer 1 located on the outermost layer of the wiring substrate. Specifically, the pads 2 are positioned on the first surface 1a of the main surfaces (the first surface 1a and the second surface 1b located on the opposite side of the first surface 1a) of the insulating layer 1 located on the outermost layer. are doing. As shown in FIG. 1, pads 2 are connected to conductor layers 3 through via-hole conductors 5 .
  • the first surface 1a has a first region 11 and a second region 12.
  • the first area 11 is an area including a plane along the second surface 1b.
  • the second area 12 is located around the first area 11 and includes an inclined surface 12a inclined from the first area 11 toward the second surface 1b.
  • the surface of the second region 12 has a plurality of concave portions and convex portions, and the arithmetic mean roughness of the surface of the second region 12 is larger than the arithmetic mean roughness of the surface of the first region 11 .
  • a gap (height difference) between the bottom of the concave portion and the top of the convex portion is about 0.2 ⁇ m or more and 0.4 ⁇ m or less.
  • the arithmetic average roughness of the surface of the second region 12 may be, for example, 0.05 ⁇ m or more and 0.5 ⁇ m or less in terms of further reducing peeling between the insulating layer 1 and the pad 2 . Furthermore, the arithmetic mean roughness of the surface of the second region 12 may be greater than the arithmetic mean roughness of the surface of the first region 11 by approximately 0.03 ⁇ m or more and 0.4 ⁇ m or less.
  • the width of the second region 12 is not limited, and may be, for example, 1 ⁇ m or more and 5 ⁇ m or less. When the width of the second region 12 is 3.5 ⁇ m or more and 4.5 ⁇ m or less, it is particularly advantageous in terms of ensuring close contact between the pad 2 and the insulating layer 1 .
  • the central portion of the pad 2 is positioned in the first region 11 and the peripheral portion of the pad 2 is positioned in the second region 12 . That is, the peripheral portion of the pad 2 which is easily peeled off is located in the second region 12 having a relatively high arithmetic mean roughness. As a result, as shown in FIG. 2, the anchor effect is more likely to be exhibited at the peripheral edge of the pad 2, and peeling between the insulating layer 1 and the pad 2 can be reduced as described above.
  • the structure of the pad 2 is not limited, and may have, for example, a three-layer structure as shown in FIG. That is, as shown in FIG. 1, the pad 2 includes a first metal portion 21, a second metal portion 22 and a third metal portion .
  • the first metal part 21 is made of a first metal and located in the first region 11 .
  • the first metal portion 21 is located at the center of the pad 2 .
  • Examples of the first metal include copper plating and copper foil.
  • the thickness (height from the first region 11) of the first metal part 21 is not limited, and may be, for example, 2 ⁇ m or more and 70 ⁇ m or less.
  • the via-hole conductor 5 is located in the first region 11 and connected to the first metal portion 21, as shown in FIG.
  • the second metal portion 22 is made of a second metal and positioned so as to cover the first metal portion 21 . At least part of the second metal portion 22 is located in the second region 12 . In other words, at least part of the second metal part 22 is in contact with the insulating layer 1 in the second region 12 .
  • the second metal is preferably a metal that is less likely to form a compound than the first metal due to heat when solder is welded to the pad 2, for example. Examples of the second metal include nickel.
  • the thickness of the second metal portion 22 is not limited as long as it can cover the first metal portion 21, and may be, for example, 1 ⁇ m or more and 6 ⁇ m or less.
  • a portion of the second metal portion 22 may be positioned within the recess of the second region 12 as shown in FIG. With such a configuration, a stronger anchor effect is exhibited, and peeling between the insulating layer 1 and the pad 2 can be further reduced.
  • the third metal portion 23 is made of a third metal and positioned so as to cover the second metal portion 22 .
  • the third metal portion 23 is located in the second region 12 .
  • the third metal portion 23 is in contact with the insulating layer 1 in the second region 12 .
  • the third metal is preferably a metal with better solder wettability than the second metal.
  • the improved solder wettability improves the connection reliability between the solder and the electrodes of the semiconductor element when the semiconductor element is mounted.
  • Examples of the third metal include gold and palladium.
  • the thickness of the third metal portion 23 is not limited as long as it can cover the second metal portion 22, and may be, for example, 0.05 ⁇ m or more and 0.15 ⁇ m or less.
  • the first metal forming the first metal portion 21 contains copper
  • the second metal forming the second metal portion 22 contains nickel
  • the third metal forming the third metal portion 23 preferably contains gold.
  • the underlying metal layer 4 may be positioned at least between the first metal portion 21 and the insulating layer 1 .
  • the underlying metal layer 4 include nickel, chromium, and an alloy of nickel and chromium (nichrome).
  • transition metals belonging to Groups 4, 5, or 6 of the periodic table such as titanium, chromium, nickel, tantalum, molybdenum, tungsten, and palladium, may be formed by sputtering and vapor deposition methods other than sputtering. do not have.
  • the underlying metal layer 4 preferably contains nickel and chromium, such as nichrome, among these metals.
  • a palladium layer (not shown) may be positioned between the second metal portion 22 and the third metal portion 23 .
  • the palladium layer When the palladium layer is positioned between the second metal portion 22 and the third metal portion 23, the intermetallic compound generated between the second metal portion 22 and the third metal portion 23 due to heat is reduced. can be done.
  • the thickness of the palladium layer is not limited, and may be, for example, 0.02 ⁇ m or more and 0.10 ⁇ m or less.
  • the wiring board according to one embodiment has the second region 12 including the inclined surface 12a inclined from the first region 11 toward the second surface 1b, and the surface of the second region 12 has a plurality of concave portions. and convex portions, and the arithmetic mean roughness of the surface of the second region 12 is larger than the arithmetic mean roughness of the surface of the first region 11 .
  • the method of forming the pads 2 is not limited, and the pads 2 are formed, for example, by the steps shown in FIG.
  • FIG. 3 is an explanatory diagram for explaining an example of the process of forming the pads 2 included in the wiring board according to the embodiment of the present disclosure.
  • a via hole having an opening on the side of the first surface 1a is formed in the insulating layer 1 located on the uppermost layer of the wiring board.
  • the via holes are formed by laser processing such as CO 2 laser, UV-YAG laser, excimer laser, and the like.
  • the conductor layer 3 is exposed on the bottom surface of the via hole (on the side of the second surface 1b).
  • a base metal layer 4 is formed on the first surface 1a of the insulating layer 1, the inner peripheral surface and the bottom surface of the via hole.
  • the underlying metal layer 4 is as described above, and detailed description thereof will be omitted. An even thinner copper layer may be formed on the surface of the underlying metal layer 4 as part of the underlying metal layer 4 .
  • a dry film resist 6 is formed near the opening of the via hole so as to surround the opening.
  • Dry film resist 6 is made of, for example, a polymer, an acrylic compound, or the like.
  • the thickness (height) of the dry film resist 6 may be appropriately set according to the desired thickness (height) of the pad 2 (first metal portion 21).
  • the thickness (height) of the first metal portion 21 is as described above, and detailed description thereof will be omitted.
  • metal is deposited from the via hole to the portion surrounded by the dry film resist 6 .
  • Copper etc. are mentioned as a metal as mentioned above.
  • the metal deposited inside the via hole corresponds to the via hole conductor 5
  • the metal (first metal) deposited outside the via hole corresponds to the first metal portion 21 .
  • the dry film resist 6 is removed.
  • a method for removing the dry film resist 6 is not limited.
  • the dry film resist 6 is removed, for example, by a resist remover such as sodium hydroxide solution.
  • the underlying metal layer 4 (including the thin copper layer) exposed on the first surface 1a of the insulating layer 1 is removed.
  • a method for removing these layers is not limited, and examples thereof include an etching treatment such as flash etching.
  • a portion of the deposited outer peripheral surface of the first metal portion 21 is removed by etching.
  • an etchant that dissolves the first metal portion 21 but does not dissolve the base metal layer 4 is used.
  • wet blasting, sandblasting, plasma processing, or the like is applied to the exposed portion of the underlying metal layer 4 to remove the exposed underlying metal layer 4 .
  • the insulating layer 1 in the vicinity of the underlying metal layer 4 is partially removed together with the exposed underlying metal layer 4, thereby forming the inclined surface 12a.
  • the surface of the second region 12 including the inclined surface 12a has a plurality of concave portions and convex portions, and the arithmetic mean roughness of the surface of the second region 12 is equal to the arithmetic mean roughness of the surface of the first region 11. becomes larger than
  • the arithmetic mean roughness of the surface of the second region 12 and the width of the second region 12 are as described above, and detailed description thereof will be omitted.
  • an etching process is performed to remove the oxide film (copper oxide when the first metal portion 21 is made of copper) formed on the outer peripheral surface of the first metal portion 21 .
  • An etchant that dissolves the first metal part 21 but does not dissolve the base metal layer 4 is used for the etching process. A portion of the underlying metal layer 4 is exposed around the first metal portion 21 by this etching process.
  • the second metal portion 22 and the third metal portion 23 are formed.
  • the second metal portion 22 is formed by depositing the second metal by plating so as to cover the first metal portion 21 .
  • the second metal include nickel, as described above.
  • a portion of the second metal is also deposited in the recesses of the second region 12 .
  • the thickness of the second metal portion 22 is as described above, and detailed description thereof will be omitted.
  • the third metal portion 23 is formed by depositing the third metal by plating so as to cover the second metal portion 22 .
  • the third metal includes gold and the like as described above.
  • the thickness of the third metal portion 23 is as described above, and detailed description thereof will be omitted. If necessary, a palladium layer may be formed so as to cover the second metal portion 22 before forming the third metal portion 23 .
  • the pads 2 are formed in the wiring board according to the embodiment by the procedure described above. Such a pad 2 is particularly employed, for example, as a pad in an HBM (High Bandwidth Memory) connection area.
  • HBM High Bandwidth Memory
  • the pads 2 are not limited to those connected to the via-hole conductors 5 as shown in FIG.
  • the pad 2 may be in a form that is not connected to the via-hole conductor 5, as shown in FIG. 4, for example.
  • FIG. 4 is an explanatory diagram for explaining another example of the pad 2, and the same members as those shown in FIG. 1 are given the same reference numerals.
  • Reference Signs List 1 insulating layer 1a first surface 1b second surface 11 first region 12 second region 12a inclined surface 2 pad 21 first metal portion 22 second metal portion 23 third metal portion 3 conductor layer 4 base metal layer 5 via hole conductor 6 dry film resist

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
PCT/JP2023/001462 2022-01-31 2023-01-19 配線基板 Ceased WO2023145592A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202380019237.1A CN118613908A (zh) 2022-01-31 2023-01-19 布线基板
KR1020247025171A KR20240131389A (ko) 2022-01-31 2023-01-19 배선 기판
EP23746805.3A EP4475178A1 (en) 2022-01-31 2023-01-19 Wiring board
JP2023576844A JPWO2023145592A1 (https=) 2022-01-31 2023-01-19

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-012537 2022-01-31
JP2022012537 2022-01-31

Publications (1)

Publication Number Publication Date
WO2023145592A1 true WO2023145592A1 (ja) 2023-08-03

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ID=87471784

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Application Number Title Priority Date Filing Date
PCT/JP2023/001462 Ceased WO2023145592A1 (ja) 2022-01-31 2023-01-19 配線基板

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EP (1) EP4475178A1 (https=)
JP (1) JPWO2023145592A1 (https=)
KR (1) KR20240131389A (https=)
CN (1) CN118613908A (https=)
TW (1) TWI849704B (https=)
WO (1) WO2023145592A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015216344A (ja) 2014-04-21 2015-12-03 新光電気工業株式会社 配線基板及びその製造方法
JP2017098306A (ja) * 2015-11-18 2017-06-01 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
WO2020004271A1 (ja) * 2018-06-26 2020-01-02 京セラ株式会社 配線基板
WO2020188923A1 (ja) * 2019-03-15 2020-09-24 京セラ株式会社 配線基板およびその製造方法
WO2021065601A1 (ja) * 2019-09-30 2021-04-08 京セラ株式会社 配線基板

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013093405A (ja) * 2011-10-25 2013-05-16 Ngk Spark Plug Co Ltd 配線基板及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015216344A (ja) 2014-04-21 2015-12-03 新光電気工業株式会社 配線基板及びその製造方法
JP2017098306A (ja) * 2015-11-18 2017-06-01 新光電気工業株式会社 配線基板、半導体装置及び配線基板の製造方法
WO2020004271A1 (ja) * 2018-06-26 2020-01-02 京セラ株式会社 配線基板
WO2020188923A1 (ja) * 2019-03-15 2020-09-24 京セラ株式会社 配線基板およびその製造方法
WO2021065601A1 (ja) * 2019-09-30 2021-04-08 京セラ株式会社 配線基板

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Publication number Publication date
EP4475178A1 (en) 2024-12-11
JPWO2023145592A1 (https=) 2023-08-03
KR20240131389A (ko) 2024-08-30
TWI849704B (zh) 2024-07-21
TW202341824A (zh) 2023-10-16
CN118613908A (zh) 2024-09-06

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