WO2023123544A1 - 像素电路及显示面板 - Google Patents

像素电路及显示面板 Download PDF

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Publication number
WO2023123544A1
WO2023123544A1 PCT/CN2022/070922 CN2022070922W WO2023123544A1 WO 2023123544 A1 WO2023123544 A1 WO 2023123544A1 CN 2022070922 W CN2022070922 W CN 2022070922W WO 2023123544 A1 WO2023123544 A1 WO 2023123544A1
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WO
WIPO (PCT)
Prior art keywords
module
transistor
control
driving
terminal
Prior art date
Application number
PCT/CN2022/070922
Other languages
English (en)
French (fr)
Inventor
刘林峰
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Application filed by 惠州华星光电显示有限公司, Tcl华星光电技术有限公司 filed Critical 惠州华星光电显示有限公司
Priority to US17/597,948 priority Critical patent/US11996028B2/en
Publication of WO2023123544A1 publication Critical patent/WO2023123544A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods
    • G09G3/2081—Display of intermediate tones by a combination of two or more gradation control methods with combination of amplitude modulation and time modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to the field of display technology, in particular to a pixel circuit and a display panel.
  • the driving method of the pixel circuit can be divided into pulse amplitude modulation (PAM, Pulse Amplitude Modulation) driving mode, pulse width modulation (PWM, Pulse Width Modulation) driving mode and hybrid driving mode, among which, the hybrid driving mode is a combination of pulse amplitude modulation driving mode and pulse width modulation driving mode, which can solve low gray scale display Problems in bad taste, such as brightness dispersion, color point drift, etc.
  • Pixel circuits can be divided into internal compensation pixel circuits and external compensation pixel circuits according to different compensation methods. Among them, the external compensation pixel circuit needs to rely on external circuits to complete the compensation function. Compared with the internal compensation pixel circuit, the external compensation pixel circuit The production cost of the circuit is relatively high.
  • the present application provides a pixel circuit and a display panel to realize the technical problems of internal compensation and hybrid driving of the pixel circuit.
  • the present application provides a pixel circuit, which includes a driving module, a pulse-width modulation module, a pulse-width modulation module, an internal compensation module, and a potential holding module.
  • the output terminal of the pulse-width modulation module is electrically connected to the control terminal of the driving module. Connection; the output end of the pulse width modulation module is electrically connected to the control end of the drive module; the output end of the internal compensation module is electrically connected to the first end of the drive module; the first end of the potential holding module is connected to the first end of the drive module electrical connection.
  • the pixel circuit further includes a light emitting control module, a storage module, and a light emitting device.
  • the first end of the light emitting control module is electrically connected to the second end of the potential holding module and connected to the positive signal of the power supply.
  • the second terminal is electrically connected to the second terminal of the driving module, and the control terminal of the lighting control module is connected to the first control signal;
  • the first terminal of the storage module is electrically connected to the control terminal of the driving module, and the second terminal of the storage module is connected to the control terminal of the driving module.
  • the first end of the driving module is electrically connected; the anode of the light-emitting device is electrically connected with the first end of the driving module, and the cathode of the light-emitting device is connected to the negative signal of the power supply.
  • the drive module includes a drive transistor, the gate of the drive transistor is electrically connected to the output terminal of the pulse width modulation module, the output terminal of the pulse width modulation module, and the first terminal of the storage module, and the source of the drive transistor
  • One of the /drains is electrically connected to the output end of the internal compensation module and the first end of the potential holding module, and the other of the source/drain of the driving transistor is electrically connected to the second end of the light-emitting control module; wherein , the control terminal of the driving module is the gate of the driving transistor, the first terminal of the driving module is one of the source/drain of the driving transistor, and the second terminal of the driving module is the other of the source/drain of the driving transistor one.
  • the pulse amplitude modulation module includes a pulse amplitude control transistor, one of the source/drain of the pulse amplitude control transistor is connected to the pulse amplitude data signal, and the gate of the pulse amplitude control transistor is connected to the second control signal , the other of the source/drain of the pulse width control transistor is electrically connected to the gate of the driving transistor; wherein, the output terminal of the pulse width modulation module is the other of the source/drain of the pulse width control transistor.
  • the pulse width modulation module includes a pulse width control transistor, one of the source/drain of the pulse width control transistor is connected to the pulse width data signal, and the gate of the pulse width control transistor is connected to the third control signal , the other of the source/drain of the pulse width control transistor is electrically connected to the gate of the driving transistor; wherein, the output terminal of the pulse width modulation module is the other of the source/drain of the pulse width control transistor.
  • the internal compensation module includes a compensation transistor, one of the source/drain of the compensation transistor is connected to the reset signal, the gate of the compensation transistor is connected to the fourth control signal, and the source/drain of the compensation transistor The other one is electrically connected to one of the source/drain of the driving transistor; wherein, the output terminal of the internal compensation module is the other of the source/drain of the compensation transistor.
  • the potential holding module includes a first capacitor, the first end of the first capacitor is electrically connected to one of the source/drain of the driving transistor, and the second end of the first capacitor is connected to the light emitting control module. The first end is electrically connected and connected to the positive signal of the power supply.
  • one frame time of the pixel circuit includes a write-in phase and a light-emitting phase.
  • the internal compensation module first resets the potential of the first end of the driving module, and then the pulse amplitude modulation module writes the pulse amplitude
  • the data signal is sent to the control terminal of the driving module; in the lighting stage, the pulse width modulation module writes the pulse width data signal to the control terminal of the driving module to intermittently turn off the driving module.
  • the internal compensation module resets the potential of the first end of the driving module when the light emission control module is in the on state, and the pulse amplitude modulation module is in the off state.
  • the pulse width modulation module outputs a pulse width data signal with at least one pulse to the control terminal of the driving module, so as to control the light emitting time of the light emitting device in low gray scale display.
  • the present application provides a display panel, which includes the pixel circuit in at least one embodiment above.
  • the pixel circuit and display panel provided by this application can control the high gray scale display in the pulse width modulation mode through the pulse width modulation module, and the pulse width modulation module can control the low gray scale display in the pulse width modulation mode, thus realizing the hybrid driving mode.
  • the internal compensation module can internally compensate the first end of the drive module to reduce the cost of compensation, realize the internal compensation and hybrid driving of the pixel circuit, and then achieve high display quality at a lower cost;
  • the holding module can maintain the potential of the first terminal of the driving module after compensation, and can stabilize the voltage difference between the control terminal of the driving module and the first terminal of the driving module, thereby improving the control accuracy of the display time.
  • FIG. 1 is a schematic diagram of a first structure of a pixel circuit provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a second structure of a pixel circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a third structure of a pixel circuit provided by an embodiment of the present application.
  • FIG. 4 is a timing schematic diagram of the pixel circuit shown in FIG. 3 .
  • the pixel circuit includes a driving transistor T1, a switching transistor T2, a switching transistor T3, a switching transistor T4, a storage capacitor Cst, and a light emitting device D1.
  • the source of the driving transistor T1 One of the /drains is connected to the positive power signal VDD, the other of the source/drain of the drive transistor T1 is electrically connected to the anode of the light emitting device D1, and the cathode of the light emitting device D1 is connected to the negative power signal VSS;
  • the switching transistor One of the source/drain of T4 is connected to the reference signal Vref or the potential of the other of the source/drain of the output drive transistor T1, the gate of the switching transistor T4 is connected to the control signal SCAN2, and the source of the switching transistor T4
  • the other of the pole/drain is electrically connected to the other of the source/drain of the drive transistor T1; one of the source/drain of the switch transistor T2 is connected to the pulse
  • the switching transistor T3 can control the pulse width data signal DPWM to be written into the gate of the driving transistor T1, so as to control the low grayscale display of the pixel circuit.
  • the switching transistor T2 can control the pulse amplitude data signal DPAM to be written into the gate of the driving transistor T1 , so as to control the high gray scale display of the pixel circuit.
  • the switching transistor T4 can control the reference signal Vref to be written into the other of the source/drain of the driving transistor T1, so as to initialize the potential of the other of the source/drain of the driving transistor T1 and/or the anode potential of the light-emitting device D1; the switching transistor T4 can also output the potential of the other of the source/drain of the driving transistor T1 to an external compensation system, so that the external compensation system can be based on the source/drain of the driving transistor T1
  • the potential of the other of the drains compensates for the pulse width data signal DPAM and/or the pulse width data signal DPWM.
  • the pixel circuit in this embodiment needs to realize the compensation for the pixel circuit through an external compensation system, however, the configuration of the external compensation system obviously needs to increase the cost.
  • this embodiment provides another pixel circuit, as shown in Figure 2, the pixel circuit includes a drive transistor T1, a switch transistor T2, a switch transistor T4, a switch transistor T5, a The capacitor Cst, the light-emitting device D1 and the first capacitor C1, one of the source/drain of the switching transistor T5 is connected to the positive power signal VDD, the gate of the switching transistor T5 is connected to the control signal SCAN3, and the source/drain of the switching transistor T5 is connected to the positive power signal VDD.
  • the other of the drains is electrically connected to one of the source/drain of the driving transistor T1, the other of the source/drain of the driving transistor T1 is electrically connected to the anode of the light emitting device D1, and the light emitting device D1
  • the cathode is connected to the negative signal VSS of the power supply; one of the source/drain of the switching transistor T4 is connected to the reset signal RESET, the gate of the switching transistor T4 is connected to the control signal SCAN2, and the other of the source/drain of the switching transistor T4
  • One is electrically connected to the other of the source/drain of the driving transistor T1; one of the source/drain of the switching transistor T2 is connected to the pulse amplitude data signal DPAM, and the gate of the switching transistor T2 is connected to the control signal SCAN1 , the other of the source/drain of the switching transistor T2 is electrically connected to the gate of the driving transistor T1; one end of the storage capacitor Cst is electrically connected to the gate of the driving
  • the switching transistor T2 can control the data signal DPAM to be written into the gate of the driving transistor T1, so as to control the gray scale display of the pixel circuit.
  • the switching transistor T4 can control the reset signal RESET to be written into the other of the source/drain of the driving transistor T1, so as to initialize the potential of the other of the source/drain of the driving transistor T1 And/or the anode potential of the light emitting device D1.
  • the switching transistor T2 can control the data signal DPAM to be written into the gate of the driving transistor T1, which only The driving mode of pulse width modulation can be realized, but the driving mode of pulse width modulation cannot be realized, and the display quality of low gray scale cannot be controlled.
  • this embodiment provides another pixel circuit.
  • the output end of the pulse width modulation module 20 is electrically connected to the control end of the drive module 10;
  • the output end of the pulse width modulation module 30 is electrically connected to the control end of the drive module 10;
  • the output end of the internal compensation module 40 is electrically connected to the drive module 10
  • the first end of the potential holding module 50 is electrically connected to the first end of the driving module 10 .
  • the pixel circuit provided in this embodiment can control the high grayscale display in the pulse width modulation mode through the pulse width modulation module 20, and the pulse width modulation module 30 can control the low gray scale display in the pulse width modulation mode, thereby realizing the hybrid driving mode.
  • the internal compensation module 40 can internally compensate the first end of the driving module 10 to reduce the cost of compensation, realize the internal compensation and hybrid driving of the pixel circuit, and then achieve high display quality at a lower cost; and
  • the potential holding module 50 can maintain the potential of the first end of the driving module 10 after compensation, and can stabilize the voltage difference between the control end of the driving module 10 and the first end of the driving module 10, thereby improving the control of the display time precision.
  • the pixel circuit further includes a light emission control module 60, a storage module 70, and a light emitting device D1.
  • the first end of the light emission control module 60 is electrically connected to the second end of the potential holding module 50 and connected to the positive signal of the power supply.
  • the second terminal of the lighting control module 60 is electrically connected to the second terminal of the driving module 10
  • the control terminal of the lighting control module 60 is connected to the first control signal SCAN3
  • the first terminal of the storage module 70 is connected to the control terminal of the driving module 10 Terminals are electrically connected, the second end of the storage module 70 is electrically connected to the first end of the drive module 10
  • the anode of the light emitting device D1 is electrically connected to the first end of the drive module 10
  • the cathode of the light emitting device D1 is connected to the power supply negative Signal VSS.
  • the light emission control module 60 includes a light emission control transistor T5, one of the sources/drains of the light emission control transistor T5 is connected to the power supply positive signal VDD, and the other source/drain of the light emission control transistor T5 is One is electrically connected to the other of the source/drain of the driving transistor T1, and the gate of the light emission control transistor T5 is connected to the first control signal SCAN3.
  • the storage module 70 includes a storage capacitor Cst, one end of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1, and the other end of the storage capacitor Cst is connected to one of the source/drain of the driving transistor T1 electrical connection.
  • the light emitting device D1 may be one of mini LEDs, micro LEDs or organic light emitting diodes.
  • the driving module 10 includes a driving transistor T1, the gate of the driving transistor T1 is electrically connected to the output terminal of the pulse width modulation module 20, the output terminal of the pulse width modulation module 30 and the first terminal of the storage module 70.
  • One of the source/drain of the driving transistor T1 is electrically connected to the output terminal of the internal compensation module 40 and the first terminal of the potential holding module 50, and the other of the source/drain of the driving transistor T1 is connected to the light emission control
  • the second terminal of the module 60 is electrically connected; wherein, the control terminal of the driving module 10 is the gate of the driving transistor T1, the first terminal of the driving module 10 is one of the source/drain of the driving transistor T1, and the driving module 10 The second terminal of is the other of the source/drain of the driving transistor T1.
  • the pulse amplitude modulation module 20 includes a pulse amplitude control transistor T2, one of the source/drain of the pulse amplitude control transistor T2 is connected to the pulse amplitude data signal DPAM, and the gate of the pulse amplitude control transistor T2 is connected to input the second control signal SCAN1, the other of the source/drain of the pulse width control transistor T2 is electrically connected to the gate of the driving transistor T1; wherein, the output terminal of the pulse width modulation module 20 is the pulse width control transistor T2 The other of the source/drain.
  • the pulse width modulation module 30 includes a pulse width control transistor T3, one of the source/drain of the pulse width control transistor T3 is connected to the pulse width data signal DPWM, and the gate of the pulse width control transistor T3 is connected to The third control signal SCAN4 is input, and the other of the source/drain of the pulse width control transistor T3 is electrically connected to the gate of the driving transistor T1; wherein, the output terminal of the pulse width modulation module 30 is the pulse width control transistor T3 The other of the source/drain.
  • the internal compensation module 40 includes a compensation transistor T4, one of the source/drain of the compensation transistor T4 is connected to the reset signal RESET, the gate of the compensation transistor T4 is connected to the fourth control signal SCAN2, and the compensation transistor T4 The other of the source/drain of T4 is electrically connected to one of the source/drain of the driving transistor T1; wherein, the output terminal of the internal compensation module 40 is the other of the source/drain of the compensation transistor T4 one.
  • the potential holding module 50 includes a first capacitor C1, the first terminal of the first capacitor C1 is electrically connected to one of the source/drain of the driving transistor T1, and the second terminal of the first capacitor C1 It is electrically connected with the first end of the lighting control module 60 and connected to the positive power signal VDD.
  • the pulse width control transistor T3, the pulse width control transistor T2, the compensation transistor T4, and the light emission control transistor T5 are all N-channel thin film transistors, for example, N-channel metal oxide thin film transistors;
  • the driving transistor T1 can be a P-channel thin film transistor, for example, a P-channel low-temperature polysilicon thin film transistor. It can be understood that such a configuration can not only ensure the dynamic performance of the pixel circuit, but also ensure the low leakage of the pixel circuit.
  • a frame F1 may include the first sub-frame F11 and the second sub-frame F12 in time sequence, or may also include subsequent The third subframe F13 to the Mth subframe F1M, where M may be a positive integer greater than or equal to 3.
  • the first control signal SCAN3, the second control signal SCAN1, and the fourth control signal SCAN2 are all at high potential, and the pulse width control transistor T2, the compensation transistor T4, and the light emission control transistor T5 are all turned on, and reset
  • the signal RESET compensates the potential of one of the source/drain of the driving transistor T1 through the compensation transistor T4, and maintains the compensated potential of one of the source/drain of the driving transistor T1 through the first capacitor C1 .
  • the first control signal SCAN3 is at a low potential, and the luminescence control transistor T5 is turned off; the second control signal SCAN1 is still at a high potential, and the pulse width control transistor T2 remains on, and a pulse of the pulse width data signal DPAM is written through the pulse width control transistor T2 into the gate of drive transistor T1. That is to say, the first sub-frame F11 is used for compensation and high grayscale display of driving pixel circuits through pulse amplitude modulation.
  • both the second control signal SCAN1 and the fourth control signal SCAN2 are at low potential, the pulse width control transistor T2 and the compensation transistor T4 are both turned off; the first control signal SCAN3 is at high potential, and the light emission control transistor T5 keeps Open; when the third control signal SCAN4 is at a high potential, the opened pulse width control transistor T3 outputs a pulse width data signal DPWM at a high potential to the gate of the drive transistor T1, causing the drive transistor T1 to be turned off to control low gray scale display time, thereby improving the display quality of low grayscale.
  • the pulse width data signal DPWM may have at least one pulse, so as to control the display quality of the low grayscale.
  • one frame time of the pixel circuit may include a write-in phase, that is, the first sub-frame F11 and a light-emitting phase, that is, the second sub-frame F12 or at least one of the second sub-frame F12 to the Mth sub-frame F1M.
  • the internal compensation module 40 first resets the potential of the first terminal of the driving module 10, and then the pulse width modulation module 20 writes the pulse width data signal DPAM to the control terminal of the driving module 10; in the light emitting phase, the pulse width modulation module 30 Write the pulse width data signal DPWM to the control terminal of the driving module 10 to intermittently turn off the driving module 10 .
  • the internal compensation module 40 resets the potential of the first end of the driving module 10 when the light emission control module 60 is in the on state, and the pulse amplitude modulation Module 20 outputs pulse amplitude data signal DPAM with pulse to the control end of drive module 10, and the reset time of the first end of drive module 10 is earlier than the pulse start time of pulse amplitude data signal DPAM in a frame time;
  • the pulse width modulation module 30 outputs a pulse width data signal DPWM with at least one pulse to the control terminal of the driving module 10 to control the light emitting device D1 to display in low grayscale luminous time in .
  • this embodiment provides a display panel, which includes the pixel circuit in at least one embodiment above.
  • the high gray scale display can be controlled by the pulse width modulation module 20, and the low gray scale display can be controlled by the pulse width modulation module 30, thereby realizing the hybrid driving mode.
  • the internal compensation module 40 can internally compensate the first end of the driving module 10 to reduce the cost of compensation, realize the internal compensation and hybrid driving of the pixel circuit, and then achieve high display quality at a lower cost; and
  • the potential holding module 50 can maintain the potential of the first end of the driving module 10 after compensation, and can stabilize the voltage difference between the control end of the driving module 10 and the first end of the driving module 10, thereby improving the control of the display time precision.

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Abstract

一种像素电路及显示面板，像素电路包括驱动模块(10)、脉幅调制模块(20)、脉宽调制模块(30)、内部补偿模块(40)以及电位保持模块(50)，通过脉幅调制模块(20)以脉幅调制方式控制高灰阶显示，脉宽调制模块(30)以脉宽调制方式控制低灰阶显示，内部补偿模块(40)对驱动模块(10)的第一端进行内部补偿，实现了像素电路的内部补偿与混合驱动。

Description

像素电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素电路及显示面板。
 背景技术
像素电路的驱动方式可以分为脉幅调制（PAM，Pulse Amplitude Modulation）驱动方式、脉宽调制（PWM，Pulse Width Modulation）驱动方式以及混合驱动方式，其中，混合驱动方式为脉幅调制驱动方式与脉宽调制驱动方式的结合，其可以解决低灰阶显示品味不佳的问题，例如，亮度离散、色点漂移等等。像素电路按照补偿方式的不同可以分为内部补偿型像素电路和外部补偿型像素电路，其中，外部补偿型像素电路需要依靠外部电路完成补偿功能，相比于内部补偿型像素电路，外部补偿型像素电路的制作成本较高。
因此，有必要提出一种兼有内部补偿与混合驱动方式的像素电路，以较低的成本实现高显示品质。
需要注意的是，上述关于背景技术的介绍仅仅是为了便于清楚、完整地理解本申请的技术方案。因此，不能仅仅由于其出现在本申请的背景技术中，而认为上述所涉及到的技术方案为本领域所属技术人员所公知。
 技术问题
本申请提供一种像素电路及显示面板，以实现像素电路的内部补偿与混合驱动的技术问题。
 技术解决方案
第一方面，本申请提供一种像素电路，其包括驱动模块、脉幅调制模块、脉宽调制模块、内部补偿模块以及电位保持模块，脉幅调制模块的输出端与驱动模块的控制端电性连接；脉宽调制模块的输出端与驱动模块的控制端电性连接；内部补偿模块的输出端与驱动模块的第一端电性连接；电位保持模块的第一端与驱动模块的第一端电性连接。
在其中一些实施方式中，像素电路还包括发光控制模块、存储模块以及发光器件，发光控制模块的第一端与电位保持模块的第二端电性连接并接入电源正信号，发光控制模块的第二端与驱动模块的第二端电性连接，发光控制模块的控制端接入第一控制信号；存储模块的第一端与驱动模块的控制端电性连接，存储模块的第二端与驱动模块的第一端电性连接；发光器件的阳极与驱动模块的第一端电性连接，发光器件的阴极接入电源负信号。
在其中一些实施方式中，驱动模块包括驱动晶体管，驱动晶体管的栅极与脉幅调制模块的输出端、脉宽调制模块的输出端以及存储模块的第一端电性连接，驱动晶体管的源极/漏极中的一个与内部补偿模块的输出端、电位保持模块的第一端电性连接，驱动晶体管的源极/漏极中的另一个与发光控制模块的第二端电性连接；其中，驱动模块的控制端为驱动晶体管的栅极，驱动模块的第一端为驱动晶体管的源极/漏极中的一个，驱动模块的第二端为驱动晶体管的源极/漏极中的另一个。
在其中一些实施方式中，脉幅调制模块包括脉幅控制晶体管，脉幅控制晶体管的源极/漏极中的一个接入脉幅数据信号，脉幅控制晶体管的栅极接入第二控制信号，脉幅控制晶体管的源极/漏极中的另一个与驱动晶体管的栅极电性连接；其中，脉幅调制模块的输出端为脉幅控制晶体管的源极/漏极中的另一个。
在其中一些实施方式中，脉宽调制模块包括脉宽控制晶体管，脉宽控制晶体管的源极/漏极中的一个接入脉宽数据信号，脉宽控制晶体管的栅极接入第三控制信号，脉宽控制晶体管的源极/漏极中的另一个与驱动晶体管的栅极电性连接；其中，脉宽调制模块的输出端为脉宽控制晶体管的源极/漏极中的另一个。
在其中一些实施方式中，内部补偿模块包括补偿晶体管，补偿晶体管的源极/漏极中的一个接入复位信号，补偿晶体管的栅极接入第四控制信号，补偿晶体管的源极/漏极中的另一个与驱动晶体管的源极/漏极中的一个电性连接；其中，内部补偿模块的输出端为补偿晶体管的源极/漏极中的另一个。
在其中一些实施方式中，电位保持模块包括第一电容，第一电容的第一端与驱动晶体管的源极/漏极中的一个电性连接，第一电容的第二端与发光控制模块的第一端电性连接并接入电源正信号。
在其中一些实施方式中，像素电路的一帧时间包括写入阶段和发光阶段，在写入阶段中，内部补偿模块先复位驱动模块的第一端的电位，然后脉幅调制模块写入脉幅数据信号至驱动模块的控制端；在发光阶段中，脉宽调制模块写入脉宽数据信号至驱动模块的控制端以间歇性关断驱动模块。
在其中一些实施方式中，在脉幅调制模块的导通期间内，发光控制模块处于导通状态时内部补偿模块复位驱动模块的第一端的电位，发光控制模块处于关闭状态时脉幅调制模块输出具有脉冲的脉幅数据信号至驱动模块的控制端，且一帧时间中驱动模块的第一端的复位时间早于脉幅数据信号的脉冲开始时间；在脉幅调制模块的关闭期间且发光控制模块处于导通状态时，脉宽调制模块输出具有至少一个脉冲的脉宽数据信号至驱动模块的控制端，以控制发光器件在低灰阶显示中的发光时间。
第二方面，本申请提供一种显示面板，其包括上述至少一实施方式中的像素电路。
 有益效果
本申请提供的像素电路及显示面板，通过脉幅调制模块可以以脉幅调制方式控制高灰阶显示，脉宽调制模块可以以脉宽调制方式控制低灰阶显示，从而实现了混合驱动方式的高显示品质，内部补偿模块可以对驱动模块的第一端进行内部补偿以降低补偿的成本，实现了像素电路的内部补偿与混合驱动，进而能够以较低的成本实现高显示品质；又，电位保持模块可以对补偿后的驱动模块的第一端的电位进行保持，能够稳定驱动模块的控制端与驱动模块的第一端之间的压差，进而提高显示时间的控制精度。
 附图说明
图1为本申请实施例提供的像素电路的第一种结构示意图。
图2为本申请实施例提供的像素电路的第二种结构示意图。
图3为本申请实施例提供的像素电路的第三种结构示意图。
图4为图3所示像素电路的时序示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本实施例提供了一种像素电路，如图1所示，该像素电路包括驱动晶体管T1、开关晶体管T2、开关晶体管T3、开关晶体管T4、存储电容Cst以及发光器件D1，驱动晶体管T1的源极/漏极中的一个接入电源正信号VDD，驱动晶体管T1的源极/漏极中的另一个与发光器件D1的阳极电性连接，发光器件D1的阴极接入电源负信号VSS；开关晶体管T4的源极/漏极中的一个接入参考信号Vref或者输出驱动晶体管T1的源极/漏极中的另一个的电位，开关晶体管T4的栅极接入控制信号SCAN2，开关晶体管T4的源极/漏极中的另一个与驱动晶体管T1的源极/漏极中的另一个电性连接；开关晶体管T2的源极/漏极中的一个接入脉幅数据信号DPAM，开关晶体管T2的栅极接入控制信号SCAN1，开关晶体管T2的源极/漏极中的另一个与驱动晶体管T1的栅极电性连接；开关晶体管T3的源极/漏极中的一个接入脉宽数据信号DPWM，开关晶体管T3的栅极接入控制信号SCAN3，开关晶体管T3的源极/漏极中的另一个与驱动晶体管T1的栅极电性连接；存储电容Cst的一端与驱动晶体管T1的栅极电性连接，存储电容Cst的另一端与驱动晶体管T1的源极/漏极中的另一个电性连接。
其中，在控制信号SCAN3的控制下，开关晶体管T3可以控制脉宽数据信号DPWM写入至驱动晶体管T1的栅极，以控制像素电路的低灰阶显示。在控制信号SCAN1的控制下，开关晶体管T2可以控制脉幅数据信号DPAM写入至驱动晶体管T1的栅极，以控制像素电路的高灰阶显示。在控制信号SCAN2的控制下，开关晶体管T4可以控制参考信号Vref写入至驱动晶体管T1的源极/漏极中的另一个，以初始化驱动晶体管T1的源极/漏极中的另一个的电位和/或发光器件D1的阳极电位；开关晶体管T4也可以输出驱动晶体管T1的源极/漏极中的另一个的电位至外部补偿系统，以便该外部补偿系统可以根据驱动晶体管T1的源极/漏极中的另一个的电位对脉幅数据信号DPAM和/或脉宽数据信号DPWM进行补偿。
基于上述分析，本实施例中的像素电路需要通过外部补偿系统实现对像素电路的补偿，然而，配置外部补偿系统显然需要增加成本。
有鉴于配置外部补偿系统需要增加成本的问题，本实施例提供了另一种像素电路，如图2所示，该像素电路包括驱动晶体管T1、开关晶体管T2、开关晶体管T4、开关晶体管T5、存储电容Cst、发光器件D1以及第一电容C1，开关晶体管T5的源极/漏极中的一个接入电源正信号VDD，开关晶体管T5的栅极接入控制信号SCAN3，开关晶体管T5的源极/漏极中的另一个与驱动晶体管T1的源极/漏极中的一个电性连接，驱动晶体管T1的源极/漏极中的另一个与发光器件D1的阳极电性连接，发光器件D1的阴极接入电源负信号VSS；开关晶体管T4的源极/漏极中的一个接入复位信号RESET，开关晶体管T4的栅极接入控制信号SCAN2，开关晶体管T4的源极/漏极中的另一个与驱动晶体管T1的源极/漏极中的另一个电性连接；开关晶体管T2的源极/漏极中的一个接入脉幅数据信号DPAM，开关晶体管T2的栅极接入控制信号SCAN1，开关晶体管T2的源极/漏极中的另一个与驱动晶体管T1的栅极电性连接；存储电容Cst的一端与驱动晶体管T1的栅极电性连接，存储电容Cst的另一端与驱动晶体管T1的源极/漏极中的另一个电性连接；第一电容C1的一端与驱动晶体管T1的源极/漏极中的另一个电性连接，第一电容C1的另一端与开关晶体管T5的源极/漏极中的一个电性连接，以保持驱动晶体管T1的源极/漏极中的另一个的电位。
其中，在控制信号SCAN1的控制下，开关晶体管T2可以控制数据信号DPAM写入至驱动晶体管T1的栅极，以控制像素电路的各灰阶显示。在控制信号SCAN2的控制下，开关晶体管T4可以控制复位信号RESET写入至驱动晶体管T1的源极/漏极中的另一个，以初始化驱动晶体管T1的源极/漏极中的另一个的电位和/或发光器件D1的阳极电位。
基于上述分析，本实施例中的像素电路虽然通过开关晶体管T4实现了内部补偿，但是在控制信号SCAN1的控制下，开关晶体管T2可以控制数据信号DPAM写入至驱动晶体管T1的栅极，其仅可以实现脉幅调制驱动方式，并不能够实现脉宽调制驱动方式，低灰阶的显示品质得不到控制。
在对像素电路的持续研发过程中，像素电路的结构也一直在不断变化，但是，一直缺少一种兼有内部补偿与混合驱动方式的像素电路，其能够以较低的成本实现高显示品质，有鉴于此，本实施例提供了另一种像素电路，如图3所示，该像素电路包括驱动模块10、脉幅调制模块20、脉宽调制模块30、内部补偿模块40以及电位保持模块50，脉幅调制模块20的输出端与驱动模块10的控制端电性连接；脉宽调制模块30的输出端与驱动模块10的控制端电性连接；内部补偿模块40的输出端与驱动模块10的第一端电性连接；电位保持模块50的第一端与驱动模块10的第一端电性连接。
本实施例提供的像素电路，通过脉幅调制模块20可以以脉幅调制方式控制高灰阶显示，脉宽调制模块30可以以脉宽调制方式控制低灰阶显示，从而实现了混合驱动方式的高显示品质，内部补偿模块40可以对驱动模块10的第一端进行内部补偿以降低补偿的成本，实现了像素电路的内部补偿与混合驱动，进而能够以较低的成本实现高显示品质；又，电位保持模块50可以对补偿后的驱动模块10的第一端的电位进行保持，能够稳定驱动模块10的控制端与驱动模块10的第一端之间的压差，进而提高显示时间的控制精度。
在其中一个实施例中，像素电路还包括发光控制模块60、存储模块70以及发光器件D1，发光控制模块60的第一端与电位保持模块50的第二端电性连接并接入电源正信号VDD，发光控制模块60的第二端与驱动模块10的第二端电性连接，发光控制模块60的控制端接入第一控制信号SCAN3；存储模块70的第一端与驱动模块10的控制端电性连接，存储模块70的第二端与驱动模块10的第一端电性连接；发光器件D1的阳极与驱动模块10的第一端电性连接，发光器件D1的阴极接入电源负信号VSS。
在其中一个实施例中，发光控制模块60包括发光控制晶体管T5，发光控制晶体管T5的源极/漏极中的一个接入电源正信号VDD，发光控制晶体管T5的源极/漏极中的另一个与驱动晶体管T1的源极/漏极中的另一个电性连接，发光控制晶体管T5的栅极接入第一控制信号SCAN3。
在其中一个实施例中，存储模块70包括存储电容Cst，存储电容Cst的一端与驱动晶体管T1的栅极电性连接，存储电容Cst的另一端与驱动晶体管T1的源极/漏极中的一个电性连接。
在其中一个实施例中，发光器件D1可以为迷你发光二极管、微发光二极管或者有机发光二极管中的一个。
在其中一个实施例中，驱动模块10包括驱动晶体管T1，驱动晶体管T1的栅极与脉幅调制模块20的输出端、脉宽调制模块30的输出端以及存储模块70的第一端电性连接，驱动晶体管T1的源极/漏极中的一个与内部补偿模块40的输出端、电位保持模块50的第一端电性连接，驱动晶体管T1的源极/漏极中的另一个与发光控制模块60的第二端电性连接；其中，驱动模块10的控制端为驱动晶体管T1的栅极，驱动模块10的第一端为驱动晶体管T1的源极/漏极中的一个，驱动模块10的第二端为驱动晶体管T1的源极/漏极中的另一个。
在其中一个实施例中，脉幅调制模块20包括脉幅控制晶体管T2，脉幅控制晶体管T2的源极/漏极中的一个接入脉幅数据信号DPAM，脉幅控制晶体管T2的栅极接入第二控制信号SCAN1，脉幅控制晶体管T2的源极/漏极中的另一个与驱动晶体管T1的栅极电性连接；其中，脉幅调制模块20的输出端为脉幅控制晶体管T2的源极/漏极中的另一个。
在其中一个实施例中，脉宽调制模块30包括脉宽控制晶体管T3，脉宽控制晶体管T3的源极/漏极中的一个接入脉宽数据信号DPWM，脉宽控制晶体管T3的栅极接入第三控制信号SCAN4，脉宽控制晶体管T3的源极/漏极中的另一个与驱动晶体管T1的栅极电性连接；其中，脉宽调制模块30的输出端为脉宽控制晶体管T3的源极/漏极中的另一个。
在其中一个实施例中，内部补偿模块40包括补偿晶体管T4，补偿晶体管T4的源极/漏极中的一个接入复位信号RESET，补偿晶体管T4的栅极接入第四控制信号SCAN2，补偿晶体管T4的源极/漏极中的另一个与驱动晶体管T1的源极/漏极中的一个电性连接；其中，内部补偿模块40的输出端为补偿晶体管T4的源极/漏极中的另一个。
在其中一个实施例中，电位保持模块50包括第一电容C1，第一电容C1的第一端与驱动晶体管T1的源极/漏极中的一个电性连接，第一电容C1的第二端与发光控制模块60的第一端电性连接并接入电源正信号VDD。
在其中一个实施例中，脉宽控制晶体管T3、脉幅控制晶体管T2、补偿晶体管T4以及发光控制晶体管T5均为N沟道型薄膜晶体管，例如，可以为N沟道型金属氧化物薄膜晶体管；驱动晶体管T1可以为P沟道型薄膜晶体管，例如，可以为P沟道型低温多晶硅薄膜晶体管，可以理解的是，如此配置既可以保证像素电路的动态性能，又可以保证像素电路的低漏电。
在其中一个实施例中，图3所示像素电路的工作过程具体如图4所示，一帧F1可以包括先后时间顺序的第一子帧F11和第二子帧F12，或者还可以包括后续的第三子帧F13至第M子帧F1M，其中，M可以为大于或者等于3的正整数。
其中，在第一子帧F11中，第一控制信号SCAN3、第二控制信号SCAN1、第四控制信号SCAN2均处于高电位，脉幅控制晶体管T2、补偿晶体管T4、发光控制晶体管T5均打开，复位信号RESET通过补偿晶体管T4对驱动晶体管T1的源极/漏极中的一个的电位进行补偿，并通过第一电容C1对补偿后的驱动晶体管T1的源极/漏极中的一个的电位进行保持。然后，第一控制信号SCAN3处于低电位，发光控制晶体管T5关闭；第二控制信号SCAN1仍然处于高电位，脉幅控制晶体管T2保持打开，脉幅数据信号DPAM的一个脉冲通过脉幅控制晶体管T2写入至驱动晶体管T1的栅极。也就是说，第一子帧F11是用于补偿以及通过脉幅调制驱动像素电路的高灰阶显示的。
在第二子帧F12中，第二控制信号SCAN1、第四控制信号SCAN2均处于低电位，脉幅控制晶体管T2、补偿晶体管T4均关闭；第一控制信号SCAN3处于高电位，发光控制晶体管T5保持打开；第三控制信号SCAN4处于高电位时，打开的脉宽控制晶体管T3输出处于高电位的脉宽数据信号DPWM至驱动晶体管T1的栅极，致使驱动晶体管T1关断，以控制低灰阶显示的时间，进而提高低灰阶的显示品质。
在后续的第三子帧F13至第M子帧F1M中的任一个中，脉宽数据信号DPWM可以具有至少一个脉冲，以控制低灰阶的显示品质。
也就是说，像素电路的一帧时间可以包括写入阶段即第一子帧F11和发光阶段即第二子帧F12或者第二子帧F12至第M子帧F1M中的至少一个，在写入阶段中，内部补偿模块40先复位驱动模块10的第一端的电位，然后脉幅调制模块20写入脉幅数据信号DPAM至驱动模块10的控制端；在发光阶段中，脉宽调制模块30写入脉宽数据信号DPWM至驱动模块10的控制端以间歇性关断驱动模块10。
具体地，在脉幅调制模块20的导通期间内，发光控制模块60处于导通状态时内部补偿模块40复位驱动模块10的第一端的电位，发光控制模块60处于关闭状态时脉幅调制模块20输出具有脉冲的脉幅数据信号DPAM至驱动模块10的控制端，且一帧时间中驱动模块10的第一端的复位时间早于脉幅数据信号DPAM的脉冲开始时间；在脉幅调制模块20的关闭期间且发光控制模块60处于导通状态时，脉宽调制模块30输出具有至少一个脉冲的脉宽数据信号DPWM至驱动模块10的控制端，以控制发光器件D1在低灰阶显示中的发光时间。
在其中一个实施例中，本实施例提供一种显示面板，其包括上述至少一实施例中的像素电路。
本实施例提供的显示面板，通过脉幅调制模块20可以以脉幅调制方式控制高灰阶显示，脉宽调制模块30可以以脉宽调制方式控制低灰阶显示，从而实现了混合驱动方式的高显示品质，内部补偿模块40可以对驱动模块10的第一端进行内部补偿以降低补偿的成本，实现了像素电路的内部补偿与混合驱动，进而能够以较低的成本实现高显示品质；又，电位保持模块50可以对补偿后的驱动模块10的第一端的电位进行保持，能够稳定驱动模块10的控制端与驱动模块10的第一端之间的压差，进而提高显示时间的控制精度。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种像素电路，包括：
    驱动模块；
    脉幅调制模块，所述脉幅调制模块的输出端与所述驱动模块的控制端电性连接；
    脉宽调制模块，所述脉宽调制模块的输出端与所述驱动模块的控制端电性连接；
    内部补偿模块，所述内部补偿模块的输出端与所述驱动模块的第一端电性连接；
    电位保持模块，所述电位保持模块的第一端与所述驱动模块的第一端电性连接。
  2. 根据权利要求1所述的像素电路，其中，所述像素电路还包括：
    发光控制模块，所述发光控制模块的第一端与所述电位保持模块的第二端电性连接并接入电源正信号，所述发光控制模块的第二端与所述驱动模块的第二端电性连接，所述发光控制模块的控制端接入第一控制信号；
    存储模块，所述存储模块的第一端与所述驱动模块的控制端电性连接，所述存储模块的第二端与所述驱动模块的第一端电性连接；以及
    发光器件，所述发光器件的阳极与所述驱动模块的第一端电性连接，所述发光器件的阴极接入电源负信号。
  3. 根据权利要求2所述的像素电路，其中，所述驱动模块包括驱动晶体管，所述驱动晶体管的栅极与所述脉幅调制模块的输出端、所述脉宽调制模块的输出端以及所述存储模块的第一端电性连接，所述驱动晶体管的源极/漏极中的一个与所述内部补偿模块的输出端、所述电位保持模块的第一端电性连接，所述驱动晶体管的源极/漏极中的另一个与所述发光控制模块的第二端电性连接；
    其中，所述驱动模块的控制端为所述驱动晶体管的栅极，所述驱动模块的第一端为所述驱动晶体管的源极/漏极中的一个，所述驱动模块的第二端为所述驱动晶体管的源极/漏极中的另一个。
  4. 根据权利要求3所述的像素电路，其中，所述脉幅调制模块包括脉幅控制晶体管，所述脉幅控制晶体管的源极/漏极中的一个接入脉幅数据信号，所述脉幅控制晶体管的栅极接入第二控制信号，所述脉幅控制晶体管的源极/漏极中的另一个与所述驱动晶体管的栅极电性连接；
    其中，所述脉幅调制模块的输出端为所述脉幅控制晶体管的源极/漏极中的另一个。
  5. 根据权利要求4所述的像素电路，其中，所述脉宽调制模块包括脉宽控制晶体管，所述脉宽控制晶体管的源极/漏极中的一个接入脉宽数据信号，所述脉宽控制晶体管的栅极接入第三控制信号，所述脉宽控制晶体管的源极/漏极中的另一个与所述驱动晶体管的栅极电性连接；
    其中，所述脉宽调制模块的输出端为所述脉宽控制晶体管的源极/漏极中的另一个。
  6. 根据权利要求5所述的像素电路，其中，所述内部补偿模块包括补偿晶体管，所述补偿晶体管的源极/漏极中的一个接入复位信号，所述补偿晶体管的栅极接入第四控制信号，所述补偿晶体管的源极/漏极中的另一个与所述驱动晶体管的源极/漏极中的一个电性连接；
    其中，所述内部补偿模块的输出端为所述补偿晶体管的源极/漏极中的另一个。
  7. 根据权利要求6所述的像素电路，其中，所述电位保持模块包括第一电容，所述第一电容的第一端与所述驱动晶体管的源极/漏极中的一个电性连接，所述第一电容的第二端与所述发光控制模块的第一端电性连接并接入所述电源正信号。
  8. 根据权利要求1所述的像素电路，其中，所述像素电路的一帧时间包括写入阶段和发光阶段，在所述写入阶段中，所述内部补偿模块先复位所述驱动模块的第一端的电位，然后所述脉幅调制模块写入脉幅数据信号至所述驱动模块的控制端；在所述发光阶段中，所述脉宽调制模块写入脉宽数据信号至所述驱动模块的控制端以间歇性关断所述驱动模块。
  9. 根据权利要求2所述的像素电路，其中，在所述脉幅调制模块的导通期间内，所述发光控制模块处于导通状态时所述内部补偿模块复位所述驱动模块的第一端的电位，所述发光控制模块处于关闭状态时所述脉幅调制模块输出具有脉冲的脉幅数据信号至所述驱动模块的控制端，且一帧时间中所述驱动模块的第一端的复位时间早于所述脉幅数据信号的脉冲开始时间；
    在所述脉幅调制模块的关闭期间且所述发光控制模块处于导通状态时，所述脉宽调制模块输出具有至少一个脉冲的脉宽数据信号至所述驱动模块的控制端，以控制所述发光器件在低灰阶显示中的发光时间。
  10. 一种显示面板，包括如权利要求1所述的像素电路。
  11. 根据权利要求10所述的显示面板，其中，所述像素电路还包括：
    发光控制模块，所述发光控制模块的第一端与所述电位保持模块的第二端电性连接并接入电源正信号，所述发光控制模块的第二端与所述驱动模块的第二端电性连接，所述发光控制模块的控制端接入第一控制信号；
    存储模块，所述存储模块的第一端与所述驱动模块的控制端电性连接，所述存储模块的第二端与所述驱动模块的第一端电性连接；以及
    发光器件，所述发光器件的阳极与所述驱动模块的第一端电性连接，所述发光器件的阴极接入电源负信号。
  12. 根据权利要求11所述的显示面板，其中，所述驱动模块包括驱动晶体管，所述驱动晶体管的栅极与所述脉幅调制模块的输出端、所述脉宽调制模块的输出端以及所述存储模块的第一端电性连接，所述驱动晶体管的源极/漏极中的一个与所述内部补偿模块的输出端、所述电位保持模块的第一端电性连接，所述驱动晶体管的源极/漏极中的另一个与所述发光控制模块的第二端电性连接；
    其中，所述驱动模块的控制端为所述驱动晶体管的栅极，所述驱动模块的第一端为所述驱动晶体管的源极/漏极中的一个，所述驱动模块的第二端为所述驱动晶体管的源极/漏极中的另一个。
  13. 根据权利要求12所述的显示面板，其中，所述脉幅调制模块包括脉幅控制晶体管，所述脉幅控制晶体管的源极/漏极中的一个接入脉幅数据信号，所述脉幅控制晶体管的栅极接入第二控制信号，所述脉幅控制晶体管的源极/漏极中的另一个与所述驱动晶体管的栅极电性连接；
    其中，所述脉幅调制模块的输出端为所述脉幅控制晶体管的源极/漏极中的另一个。
  14. 根据权利要求13所述的显示面板，其中，所述脉宽调制模块包括脉宽控制晶体管，所述脉宽控制晶体管的源极/漏极中的一个接入脉宽数据信号，所述脉宽控制晶体管的栅极接入第三控制信号，所述脉宽控制晶体管的源极/漏极中的另一个与所述驱动晶体管的栅极电性连接；
    其中，所述脉宽调制模块的输出端为所述脉宽控制晶体管的源极/漏极中的另一个。
  15. 根据权利要求14所述的显示面板，其中，所述内部补偿模块包括补偿晶体管，所述补偿晶体管的源极/漏极中的一个接入复位信号，所述补偿晶体管的栅极接入第四控制信号，所述补偿晶体管的源极/漏极中的另一个与所述驱动晶体管的源极/漏极中的一个电性连接；
    其中，所述内部补偿模块的输出端为所述补偿晶体管的源极/漏极中的另一个。
  16. 根据权利要求15所述的显示面板，其中，所述电位保持模块包括第一电容，所述第一电容的第一端与所述驱动晶体管的源极/漏极中的一个电性连接，所述第一电容的第二端与所述发光控制模块的第一端电性连接并接入所述电源正信号。
  17. 根据权利要求10所述的显示面板，其中，所述像素电路的一帧时间包括写入阶段和发光阶段，在所述写入阶段中，所述内部补偿模块先复位所述驱动模块的第一端的电位，然后所述脉幅调制模块写入脉幅数据信号至所述驱动模块的控制端；在所述发光阶段中，所述脉宽调制模块写入脉宽数据信号至所述驱动模块的控制端以间歇性关断所述驱动模块。
  18. 根据权利要求11所述的显示面板，其中，在所述脉幅调制模块的导通期间内，所述发光控制模块处于导通状态时所述内部补偿模块复位所述驱动模块的第一端的电位，所述发光控制模块处于关闭状态时所述脉幅调制模块输出具有脉冲的脉幅数据信号至所述驱动模块的控制端，且一帧时间中所述驱动模块的第一端的复位时间早于所述脉幅数据信号的脉冲开始时间；
    在所述脉幅调制模块的关闭期间且所述发光控制模块处于导通状态时，所述脉宽调制模块输出具有至少一个脉冲的脉宽数据信号至所述驱动模块的控制端，以控制所述发光器件在低灰阶显示中的发光时间。
  19. 根据权利要求12所述的显示面板，其中，所述发光控制模块包括发光控制晶体管，所述发光控制晶体管的源极/漏极中的一个接入所述电源正信号，所述发光控制晶体管的源极/漏极中的另一个与所述驱动晶体管的源极/漏极中的另一个电性连接，所述发光控制晶体管的栅极接入第一控制信号。
  20. 根据权利要求11所述的显示面板，其中，所述发光器件为迷你发光二极管、微发光二极管或者有机发光二极管中的一个。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114783358B (zh) * 2022-04-15 2023-06-30 Tcl华星光电技术有限公司 像素驱动电路及其控制方法、显示面板

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103150992A (zh) * 2013-03-14 2013-06-12 友达光电股份有限公司 一种像素驱动电路
CN110556072A (zh) * 2018-05-31 2019-12-10 三星电子株式会社 显示面板以及显示面板的驱动方法
CN111341252A (zh) * 2019-10-22 2020-06-26 友达光电股份有限公司 像素电路
CN111402794A (zh) * 2019-09-17 2020-07-10 友达光电股份有限公司 驱动芯片与相关的显示器
CN111681598A (zh) * 2020-06-03 2020-09-18 深圳市华星光电半导体显示技术有限公司 显示面板及其制造方法
CN112102772A (zh) * 2019-06-17 2020-12-18 三星电子株式会社 显示模块及其驱动方法
CN113396452A (zh) * 2019-03-29 2021-09-14 三星电子株式会社 显示面板和显示面板的驱动方法
WO2021210893A1 (ko) * 2020-04-16 2021-10-21 삼성전자주식회사 디스플레이 모듈 및 디스플레이 모듈의 구동 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110634433A (zh) * 2018-06-01 2019-12-31 三星电子株式会社 显示面板
CN108470539B (zh) * 2018-06-13 2020-04-21 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板和显示装置
US10657899B2 (en) * 2018-06-22 2020-05-19 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Pixel compensation circuit, driving method for the same and amoled display panel
CN113270071A (zh) * 2021-05-28 2021-08-17 长沙惠科光电有限公司 外部补偿像素电路及显示面板
CN113487994B (zh) * 2021-06-16 2022-05-06 中国科学院微电子研究所 一种像素电路、显示设备及像素补偿方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103150992A (zh) * 2013-03-14 2013-06-12 友达光电股份有限公司 一种像素驱动电路
CN110556072A (zh) * 2018-05-31 2019-12-10 三星电子株式会社 显示面板以及显示面板的驱动方法
CN113396452A (zh) * 2019-03-29 2021-09-14 三星电子株式会社 显示面板和显示面板的驱动方法
CN112102772A (zh) * 2019-06-17 2020-12-18 三星电子株式会社 显示模块及其驱动方法
CN111402794A (zh) * 2019-09-17 2020-07-10 友达光电股份有限公司 驱动芯片与相关的显示器
CN111341252A (zh) * 2019-10-22 2020-06-26 友达光电股份有限公司 像素电路
WO2021210893A1 (ko) * 2020-04-16 2021-10-21 삼성전자주식회사 디스플레이 모듈 및 디스플레이 모듈의 구동 방법
CN111681598A (zh) * 2020-06-03 2020-09-18 深圳市华星光电半导体显示技术有限公司 显示面板及其制造方法

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