WO2023115444A1 - 发光电路、背光模组以及显示面板 - Google Patents

发光电路、背光模组以及显示面板 Download PDF

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Publication number
WO2023115444A1
WO2023115444A1 PCT/CN2021/140753 CN2021140753W WO2023115444A1 WO 2023115444 A1 WO2023115444 A1 WO 2023115444A1 CN 2021140753 W CN2021140753 W CN 2021140753W WO 2023115444 A1 WO2023115444 A1 WO 2023115444A1
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WIPO (PCT)
Prior art keywords
transistor
signal
source
drain
node
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PCT/CN2021/140753
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English (en)
French (fr)
Inventor
徐健
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Priority to US17/623,590 priority Critical patent/US20240038179A1/en
Publication of WO2023115444A1 publication Critical patent/WO2023115444A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/3406—Control of illumination source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
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    • G—PHYSICS
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    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
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    • G09G2320/02—Improving the quality of display appearance
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    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel

Definitions

  • the present application relates to the field of display technology, in particular to a light emitting circuit, a backlight module and a display panel.
  • Light-emitting devices such as mini light-emitting diodes, micro light-emitting diodes, and organic light-emitting diodes have the advantages of high brightness, high contrast, and high color gamut, and have been widely used in the field of high-performance displays.
  • the current common driving methods of LED display technology include PAM (Pulse Amplitude Modulation, Pulse Amplitude Modulation), PWM (Pulse Width Modulation, Pulse Width Modulation) and their mixture.
  • the PWM driving method has the advantages of constant current, high luminous efficiency of light-emitting devices, and good image quality of low gray scale display. Therefore, PWM and PWM-based hybrid drive displays have been extensively studied. However, in the existing PWM driving method, there is a problem that it is difficult to accurately control the light-emitting time of the light-emitting device in the light-emitting circuit.
  • the present application provides a light emitting circuit, a backlight module and a display panel to solve the technical problem that it is difficult to accurately control the light emitting time of light emitting devices in the existing light emitting circuit.
  • the application provides a lighting circuit, which includes:
  • one of the source and the drain of the driving transistor is connected to the first power supply signal
  • the first end of the light emitting device is electrically connected to the other of the source and the drain of the driving transistor, and the second end of the light emitting device is connected to a second power supply signal;
  • a data signal writing module accesses the scanning signal and the data signal, and is electrically connected to the gate of the driving transistor, and the data signal writing module is used for controlling the scanning signal Next, write the data signal into the gate of the driving transistor;
  • the first control module accesses the control signal, the first voltage signal and the second voltage signal, and is electrically connected to the first node, and the first control module is used for receiving the control signal, the first voltage signal, and the second voltage signal. controlling the potential of the first node under the control of the first voltage signal and the second voltage signal;
  • a bistable circuit module is connected to the first power supply signal and the third power supply signal, and is electrically connected to the first node and the second node, and the bistable circuit module uses controlling the potential of the second node under the control of the potential of the first node, the first power signal, and the third power signal;
  • a second control module is connected to the third power supply signal, and is electrically connected to the second node and the gate of the driving transistor, and the second control module is used for the potential of the second node and the potential of the gate of the driving transistor under the control of the third power supply signal;
  • a storage module is electrically connected to the gate of the driving transistor and the second terminal of the light emitting device, and the storage module is used for storing the potential of the gate of the driving transistor.
  • the data signal writing module includes a first transistor, the gate of the first transistor is connected to the scanning signal, and the source and drain of the first transistor One of them is connected to the data signal, and the other of the source and drain of the first transistor is electrically connected to the gate of the driving transistor;
  • the storage module includes a storage capacitor, one end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is electrically connected to the second end of the light emitting device.
  • the first control module includes a second transistor and a first capacitor
  • the gate of the second transistor is connected to the control signal, one of the source and drain of the second transistor is connected to the first voltage signal, and the source and drain of the second transistor are The other one and one end of the first capacitor are electrically connected to the first node, and the other end of the first capacitor is connected to the second voltage signal.
  • the bistable circuit module includes a first inverter and a second inverter
  • the first inverter includes a third transistor and a fourth transistor, the gate of the third transistor and one of the source and drain of the third transistor are connected to the first power supply signal, The other of the source and drain of the third transistor and one of the source and drain of the fourth transistor are electrically connected to the second node, and the gate of the fourth transistor The pole is electrically connected to the first node, and the other of the source and the drain of the fourth transistor is connected to the third power supply signal;
  • the second inverter includes a fifth transistor and a sixth transistor, the gate of the fifth transistor and one of the source and the drain of the fifth transistor are connected to the first power supply signal, The other of the source and drain of the fifth transistor and one of the source and drain of the sixth transistor are electrically connected to the first node, and the gate of the sixth transistor The pole is electrically connected to the second node, and the other of the source and the drain of the sixth transistor is connected to the third power supply signal.
  • the channel aspect ratio of the third transistor is smaller than the channel aspect ratio of the fourth transistor, and the channel aspect ratio of the fifth transistor is smaller than the channel aspect ratio of the fifth transistor.
  • Channel aspect ratio of the sixth transistor is smaller than the channel aspect ratio of the third transistor.
  • the bistable circuit module includes a first inverter and a second inverter
  • the first inverter includes a third transistor and a fourth transistor, the gates of the third transistor and the fourth transistor are both electrically connected to the first node, and the source of the third transistor is connected to the first node.
  • One of the drains is connected to the first power supply signal, the other of the source and the drain of the third transistor and one of the source and the drain of the fourth transistor are connected to the The second node is electrically connected, and the other of the source and the drain of the fourth transistor is connected to the third power supply signal;
  • the second inverter includes a fifth transistor and a sixth transistor, the gates of the fifth transistor and the sixth transistor are both electrically connected to the second node, and the source of the fifth transistor is connected to the second node.
  • One of the drains is connected to the first power supply signal, the other of the source and the drain of the fifth transistor and one of the source and the drain of the sixth transistor are connected to the The first node is electrically connected, and the other of the source and the drain of the sixth transistor is connected to the third power supply signal;
  • the third transistor and the fifth transistor are P-type transistors
  • the fourth transistor and the sixth transistor are N-type transistors.
  • the third transistor and the fifth transistor are P-type transistors
  • the fourth transistor and the sixth transistor are N-type transistors
  • the third transistor A channel aspect ratio is smaller than that of the fourth transistor
  • a channel aspect ratio of the fifth transistor is smaller than that of the sixth transistor.
  • the second control module includes a seventh crystal
  • the gate of the seventh transistor is electrically connected to the second node
  • the source of the seventh transistor and One of the drains is connected to the third power supply signal
  • the other of the source and the drain of the seventh transistor is electrically connected to the gate of the driving transistor.
  • the light emitting circuit further includes a sensing module, the sensing module receives a sensing signal and is electrically connected to the source and drain of the driving transistor. The other and the initial voltage input end, the sensing module is used to sense the threshold voltage of the driving transistor under the control of the sensing signal.
  • the sensing module includes an eighth transistor, the gate of the eighth transistor is connected to the sensing signal, and the source and drain of the eighth transistor are One of the eighth transistors is electrically connected to the other of the source and drain of the driving transistor, and the other of the source and drain of the eighth transistor is electrically connected to the initial voltage input end.
  • the second voltage signal is a triangular wave signal.
  • a backlight module which includes:
  • the data line is used to provide a data signal
  • Scanning lines the scanning lines are used to provide scanning signals
  • control line the enable line is used to provide a control signal
  • the first signal line is used to provide a first voltage signal
  • the second signal line is used to provide a second voltage signal
  • the first power line is used to provide a first power signal
  • the second power line is used to provide a second power signal
  • the third power line is used to provide a third power signal
  • a light emitting circuit includes:
  • one of the source and the drain of the driving transistor is connected to the first power supply signal
  • the first end of the light emitting device is electrically connected to the other of the source and the drain of the driving transistor, and the second end of the light emitting device is connected to the second power supply signal;
  • a data signal writing module accesses the scanning signal and the data signal, and is electrically connected to the gate of the driving transistor, and the data signal writing module is used for Under the control of a scanning signal, writing the data signal into the gate of the driving transistor;
  • a first control module accesses the control signal, the first voltage signal and the second voltage signal, and is electrically connected to the first node, and the first control module is used for controlling the potential of the first node under the control of the control signal, the first voltage signal, and the second voltage signal;
  • a bistable circuit module is connected to the first power supply signal and the third power supply signal, and is electrically connected to the first node and the second node, and the bistable circuit module The module is used to control the potential of the second node under the control of the potential of the first node, the first power signal and the third power signal;
  • a second control module is connected to the third power supply signal, and is electrically connected to the second node and the gate of the driving transistor, and the second control module is used for the potential of the second node and the potential of the gate of the driving transistor under the control of the third power supply signal;
  • a storage module is electrically connected to the gate of the driving transistor and the second terminal of the light emitting device, and the storage module is used for storing the potential of the gate of the driving transistor.
  • the data signal writing module includes a first transistor, the gate of the first transistor is connected to the scanning signal, and the source and drain of the first transistor One of them is connected to the data signal, and the other of the source and drain of the first transistor is electrically connected to the gate of the driving transistor;
  • the storage module includes a storage capacitor, one end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end of the storage capacitor is electrically connected to the second end of the light emitting device.
  • the first control module includes a second transistor and a first capacitor
  • the gate of the second transistor is connected to the control signal, one of the source and drain of the second transistor is connected to the first voltage signal, and the source and drain of the second transistor are The other one and one end of the first capacitor are electrically connected to the first node, and the other end of the first capacitor is connected to the second voltage signal.
  • the bistable circuit module includes a first inverter and a second inverter
  • the first inverter includes a third transistor and a fourth transistor, the gate of the third transistor and one of the source and drain of the third transistor are connected to the first power supply signal, The other of the source and drain of the third transistor and one of the source and drain of the fourth transistor are electrically connected to the second node, and the gate of the fourth transistor The pole is electrically connected to the first node, and the other of the source and the drain of the fourth transistor is connected to the third power supply signal;
  • the second inverter includes a fifth transistor and a sixth transistor, the gate of the fifth transistor and one of the source and the drain of the fifth transistor are connected to the first power supply signal, The other of the source and drain of the fifth transistor and one of the source and drain of the sixth transistor are electrically connected to the first node, and the gate of the sixth transistor The pole is electrically connected to the second node, and the other of the source and the drain of the sixth transistor is connected to the third power supply signal.
  • the channel aspect ratio of the third transistor is smaller than the channel aspect ratio of the fourth transistor, and the channel aspect ratio of the fifth transistor is smaller than the channel aspect ratio of the fifth transistor.
  • Channel aspect ratio of the sixth transistor is smaller than the channel aspect ratio of the third transistor.
  • the bistable circuit module includes a first inverter and a second inverter
  • the first inverter includes a third transistor and a fourth transistor, the gates of the third transistor and the fourth transistor are both electrically connected to the first node, and the source of the third transistor is connected to the first node.
  • One of the drains is connected to the first power supply signal, the other of the source and the drain of the third transistor and one of the source and the drain of the fourth transistor are connected to the The second node is electrically connected, and the other of the source and the drain of the fourth transistor is connected to the third power supply signal;
  • the second inverter includes a fifth transistor and a sixth transistor, the gates of the fifth transistor and the sixth transistor are both electrically connected to the second node, and the source of the fifth transistor is connected to the second node.
  • One of the drains is connected to the first power supply signal, the other of the source and the drain of the fifth transistor and one of the source and the drain of the sixth transistor are connected to the The first node is electrically connected, and the other of the source and the drain of the sixth transistor is connected to the third power supply signal;
  • the third transistor and the fifth transistor are P-type transistors
  • the fourth transistor and the sixth transistor are N-type transistors.
  • the present application also provides a display panel, which includes a plurality of pixel units arranged in an array, and each of the pixel units includes a light emitting circuit, and the light emitting circuit includes:
  • one of the source and the drain of the driving transistor is connected to the first power supply signal
  • the first end of the light emitting device is electrically connected to the other of the source and the drain of the driving transistor, and the second end of the light emitting device is connected to a second power supply signal;
  • a data signal writing module accesses the scanning signal and the data signal, and is electrically connected to the gate of the driving transistor, and the data signal writing module is used for controlling the scanning signal Next, write the data signal into the gate of the driving transistor;
  • the first control module accesses the control signal, the first voltage signal and the second voltage signal, and is electrically connected to the first node, and the first control module is used for receiving the control signal, the first voltage signal, and the second voltage signal. controlling the potential of the first node under the control of the first voltage signal and the second voltage signal;
  • a bistable circuit module is connected to the first power supply signal and the third power supply signal, and is electrically connected to the first node and the second node, and the bistable circuit module uses controlling the potential of the second node under the control of the potential of the first node, the first power signal, and the third power signal;
  • a second control module is connected to the third power supply signal, and is electrically connected to the second node and the gate of the driving transistor, and the second control module is used for the potential of the second node and the potential of the gate of the driving transistor under the control of the third power supply signal;
  • a storage module is electrically connected to the gate of the driving transistor and the second terminal of the light emitting device, and the storage module is used for storing the potential of the gate of the driving transistor.
  • the first control module includes a second transistor and a first capacitor
  • the gate of the second transistor is connected to the control signal, one of the source and drain of the second transistor is connected to the first voltage signal, and the source and drain of the second transistor are The other one and one end of the first capacitor are electrically connected to the first node, and the other end of the first capacitor is connected to the second voltage signal.
  • the bistable circuit module includes a first inverter and a second inverter
  • the first inverter includes a third transistor and a fourth transistor, the gate of the third transistor and one of the source and drain of the third transistor are connected to the first power supply signal, The other of the source and drain of the third transistor and one of the source and drain of the fourth transistor are electrically connected to the second node, and the gate of the fourth transistor The pole is electrically connected to the first node, and the other of the source and the drain of the fourth transistor is connected to the third power supply signal;
  • the second inverter includes a fifth transistor and a sixth transistor, the gate of the fifth transistor and one of the source and the drain of the fifth transistor are connected to the first power supply signal, The other of the source and drain of the fifth transistor and one of the source and drain of the sixth transistor are electrically connected to the first node, and the gate of the sixth transistor The pole is electrically connected to the second node, and the other of the source and the drain of the sixth transistor is connected to the third power supply signal.
  • the channel aspect ratio of the third transistor is smaller than the channel aspect ratio of the fourth transistor, and the channel aspect ratio of the fifth transistor is smaller than the channel aspect ratio of the fifth transistor.
  • Channel aspect ratio of the sixth transistor is smaller than the channel aspect ratio of the third transistor.
  • the application discloses a light emitting circuit, a backlight module and a display panel.
  • the light emitting circuit includes a light emitting device, a driving transistor, a data signal writing module, a first control module, a bistable circuit module and a second control module.
  • the first control module, the bistable circuit module and the second control module work together to control the potential inversion of the gate of the drive transistor.
  • the bistable circuit module and the second control module work together to control the potential inversion of the gate of the drive transistor.
  • Fig. 1 is a first structural schematic diagram of the lighting circuit provided by the present application.
  • Fig. 2 is a schematic circuit diagram of the lighting circuit shown in Fig. 1 provided by the present application;
  • Fig. 3 is the first schematic circuit diagram of the bistable circuit module provided by the present application.
  • 4A-4B are schematic diagrams of voltage changes between the first node and the second node in the bistable circuit module provided by the present application;
  • Fig. 5 is the second schematic circuit diagram of the bistable circuit module provided by the present application.
  • FIG. 6 is a timing diagram of the lighting circuit shown in FIG. 2 provided by the present application.
  • Fig. 7 is a second structural schematic diagram of the lighting circuit provided by the present application.
  • FIG. 8 is a schematic circuit diagram of the lighting circuit shown in FIG. 7 provided by the present application.
  • FIG. 9 is a schematic structural view of a backlight module provided by the present application.
  • FIG. 10 is a schematic structural diagram of a display panel provided by the present application.
  • first and second are used for description purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features.
  • features defined as “first” and “second” may explicitly or implicitly include one or more of the features, and thus should not be construed as limiting the present application.
  • the present application provides a light emitting circuit, a backlight module and a display panel, which will be described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments of the present application.
  • FIG. 1 is a schematic diagram of the first structure of the lighting circuit provided in the present application.
  • the light emitting circuit 100 provided in this application includes a light emitting device D, a driving transistor Td, a data signal writing module 101 , a storage module 102 , a first control module 103 , a bistable circuit module 104 and a second control module 105 .
  • one of the source and the drain of the driving transistor Td is connected to the first power signal VDD.
  • a first end of the light emitting device D is electrically connected to the other of the source and the drain of the driving transistor Td.
  • the second end of the light emitting device D is connected to the second power signal VSS.
  • the data signal writing module 101 receives the scan signal SPAW and the data signal Da, and is electrically connected to the gate of the driving transistor Td.
  • the data signal writing module 101 is used for writing the data signal Da into the gate of the driving transistor Td under the control of the scanning signal SPAW.
  • the first control module 103 receives the control signal EN, the first voltage signal V1 and the second voltage signal V2, and is electrically connected to the first node A.
  • the first control module 103 is used for controlling the potential of the first node A under the control of the control signal EN, the first voltage signal V1 and the second voltage signal V2.
  • the bistable circuit module 104 receives the first power signal VDD and the third power signal Vneg, and is electrically connected to the first node A and the second node B.
  • the bistable circuit module 104 is used for controlling the potential of the second node B under the control of the potential of the first node A, the first power signal VDD and the third power signal Vneg.
  • the second control module 105 receives the third power signal Vneg, and is electrically connected to the second node B and the gate of the driving transistor Td.
  • the second control module 105 is used for controlling the potential of the gate of the driving transistor Td under the control of the potential of the second node B and the third power signal Vneg.
  • the storage module 102 is electrically connected to the gate of the driving transistor Td and the second terminal of the light emitting device D. As shown in FIG. The storage module 102 is used to store the potential of the gate of the driving transistor Td.
  • the first control module 103 controls to change the potential of the first node A.
  • the bistable circuit module 104 can rapidly change the potential of the second node B under the control of the potential of the first node A.
  • the second control module 105 rapidly changes the potential of the gate of the driving transistor Td under the control of the potential of the second node B, thereby turning off the driving transistor Td. It can be understood that, in the light-emitting phase, when the driving transistor Td is turned off, the light-emitting device D also stops emitting light.
  • the potential of the gate of the driving transistor Td can be changed rapidly, so as to accurately control the light-emitting time of the light-emitting device D.
  • the light emitting device D may be a mini light emitting diode, a micro light emitting diode or an organic light emitting diode.
  • the first end of the light emitting device D may be one of the anode or cathode of the light emitting diode.
  • the second terminal of the light emitting device D may be the other pole of the anode or the cathode of the light emitting diode.
  • both the first power signal VDD and the second power signal VSS are used to output a preset voltage value.
  • the potential of the first power signal VDD is greater than the potential of the second power signal VSS.
  • the potential of the second power signal VSS may be the potential of the ground terminal.
  • the third power signal Vneg may be the same signal as the second power signal VSS, or may be a different signal.
  • the driving transistor Td is an N-type transistor
  • both the third power signal Vneg and the second power signal VSS may be ground signals.
  • the third power signal Vneg may be a high level signal.
  • FIG. 2 is a schematic circuit diagram of the lighting circuit shown in FIG. 1 provided in the present application.
  • the data signal writing module 101 includes a first transistor T1 .
  • the gate of the first transistor T1 is connected to the scanning signal SPAW.
  • One of the source and the drain of the first transistor T1 is connected to the data signal Da.
  • the other of the source and the drain of the first transistor T1 is electrically connected to the gate of the driving transistor Td.
  • the data signal writing module 101 can also be formed by connecting multiple transistors in series.
  • the storage module 102 includes a storage capacitor C1.
  • One end of the storage capacitor C1 is electrically connected to the gate of the driving transistor Td.
  • the other end of the storage capacitor C1 is electrically connected to the second end of the light emitting device D. As shown in FIG.
  • the first control module 103 includes a second transistor T2 and a first capacitor C2.
  • the gate of the second transistor T2 is connected to the control signal EN.
  • One of the source and the drain of the second transistor T2 is connected to the first voltage signal V1.
  • the other of the source and the drain of the second transistor T2 and one end of the first capacitor C2 are electrically connected to the first node A.
  • the other end of the first capacitor C2 is connected to the second voltage signal V2.
  • the data signal writing module 101 can also be formed by connecting multiple transistors in series and then connecting them in parallel with the first capacitor C2.
  • the second transistor T2 and the first capacitor C2 are set in the first control module 103 . Then, the potential of the first node A is controlled by the control signal EN, the first voltage signal V1 and the second voltage signal V2.
  • This setting does not require an external driver chip to provide a very high frequency SPWM (Sinusoidal Pulse Width Modulation, sinusoidal pulse width modulation) signal, lower requirements for the driver chip.
  • FIG. 3 is a first schematic circuit diagram of the bistable circuit module provided in this application.
  • the bistable circuit module 104 includes a first inverter 104a and a second inverter 104b. Both the first inverter 104 a and the second inverter 104 b are NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor) inverters.
  • NMOS N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor
  • the first inverter 104a includes a third transistor T3 and a fourth transistor T4.
  • the gate of the third transistor T3 and one of the source and the drain of the third transistor T3 are connected to the first power signal VDD.
  • the other of the source and the drain of the third transistor T3 and one of the source and the drain of the fourth transistor T4 are both electrically connected to the second node B.
  • the gate of the fourth transistor T4 is electrically connected to the first node A.
  • the other of the source and the drain of the fourth transistor T4 is connected to the third power signal Vneg.
  • the second inverter 104b includes a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 and one of the source and the drain of the fifth transistor T5 are connected to the first power signal VDD.
  • the other of the source and the drain of the fifth transistor T5 and one of the source and the drain of the sixth transistor T6 are both electrically connected to the first node A.
  • the gate of the sixth transistor T6 is electrically connected to the second node B.
  • the other of the source and the drain of the sixth transistor T6 is connected to the third power signal Vneg.
  • FIGS. 4A-4B are schematic diagrams of voltage changes at the first node and the second node in the bistable circuit module provided by the present application.
  • the curve L1 represents the relationship between the input voltage and the output voltage of a single inverter.
  • the curve L2 represents the variation relationship between the input voltage and the output voltage of the bistable circuit module 104 , that is, the voltage variation relationship between the first node A and the second node B. It can be seen that it takes a certain time for the state transition of the input and output voltages of a single inverter. For the bistable circuit module 104 , when the state of the input signal of the bistable circuit module 104 is switched, the state of the output signal can be quickly switched.
  • the first node A is given an initial high potential through the control signal EN and the first voltage signal V1. Both the third transistor T3 and the fourth transistor T4 are turned on. Since the resistance of the fourth transistor T4 is smaller than the resistance of the third transistor T3, according to the principle of voltage division, the initial potential VB of the second node B is at a low level.
  • the fourth transistor T4 is turned off, and the third transistor T3 is turned on.
  • the first power signal VDD is transmitted to the second node B through the third transistor T3, so that the potential VB of the second node B increases.
  • the fifth transistor T5 and the sixth transistor T6 are gradually turned on.
  • the resistance of the sixth transistor T6 is smaller than the resistance of the fifth transistor T5. Therefore, according to the principle of voltage division, the potential VA of the first node A is at a low level, so that the potential VA of the first node A further decreases.
  • the further reduction of the potential VA of the first node A causes the potential VB of the second node B to flip to a high level more rapidly. Therefore, through the above positive feedback process, the inversion speed of the potential VB of the second node B is accelerated, thereby obtaining a VB output similar to a square wave.
  • the channel aspect ratio of the third transistor T3 is smaller than the channel aspect ratio of the fourth transistor T4.
  • the resistance of a transistor is related to the size of the device. The larger the channel width-to-length ratio W/L of the transistor, the smaller the resistance under the same conditions.
  • the first inverter 104a when the potential VA of the first node A is low, the fourth transistor T4 is turned off, the third transistor T3 is turned on, and the potential VB of the second node B is high. And when the VA of the first node A is high, both the third transistor T3 and the fourth transistor T4 are turned on.
  • R(T3)>R(T4) should be made, so that when both devices are turned on, the divided voltage on the fourth transistor T4 is small, and the potential of the second node B VB is close to the voltage of the third power supply signal Vneg, and thus is at a low level.
  • the channel aspect ratio of the fifth transistor T5 is smaller than the channel aspect ratio of the sixth transistor T6.
  • the channel aspect ratio of the fifth transistor T5 is smaller than the channel aspect ratio of the sixth transistor T6.
  • both the first inverter 104a and the second inverter 104b can also be PMOS (P-Metal-Oxide-Semiconductor, P-type metal-oxide-semiconductor) inversion device.
  • PMOS P-Metal-Oxide-Semiconductor, P-type metal-oxide-semiconductor
  • the second control module 105 includes a seventh crystal T7.
  • the gate of the seventh transistor T7 is electrically connected to the second node B.
  • One of the source and the drain of the seventh transistor T7 is connected to the third power signal Vneg.
  • the other of the source and the drain of the seventh transistor T7 is electrically connected to the gate of the driving transistor Td.
  • the second control module 105 can also be formed by using a plurality of transistors connected in series.
  • FIG. 5 is a second schematic circuit diagram of the bistable circuit module provided in the present application.
  • the bistable circuit module 104 includes a first inverter 104a and a second inverter 104b. Both the first inverter 104a and the second inverter 104b are CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) inverter.
  • CMOS Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor
  • the first inverter 104a includes a third transistor T3 and a fourth transistor T4.
  • the gates of the third transistor T3 and the fourth transistor T4 are electrically connected to the first node A.
  • One of the source and the drain of the third transistor T3 is connected to the first power signal VDD.
  • the other of the source and the drain of the third transistor T3 and one of the source and the drain of the fourth transistor T4 are both electrically connected to the second node B. As shown in FIG.
  • the other of the source and the drain of the fourth transistor T4 is connected to the third power signal Vneg.
  • the second inverter 104b includes a fifth transistor T5 and a sixth transistor T6.
  • the gates of the fifth transistor T5 and the sixth transistor T6 are electrically connected to the second node B.
  • One of the source and the drain of the fifth transistor T5 is connected to the first power signal VDD.
  • the other of the source and the drain of the fifth transistor T5 and one of the source and the drain of the sixth transistor T6 are both electrically connected to the first node A. As shown in FIG.
  • the other of the source and the drain of the sixth transistor T6 is connected to the third power signal Vneg.
  • the third transistor T3 and the fifth transistor T5 are P-type transistors.
  • the fourth transistor T4 and the sixth transistor T6 are N-type transistors.
  • the first inverter 104a when the potential VA of the first node A is high, the third transistor T3 is turned off, the fourth transistor T4 is turned on, and the potential VB of the second node B is high. And when the potential VA of the first node A is low, the third transistor T3 is turned on, the fourth transistor T4 is turned off, and the potential VB of the second node B is low.
  • the second inverter 104b when the potential VB of the second node B is high, the fifth transistor T5 is turned off, the sixth transistor T6 is turned on, and the potential VA of the first node A is low. And when the potential VB of the second node B is low, the fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the potential VA of the first node A is high.
  • the third transistor T3 and the fourth transistor T4 are turned on in time division. Therefore, there is no need to define the resistance of the third transistor T3 and the fourth transistor T4, that is, it is not necessary to define the channel aspect ratio of the third transistor T3 and the fourth transistor T4. Therefore, the manufacturing process is simpler. The same is true for the second inverter 104b, which will not be repeated here.
  • the light-emitting circuit 100 provided in this application uses a light-emitting circuit with a 7T2C (7 transistors and 2 capacitors) structure to control the light-emitting device D, uses fewer components, has a simple and stable structure, and saves costs.
  • the light emitting circuit 100 has the advantages of high grayscale segmentation accuracy and low requirements on the signal of the driving chip.
  • the seventh transistor T7 does not need to undergo a slow turn-on process, even if the threshold voltages of the seventh transistor T7 at different positions are different, there is no need to design a compensation circuit for the seventh transistor T7.
  • the driving transistor Td, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be low temperature polysilicon thin film transistors, One or more of oxide semiconductor thin film transistors or amorphous silicon thin film transistors.
  • the transistors in the lighting circuit 100 provided in the present application may also be P-type transistors or N-type transistors.
  • the driving transistor Td, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 is an N-type transistor as an example for illustration, but it should not be understood as a limitation to the present application.
  • FIG. 6 is a timing diagram of the lighting circuit shown in FIG. 2 provided by the present application.
  • the combination of the scan signal SPAW, the data signal Da, the control signal EN, the first voltage signal V1 and the second voltage signal V2 corresponds to the preparation phase t1 and the light emitting phase t2 successively. That is, within one frame time, the driving control sequence of the lighting circuit 100 shown in FIG. 2 provided in the present application includes a preparation phase t1 and a lighting phase t2.
  • FIG. 6 only shows a part of the signal timing diagram of the lighting circuit 100 , which should not be construed as a limitation to the present application.
  • both the scan signal SPAW and the control signal EN are at low level. Both the first transistor T1 and the second transistor T2 are turned off. The second voltage signal V2 is at a high level. Through the coupling effect of the first capacitor C2, the potential of the first node A is high. Both the third transistor T3 and the fourth transistor T4 are turned on. Since the resistance of the fourth transistor T4 is smaller than the resistance of the third transistor T3, the potential of the second node B is low. The sixth transistor T6 is turned off, the fifth transistor T5 is turned on, and the potential of the first node A is continuously high.
  • the gate potential Vg of the driving transistor Td is low.
  • the driving transistor Td is turned off.
  • the light emitting circuit is not conducting. Therefore, the current I LED flowing through the light emitting device D is 0, and the light emitting device D does not emit light.
  • the light-emitting circuit refers to the conduction path in the light-emitting circuit 100 when the light-emitting device D emits light.
  • the scanning signal SPAW changes from a low level to a high level.
  • the first transistor T1 is turned on.
  • the data signal Da is written into the gate of the driving transistor Td through the first transistor T1 and stored in the storage capacitor C1.
  • the driving transistor Td is turned on, and the first power signal VDD is transmitted to the anode of the light emitting device D through the driving transistor Td.
  • the light-emitting circuit is turned on, and the light-emitting device D emits light.
  • the control signal EN changes from low level to high level.
  • the second transistor T2 is turned on.
  • the first voltage signal V1 is at a high level.
  • the first voltage signal V1 is transmitted to the first node A through the first transistor T1.
  • the potential of the first node A is high level.
  • the second voltage signal V2 is a triangular wave signal. That is, the voltage value of the second voltage signal V2 decreases linearly during the light-emitting period t2.
  • the second voltage signal V2 may also be another signal whose voltage value keeps decreasing, which is not specifically limited in this application.
  • the potential of the first node A decreases continuously due to the coupling effect of the first capacitor C2.
  • the voltage value of the second voltage signal V2 drops to a certain value (depending on the threshold voltage of the fourth transistor T4 )
  • the potential of the second node B flips rapidly from low level to high level.
  • the fourth transistor T4 is quickly turned on, so that the gate potential of the driving transistor Td is quickly pulled down to the potential of the third power signal Vneg.
  • the driving transistor Td is turned off rapidly. Then the light-emitting device D rapidly changes from the light-emitting state to the non-light-emitting state.
  • the driving transistor Td is turned off quickly, the light emitting device D is rapidly turned into a non-light emitting state, so the light emitting time of the light emitting device D can be precisely controlled.
  • the speed of potential change of the first node A can be controlled by controlling the magnitude of the initial voltage value of the second voltage signal V2, thereby controlling the light-emitting time of the light-emitting device D. It can be seen from the foregoing analysis that in the initial stage of the light-emitting period t2, the potential of the first node A is at a high level, and the seventh transistor T7 is turned off, which does not affect the gate potential of the driving transistor Td. Only when the potential of the first node A drops to a certain value, the potential of the second node B flips rapidly from a level to a high level. Then, the seventh transistor T7 is turned on to pull down the gate potential of the driving transistor Td.
  • the falling speed of the potential of the first node A depends on the initial voltage value of the second voltage signal V2. Therefore, by controlling the initial voltage value of the second voltage signal V2, the light emitting time of the light emitting device D can be controlled. Further, by controlling the light-emitting time of the light-emitting device D, the light-emitting brightness of the light-emitting device D can be controlled, thereby realizing some functions such as brightness adjustment, which is not specifically limited in the present application.
  • FIG. 7 is a second structural schematic diagram of the lighting circuit provided by the present application.
  • the lighting circuit 100 further includes a sensing module 106 .
  • the sensing module 106 receives the sensing signal Se, and is electrically connected to one of the source and the drain of the driving transistor Td and the initial voltage input terminal Vref.
  • the sensing module 106 is used for sensing the threshold voltage of the driving transistor Td under the control of the sensing signal Se.
  • FIG. 8 is a schematic circuit diagram of the lighting circuit shown in FIG. 7 provided by the present application.
  • the sensing module 106 includes an eighth transistor T8.
  • the gate of the eighth transistor T8 is connected to the sensing signal Se.
  • One of the source and the drain of the eighth transistor T8 is electrically connected to the other of the source and the drain of the driving transistor Td.
  • the other of the source and the drain of the eighth transistor T8 is electrically connected to the initial voltage input terminal Vref.
  • the eighth transistor T8 may be an N-type transistor or a P-type transistor.
  • the sensing module 106 can also be formed by connecting multiple transistors in series.
  • a threshold voltage detection stage can be inserted as required within one frame display period of the light-emitting circuit 100 to realize the function of threshold voltage compensation, thereby improving Uniformity of light emitting brightness of multiple light emitting devices D.
  • an internal compensation circuit may be added in the light emitting circuit 100 to compensate the threshold voltage of the driving transistor Td.
  • a lighting control module may also be added to the lighting circuit 100 .
  • the lighting control module is connected with the lighting control signal and connected in series with the lighting circuit.
  • the light emitting control module is used to control the conduction of the light emitting circuit under the control of the light emitting control signal, so as to prevent the light emitting device D from emitting light in the non-light emitting stage. That is to say, the first control module 103 , the bistable circuit module 104 and the second control module 105 in the lighting circuit 100 provided in this application can be applied to various types of lighting circuits, and details will not be repeated here.
  • FIG. 9 is a schematic structural diagram of a backlight module provided by the present application.
  • the embodiment of the present application also provides a backlight module 200, which includes data lines 10, scanning lines 20, control lines 30, first signal lines 40, second signal lines 50, first power lines 60, and second power lines 70 , the third power source 80 and the lighting circuit 100 described in any one of the above embodiments.
  • the data line 10 is used to provide data signals.
  • the scan lines 20 are used to provide scan signals.
  • the control line 30 is used to provide control signals.
  • the first signal line 40 is used for providing a first voltage signal.
  • the second signal line 50 is used for providing the first voltage signal.
  • the first power line 60 is used to provide a first power signal.
  • the second power line 70 is used to provide a second power signal.
  • the third power line 80 is used for providing a third power signal.
  • the light emitting circuit 100 is electrically connected to the data line 10 , the scan line 20 , the control line 30 , the first signal line 40 , the second signal line 50 , the first power line 60 , the second power line 70 and the third power source 80 .
  • the light emitting circuit 100 For details of the light emitting circuit 100 , reference may be made to the above description of the light emitting circuit, which will not be repeated here.
  • one of the source and the drain of the driving transistor is electrically connected to the first power line 60 .
  • the second end of the light emitting device D is electrically connected to the second power line 70 .
  • the data signal writing module 101 is electrically connected to the data line 10 and the scan line 20 .
  • the first control module 103 is electrically connected to the control line 30 , the first signal line 40 and the second signal line 50 .
  • the bistable circuit module 104 is electrically connected to the first power line 60 and the third power line 80 .
  • the second control module 105 is electrically connected to the third power line 80 .
  • the light emitting circuit 100 includes a light emitting device, a driving transistor, a data signal writing module, a first control module, a bistable circuit module and a second control module.
  • the first control module, the bistable circuit module and the second control module work together to rapidly change the potential of the gate of the drive transistor, accurately control the light-emitting time of the light-emitting device, and improve the quality of the light source of the backlight module 200 .
  • FIG. 10 is a schematic structural diagram of a display panel provided by the present application.
  • the embodiment of the present application also provides a display panel 300, including a plurality of pixel units 301 arranged in an array, and each pixel unit 301 includes the above-mentioned light emitting circuit 100, for details, please refer to the above description of the light emitting circuit 100 , which will not be described here.
  • the light emitting circuit 100 includes a light emitting device, a driving transistor, a data signal writing module, a first control module, a bistable circuit module and a second control module.
  • the first control module, the bistable circuit module and the second control module work together to rapidly change the potential of the gate of the drive transistor, thereby accurately controlling the light-emitting time of the light-emitting device.
  • the display picture of the display panel 300 is improved.

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Abstract

一种发光电路（100）、背光模组以及显示面板。发光电路（100）包括发光器件（D）、驱动晶体管（Td）、数据信号写入模块（101）、第一控制模块（103）、双稳态电路模块（104）以及第二控制模块（105）。其中，第一控制模块（103）、双稳态电路模块（104）以及第二控制模块（105）协同工作，以控制驱动晶体管（Td）的栅极的电位翻转。通过在发光电路（100）中设置双稳态电路模块（104），能够快速改变驱动晶体管（Td）的栅极的电位，从而精确控制发光器件的发光时间。

Description

发光电路、背光模组以及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种发光电路、背光模组以及显示面板。
 背景技术
迷你发光二极管、微型发光二极管以及有机发光二极管等发光器件具有高亮度、高对比度及高色域等优点，目前已被广泛地应用于高性能显示领域中。发光二极管显示技术目前常见的驱动方式有PAM（Pulse Amplitude Modulation，脉冲幅度调制）、PWM（Pulse Width Modulation，脉冲宽度调制）及其混合。
 技术问题
PWM驱动方式具有电流恒定、发光器件光效高、低灰阶显示画质好等优点。因此，PWM和基于PWM的混合驱动显示得到了广泛的研究。但是在现有的PWM驱动方式中，存在发光电路中发光器件的发光时间难以精确控制的问题。
 技术解决方案
本申请提供一种发光电路、背光模组以及显示面板，以解决现有发光电路中发光器件的发光时间难以精确控制的技术问题。
本申请提供一种发光电路，其包括：
驱动晶体管，所述驱动晶体管的源极和漏极中的一者接入第一电源信号；
发光器件，所述发光器件的第一端与所述驱动晶体管的源极和漏极的另一者电连接，所述发光器件的第二端接入第二电源信号；
数据信号写入模块，所述数据信号写入模块接入扫描信号和数据信号，并电性连接于所述驱动晶体管的栅极，所述数据信号写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
第一控制模块，所述第一控制模块接入控制信号、第一电压信号以及第二电压信号，并电性连接于第一节点，所述第一控制模块用于在所述控制信号、所述第一电压信号以及所述第二电压信号的控制下控制所述第一节点的电位；
双稳态电路模块，所述双稳态电路模块接入所述第一电源信号和第三电源信号，并电性连接于所述第一节点和第二节点，所述双稳态电路模块用于在所述第一节点的电位、所述第一电源信号以及所述第三电源信号的控制下控制所述第二节点的电位；
第二控制模块，所述第二控制模块接入所述第三电源信号，并电性连接于所述第二节点和所述驱动晶体管的栅极，所述第二控制模块用于在所述第二节点的电位以及所述第三电源信号的控制下控制所述驱动晶体管的栅极的电位；
存储模块，所述存储模块电性连接于所述驱动晶体管的栅极以及发光器件的第二端，所述存储模块用于存储所述驱动晶体管的栅极的电位。
可选的，在本申请一些实施例中，所述数据信号写入模块包括第一晶体管，所述第一晶体管的栅极接入所述扫描信号，所述第一晶体管的源极和漏极中的一者接入所述数据信号，所述第一晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接；
所述存储模块包括存储电容，所述存储电容的一端电性连接于所述驱动晶体管的栅极，所述存储电容的另一端电性连接于所述发光器件的第二端。
可选的，在本申请一些实施例中，所述第一控制模块包括第二晶体管和第一电容；
所述第二晶体管的栅极接入所述控制信号，所述第二晶体管的源极和漏极中的一者接入所述第一电压信号，所述第二晶体管的源极和漏极中的另一者以及所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端接入所述第二电压信号。
可选的，在本申请一些实施例中，所述双稳态电路模块包括第一反相器和第二反相器；
所述第一反相器包括第三晶体管和第四晶体管，所述第三晶体管的栅极以及所述第三晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第三晶体管的源极和漏极中的另一者以及所述第四晶体管的源极和漏极中的一者均与所述第二节点电性连接，所述第四晶体管的栅极与所述第一节点电性连接，所述第四晶体管的源极和漏极中的另一者接入所述第三电源信号；
所述第二反相器包括第五晶体管和第六晶体管，所述第五晶体管的栅极以及所述第五晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者以及所述第六晶体管的源极和漏极中的一者均与所述第一节点电性连接，所述第六晶体管的栅极与所述第二节点电性连接，所述第六晶体管的源极和漏极中的另一者接入所述第三电源信号。
可选的，在本申请一些实施例中，所述第三晶体管的沟道长宽比小于所述第四晶体管的沟道长宽比，所述第五晶体管的沟道长宽比小于所述第六晶体管的沟道长宽比。
可选的，在本申请一些实施例中，所述双稳态电路模块包括第一反相器和第二反相器；
所述第一反相器包括第三晶体管和第四晶体管，所述第三晶体管和所述第四晶体管的栅极均电性连接于所述第一节点，所述第三晶体管的源极和漏极中的一者接入所述第一电源信号，所述第三晶体管的源极和漏极中的另一者以及所述第四晶体管的源极和漏极中的一者均与所述第二节点电性连接，所述第四晶体管的源极和漏极中的另一者接入所述第三电源信号；
所述第二反相器包括第五晶体管和第六晶体管，所述第五晶体管和所述第六晶体管的栅极均电性连接于所述第二节点，所述第五晶体管的源极和漏极中的一者接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者以及所述第六晶体管的源极和漏极中的一者均与所述第一节点电性连接，所述第六晶体管的源极和漏极中的另一者接入所述第三电源信号；
其中，所述第三晶体管与所述第五晶体管为P型晶体管，所述第四晶体管与所述第六晶体管为N型晶体管。
可选的，在本申请一些实施例中，所述第三晶体管与所述第五晶体管为P型晶体管，所述第四晶体管与所述第六晶体管为N型晶体管，所述第三晶体管的沟道长宽比小于所述第四晶体管的沟道长宽比，所述第五晶体管的沟道长宽比小于所述第六晶体管的沟道长宽比。
可选的，在本申请一些实施例中，所述第二控制模块包括第七晶体，所述第七晶体管的栅极与所述第二节点电性连接，所述第七晶体管的源极和漏极中的一者接入所述第三电源信号，所述第七晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接。
可选的，在本申请一些实施例中，所述发光电路还包括感测模块，所述感测模块接入感测信号，并电性连接于所述驱动晶体管的源极和漏极中的另一者以及初始电压输入端，所述感测模块用于在所述感测信号的控制下感测所述驱动晶体管的阈值电压。
可选的，在本申请一些实施例中，所述感测模块包括第八晶体管，所述第八晶体管的栅极接入所述感测信号，所述第八晶体管的源极和漏极中的一者电性连接于所述驱动晶体管的源极和漏极中的另一者，所述第八晶体管的源极和漏极中的另一者电性连接于所述初始电压输入端。
可选的，在本申请一些实施例中，所述第二电压信号为三角波信号。
相应的，本申请还提供一种背光模组，其包括：
数据线，所述数据线用于提供数据信号；
扫描线，所述扫描线用于提供扫描信号；
控制线，所述使能线用于提供控制信号；
第一信号线，所述第一信号线用于提供第一电压信号；
第二信号线，所述第二信号线用于提供第二电压信号；
第一电源线，所述第一电源线用于提供第一电源信号；
第二电源线，所述第二电源线用于提供第二电源信号；
第三电源线，所述第三电源线用于提供第三电源信号；以及
发光电路，所述发光电路包括：
驱动晶体管，所述驱动晶体管的源极和漏极中的一者接入所述第一电源信号；
发光器件，所述发光器件的第一端与所述驱动晶体管的源极和漏极的另一者电连接，所述发光器件的第二端接入所述第二电源信号；
数据信号写入模块，所述数据信号写入模块接入所述扫描信号和所述数据信号，并电性连接于所述驱动晶体管的栅极，所述数据信号写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
第一控制模块，所述第一控制模块接入所述控制信号、所述第一电压信号以及所述第二电压信号，并电性连接于第一节点，所述第一控制模块用于在所述控制信号、所述第一电压信号以及所述第二电压信号的控制下控制所述第一节点的电位；
双稳态电路模块，所述双稳态电路模块接入所述第一电源信号和所述第三电源信号，并电性连接于所述第一节点和第二节点，所述双稳态电路模块用于在所述第一节点的电位、所述第一电源信号以及所述第三电源信号的控制下控制所述第二节点的电位；
第二控制模块，所述第二控制模块接入所述第三电源信号，并电性连接于所述第二节点和所述驱动晶体管的栅极，所述第二控制模块用于在所述第二节点的电位以及所述第三电源信号的控制下控制所述驱动晶体管的栅极的电位；
存储模块，所述存储模块电性连接于所述驱动晶体管的栅极以及所述发光器件的第二端，所述存储模块用于存储所述驱动晶体管的栅极的电位。
可选的，在本申请一些实施例中，所述数据信号写入模块包括第一晶体管，所述第一晶体管的栅极接入所述扫描信号，所述第一晶体管的源极和漏极中的一者接入所述数据信号，所述第一晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接；
所述存储模块包括存储电容，所述存储电容的一端电性连接于所述驱动晶体管的栅极，所述存储电容的另一端电性连接于所述发光器件的第二端。
可选的，在本申请一些实施例中，所述第一控制模块包括第二晶体管和第一电容；
所述第二晶体管的栅极接入所述控制信号，所述第二晶体管的源极和漏极中的一者接入所述第一电压信号，所述第二晶体管的源极和漏极中的另一者以及所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端接入所述第二电压信号。
可选的，在本申请一些实施例中，所述双稳态电路模块包括第一反相器和第二反相器；
所述第一反相器包括第三晶体管和第四晶体管，所述第三晶体管的栅极以及所述第三晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第三晶体管的源极和漏极中的另一者以及所述第四晶体管的源极和漏极中的一者均与所述第二节点电性连接，所述第四晶体管的栅极与所述第一节点电性连接，所述第四晶体管的源极和漏极中的另一者接入所述第三电源信号；
所述第二反相器包括第五晶体管和第六晶体管，所述第五晶体管的栅极以及所述第五晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者以及所述第六晶体管的源极和漏极中的一者均与所述第一节点电性连接，所述第六晶体管的栅极与所述第二节点电性连接，所述第六晶体管的源极和漏极中的另一者接入所述第三电源信号。
可选的，在本申请一些实施例中，所述第三晶体管的沟道长宽比小于所述第四晶体管的沟道长宽比，所述第五晶体管的沟道长宽比小于所述第六晶体管的沟道长宽比。
可选的，在本申请一些实施例中，所述双稳态电路模块包括第一反相器和第二反相器；
所述第一反相器包括第三晶体管和第四晶体管，所述第三晶体管和所述第四晶体管的栅极均电性连接于所述第一节点，所述第三晶体管的源极和漏极中的一者接入所述第一电源信号，所述第三晶体管的源极和漏极中的另一者以及所述第四晶体管的源极和漏极中的一者均与所述第二节点电性连接，所述第四晶体管的源极和漏极中的另一者接入所述第三电源信号；
所述第二反相器包括第五晶体管和第六晶体管，所述第五晶体管和所述第六晶体管的栅极均电性连接于所述第二节点，所述第五晶体管的源极和漏极中的一者接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者以及所述第六晶体管的源极和漏极中的一者均与所述第一节点电性连接，所述第六晶体管的源极和漏极中的另一者接入所述第三电源信号；
其中，所述第三晶体管与所述第五晶体管为P型晶体管，所述第四晶体管与所述第六晶体管为N型晶体管。
相应的，本申请还提供一种显示面板，所述显示面板包括多个呈阵列排布的像素单元，每一所述像素单元均包括发光电路，所述发光电路包括：
驱动晶体管，所述驱动晶体管的源极和漏极中的一者接入第一电源信号；
发光器件，所述发光器件的第一端与所述驱动晶体管的源极和漏极的另一者电连接，所述发光器件的第二端接入第二电源信号；
数据信号写入模块，所述数据信号写入模块接入扫描信号和数据信号，并电性连接于所述驱动晶体管的栅极，所述数据信号写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
第一控制模块，所述第一控制模块接入控制信号、第一电压信号以及第二电压信号，并电性连接于第一节点，所述第一控制模块用于在所述控制信号、所述第一电压信号以及所述第二电压信号的控制下控制所述第一节点的电位；
双稳态电路模块，所述双稳态电路模块接入所述第一电源信号和第三电源信号，并电性连接于所述第一节点和第二节点，所述双稳态电路模块用于在所述第一节点的电位、所述第一电源信号以及所述第三电源信号的控制下控制所述第二节点的电位；
第二控制模块，所述第二控制模块接入所述第三电源信号，并电性连接于所述第二节点和所述驱动晶体管的栅极，所述第二控制模块用于在所述第二节点的电位以及所述第三电源信号的控制下控制所述驱动晶体管的栅极的电位；
存储模块，所述存储模块电性连接于所述驱动晶体管的栅极以及所述发光器件的第二端，所述存储模块用于存储所述驱动晶体管的栅极的电位。
可选的，在本申请一些实施例中，所述第一控制模块包括第二晶体管和第一电容；
所述第二晶体管的栅极接入所述控制信号，所述第二晶体管的源极和漏极中的一者接入所述第一电压信号，所述第二晶体管的源极和漏极中的另一者以及所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端接入所述第二电压信号。
可选的，在本申请一些实施例中，所述双稳态电路模块包括第一反相器和第二反相器；
所述第一反相器包括第三晶体管和第四晶体管，所述第三晶体管的栅极以及所述第三晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第三晶体管的源极和漏极中的另一者以及所述第四晶体管的源极和漏极中的一者均与所述第二节点电性连接，所述第四晶体管的栅极与所述第一节点电性连接，所述第四晶体管的源极和漏极中的另一者接入所述第三电源信号；
所述第二反相器包括第五晶体管和第六晶体管，所述第五晶体管的栅极以及所述第五晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者以及所述第六晶体管的源极和漏极中的一者均与所述第一节点电性连接，所述第六晶体管的栅极与所述第二节点电性连接，所述第六晶体管的源极和漏极中的另一者接入所述第三电源信号。
可选的，在本申请一些实施例中，所述第三晶体管的沟道长宽比小于所述第四晶体管的沟道长宽比，所述第五晶体管的沟道长宽比小于所述第六晶体管的沟道长宽比。
 有益效果
本申请公开一种发光电路、背光模组以及显示面板。发光电路包括发光器件、驱动晶体管、数据信号写入模块、第一控制模块、双稳态电路模块以及第二控制模块。其中，第一控制模块、双稳态电路模块以及第二控制模块协同工作，以控制驱动晶体管的栅极的电位翻转。本申请通过在发光电路中设置双稳态电路模块，能够快速改变驱动晶体管的栅极的电位，从而精确控制发光器件的发光时间。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1是本申请提供的发光电路的第一结构示意图；
图2是本申请提供的图1所示的发光电路的电路示意图；
图3是本申请提供的双稳态电路模块的第一电路示意图；
图4A-4B是本申请提供的双稳态电路模块中第一节点和第二节点的电压变化示意图；
图5是本申请提供的双稳态电路模块的第二电路示意图；
图6是本申请提供的图2所示的发光电路的时序图；
图7是本申请提供的发光电路的第二结构示意图；
图8是本申请提供的图7所示的发光电路的电路示意图；
图9是本申请提供的背光模组的一种结构示意图；
图10是本申请提供的显示面板的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获取的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“第一”和“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”和“第二”等的特征可以明示或者隐含地包括一个或者更多个所述特征，因此不能理解为对本申请的限制。
本申请提供一种发光电路、背光模组以及显示面板，以下进行详细说明。需要说明的是，以下实施例的描述顺序不作为对本申请实施例优选顺序的限定。
请参阅图1，图1是本申请提供的发光电路的第一结构示意图。本申请提供的发光电路100包括发光器件D、驱动晶体管Td、数据信号写入模块101、存储模块102、第一控制模块103、双稳态电路模块104以及第二控制模块105。
其中，驱动晶体管Td的源极和漏极中的一者接入第一电源信号VDD。发光器件D的第一端与驱动晶体管Td的源极和漏极的另一者电连接。发光器件D的第二端接入第二电源信号VSS。
数据信号写入模块101接入扫描信号SPAW和数据信号Da，并电性连接于驱动晶体管Td的栅极。数据信号写入模块101用于在扫描信号SPAW的控制下，将数据信号Da写入驱动晶体管Td的栅极。
第一控制模块103接入控制信号EN、第一电压信号V1以及第二电压信号V2，并电性连接于第一节点A。第一控制模块103用于在控制信号EN、第一电压信号V1以及第二电压信号V2的控制下控制第一节点A的电位。
双稳态电路模块104接入第一电源信号VDD和第三电源信号Vneg，并电性连接于第一节点A和第二节点B。双稳态电路模块104用于在第一节点A的电位、第一电源信号VDD以及第三电源信号Vneg的控制下控制第二节点B的电位。
第二控制模块105接入第三电源信号Vneg，并电性连接于第二节点B和驱动晶体管Td的栅极。第二控制模块105用于在第二节点B的电位以及第三电源信号Vneg的控制下控制驱动晶体管Td的栅极的电位。
存储模块102电性连接于驱动晶体管Td的栅极以及发光器件D的第二端。存储模块102用于存储驱动晶体管Td的栅极的电位。
在本申请提供的发光电路100中，第一控制模块103控制改变第一节点A的电位。双稳态电路模块104能够在第一节点A的电位的控制下迅速改变第二节点B的电位。第二控制模块105在第二节点B的电位的控制下迅速改变驱动晶体管Td的栅极的电位，从而关闭驱动晶体管Td。可以理解的是，在发光阶段，当驱动晶体管Td关闭时，发光器件D也停止发光。由此，在第一控制模块103、双稳态电路模块104以及第二控制模块105的协同工作下，能够快速改变驱动晶体管Td的栅极的电位，从而精确控制发光器件D的发光时间。
在本申请中，发光器件D可以是迷你发光二极管、微型发光二极管或有机发光二极管。当发光器件D为上述发光二极管时。发光器件D的第一端可以是发光二极管的阳极或阴极中的一极。发光器件D的第二端可以是发光二极管的阳极或阴极中的另一极。
在本申请中，第一电源信号VDD和第二电源信号VSS均用于输出一预设电压值。此外，在本申请中，第一电源信号VDD的电位大于第二电源信号VSS的电位。具体的，第二电源信号VSS的电位可以为接地端的电位。当然，可以理解地，第二电源信号VSS的电位还可以为其它。需要说明的是，第三电源信号Vneg可以与第二电源信号VSS为同一信号，也可以是不相同的信号。比如，当驱动晶体管Td为N型晶体管时，第三电源信号Vneg与第二电源信号VSS可以均是接地信号。当驱动晶体管Td为P型晶体管时，第三电源信号Vneg可以是一高电平信号。
请参阅图2，图2是本申请提供的图1所示的发光电路的电路示意图。结合图1和图2所示，在本申请中，数据信号写入模块101包括第一晶体管T1。第一晶体管T1的栅极接入扫描信号SPAW。第一晶体管T1的源极和漏极中的一者接入数据信号Da。第一晶体管T1的源极和漏极中的另一者与驱动晶体管Td的栅极电性连接。当然，可以理解地，数据信号写入模块101还可以采用多个晶体管串联形成。
在本申请中，存储模块102包括存储电容C1。存储电容C1的一端电性连接于驱动晶体管Td的栅极。存储电容C1的另一端电性连接于发光器件D的第二端。
在本申请中，第一控制模块103包括第二晶体管T2和第一电容C2。第二晶体管T2的栅极接入控制信号EN。第二晶体管T2的源极和漏极中的一者接入第一电压信号V1。第二晶体管T2的源极和漏极中的另一者以及第一电容C2的一端电性连接于第一节点A。第一电容C2的另一端接入第二电压信号V2。当然，数据信号写入模块101还可以采用多个晶体管串联，然后与第一电容C2并联形成。
可以理解的是，本申请在第一控制模块103中设置第二晶体管T2和第一电容C2。然后，通过控制信号EN、第一电压信号V1以及第二电压信号V2控制第一节点A的电位。该设置不需要外部驱动芯片提供频率极高的SPWM(Sinusoidal Pulse Width Modulation，正弦脉冲宽度调制)信号，对驱动芯片的要求较低。
在本申请中，请参阅图3，图3是本申请提供的双稳态电路模块的第一电路示意图。其中，双稳态电路模块104包括第一反相器104a和第二反相器104b。第一反相器104a和第二反相器104b均为NMOS（N-Metal-Oxide-Semiconductor，N型金属-氧化物-半导体）反相器。
其中，第一反相器104a包括第三晶体管T3和第四晶体管T4。第三晶体管T3的栅极以及第三晶体管T3的源极和漏极中的一者均接入第一电源信号VDD。第三晶体管T3的源极和漏极中的另一者以及第四晶体管T4的源极和漏极中的一者均与第二节点B电性连接。第四晶体管T4的栅极与第一节点A电性连接。第四晶体管T4的源极和漏极中的另一者接入第三电源信号Vneg。
第二反相器104b包括第五晶体管T5和第六晶体管T6。第五晶体管T5的栅极以及第五晶体管T5的源极和漏极中的一者均接入第一电源信号VDD。第五晶体管T5的源极和漏极中的另一者以及第六晶体管T6的源极和漏极中的一者均与第一节点A电性连接。第六晶体管T6的栅极与第二节点B电性连接。第六晶体管T6的源极和漏极中的另一者接入第三电源信号Vneg。
具体的，请参阅图4A-4B，图4A-4B是本申请提供的双稳态电路模块中第一节点和第二节点的电压变化示意图。在图4A中，曲线L1表示单个反相器的输入电压与输出电压的变化关系。在图4B中，曲线L2表示双稳态电路模块104的输入电压与输出电压的变化关系，也即第一节点A和第二节点B的电压变化关系。可知，单个反相器的输入输出电压状态转换需要一定时间。而对于双稳态电路模块104而言，当双稳态电路模块104的输入信号状态转换时，输出信号状态能够快速转换。
比如，通过控制信号EN和第一电压信号V1给第一节点A一个初始高电位。第三晶体管T3和第四晶体管T4均打开。由于第四晶体管T4的电阻小于第三晶体管T3的电阻，根据分压原理，第二节点B的初始电位VB为低电平。当第一节点A的电位VA减小到某一数值时，第四晶体管T4关闭，第三晶体管T3打开。此时，第一电源信号VDD通过第三晶体管T3传输至第二节点B，使得第二节点B的电位VB增大。第二节点B的电位VB增大后，第五晶体管T5和第六晶体管T6逐渐打开。由于第六晶体管T6的电阻小于第五晶体管T5的电阻。因此，根据分压原理，第一节点A的电位VA为低电平，使得第一节点A的电位VA进一步减小。第一节点A的电位VA进一步减小使得第二节点B的电位VB更加快速翻转至高电平。由此，通过上述正反馈过程使第二节点B的电位VB翻转速度加快，从而得到类似方波的VB输出。
进一步的，在第一反相器104a中，第三晶体管T3的沟道长宽比小于第四晶体管T4的沟道长宽比。
可以理解的是，晶体管的电阻大小与器件尺寸有关。晶体管的沟道宽长比W/L越大，相同条件下电阻越小。而在第一反相器104a中，当第一节点A的电位VA为低时，第四晶体管T4关闭，第三晶体管T3导通，第二节点B的电位VB为高。而当第一节点A的VA为高时，第三晶体管T3和第四晶体管T4均打开。为了使第二节点B的电位VB为低，应使R(T3)＞R(T4)，从而在两个器件均导通时，第四晶体管T4上分压较小，第二节点B的电位VB接近第三电源信号Vneg的电压，从而为低电平。
同理，在第二反相器104b中，第五晶体管T5的沟道长宽比小于第六晶体管T6的沟道长宽比。具体分析可参阅上述内容，在此不再赘述。
当然，可以理解的是，在本申请中，第一反相器104a和第二反相器104b也可以均为PMOS（P-Metal-Oxide-Semiconductor，P型金属-氧化物-半导体）反相器。PMOS反相器的工作原理与NMOS反相器的工作原理相似，在此不再赘述。
在本申请中，第二控制模块105包括第七晶体T7。第七晶体管T7的栅极与第二节点B电性连接。第七晶体管T7的源极和漏极中的一者接入第三电源信号Vneg。第七晶体T7的源极和漏极中的另一者与驱动晶体管Td的栅极电性连接。当然，可以理解地，第二控制模块105还可以采用多个晶体管串联形成。
在本申请一些实施例中，请参阅图5，图5是本申请提供的双稳态电路模块的第二电路示意图。其中，双稳态电路模块104包括第一反相器104a和第二反相器104b。第一反相器104a和第二反相器104b均为CMOS（Complementary Metal Oxide Semiconductor，互补金属氧化物半导体）反相器。
其中，第一反相器104a包括第三晶体管T3和第四晶体管T4。第三晶体管T3和第四晶体管T4的栅极均电性连接于第一节点A。第三晶体管T3的源极和漏极中的一者接入第一电源信号VDD。第三晶体管T3的源极和漏极中的另一者以及第四晶体管T4的源极和漏极中的一者均与第二节点B电性连接。第四晶体管T4的源极和漏极中的另一者接入第三电源信号Vneg。
第二反相器104b包括第五晶体管T5和第六晶体管T6。第五晶体管T5和第六晶体管T6的栅极均电性连接于第二节点B。第五晶体管T5的源极和漏极中的一者接入第一电源信号VDD。第五晶体管T5的源极和漏极中的另一者以及第六晶体管T6的源极和漏极中的一者均与第一节点A电性连接。第六晶体管T6的源极和漏极中的另一者接入第三电源信号Vneg。
进一步的，第三晶体管T3与第五晶体管T5为P型晶体管。第四晶体管T4与第六晶体管T6为N型晶体管。
在第一反相器104a中，当第一节点A的电位VA为高时，第三晶体管T3关闭，第四晶体管T4导通，第二节点B的电位VB为高。而当第一节点A的电位VA为低时，第三晶体管T3导通，第四晶体管T4关闭，第二节点B的电位VB为低。在第二反相器104b中，当第二节点B的电位VB为高时，第五晶体管T5关闭，第六晶体管T6导通，第一节点A的电位VA为低。而当第二节点B的电位VB为低时，第五晶体管T5导通，第六晶体管T6关闭，第一节点A的电位VA为高。
可知，在第一反相器104a中，第三晶体管T3和第四晶体管T4分时导通。因此，不需要限定第三晶体管T3和第四晶体管T4的电阻，也即不需要限定第三晶体管T3和第四晶体管T4的沟道长宽比。由此，制成工艺更加简单。第二反相器104b亦然，在此不再赘述。
本申请提供的发光电路100采用7T2C（7个晶体管以及2个电容）结构的发光电路对发光器件D进行控制，用了较少的元器件，结构简单稳定，节约了成本。此外，发光电路100具有灰阶切分精度高、对驱动芯片的信号要求低等优点。而且由于第七晶体管T7无需经历缓慢打开的过程，即便不同位置处的第七晶体管T7的阈值电压不同，也无需设计针对第七晶体管T7的补偿电路。
在本申请中，驱动晶体管Td、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7可以为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管中的一种或者多种。此外，本申请提供的发光电路100中的晶体管还可以是P型晶体管或N型晶体管。
需要说明的是，本申请以下实施例中均以驱动晶体管Td、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6以及第七晶体管T7为N型晶体管为例进行说明，但不能理解为对本申请的限定。
请同时参阅图2、图3以及图6，图6是本申请提供的图2所示的发光电路的时序图。扫描信号SPAW、数据信号Da、控制信号EN、第一电压信号V1以及第二电压信号V2相组合先后对应于准备阶段t1和发光阶段t2。也即，在一帧时间内，本申请提供的图2所示的发光电路100的驱动控制时序包括准备阶段t1和发光阶段t2。图6仅示出了发光电路100的部分信号时序图，不能理解为对本申请的限定。
在准备阶段t1，扫描信号SPAW和控制信号EN均为低电平。第一晶体管T1和第二晶体管T2均关闭。第二电压信号V2为高电平。通过第一电容C2的耦合作用，第一节点A的电位为高。第三晶体管T3和第四晶体管T4均打开。由于第四晶体管T4的电阻小于第三晶体管T3的电阻，第二节点B的电位为低。第六晶体管T6关闭，第五晶体管T5打开，第一节点A的电位持续为高。
此时，驱动晶体管Td的栅极电位Vg为低。驱动晶体管Td关闭。发光回路不导通。因此，流经发光器件D的电流I LED为0，发光器件D不发光。其中，发光回路指的是发光器件D发光时，发光电路100中导通的通路。
在发光阶段t2，扫描信号SPAW由低电平转变为高电平。第一晶体管T1打开。数据信号Da通过第一晶体管T1写入驱动晶体管Td的栅极，并存储在存储电容C1内。驱动晶体管Td打开，第一电源信号VDD通过驱动晶体管Td传输至发光器件D的阳极。发光回路导通，发光器件D发光。
此时，控制信号EN由低电平转变为高电平。第二晶体管T2打开。第一电压信号V1为高电平。第一电压信号V1通过第一晶体管T1传输至第一节点A。第一节点A的电位为高电平。第二电压信号V2为一三角波信号。也即，第二电压信号V2的电压值在发光阶段t2线性降低。当然，第二电压信号V2也可以是其他电压值持续降低的信号，本申请对此不作具体限定。
随着第二电压信号V2电压值的降低，由于第一电容C2的耦合作用，第一节点A的电位不断降低。当第二电压信号V2的电压值降低到某一数值时（取决于第四晶体管T4的阈值电压），由前述分析可知，第二节点B的电位由低电平快速翻转至高电平。第四晶体管T4迅速打开，使得驱动晶体管Td的栅极电位被快速拉低至第三电源信号Vneg的电位。驱动晶体管Td迅速关闭。则发光器件D由发光状态迅速转变为非发光状态。
可以理解的是，由于驱动晶体管Td迅速关闭，使得发光器件D迅速转变为非发光状态，因此可以精确控制发光器件D的发光时间。
在本申请中，可以通过控制第二电压信号V2的初始电压值的大小控制第一节点A的电位变化快慢，进而控制发光器件D的发光时间。由前述分析可知，在发光阶段t2的初始阶段，第一节点A的电位为高电平，第七晶体管T7关闭，不影响驱动晶体管Td的栅极电位。只有当第一节点A的电位降低到某一数值时，第二节点B的电位由电平快速翻转至高电平。然后，第七晶体管T7打开，才能下拉驱动晶体管Td的栅极电位。而第一节点A的电位的下降速度取决于第二电压信号V2的初始电压值。因此，通过控制第二电压信号V2的初始电压值大小，可以控制发光器件D的发光时间。进一步的，通过控制发光器件D的发光时间，可以控制发光器件D的发光亮度，从而实现一些亮度调整等功能，本申请对此不作具体限定。
请参阅图7，图7是本申请提供的发光电路的第二结构示意图。与图1所示的发光电路100的不同之处在于，在本实施例中，发光电路100还包括感测模块106。感测模块106接入感测信号Se，并电性连接于驱动晶体管Td的源极和漏极中的一者以及初始电压输入端Vref。感测模块106用于在感测信号Se的控制下感测驱动晶体管Td的阈值电压。
进一步的，图8是本申请提供的图7所示的发光电路的电路示意图。其中，感测模块106包括第八晶体管T8。第八晶体管T8的栅极接入感测信号Se。第八晶体管T8的源极和漏极中的一者电性连接于驱动晶体管Td的源极和漏极中的另一者。第八晶体管T8的源极和漏极中的另一者电性连接于初始电压输入端Vref。第八晶体管T8可以是N型晶体管或P型晶体管。当然，可以理解地，感测模块106还可以采用多个晶体管串联形成。
本实施例通过在发光电路100中设置感测模块106，采用外部补偿的原理，可以在发光电路100的一帧显示周期内根据需求插入阈值电压侦测阶段以实现阈值电压补偿的功能，从而提高多个发光器件D的发光亮度均一性。
需要说明的是，在本申请一些实施例中，可以在发光电路100中增设内部补偿电路，以补偿驱动晶体管Td的阈值电压。在本申请一些实施例中，也可以在发光电路100中增设发光控制模块。发光控制模块接入发光控制信号，并串接于发光回路。发光控制模块用于在发光控制信号的控制下控制发光回路的导通，以避免发光器件D在非发光阶段发光。也即，本申请提供的发光电路100中的第一控制模块103、双稳态电路模块104以及第二控制模块105可以应用到多种类型的发光电路中，在此不一一赘述。
请参阅图9，图9是本申请提供的背光模组的一种结构示意图。本申请实施例还提供一种背光模组200，其包括数据线10、扫描线20、控制线30、第一信号线40、第二信号线50、第一电源线60、第二电源线70、第三电源80以及以上任一实施例所述的发光电路100。其中，数据线10用于提供数据信号。扫描线20用于提供扫描信号。控制线30用于提供控制信号。第一信号线40用于提供第一电压信号。第二信号线50用于提供第一电压信号。第一电源线60用于提供第一电源信号。第二电源线70用于提供第二电源信号。第三电源线80用于提供第三电源信号。发光电路100分别与数据线10、扫描线20、控制线30、第一信号线40、第二信号线50、第一电源线60、第二电源线70以及第三电源80电性连接。发光电路100具体可参照以上对该发光电路的描述，在此不再赘述。
具体的，在发光电路100中，驱动晶体管的源极和漏极中的一者与第一电源线60电连接。发光器件D的第二端与第二电源线70电连接。数据信号写入模块101与数据线10以及扫描线20电连接。第一控制模块103与控制线30、第一信号线40以及第二信号线50电连接。双稳态电路模块104与第一电源线60以及第三电源线80电连接。第二控制模块105与第三电源线80电连接。
本申请提供的背光模组200中，使用了一种新型发光电路100。发光电路100包括发光器件、驱动晶体管、数据信号写入模块、第一控制模块、双稳态电路模块以及第二控制模块。其中，第一控制模块、双稳态电路模块以及第二控制模块协同工作，能够快速改变驱动晶体管的栅极的电位，精确控制发光器件的发光时间，提高背光模组200的光源质量。
请参阅图10，图10是本申请提供的显示面板的一种结构示意图。本申请实施例还提供一种显示面板300，包括多个呈阵列排布的像素单元301，每一像素单元301均包括以上所述的发光电路100，具体可参照以上对该发光电路100的描述，在此不做赘述。
本申请提供的显示面板300中，使用了一种新型发光电路100。发光电路100包括发光器件、驱动晶体管、数据信号写入模块、第一控制模块、双稳态电路模块以及第二控制模块。其中，第一控制模块、双稳态电路模块以及第二控制模块协同工作，能够快速改变驱动晶体管的栅极的电位，从而精确控制发光器件的发光时间。从而改善显示面板300的显示画面。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种发光电路，其中，包括：
    驱动晶体管，所述驱动晶体管的源极和漏极中的一者接入第一电源信号；
    发光器件，所述发光器件的第一端与所述驱动晶体管的源极和漏极的另一者电连接，所述发光器件的第二端接入第二电源信号；
    数据信号写入模块，所述数据信号写入模块接入扫描信号和数据信号，并电性连接于所述驱动晶体管的栅极，所述数据信号写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
    第一控制模块，所述第一控制模块接入控制信号、第一电压信号以及第二电压信号，并电性连接于第一节点，所述第一控制模块用于在所述控制信号、所述第一电压信号以及所述第二电压信号的控制下控制所述第一节点的电位；
    双稳态电路模块，所述双稳态电路模块接入所述第一电源信号和第三电源信号，并电性连接于所述第一节点和第二节点，所述双稳态电路模块用于在所述第一节点的电位、所述第一电源信号以及所述第三电源信号的控制下控制所述第二节点的电位；
    第二控制模块，所述第二控制模块接入所述第三电源信号，并电性连接于所述第二节点和所述驱动晶体管的栅极，所述第二控制模块用于在所述第二节点的电位以及所述第三电源信号的控制下控制所述驱动晶体管的栅极的电位；
    存储模块，所述存储模块电性连接于所述驱动晶体管的栅极以及所述发光器件的第二端，所述存储模块用于存储所述驱动晶体管的栅极的电位。
  2. 根据权利要求1所述的发光电路，其中，所述数据信号写入模块包括第一晶体管，所述第一晶体管的栅极接入所述扫描信号，所述第一晶体管的源极和漏极中的一者接入所述数据信号，所述第一晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接；
    所述存储模块包括存储电容，所述存储电容的一端电性连接于所述驱动晶体管的栅极，所述存储电容的另一端电性连接于所述发光器件的第二端。
  3. 根据权利要求1所述的发光电路，其中，所述第一控制模块包括第二晶体管和第一电容；
    所述第二晶体管的栅极接入所述控制信号，所述第二晶体管的源极和漏极中的一者接入所述第一电压信号，所述第二晶体管的源极和漏极中的另一者以及所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端接入所述第二电压信号。
  4. 根据权利要求1所述的发光电路，其中，所述双稳态电路模块包括第一反相器和第二反相器；
    所述第一反相器包括第三晶体管和第四晶体管，所述第三晶体管的栅极以及所述第三晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第三晶体管的源极和漏极中的另一者以及所述第四晶体管的源极和漏极中的一者均与所述第二节点电性连接，所述第四晶体管的栅极与所述第一节点电性连接，所述第四晶体管的源极和漏极中的另一者接入所述第三电源信号；
    所述第二反相器包括第五晶体管和第六晶体管，所述第五晶体管的栅极以及所述第五晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者以及所述第六晶体管的源极和漏极中的一者均与所述第一节点电性连接，所述第六晶体管的栅极与所述第二节点电性连接，所述第六晶体管的源极和漏极中的另一者接入所述第三电源信号。
  5. 根据权利要求4所述的发光电路，其中，所述第三晶体管的沟道长宽比小于所述第四晶体管的沟道长宽比，所述第五晶体管的沟道长宽比小于所述第六晶体管的沟道长宽比。
  6. 根据权利要求1所述的发光电路，其中，所述双稳态电路模块包括第一反相器和第二反相器；
    所述第一反相器包括第三晶体管和第四晶体管，所述第三晶体管和所述第四晶体管的栅极均电性连接于所述第一节点，所述第三晶体管的源极和漏极中的一者接入所述第一电源信号，所述第三晶体管的源极和漏极中的另一者以及所述第四晶体管的源极和漏极中的一者均与所述第二节点电性连接，所述第四晶体管的源极和漏极中的另一者接入所述第三电源信号；
    所述第二反相器包括第五晶体管和第六晶体管，所述第五晶体管和所述第六晶体管的栅极均电性连接于所述第二节点，所述第五晶体管的源极和漏极中的一者接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者以及所述第六晶体管的源极和漏极中的一者均与所述第一节点电性连接，所述第六晶体管的源极和漏极中的另一者接入所述第三电源信号；
    其中，所述第三晶体管与所述第五晶体管为P型晶体管，所述第四晶体管与所述第六晶体管为N型晶体管。
  7. 根据权利要求1所述的发光电路，其中，所述第二控制模块包括第七晶体，所述第七晶体管的栅极与所述第二节点电性连接，所述第七晶体管的源极和漏极中的一者接入所述第三电源信号，所述第七晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接。
  8. 根据权利要求1所述的发光电路，其中，所述发光电路还包括感测模块，所述感测模块接入感测信号，并电性连接于所述驱动晶体管的源极和漏极中的另一者以及初始电压输入端，所述感测模块用于在所述感测信号的控制下感测所述驱动晶体管的阈值电压。
  9. 根据权利要求8所述的发光电路，其中，所述感测模块包括第八晶体管，所述第八晶体管的栅极接入所述感测信号，所述第八晶体管的源极和漏极中的一者电性连接于所述驱动晶体管的源极和漏极中的一者，所述第八晶体管的源极和漏极中的另一者电性连接于所述初始电压输入端。
  10. 根据权利要求1所述的发光电路，其中，所述第二电压信号为三角波信号。
  11. 一种背光模组，其中，包括：
    数据线，所述数据线用于提供数据信号；
    扫描线，所述扫描线用于提供扫描信号；
    控制线，所述控制线用于提供控制信号；
    第一信号线，所述第一信号线用于提供第一电压信号；
    第二信号线，所述第二信号线用于提供第二电压信号；
    第一电源线，所述第一电源线用于提供第一电源信号；
    第二电源线，所述第二电源线用于提供第二电源信号；
    第三电源线，所述第三电源线用于提供第三电源信号；以及
    发光电路，所述发光电路包括：
    驱动晶体管，所述驱动晶体管的源极和漏极中的一者接入所述第一电源信号；
    发光器件，所述发光器件的第一端与所述驱动晶体管的源极和漏极的另一者电连接，所述发光器件的第二端接入所述第二电源信号；
    数据信号写入模块，所述数据信号写入模块接入所述扫描信号和所述数据信号，并电性连接于所述驱动晶体管的栅极，所述数据信号写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
    第一控制模块，所述第一控制模块接入所述控制信号、所述第一电压信号以及所述第二电压信号，并电性连接于第一节点，所述第一控制模块用于在所述控制信号、所述第一电压信号以及所述第二电压信号的控制下控制所述第一节点的电位；
    双稳态电路模块，所述双稳态电路模块接入所述第一电源信号和所述第三电源信号，并电性连接于所述第一节点和第二节点，所述双稳态电路模块用于在所述第一节点的电位、所述第一电源信号以及所述第三电源信号的控制下控制所述第二节点的电位；
    第二控制模块，所述第二控制模块接入所述第三电源信号，并电性连接于所述第二节点和所述驱动晶体管的栅极，所述第二控制模块用于在所述第二节点的电位以及所述第三电源信号的控制下控制所述驱动晶体管的栅极的电位；
    存储模块，所述存储模块电性连接于所述驱动晶体管的栅极以及所述发光器件的第二端，所述存储模块用于存储所述驱动晶体管的栅极的电位。
  12. 根据权利要求11所述的背光模组，其中，所述数据信号写入模块包括第一晶体管，所述第一晶体管的栅极接入所述扫描信号，所述第一晶体管的源极和漏极中的一者接入所述数据信号，所述第一晶体管的源极和漏极中的另一者与所述驱动晶体管的栅极电性连接；
    所述存储模块包括存储电容，所述存储电容的一端电性连接于所述驱动晶体管的栅极，所述存储电容的另一端电性连接于所述发光器件的第二端。
  13. 根据权利要求11所述的背光模组，其中，所述第一控制模块包括第二晶体管和第一电容；
    所述第二晶体管的栅极接入所述控制信号，所述第二晶体管的源极和漏极中的一者接入所述第一电压信号，所述第二晶体管的源极和漏极中的另一者以及所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端接入所述第二电压信号。
  14. 根据权利要求11所述的背光模组，其中，所述双稳态电路模块包括第一反相器和第二反相器；
    所述第一反相器包括第三晶体管和第四晶体管，所述第三晶体管的栅极以及所述第三晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第三晶体管的源极和漏极中的另一者以及所述第四晶体管的源极和漏极中的一者均与所述第二节点电性连接，所述第四晶体管的栅极与所述第一节点电性连接，所述第四晶体管的源极和漏极中的另一者接入所述第三电源信号；
    所述第二反相器包括第五晶体管和第六晶体管，所述第五晶体管的栅极以及所述第五晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者以及所述第六晶体管的源极和漏极中的一者均与所述第一节点电性连接，所述第六晶体管的栅极与所述第二节点电性连接，所述第六晶体管的源极和漏极中的另一者接入所述第三电源信号。
  15. 根据权利要求14所述的背光模组，其中，所述第三晶体管的沟道长宽比小于所述第四晶体管的沟道长宽比，所述第五晶体管的沟道长宽比小于所述第六晶体管的沟道长宽比。
  16. 根据权利要求11所述的背光模组，其中，所述双稳态电路模块包括第一反相器和第二反相器；
    所述第一反相器包括第三晶体管和第四晶体管，所述第三晶体管和所述第四晶体管的栅极均电性连接于所述第一节点，所述第三晶体管的源极和漏极中的一者接入所述第一电源信号，所述第三晶体管的源极和漏极中的另一者以及所述第四晶体管的源极和漏极中的一者均与所述第二节点电性连接，所述第四晶体管的源极和漏极中的另一者接入所述第三电源信号；
    所述第二反相器包括第五晶体管和第六晶体管，所述第五晶体管和所述第六晶体管的栅极均电性连接于所述第二节点，所述第五晶体管的源极和漏极中的一者接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者以及所述第六晶体管的源极和漏极中的一者均与所述第一节点电性连接，所述第六晶体管的源极和漏极中的另一者接入所述第三电源信号；
    其中，所述第三晶体管与所述第五晶体管为P型晶体管，所述第四晶体管与所述第六晶体管为N型晶体管。
  17. 一种显示面板，其中，所述显示面板包括多个呈阵列排布的像素单元，每一所述像素单元均包括发光电路，所述发光电路包括：
    驱动晶体管，所述驱动晶体管的源极和漏极中的一者接入第一电源信号；
    发光器件，所述发光器件的第一端与所述驱动晶体管的源极和漏极的另一者电连接，所述发光器件的第二端接入第二电源信号；
    数据信号写入模块，所述数据信号写入模块接入扫描信号和数据信号，并电性连接于所述驱动晶体管的栅极，所述数据信号写入模块用于在所述扫描信号的控制下，将所述数据信号写入所述驱动晶体管的栅极；
    第一控制模块，所述第一控制模块接入控制信号、第一电压信号以及第二电压信号，并电性连接于第一节点，所述第一控制模块用于在所述控制信号、所述第一电压信号以及所述第二电压信号的控制下控制所述第一节点的电位；
    双稳态电路模块，所述双稳态电路模块接入所述第一电源信号和第三电源信号，并电性连接于所述第一节点和第二节点，所述双稳态电路模块用于在所述第一节点的电位、所述第一电源信号以及所述第三电源信号的控制下控制所述第二节点的电位；
    第二控制模块，所述第二控制模块接入所述第三电源信号，并电性连接于所述第二节点和所述驱动晶体管的栅极，所述第二控制模块用于在所述第二节点的电位以及所述第三电源信号的控制下控制所述驱动晶体管的栅极的电位；
    存储模块，所述存储模块电性连接于所述驱动晶体管的栅极以及所述发光器件的第二端，所述存储模块用于存储所述驱动晶体管的栅极的电位。
  18. 根据权利要求17所述的显示面板，所述第一控制模块包括第二晶体管和第一电容；
    所述第二晶体管的栅极接入所述控制信号，所述第二晶体管的源极和漏极中的一者接入所述第一电压信号，所述第二晶体管的源极和漏极中的另一者以及所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端接入所述第二电压信号。
  19. 根据权利要求17所述的显示面板，其中，所述双稳态电路模块包括第一反相器和第二反相器；
    所述第一反相器包括第三晶体管和第四晶体管，所述第三晶体管的栅极以及所述第三晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第三晶体管的源极和漏极中的另一者以及所述第四晶体管的源极和漏极中的一者均与所述第二节点电性连接，所述第四晶体管的栅极与所述第一节点电性连接，所述第四晶体管的源极和漏极中的另一者接入所述第三电源信号；
    所述第二反相器包括第五晶体管和第六晶体管，所述第五晶体管的栅极以及所述第五晶体管的源极和漏极中的一者均接入所述第一电源信号，所述第五晶体管的源极和漏极中的另一者以及所述第六晶体管的源极和漏极中的一者均与所述第一节点电性连接，所述第六晶体管的栅极与所述第二节点电性连接，所述第六晶体管的源极和漏极中的另一者接入所述第三电源信号。
  20. 根据权利要求19所述的显示面板，其中，所述第三晶体管的沟道长宽比小于所述第四晶体管的沟道长宽比，所述第五晶体管的沟道长宽比小于所述第六晶体管的沟道长宽比。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023236043A1 (zh) * 2022-06-07 2023-12-14 京东方科技集团股份有限公司 移位寄存器及其驱动方法、显示基板、显示装置
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020140642A1 (en) * 2001-01-18 2002-10-03 Shigetsugu Okamoto Memory-integrated display element
JP2009049859A (ja) * 2007-08-22 2009-03-05 Seiko Epson Corp 電気回路、電気回路の駆動方法、表示装置および電子機器。
CN102792363A (zh) * 2010-03-15 2012-11-21 夏普株式会社 扫描信号线驱动电路和具有该扫描信号线驱动电路的显示装置
CN103490748A (zh) * 2013-06-21 2014-01-01 北京大学深圳研究生院 一种锁存器电路单元及用于显示装置的数据驱动电路
CN109801592A (zh) * 2019-03-27 2019-05-24 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板
CN113689821A (zh) * 2021-09-03 2021-11-23 深圳市华星光电半导体显示技术有限公司 发光器件驱动电路、背光模组以及显示面板

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5309470B2 (ja) * 2007-05-21 2013-10-09 ソニー株式会社 表示装置及びその駆動方法と電子機器
CN104299570B (zh) * 2014-11-03 2017-06-16 厦门天马微电子有限公司 一种像素电路及其驱动方法、阵列基板和显示面板
CN106531074B (zh) * 2017-01-10 2019-02-05 上海天马有机发光显示技术有限公司 有机发光像素驱动电路、驱动方法以及有机发光显示面板
CN108831384B (zh) * 2018-07-26 2019-10-25 深圳市华星光电半导体显示技术有限公司 有机发光二极管显示装置的驱动电路
CN210142495U (zh) * 2019-08-27 2020-03-13 云谷（固安）科技有限公司 一种像素电路、显示面板和显示装置
GB201914186D0 (en) * 2019-10-01 2019-11-13 Barco Nv Driver for LED or OLED display
CN111477162B (zh) * 2020-04-17 2021-04-13 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN111583857B (zh) * 2020-05-29 2021-04-30 厦门天马微电子有限公司 像素驱动电路及其驱动方法、显示面板
CN112382235A (zh) * 2020-12-01 2021-02-19 合肥维信诺科技有限公司 一种像素电路及其控制方法、显示面板
CN112669775B (zh) * 2020-12-30 2024-04-19 视涯科技股份有限公司 一种显示面板、驱动方法及显示装置
CN113808547B (zh) * 2021-09-26 2023-06-27 Tcl华星光电技术有限公司 发光器件驱动电路、背光模组以及显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020140642A1 (en) * 2001-01-18 2002-10-03 Shigetsugu Okamoto Memory-integrated display element
JP2009049859A (ja) * 2007-08-22 2009-03-05 Seiko Epson Corp 電気回路、電気回路の駆動方法、表示装置および電子機器。
CN102792363A (zh) * 2010-03-15 2012-11-21 夏普株式会社 扫描信号线驱动电路和具有该扫描信号线驱动电路的显示装置
CN103490748A (zh) * 2013-06-21 2014-01-01 北京大学深圳研究生院 一种锁存器电路单元及用于显示装置的数据驱动电路
CN109801592A (zh) * 2019-03-27 2019-05-24 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板
CN113689821A (zh) * 2021-09-03 2021-11-23 深圳市华星光电半导体显示技术有限公司 发光器件驱动电路、背光模组以及显示面板

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