WO2023108650A1 - 像素电路及显示面板 - Google Patents

像素电路及显示面板 Download PDF

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Publication number
WO2023108650A1
WO2023108650A1 PCT/CN2021/139318 CN2021139318W WO2023108650A1 WO 2023108650 A1 WO2023108650 A1 WO 2023108650A1 CN 2021139318 W CN2021139318 W CN 2021139318W WO 2023108650 A1 WO2023108650 A1 WO 2023108650A1
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Prior art keywords
transistor
electrically connected
source
drain
gate
Prior art date
Application number
PCT/CN2021/139318
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English (en)
French (fr)
Inventor
徐健
Original Assignee
Tcl华星光电技术有限公司
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/622,803 priority Critical patent/US20240029623A1/en
Publication of WO2023108650A1 publication Critical patent/WO2023108650A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters

Definitions

  • the present application relates to the field of display technology, in particular to a pixel circuit and a display panel.
  • the driving method of the display technology includes PAM (Pulse Amplitude Modulation, Pulse Width Modulation), PWM (Pulse Width Modulation, Pulse Width Modulation) and a mixture of the two.
  • PAM Pulse Amplitude Modulation, Pulse Width Modulation
  • PWM Pulse Width Modulation, Pulse Width Modulation
  • the PWM driving method has the advantages of constant current, high luminous efficiency, and low grayscale display quality, so PWM or based on The hybrid driving method of PWM has been extensively studied.
  • the pixel circuit shown in Figure 1 adopts PWM (Pulse Width Modulation, pulse width modulation) driving mode, and the display time of the pixel circuit can be controlled by the signal SPWM, but the signal SPWM needs a higher frequency, when it passes through the gate
  • PWM Pulse Width Modulation, pulse width modulation
  • the working process of the pixel circuit in Figure 1 includes a preparation stage S1 and a light-emitting stage S2.
  • the preparation stage S1 the potential V-G of point G and the potential V-SPWM of the signal SPWM are both low potentials. Therefore, the light-emitting device The light emitting current I-LED does not flow through the LED.
  • the light-emitting phase S2 when the potential V-G at point G is at a high potential, a light-emitting current I-LED flows through the light-emitting device LED; however, when the potential V-SPWM of the signal SPWM is at a high potential, the light-emitting current I-LED will stop Flow through the light emitting device LED.
  • the pixel circuit shown in Figure 3 adopts another PWM driving method.
  • the level of point A can be increased at a uniform speed.
  • the time required for the potential of point A to rise from different initial voltages to the threshold voltage of the transistor T4 is different, and the time for the transistor T4 to be turned on or turned on is also different, and the display time or light-emitting time of the pixel circuit is also different.
  • the transistor T4 and the transistor T2 are slowly turned off or turned off as shown in FIG. 4 , which makes it difficult to accurately control the light-emitting time.
  • the working process of the pixel circuit in Figure 3 includes a preparation stage S3 and a light emitting stage S4.
  • the light emitting current I-LED does not flow through the LED.
  • the potential V-G at point G is at a high potential
  • a light-emitting current I-LED flows through the light-emitting device LED; however, as the potential V-Sweep of the signal Sweep gradually increases, there is a potential V-G at point G.
  • the slow down process causes the luminous current I-LED not to stop immediately, which makes it difficult to precisely control the luminous time of the pixel circuit.
  • the present application provides a pixel circuit and a display panel to improve the control accuracy of light emitting time in the pulse width driving mode.
  • the present application provides a pixel circuit, which includes a driving transistor T2 and a pulse width driving module, and the pulse width driving module is electrically connected to the gate of the driving transistor T2; wherein, the pulse width driving module includes a display time control unit, A potential modulation unit and a Schmitt trigger, one end of the display time control unit is electrically connected to the gate of the drive transistor T2, and the other end of the display time control unit is used to access the first reference signal for turning off the drive transistor T2 ;
  • the input end of the Schmitt trigger is electrically connected to the output end of the potential modulation unit, and the output end of the Schmitt trigger is electrically connected to the control end of the display time control unit.
  • the Schmitt trigger includes an inverter INV1, an inverter INV2 and a resistor R2, the input terminal of the inverter INV1 is electrically connected to the output terminal of the potential modulation unit; the input terminal of the inverter INV2 terminal is electrically connected to the output terminal of the inverter INV1, and the output terminal of the inverter INV2 is electrically connected to the control terminal of the display time control unit; one terminal of the resistor R2 is electrically connected to the input terminal of the inverter INV1, and the resistor R2 is electrically connected to the input terminal of the inverter INV1. The other end of is electrically connected to the output end of the inverter INV2.
  • the Schmitt trigger further includes a resistor R1, one end of the resistor R1 is electrically connected to the output end of the potential modulation unit, and the other end of the resistor R1 is electrically connected to the input end of the inverter INV1.
  • the inverter INV1 includes a transistor M1 and a transistor M2, one of the source/drain of the transistor M1 is electrically connected to the gate of the transistor M1, and is connected to a high potential signal; the source of the transistor M2 One of the poles/drains is electrically connected to the other of the source/drain of the transistor M1 and the input terminal of the inverter INV2, the gate of the transistor M2 is electrically connected to the output terminal of the potential modulation unit, and the transistor M2 The other of the source/drain is used to access the first reference signal.
  • the inverter INV2 includes a transistor M3 and a transistor M4, one of the source/drain of the transistor M3 is electrically connected to the gate of the transistor M3, and is connected to a high potential signal; the source of the transistor M4 One of the poles/drains is electrically connected to the other of the source/drain of the transistor M3 and the control terminal of the display time control unit, and the gate of the transistor M4 is electrically connected to one of the source/drains of the transistor M2 The other one of the source/drain of the transistor M4 is used to access the first reference signal.
  • the display time control unit includes a transistor T4, one of the source/drain of the transistor T4 is electrically connected to the gate of the driving transistor T2, and the other of the source/drain of the transistor T4 is connected to After receiving the first reference signal, the gate of the transistor T4 is electrically connected to the output terminal of the Schmitt trigger.
  • the potential modulating unit includes a capacitor C2, one end of the capacitor C2 is electrically connected to the input end of the Schmitt trigger, and the other end of the capacitor C2 is used to receive the triangular wave control signal.
  • the potential modulation unit further includes a transistor T5, one of the source/drain of the transistor T5 is used for connecting the potential setting signal, and the gate of the transistor T5 is used for connecting the pulse width control signal.
  • the pixel circuit further includes a transistor T1, a transistor T3, a capacitor C1, and a light emitting device D1, one of the source/drain of the transistor T1 is used for connecting the data signal, and the gate of the transistor T1 is used for connecting Input the pulse width control signal, the other of the source/drain of the transistor T1 is electrically connected to the gate of the drive transistor T2; one of the source/drain of the transistor T3 is used to access the second reference signal, the transistor The gate of T3 is used to access the pulse width control signal, the other of the source/drain of transistor T3 is electrically connected to the source of the driving transistor T2; one end of the capacitor C1 is electrically connected to the gate of the driving transistor T2 , the other end of the capacitor C1 is electrically connected to the source of the driving transistor T2; the anode of the light-emitting device D1 is electrically connected to the source of the driving transistor T2, and the cathode of the light-emitting device D
  • the present application provides a display panel, which includes the pixel circuit in at least one embodiment above, and the pixel circuit further includes a light-emitting chip, and a Schmitt trigger is integrated in the light-emitting chip.
  • the display time control unit can be turned on more quickly to turn off the drive
  • the transistor T2 can further precisely control the display time or light emission time of the pixel circuit.
  • FIG. 1 is a first circuit schematic diagram of a pixel circuit provided by a conventional technical solution.
  • FIG. 2 is a timing schematic diagram of the pixel circuit shown in FIG. 1 .
  • FIG. 3 is a second circuit schematic diagram of the pixel circuit provided by the conventional technical solution.
  • FIG. 4 is a timing schematic diagram of the pixel circuit shown in FIG. 3 .
  • FIG. 5 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic circuit diagram of the Schmitt trigger 20 shown in FIG. 5 .
  • FIG. 7 is a schematic circuit diagram of the inverter INV1 shown in FIG. 6 .
  • FIG. 8 is a schematic circuit diagram of the inverter INV2 shown in FIG. 6 .
  • FIG. 9 is a timing schematic diagram of the pixel circuit shown in FIG. 5 .
  • FIG. 10 is a schematic structural diagram of a light emitting chip 200 provided by an embodiment of the present application.
  • the pixel circuit includes a driving transistor T2 and the pulse width driving module 100, the pulse width driving module 100 is electrically connected to the gate of the driving transistor T2; wherein, the pulse width driving module 100 includes a display time control unit 10, a potential modulation unit 30 and a Schmitt trigger 20, One end of the display time control unit 10 is electrically connected to the gate of the driving transistor T2, and the other end of the display time control unit 10 is used to access the first reference signal Vneg to turn off the driving transistor T2; a Schmitt trigger 20 The input end of the electric potential modulation unit 30 is electrically connected to the output end of the potential modulation unit 30 , and the output end of the Schmitt trigger 20 is electrically connected to the control end of the display time control unit 10 .
  • the display time can be turned on more rapidly.
  • the control unit 10 can turn off the driving transistor T2, so as to control the display time or light emitting time of the pixel circuit more precisely.
  • the display time control unit 10 includes a transistor T4, one of the source/drain of the transistor T4 is electrically connected to the gate of the driving transistor T2, and the other of the source/drain of the transistor T4 For accessing the first reference signal Vneg, the gate of the transistor T4 is electrically connected to the output terminal of the Schmitt trigger 20 .
  • the potential modulation unit 30 includes a capacitor C2, one end of the capacitor C2 is electrically connected to the input end of the Schmitt trigger 20, and the other end of the capacitor C2 is used to receive the triangular wave control signal Sweep.
  • the potential modulation unit 30 further includes a transistor T5, one of the source/drain of the transistor T5 is used for connecting the potential setting signal, and the gate of the transistor T5 is used for connecting the pulse width control signal SPWM.
  • the potential setting signal may be, but not limited to, the data signal Data, or other signals with suitable potentials.
  • the pixel circuit further includes a transistor T1, a transistor T3, a capacitor C1, and a light emitting device D1, one of the source/drain of the transistor T1 is used to access the data signal Data, and the transistor The gate of T1 is used to access the pulse amplitude control signal SPAM, the other of the source/drain of transistor T1 is electrically connected to the gate of drive transistor T2; one of the source/drain of transistor T3 is used for Access to the second reference signal Vref, the gate of the transistor T3 is used to access the pulse width control signal SPAM, the other of the source/drain of the transistor T3 is electrically connected to the source of the driving transistor T2; one end of the capacitor C1 It is electrically connected to the gate of the driving transistor T2, and the other end of the capacitor C1 is electrically connected to the source of the driving transistor T2; the anode of the light emitting device D1 is electrically connected to the source of the driving transistor T2, and the cathode of the
  • the Schmitt trigger 20 includes an inverter INV1, an inverter INV2, and a resistor R2.
  • the input terminal of the inverter INV1 is electrically connected to the output terminal of the potential modulation unit 30. connection; the input end of the inverter INV2 is electrically connected to the output end of the inverter INV1, and the output end of the inverter INV2 is electrically connected to the control end of the display time control unit 10; one end of the resistor R2 is connected to the inverter INV1 The input end of the resistor R2 is electrically connected to the other end of the resistor R2 and the output end of the inverter INV2 is electrically connected.
  • the Schmitt trigger 20 further includes a resistor R1, one end of the resistor R1 is electrically connected to the output end of the potential modulation unit 30, and the other end of the resistor R1 is electrically connected to the input end of the inverter INV1 .
  • resistor R1 can adapt the potential of point C, so that the inverter INV1 can be connected to different potentials of point C.
  • the Schmitt trigger 20 switches states, there is such a positive feedback process: the potential VA at point A increases, and the potential VC at point C also increases accordingly.
  • the potential VM of point M decreases accordingly, the potential VB of point B increases accordingly, and the potential VC of point C increases accordingly. Due to the above-mentioned positive feedback process, the potential VB at point B can change rapidly, so that the waveform of the potential VB at point B is infinitely close to a square wave, so that the light-emitting time of the pixel circuit can be controlled more precisely.
  • the inverter INV1 includes a transistor M1 and a transistor M2, one of the source/drain of the transistor M1 is electrically connected to the gate of the transistor M1, and connected to a high potential Signal; one of the source/drain of the transistor M2 is electrically connected to the other of the source/drain of the transistor M1 and the input terminal of the inverter INV2, and the gate of the transistor M2 is connected to the output of the potential modulation unit 30 Terminals are electrically connected, and the other of the source/drain of the transistor M2 is used to access the first reference signal Vneg.
  • the high potential signal may be a positive power signal VDD.
  • the first reference signal Vneg can also be a power negative signal VSS.
  • the inverter INV2 includes a transistor M3 and a transistor M4, one of the source/drain of the transistor M3 is electrically connected to the gate of the transistor M3, and is connected to a high potential Signal; one of the source/drain of the transistor M4 is electrically connected to the other of the source/drain of the transistor M3 and the control terminal of the display time control unit 10, and the gate of the transistor M4 is connected to the source of the transistor M2 One of the /drains is electrically connected, and the other of the source/drain of the transistor M4 is used to access the first reference signal Vneg.
  • the PWM driving mode can be realized by using the triangle wave control signal Sweep.
  • the working process of the pixel circuit shown in FIG. 5 in one frame includes a preparation stage S10 and a display stage S20, wherein, in the preparation stage S10, the potential V-G of point G and the potential V-Sweep of the triangular wave control signal Sweep are both low. potential, at this time, there is no light emitting current I-LED flowing in the light emitting device D1, and the light emitting device D1 remains in the extinguished state.
  • the potential V-G at point G jumps from a low potential to a high potential, the drive transistor T2 is turned on, and the light-emitting device D1 lights up because the light-emitting current I-LED flows in the light-emitting device D1; with the triangular wave control signal Sweep
  • the potential V-Sweep of the V-Sweep gradually increases, and through the coupling effect of the capacitor C2, the potential VA of point A is also gradually increasing.
  • the output potential of the Schmitt trigger 20 That is, the potential VB at point B is quickly raised to a high potential to quickly turn on the transistor T4, and the potential V-G at point G can quickly jump from high potential to low potential, and then quickly turn off the driving transistor T2, so that the light-emitting device D1 can be quickly turned from point to point The on state changes to the off state.
  • the potential V-Sweep of the triangle wave control signal Sweep in Figure 9 and the falling edge of the light-emitting current I-LED are steeper, that is to say, the pixel circuit shown in Figure 5 can more precisely control the light-emitting time or Displays the duration of the time.
  • the Schmitt trigger 20 with high hysteresis characteristics, that is, when the input voltage of the Schmitt trigger 20 rises to its forward threshold voltage, the The output voltage of the flip-flop 20 will flip to a high potential. In this way, the high potential output voltage of the Schmitt trigger 20 can ignore the difference or drift of the threshold voltage of the transistor T4, and can ensure that the transistor T4 can be turned on directly. Therefore, In the pixel circuit of the present application using the Schmitt trigger 20, there is no need to carefully design the compensation circuit for the threshold voltage of the transistor T4, that is to say, the pixel circuit provided by the present application with the Schmitt trigger 20 can be The display function is realized with a simpler circuit structure.
  • This display function can write different initial potentials to point A, and then can correspond to different display times, and can achieve high-precision gray-scale segmentation without a particularly high-frequency signal.
  • this embodiment provides a display panel, which includes the pixel circuit in at least one of the above embodiments, the pixel circuit also includes a light emitting chip 200, a Schmitt trigger 20 is integrated in the light emitting chip 200.
  • the display time can be turned on more quickly.
  • the control unit 10 can turn off the driving transistor T2, so as to control the display time or light emitting time of the pixel circuit more precisely.
  • the light-emitting chip 200 can be a Mini-LED chip or a Micro-LED chip.
  • the light-emitting chip 200 packaged in a CMOS process can include a first pin, a second pin , the third pin and the fourth pin, wherein the first pin can be used to transmit the power supply positive signal VDD, the second pin can be used to transmit the first reference signal Vneg, and the third pin can be used to transmit point A Potential VA, the fourth pin can be used to transmit the potential VB of point B.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种像素电路及显示面板，像素电路包括驱动晶体管（T2）和脉宽驱动模块（100），脉宽驱动模块（100）包括显示时间控制单元（10）、电位调制单元（30）以及施密特触发器（20），通过在电位调制单元（30）的输出端与显示时间控制单元（10）的控制端之间串接施密特触发器（20），可以更快速地关断驱动晶体管（T2），进而能够精确地控制像素电路的显示时间或者发光时间。

Description

像素电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种像素电路及显示面板。
 背景技术
显示技术的驱动方式包括PAM（Pulse Amplitude Modulation，脉冲幅度调制）、PWM（Pulse Width Modulation，脉冲宽度调制）以及两者的混合，其中，PWM驱动方式具有电流恒定、发光效率高、低灰阶显示画质好的优点，从而PWM或者基于PWM的混合驱动方式得到了广泛的研究。
如图1所示的像素电路采用了PWM（Pulse Width Modulation，脉冲宽度调制）驱动方式，可以通过信号SPWM控制该像素电路的显示时间，但是该信号SPWM需要较高的频率，当其通过栅极驱动IC（Integrated Circuit，集成电路）生成时，要求该栅极驱动IC具有较高的性能，且该栅极驱动IC能够驱动的像素电路的行数不多。
如图2所示，图1中像素电路的工作过程包括准备阶段S1和发光阶段S2，在准备阶段S1中，G点电位V-G、信号SPWM的电位V-SPWM均为低电位，因此，发光器件LED中并未流过发光电流I-LED。在发光阶段S2中，G点电位V-G为高电位时，发光器件LED中有流过发光电流I-LED；但是，当信号SPWM的电位V-SPWM为高电位时，发光电流I-LED将停止流经发光器件LED。
如图3所示的像素电路采用了另一种PWM驱动方式，通过初始化A点电位为对应的初始电压，并利用电容C2的耦合作用，可以使得A点位匀速上升。A点电位从不同的初始电压上升到晶体管T4的阈值电压所需要的时间不同，则晶体管T4打开或者导通的时间也不同，进而像素电路的显示时间或者发光时间也不相同。其中，由于A点电位的匀速变化，导致晶体管T4、晶体管T2出现如图4所示的缓慢关断或者关闭，进而导致发光时间难以精确控制。
如图4所示，图3中像素电路的工作过程包括准备阶段S3和发光阶段S4，在准备阶段S3中，G点电位V-G、信号Sweep的电位V-Sweep均为低电位，因此，发光器件LED中并未流过发光电流I-LED。在发光阶段S4中，G点电位V-G为高电位时，发光器件LED中有流过发光电流I-LED；但是，随着信号Sweep的电位V-Sweep逐渐抬高时，G点电位V-G存在一个缓慢的下降过程，导致发光电流I-LED并未即时停止，进而致使该像素电路的发光时间难以精确控制。
同时，由于不同像素电路中晶体管T4的阈值电压存在差别，为了显示的均一性，还需要采用更为复杂的电路结构，以补偿晶体管T4的阈值电压。
 技术问题
本申请提供一种像素电路及显示面板，以提高脉宽驱动方式中发光时间的控制精准度。
 技术解决方案
第一方面，本申请提供一种像素电路，其包括驱动晶体管T2和脉宽驱动模块，脉宽驱动模块与驱动晶体管T2的栅极电性连接；其中，脉宽驱动模块包括显示时间控制单元、电位调制单元以及施密特触发器，显示时间控制单元的一端与驱动晶体管T2的栅极电性连接，显示时间控制单元的另一端用于接入第一参考信号，用于关断驱动晶体管T2；施密特触发器的输入端与电位调制单元的输出端电性连接，施密特触发器的输出端与显示时间控制单元的控制端电性连接。
在其中一些实施方式中，施密特触发器包括反相器INV1、反相器INV2以及电阻R2，反相器INV1的输入端与电位调制单元的输出端电性连接；反相器INV2的输入端与反相器INV1的输出端电性连接，反相器INV2的输出端与显示时间控制单元的控制端电性连接；电阻R2的一端与反相器INV1的输入端电性连接，电阻R2的另一端与反相器INV2的输出端电性连接。
在其中一些实施方式中，施密特触发器还包括电阻R1，电阻R1的一端与电位调制单元的输出端电性连接，电阻R1的另一端与反相器INV1的输入端电性连接。
在其中一些实施方式中，反相器INV1包括晶体管M1和晶体管M2，晶体管M1的源极/漏极中的一个与晶体管M1的栅极电性连接，并接入高电位信号；晶体管M2的源极/漏极中的一个与晶体管M1的源极/漏极中的另一个、反相器INV2的输入端电性连接，晶体管M2的栅极与电位调制单元的输出端电性连接，晶体管M2的源极/漏极中的另一个用于接入第一参考信号。
在其中一些实施方式中，反相器INV2包括晶体管M3和晶体管M4，晶体管M3的源极/漏极中的一个与晶体管M3的栅极电性连接，并接入高电位信号；晶体管M4的源极/漏极中的一个与晶体管M3的源极/漏极中的另一个、显示时间控制单元的控制端电性连接，晶体管M4的栅极与晶体管M2的源极/漏极中的一个电性连接，晶体管M4的源极/漏极中的另一个用于接入第一参考信号。
在其中一些实施方式中，显示时间控制单元包括晶体管T4，晶体管T4的源极/漏极中的一个与驱动晶体管T2的栅极电性连接，晶体管T4的源极/漏极中的另一个用于接入第一参考信号，晶体管T4的栅极与施密特触发器的输出端电性连接。
在其中一些实施方式中，电位调制单元包括电容C2，电容C2的一端与施密特触发器的输入端电性连接，电容C2的另一端用于接入三角波控制信号。
在其中一些实施方式中，电位调制单元还包括晶体管T5，晶体管T5的源极/漏极中的一个用于接入电位设置信号，晶体管T5的栅极用于接入脉宽控制信号。
在其中一些实施方式中，像素电路还包括晶体管T1、晶体管T3、电容C1以及发光器件D1，晶体管T1的源极/漏极中的一个用于接入数据信号，晶体管T1的栅极用于接入脉幅控制信号，晶体管T1的源极/漏极中的另一个与驱动晶体管T2的栅极电性连接；晶体管T3的源极/漏极中的一个用于接入第二参考信号，晶体管T3的栅极用于接入脉幅控制信号，晶体管T3的源极/漏极中的另一个与驱动晶体管T2的源极电性连接；电容C1的一端与驱动晶体管T2的栅极电性连接，电容C1的另一端与驱动晶体管T2的源极电性连接；发光器件D1的阳极与驱动晶体管T2的源极电性连接，发光器件D1的阴极用于接入电源负信号；其中，驱动晶体管T2的漏极用于接入电源正信号。
第二方面，本申请提供一种显示面板，其包括上述至少一个实施方式中的像素电路，像素电路还包括发光芯片，施密特触发器集成于发光芯片中。
 有益效果
本申请提供的像素电路及显示面板，通过在电位调制单元的输出端与显示时间控制单元的控制端之间串接施密特触发器，可以更快速地导通显示时间控制单元以关断驱动晶体管T2，进而能够更为精确地控制像素电路的显示时间或者发光时间。
 附图说明
图1为传统技术方案提供的像素电路的第一种电路原理图。
图2为图1所示像素电路的时序示意图。
图3为传统技术方案提供的像素电路的第二种电路原理图。
图4为图3所示像素电路的时序示意图。
图5为本申请实施例提供的像素电路的结构示意图。
图6为图5中所示施密特触发器20的电路原理图。
图7为图6中所示反相器INV1的电路原理图。
图8为图6中所示反相器INV2的电路原理图。
图9为图5所示像素电路的时序示意图。
图10为本申请实施例提供的发光芯片200的结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
有鉴于上述提及的难以精确控制脉宽驱动方式中发光时间的技术问题，本实施例提供了一种像素电路，请参阅图5至图10，如图5所示，该像素电路包括驱动晶体管T2和脉宽驱动模块100，脉宽驱动模块100与驱动晶体管T2的栅极电性连接；其中，脉宽驱动模块100包括显示时间控制单元10、电位调制单元30以及施密特触发器20，显示时间控制单元10的一端与驱动晶体管T2的栅极电性连接，显示时间控制单元10的另一端用于接入第一参考信号Vneg，用于关断驱动晶体管T2；施密特触发器20的输入端与电位调制单元30的输出端电性连接，施密特触发器20的输出端与显示时间控制单元10的控制端电性连接。
可以理解的是，本实施例提供的像素电路，通过在电位调制单元30的输出端与显示时间控制单元10的控制端之间串接施密特触发器20，可以更快速地导通显示时间控制单元10以关断驱动晶体管T2，进而能够更为精确地控制像素电路的显示时间或者发光时间。
在其中一个实施例中，显示时间控制单元10包括晶体管T4，晶体管T4的源极/漏极中的一个与驱动晶体管T2的栅极电性连接，晶体管T4的源极/漏极中的另一个用于接入第一参考信号Vneg，晶体管T4的栅极与施密特触发器20的输出端电性连接。
在其中一个实施例中，电位调制单元30包括电容C2，电容C2的一端与施密特触发器20的输入端电性连接，电容C2的另一端用于接入三角波控制信号Sweep。
在其中一个实施例中，电位调制单元30还包括晶体管T5，晶体管T5的源极/漏极中的一个用于接入电位设置信号，晶体管T5的栅极用于接入脉宽控制信号SPWM。其中，电位设置信号可以但不限于为数据信号Data，也可以为其他具有适合电位的信号。
如图5所示，在其中一个实施例中，像素电路还包括晶体管T1、晶体管T3、电容C1以及发光器件D1，晶体管T1的源极/漏极中的一个用于接入数据信号Data，晶体管T1的栅极用于接入脉幅控制信号SPAM，晶体管T1的源极/漏极中的另一个与驱动晶体管T2的栅极电性连接；晶体管T3的源极/漏极中的一个用于接入第二参考信号Vref，晶体管T3的栅极用于接入脉幅控制信号SPAM，晶体管T3的源极/漏极中的另一个与驱动晶体管T2的源极电性连接；电容C1的一端与驱动晶体管T2的栅极电性连接，电容C1的另一端与驱动晶体管T2的源极电性连接；发光器件D1的阳极与驱动晶体管T2的源极电性连接，发光器件D1的阴极用于接入电源负信号VSS；其中，驱动晶体管T2的漏极用于接入电源正信号VDD。
在其中一个实施例中，如图6所示，施密特触发器20包括反相器INV1、反相器INV2以及电阻R2，反相器INV1的输入端与电位调制单元30的输出端电性连接；反相器INV2的输入端与反相器INV1的输出端电性连接，反相器INV2的输出端与显示时间控制单元10的控制端电性连接；电阻R2的一端与反相器INV1的输入端电性连接，电阻R2的另一端与反相器INV2的输出端电性连接。
可以理解的是，在本实施例中，由于在反相器INV1的输入端与反相器INV2的输出端之间通过电阻T2形成了正向反馈，可以使得B点电位以更快的速度上升，以更精准的时间打开晶体管T4。
在其中一个实施例中，施密特触发器20还包括电阻R1，电阻R1的一端与电位调制单元30的输出端电性连接，电阻R1的另一端与反相器INV1的输入端电性连接。
需要进行说明的是，该电阻R1可以对C点的电位进行适配，以便能够反相器INV1可以接入不同的C点电位。
其中，单个反相器在状态转换时，需要一定时间；而施密特触发器20转换状态时，存在这样的正反馈过程：A点电位VA增大，C点电位VC也随之增大，M点电位VM随之减小，B点电位VB随之增大，C点电位VC也随之增大。由于上述正反馈过程的存在，B点电位VB能够快速变化，从而使得B点电位VB的波形无限接近于方波，以此可以更精准地控制像素电路的发光时间。
在其中一个实施例中，如图7所示，反相器INV1包括晶体管M1和晶体管M2，晶体管M1的源极/漏极中的一个与晶体管M1的栅极电性连接，并接入高电位信号；晶体管M2的源极/漏极中的一个与晶体管M1的源极/漏极中的另一个、反相器INV2的输入端电性连接，晶体管M2的栅极与电位调制单元30的输出端电性连接，晶体管M2的源极/漏极中的另一个用于接入第一参考信号Vneg。
其中，高电位信号可以为电源正信号VDD。第一参考信号Vneg也可以为电源负信号VSS。
在其中一个实施例中，如图8所示，反相器INV2包括晶体管M3和晶体管M4，晶体管M3的源极/漏极中的一个与晶体管M3的栅极电性连接，并接入高电位信号；晶体管M4的源极/漏极中的一个与晶体管M3的源极/漏极中的另一个、显示时间控制单元10的控制端电性连接，晶体管M4的栅极与晶体管M2的源极/漏极中的一个电性连接，晶体管M4的源极/漏极中的另一个用于接入第一参考信号Vneg。
如图5和图9所示，基于施密特触发器20的高滞回特性，可以利用三角波控制信号Sweep实现PWM驱动方式。具体地，图5所示像素电路在一帧中的工作过程包括准备阶段S10和显示阶段S20，其中，在准备阶段S10中，G点电位V-G、三角波控制信号Sweep的电位V-Sweep均处于低电位，此时，发光器件D1中并无发光电流I-LED流过，发光器件D1保持熄灭状态。在显示阶段S20中，G点电位V-G由低电位跳变为高电位，驱动晶体管T2打开，发光器件D1中因有发光电流I-LED流过，发光器件D1点亮；随着三角波控制信号Sweep的电位V-Sweep逐渐抬高，通过电容C2的耦合作用，A点电位VA也在逐渐增加，当VA大于施密特触发器20的正向阈值电压时，施密特触发器20的输出电位即B点电位VB迅速抬高至高电位以快速打开晶体管T4，G点电位V-G可以迅速地由高电位跳变为低电位，进而迅速地关闭驱动晶体管T2，如此可以迅速地使发光器件D1由点亮状态转变为熄灭状态。
与图4相比，图9的三角波控制信号Sweep的电位V-Sweep、发光电流I-LED的下降沿更为陡峭，也就是说，图5所示像素电路可以更为精准地控制发光时间或者显示时间的时长。
同时，在图5所示像素电路中由于了具有高滞回特性的施密特触发器20，即当该施密特触发器20的输入电压上升至其正向阈值电压时，该施密特触发器20的输出电压将翻转为高电位，如此，该施密特触发器20的高电位的输出电压可以忽略晶体管T4的阈值电压不同或者漂移，而能够确保可以直接打开该晶体管T4，因此，在采用了施密特触发器20的本申请的像素电路中，也无需精心设计针对晶体管T4的阈值电压的补偿电路，也就是说，本申请提供的具有施密特触发器20的像素电路可以以更为简单的电路结构实现显示功能。
该显示功能可以通过对A点写入不同的初始电位，进而可以对应得到不同的显示时间，也无需频率特别高的信号，即可实现高精度的灰阶切分。
如图5和图10所示，在其中一个实施例中，本实施例提供一种显示面板，其包括上述至少一个实施例中的像素电路，像素电路还包括发光芯片200，施密特触发器20集成于发光芯片200中。
可以理解的是，本实施例提供的显示面板，通过在电位调制单元30的输出端与显示时间控制单元10的控制端之间串接施密特触发器20，可以更快速地导通显示时间控制单元10以关断驱动晶体管T2，进而能够更为精确地控制像素电路的显示时间或者发光时间。
需要进行说明的是，该发光芯片200可以为Mini-LED芯片，也可以为Micro-LED芯片，如图10所示，CMOS工艺封装的该发光芯片200可以包括第一引脚、第二引脚、第三引脚以及第四引脚，其中，第一引脚可以用于传输电源正信号VDD，第二引脚可以用于传输第一参考信号Vneg，第三引脚可以用于传输A点电位VA，第四引脚可以用于传输B点电位VB。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种像素电路，包括：
    驱动晶体管T2；和
    脉宽驱动模块，与所述驱动晶体管T2的栅极电性连接；
    其中，所述脉宽驱动模块包括：
    显示时间控制单元，所述显示时间控制单元的一端与所述驱动晶体管T2的栅极电性连接，所述显示时间控制单元的另一端用于接入第一参考信号，用于关断所述驱动晶体管T2；
    电位调制单元；以及
    施密特触发器，所述施密特触发器的输入端与所述电位调制单元的输出端电性连接，所述施密特触发器的输出端与所述显示时间控制单元的控制端电性连接。
  2. 根据权利要求1所述的像素电路，其中，所述施密特触发器包括：
    反相器INV1，所述反相器INV1的输入端与所述电位调制单元的输出端电性连接；
    反相器INV2，所述反相器INV2的输入端与所述反相器INV1的输出端电性连接，所述反相器INV2的输出端与所述显示时间控制单元的控制端电性连接；以及
    电阻R2，所述电阻R2的一端与所述反相器INV1的输入端电性连接，所述电阻R2的另一端与所述反相器INV2的输出端电性连接。
  3. 根据权利要求2所述的像素电路，其中，所述施密特触发器还包括电阻R1，所述电阻R1的一端与所述电位调制单元的输出端电性连接，所述电阻R1的另一端与所述反相器INV1的输入端电性连接。
  4. 根据权利要求2所述的像素电路，其中，所述反相器INV1包括：
    晶体管M1，所述晶体管M1的源极/漏极中的一个与所述晶体管M1的栅极电性连接，并接入高电位信号；和
    晶体管M2，所述晶体管M2的源极/漏极中的一个与所述晶体管M1的源极/漏极中的另一个、所述反相器INV2的输入端电性连接，所述晶体管M2的栅极与所述电位调制单元的输出端电性连接，所述晶体管M2的源极/漏极中的另一个用于接入第一参考信号。
  5. 根据权利要求4所述的像素电路，其中，所述反相器INV2包括：
    晶体管M3，所述晶体管M3的源极/漏极中的一个与所述晶体管M3的栅极电性连接，并接入所述高电位信号；和
    晶体管M4，所述晶体管M4的源极/漏极中的一个与所述晶体管M3的源极/漏极中的另一个、所述显示时间控制单元的控制端电性连接，所述晶体管M4的栅极与所述晶体管M2的源极/漏极中的一个电性连接，所述晶体管M4的源极/漏极中的另一个用于接入所述第一参考信号。
  6. 根据权利要求1所述的像素电路，其中，所述显示时间控制单元包括晶体管T4，所述晶体管T4的源极/漏极中的一个与所述驱动晶体管T2的栅极电性连接，所述晶体管T4的源极/漏极中的另一个用于接入所述第一参考信号，所述晶体管T4的栅极与所述施密特触发器的输出端电性连接。
  7. 根据权利要求6所述的像素电路，其中，所述电位调制单元包括电容C2，所述电容C2的一端与所述施密特触发器的输入端电性连接，所述电容C2的另一端用于接入三角波控制信号。
  8. 根据权利要求7所述的像素电路，其中，所述电位调制单元还包括晶体管T5，所述晶体管T5的源极/漏极中的一个用于接入电位设置信号，所述晶体管T5的栅极用于接入脉宽控制信号。
  9. 根据权利要求1所述的像素电路，其中，所述像素电路还包括：
    晶体管T1，所述晶体管T1的源极/漏极中的一个用于接入数据信号，所述晶体管T1的栅极用于接入脉幅控制信号，所述晶体管T1的源极/漏极中的另一个与所述驱动晶体管T2的栅极电性连接；
    晶体管T3，所述晶体管T3的源极/漏极中的一个用于接入第二参考信号，所述晶体管T3的栅极用于接入所述脉幅控制信号，所述晶体管T3的源极/漏极中的另一个与所述驱动晶体管T2的源极电性连接；
    电容C1，所述电容C1的一端与所述驱动晶体管T2的栅极电性连接，所述电容C1的另一端与所述驱动晶体管T2的源极电性连接；以及
    发光器件D1，所述发光器件D1的阳极与所述驱动晶体管T2的源极电性连接，所述发光器件D1的阴极用于接入电源负信号；
    其中，所述驱动晶体管T2的漏极用于接入电源正信号。
  10. 一种显示面板，包括如权利要求1所述的像素电路，所述像素电路还包括发光芯片，所述施密特触发器集成于所述发光芯片中。
  11. 根据权利要求10所述的显示面板，其中，所述施密特触发器包括：
    反相器INV1，所述反相器INV1的输入端与所述电位调制单元的输出端电性连接；
    反相器INV2，所述反相器INV2的输入端与所述反相器INV1的输出端电性连接，所述反相器INV2的输出端与所述显示时间控制单元的控制端电性连接；以及
    电阻R2，所述电阻R2的一端与所述反相器INV1的输入端电性连接，所述电阻R2的另一端与所述反相器INV2的输出端电性连接。
  12. 根据权利要求11所述的显示面板，其中，所述施密特触发器还包括电阻R1，所述电阻R1的一端与所述电位调制单元的输出端电性连接，所述电阻R1的另一端与所述反相器INV1的输入端电性连接。
  13. 根据权利要求11所述的显示面板，其中，所述反相器INV1包括：
    晶体管M1，所述晶体管M1的源极/漏极中的一个与所述晶体管M1的栅极电性连接，并接入高电位信号；和
    晶体管M2，所述晶体管M2的源极/漏极中的一个与所述晶体管M1的源极/漏极中的另一个、所述反相器INV2的输入端电性连接，所述晶体管M2的栅极与所述电位调制单元的输出端电性连接，所述晶体管M2的源极/漏极中的另一个用于接入第一参考信号。
  14. 根据权利要求13所述的显示面板，其中，所述反相器INV2包括：
    晶体管M3，所述晶体管M3的源极/漏极中的一个与所述晶体管M3的栅极电性连接，并接入所述高电位信号；和
    晶体管M4，所述晶体管M4的源极/漏极中的一个与所述晶体管M3的源极/漏极中的另一个、所述显示时间控制单元的控制端电性连接，所述晶体管M4的栅极与所述晶体管M2的源极/漏极中的一个电性连接，所述晶体管M4的源极/漏极中的另一个用于接入所述第一参考信号。
  15. 根据权利要求10所述的显示面板，其中，所述显示时间控制单元包括晶体管T4，所述晶体管T4的源极/漏极中的一个与所述驱动晶体管T2的栅极电性连接，所述晶体管T4的源极/漏极中的另一个用于接入所述第一参考信号，所述晶体管T4的栅极与所述施密特触发器的输出端电性连接。
  16. 根据权利要求15所述的显示面板，其中，所述电位调制单元包括电容C2，所述电容C2的一端与所述施密特触发器的输入端电性连接，所述电容C2的另一端用于接入三角波控制信号。
  17. 根据权利要求16所述的显示面板，其中，所述电位调制单元还包括晶体管T5，所述晶体管T5的源极/漏极中的一个用于接入电位设置信号，所述晶体管T5的栅极用于接入脉宽控制信号。
  18. 根据权利要求10所述的显示面板，其中，所述像素电路还包括：
    晶体管T1，所述晶体管T1的源极/漏极中的一个用于接入数据信号，所述晶体管T1的栅极用于接入脉幅控制信号，所述晶体管T1的源极/漏极中的另一个与所述驱动晶体管T2的栅极电性连接；
    晶体管T3，所述晶体管T3的源极/漏极中的一个用于接入第二参考信号，所述晶体管T3的栅极用于接入所述脉幅控制信号，所述晶体管T3的源极/漏极中的另一个与所述驱动晶体管T2的源极电性连接；以及
    电容C1，所述电容C1的一端与所述驱动晶体管T2的栅极电性连接，所述电容C1的另一端与所述驱动晶体管T2的源极电性连接。
  19. 根据权利要求18所述的显示面板，其中，所述发光芯片的阳极与所述驱动晶体管T2的源极电性连接，所述发光芯片的阴极用于接入电源负信号；
    其中，所述驱动晶体管T2的漏极用于接入电源正信号。
  20. 根据权利要求10所述的显示面板，其中，所述发光芯片包括第一引脚、第二引脚、第三引脚以及第四引脚。
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