WO2023112468A1 - 高周波電源装置及び高周波電力の出力制御方法 - Google Patents
高周波電源装置及び高周波電力の出力制御方法 Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0043—Converters switched with a phase shift, i.e. interleaved
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05H—PLASMA TECHNIQUE; PRODUCTION OF ACCELERATED ELECTRICALLY-CHARGED PARTICLES OR OF NEUTRONS; PRODUCTION OR ACCELERATION OF NEUTRAL MOLECULAR OR ATOMIC BEAMS
- H05H1/00—Generating plasma; Handling plasma
- H05H1/24—Generating plasma
- H05H1/46—Generating plasma using applied electromagnetic fields, e.g. high frequency or microwave energy
Definitions
- the present invention relates to a high-frequency power supply and a high-frequency power output control method, and more particularly to a high-frequency power supply that outputs high-frequency pulse output in a plurality of stages of two or more levels, and a method for outputting high-frequency pulse output in a plurality of stages of output levels. .
- a high-frequency signal is power-amplified by a high-frequency amplifier to output a high-frequency pulse output.
- High-frequency pulse output with an output of 1 kw or more and a frequency range of 27 MHz to 100 MHz is suitable for semiconductor manufacturing equipment, flat panel display (liquid crystal panel, organic panel) manufacturing equipment, solar panel manufacturing equipment, CO 2 laser processing machines, etc. Applied for industrial use.
- the instantaneous power consumption of a transistor is represented by the product of the instantaneous current and the instantaneous voltage, and the time average of the RF one cycle integral value of the instantaneous power consumption is the time average power consumption of the transistor.
- the current and voltage at the drain terminal of the transistor are sine waves with opposite phases to each other, and in class A operation there is a large overlap between the current and voltage waveforms.
- the efficiency of the amplifier is therefore low.
- the drain current is biased to a half-wave rectified waveform, and the drain voltage is a sine wave voltage.
- the drain voltage is a sinusoidal voltage
- the overlapping portion of the current and voltage waveforms is reduced, but the overlap is not eliminated.
- Class D amplifiers are known to achieve high efficiency by the voltage-current relationship in the time domain
- class F and EF amplifiers are known to achieve high efficiency by the voltage-current relationship in the frequency domain.
- Conventionally known methods for controlling the pulse output of a switching mode amplifier include DC voltage control that varies the DC input voltage to be input to the amplifier, and PWM control that controls the pulse width of the gate signal that drives the switching element. ing.
- Patent Document 1 a power supply device using phase shift control has been proposed.
- Patent Document 2 a power supply device using phase shift control has been proposed.
- phase shift control In the method of controlling the high-frequency pulse output by phase shift control, a constant DC voltage is supplied to the amplification section, and the phase difference ⁇ between the two amplification sections is set to a first predetermined value on the High side and a second predetermined value on the Low side. By switching between predetermined values, pulse outputs with two output levels are output.
- phase shift control when the outputs of two amplifiers are combined by a combiner, the output power is adjusted by varying the phase difference ⁇ between the two amplifiers. At this time, an internal loss occurs due to the dummy resistors mounted in the combiner inside the power supply.
- Phase shift control has the problem of low power conversion efficiency due to internal loss consumed inside the power supply.
- the phase difference ⁇ between the two amplifiers is divided into a first predetermined value range (0 [deg] to 90 [deg]) for outputting High side power and a second predetermined value range (90 [deg]) for outputting Low side power. deg] to 180 [deg]), when the output level is switched, the differential power that was not transmitted to the output side at a phase difference other than 0 [deg] in the first predetermined value region is consumed inside the power supply as internal loss. Further, at the phase difference ⁇ in the second predetermined value range, the internal loss is greater than the output power, and the power conversion efficiency of the entire high-frequency power supply is 50% or less.
- a high-frequency power supply that performs phase shift control has a problem of low power conversion efficiency due to internal loss consumed inside the power supply. This problem also has undesirable effects in terms of manufacturing costs due to reduced productivity and environmental considerations due to CO2 reduction.
- An object of the present invention is to solve the above-described conventional problems, and to reduce the reduction in power conversion efficiency due to internal loss consumed inside the power supply of the high-frequency power supply, in a high-frequency power supply and a high-frequency power output control method.
- the present invention is a high-frequency power control that makes the output power of a high-frequency pulse output variable. reduce power conversion efficiency degradation due to internal losses.
- the DC voltage control controls the output power by controlling the DC voltage supplied to the amplifier.
- Phase difference control controls the output power by controlling the phase difference ⁇ of a plurality of control signals that control the amplifier.
- the present invention controls the output power by DC voltage control when the output level is in the high output level range, and controls the output power by phase difference control when the output level is in the low output level range.
- the phase difference ⁇ ( ⁇ d, ⁇ s) in the phase difference control is fixed and the DC voltage Vdc supplied to the amplifier is made variable in the high output level range. Since DC voltage control does not consume power due to dummy resistors inside the high-frequency power supply, the problems of internal loss consumed inside the power supply and low power conversion efficiency are resolved, and efficiency is improved. There is a drawback in that the size of the device is required to accommodate DC voltage control over the entire range of output levels.
- control of output power by phase difference control limits the controlled output level to a low output level range.
- the output level flowing through the dummy resistor of the high-frequency power supply device is suppressed to a low level, so that the internal loss generated in the dummy resistor is reduced and the efficiency is improved.
- the phase difference control of the present invention includes two controls.
- the first phase difference control is PWM control that modulates the pulse width with a phase difference ⁇ d between control signals, which is a phase difference between control signals.
- a duty ratio (Duty) of a pulse signal for driving a switching element is made variable by PWM control.
- PWM control since there is no internal loss due to the dummy resistance of the high frequency power supply, high efficiency is achieved.
- phase difference control In the second phase difference control, a pair of control signals input to each of the two amplifiers is set as one set, and the phase difference between the sets of control signals input to the two amplifiers is the phase difference ⁇ s between the control signal sets.
- the phase shift control (PS control) for shifting the phase difference ⁇ s between the control signal sets.
- Phase shift control controls the output power obtained by combining the outputs of the two amplifiers. This phase shift control (PS control) causes a loss in the dummy resistor.
- the phase difference control uses PWM control for the first phase difference control and phase shift control (PS control) for the second phase difference control depending on the output level.
- the low output level range is divided into a high level side and a low level side.
- Output power is made variable by shift control (PS control).
- Phase shift control has the characteristic of lower power conversion efficiency due to internal loss consumed inside the power supply.
- phase shift control (PS control) on the low level side where the ratio of internal loss is large compared to the output power, when phase shift control is applied to the high level side It is possible to reduce the amount of internal loss.
- the range of controllable output levels can be expanded to the low level side, internal loss within the entire range of the output level range is reduced, and efficiency is improved. is planned.
- the DC voltage control and phase difference control according to the present invention make the output power continuously variable within each output level range. Furthermore, at the time of switching between control from DC voltage control to phase difference control or from phase difference control to DC voltage control, by matching the output levels at the ends of both controls, the output power can be controlled over the entire output level range. becomes continuously variable without becoming discontinuous at .
- the present invention includes (A) an aspect of a high-frequency power supply device and (B) an aspect of a high-frequency power output control method.
- An aspect of the high-frequency power supply of the present invention includes a pair of amplifiers and a combiner that combines amplifier outputs of the pair of amplifiers to generate high-frequency pulse output power.
- the control unit for controlling the output power includes a first control unit for controlling the output power by DC voltage control for controlling the DC voltage Vdc supplied to the pair of amplifiers, and the phase difference between the control signals for controlling the amplifier outputs of the pair of amplifiers. and a second control section for phase difference control of the output power by ⁇ ( ⁇ d, ⁇ s). DC voltage control by the first controller and phase difference control by the second controller are switched according to the output level of the output power.
- the high-frequency power supply device of the present invention comprises a pair of amplifiers and a combiner for generating high-frequency pulse output power by combining the amplifier outputs of the pair of amplifiers as elements constituting the first control unit and the second control unit.
- a power control unit that calculates a DC voltage command value Vref * used for DC voltage control and a phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) used for phase difference control in controlling the output power of the high-frequency pulse output;
- a DC voltage control unit that controls a DC voltage Vdc supplied to a pair of amplifiers based on a DC voltage command value Vref * , and positions the pair of amplifiers based on a phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ).
- a control signal generator is provided for generating a control signal for phase difference control.
- the power control unit at the output level of the output power, (a) calculating a DC voltage command value Vref * for DC voltage control for a high output level range; (b) A phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) for phase difference control is calculated for a low output level range, and switching between DC voltage control and phase difference control is performed according to the output level of the output power. to control the output power.
- the first control unit that performs DC voltage control includes a DC voltage calculation unit that calculates the DC voltage command value Vref * in the power control unit, and a DC voltage control unit that performs DC voltage control based on the DC voltage command value Vref * . Configured.
- a second control unit that performs phase difference control includes a phase difference calculation unit that calculates phase difference command values ⁇ * ( ⁇ d * , ⁇ s*) and a phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) in the power control unit. * ) to generate a control signal having a phase difference ⁇ ( ⁇ d, ⁇ s).
- a single-ended signal or a differential signal can be used as the control signal used in the present invention, but a differential signal is preferable in the high-frequency region.
- a differential signal is preferable in the high-frequency region.
- the power control unit determines the output level of the output power based on the output power command value, and determines whether to apply DC voltage control or phase difference control according to the level of the output level. It determines whether the output level is in the high output level range or the low output level range, and switches between DC voltage control and phase difference control.
- the power control unit Based on the difference between the output power command value FWD_ref * and the output power feedback value FWD_FB, the power control unit performs DC voltage control when the output level is in the high output level range, and performs phase difference control when the output level is in the low output level range. I do.
- the DC voltage command value Vref * is calculated based on the difference between the output power command value FWD_ref * and the output power feedback value FWD_FB by DC voltage control.
- the DC voltage command value Vref * is a reference voltage for the DC voltage Vdc applied to the amplifier. By applying the DC voltage Vdc to the amplifier, the amplifier outputs the output power FWD based on the DC voltage command value Vref * .
- phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) is calculated based on the difference between the output power command value FWD_ref * and the output power feedback value FWD_FB by phase difference control.
- the phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) is used as a manipulated variable for generating a control signal based on the phase difference command value ⁇ * in the control signal generator, and the phase difference ⁇ ( ⁇ d, ⁇ s)
- the amplifier outputs the output power FWD based on the output power command value FWD_ref * .
- the DC voltage control unit varies the DC voltage Vdc supplied to the amplifier in the high output level range based on the DC voltage command value Vref * obtained by the DC voltage control of the power control unit, This controls the output power of the amplifier.
- the DC voltage control unit Based on the difference between the feedback voltage Vdc_FB and the DC voltage command value Vref * , the DC voltage control unit sets the manipulated variable ⁇ for controlling the DC voltage Vdc applied to the amplifier to match the DC voltage command value Vref * .
- An AD/DC converter is provided that controls the AD/DC converter of the amplifier according to the manipulated variable ⁇ to make the DC voltage Vdc variable.
- the output voltage of the DC voltage Vdc is controlled by controlling the AD/DC converter with the manipulated variable ⁇ based on the DC voltage command value Vref * .
- the control signal generating section generates two amplifiers based on the phase difference command values ⁇ * ( ⁇ d * , ⁇ s * ) obtained by the phase difference control of the power control section in the low output level range. to control the phase difference ⁇ ( ⁇ d, ⁇ s) of a pair of control signals input to .
- the phase difference ⁇ ( ⁇ d, ⁇ s) of the control signal corresponds to the phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) obtained by the phase difference control of the power control section.
- one differential signal is composed of a pair of signals, a P signal and an N signal, which have an anti-phase relationship.
- a pair of control signals has a total of two pairs of four signals.
- the phase difference control includes calculation of phase difference command values ⁇ * ( ⁇ d * , ⁇ s * ) performed by the power control unit and phase difference command values ⁇ * ( ⁇ d * , ⁇ s * ) performed by the control signal generation unit. and generating a control signal for the phase difference ⁇ ( ⁇ d, ⁇ s).
- the control signal generator generates a control signal having a phase difference ⁇ ( ⁇ d, ⁇ s) based on the phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) calculated by the power controller.
- the phase difference control of the present invention is based on the calculation of the phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) by the power control section and the control signal based on the phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ). It consists of generation of a control signal having a phase difference ⁇ ( ⁇ d, ⁇ s) by a generator.
- Control modes applied to the phase difference control by the phase difference calculator and the control signal generator include (a) PWM control (duty control) and (b) phase shift control (PS control).
- the control signal generation unit has a function of generating a control signal by phase difference control of PWM control and phase shift control (PS control), and in the low output level range, the phase difference command value obtained by the phase difference calculation of the power control unit
- a control signal having a phase difference ⁇ ( ⁇ d , ⁇ s) is generated based on ⁇ * ( ⁇ d*, ⁇ s *) .
- the control signal generated by the control signal generating section is converted into a gate signal by the driver, and drives and controls the switching element of the amplifier to control the output power.
- Phase difference control has multiple types of control modes.
- (a) First control mode of phase difference control The first control mode of phase difference control is a control mode by PWM control (duty control). For output power on the high output level side in the low output level range, a control signal having a phase difference ⁇ d between control signals is generated by PWM control using the phase difference command value ⁇ d * between control signals by PWM control. , to control the output power.
- the inter-control signal phase difference ⁇ d which is determined based on the inter-control signal phase difference command value ⁇ d * , determines the duty ratio (Duty) of the gate signal of the switching element of the amplifier. controlled.
- the second control mode of phase difference control is a control mode by phase shift control (PS control).
- PS control phase shift control
- phase shift control In the phase shift control, a pair of control signals to be input to each amplifier are set, and a phase difference ⁇ s between the control signal sets input to the two amplifiers is controlled. It controls the phase difference of the gate signals between the two amplifiers and controls the output power of the high-frequency pulse output generated by synthesizing the amplifier outputs of the two amplifiers.
- phase difference control includes PWM control (duty control) of the first control mode and phase shift control (PS control) of the second control mode. It is a control mode consisting of.
- the power control unit provides a phase difference command including a phase difference command value ⁇ d * between a pair of control signals to be input to each amplifier and a phase difference command value ⁇ s * between a control signal set composed of a pair of control signals to be input to each amplifier. Calculate the value ⁇ * .
- the control signal generator generates a control signal having a phase difference ⁇ ( ⁇ d, ⁇ s) based on the phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) obtained by the phase difference calculation of the power controller, and outputs the output level.
- the output power of the high-frequency pulse output is controlled by selectively using phase difference control of PWM control and phase shift control according to .
- the pulse width controlled by PWM control defines the pulse width of the gate signal.
- the minimum pulse width of the gate signal is limited by the operating characteristics of the switching element. Therefore, the minimum pulse width of the pulse width narrowed by the PWM control is also limited, and there is a possibility that a pulse width shorter than the minimum pulse width may interfere with the PWM control.
- the pulse width of the gate signal is narrowed by PWM control up to the minimum pulse width narrowed by PWM control, and the pulse width shorter than the minimum pulse width is controlled by phase shift control. This controls the output power down to an arbitrary low level range.
- Aspect of high-frequency power output control method of the present invention is a high-frequency power control method that controls a pair of amplifiers and makes the output power of the high-frequency pulse output variable. DC voltage control and phase difference control are switched according to the level.
- the output power is controlled by DC voltage control for controlling the DC voltage supplied to the pair of amplifiers.
- the output power is controlled by phase difference control for controlling the phase difference ⁇ ( ⁇ d, ⁇ s) of a plurality of control signals input to the pair of amplifiers.
- DC voltage control DC voltage control obtains a DC voltage command value Vref * in the high output level range, and varies the DC voltage Vdc supplied to the amplifier based on the obtained DC voltage command value Vref * . to control the output power of the
- Phase Difference Control Phase difference control is applied to the low power level range.
- the low output level range is divided into the high output level side and the low output level side, and the output power on the high output level side is controlled by PWM control (duty control) using the phase difference ⁇ d between the control signals, and the low output level is controlled.
- PWM control duty control
- the output power on the level side is controlled by phase shift control (PS control) using the phase difference ⁇ s between control signal sets.
- the phase difference control includes a phase difference calculation step of obtaining phase difference command values ⁇ * ( ⁇ d * , ⁇ s * ), and a phase difference ⁇ ( ⁇ d, ⁇ s) based on the phase difference command values ⁇ * ( ⁇ d * , ⁇ s * ). and a control signal generating step for generating
- phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) is calculated based on the difference between the output power command value and the output power feedback value.
- Control signal phase difference control generates a control signal having a phase difference ⁇ ( ⁇ d, ⁇ s) based on a phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) obtained by phase difference calculation.
- the output power is controlled by driving the amplifier with a control signal.
- Phase difference control is applied to (a) the first control mode by PWM control (duty control) and (b) the second control mode by phase shift control (PS control). Phase difference control is applied to the low output level range and the switching elements of the amplifier are driven and controlled by gate signals generated based on the control signal to control the output power.
- PWM control duty control
- PS control phase shift control
- phase difference ⁇ is the phase difference ⁇ d between the control signals input to the amplifier, and the phase difference control adjusts the pulse width between the control signals.
- the output power of the high-frequency pulse output is controlled by PWM control that controls the phase difference ⁇ d and controls the duty ratio (Duty) of the gate signal of the switching element of the amplifier.
- phase difference ⁇ is the phase difference ⁇ s between the control signal sets of the control signals input to the amplifier, and the phase difference control is phase shift control (PS control).
- phase difference control includes PWM control (duty control) of the first control mode and phase shift control (PS control) of the second control mode. It is a control mode consisting of.
- phase difference control PWM control and phase shift control (PS control) are selectively used according to the output level.
- the output power is controlled by PWM control using the phase difference ⁇ d between control signals on the high output level side, and the phase difference ⁇ s between control signal sets is used on the low output level side.
- the output power is controlled by phase shift control.
- phase difference command value ⁇ * between the control signal phase difference command value ⁇ d * to be input to each amplifier and the phase difference command value ⁇ s * between the control signal sets to be input to each amplifier are obtained by phase difference calculation, and the obtained phase difference command
- the values ⁇ * ( ⁇ d * , ⁇ s * ) are used to generate control signals with phase differences ⁇ ( ⁇ d, ⁇ s) by phase difference control.
- the pulse width controlled by PWM control defines the pulse width of the gate signal. Since the pulse width of the gate signal is limited by the operating characteristics of the switching element, the minimum pulse width of the pulse width narrowed by PWM control is also limited, and there is a possibility that problems may arise in PWM control with a pulse width shorter than the minimum pulse width. .
- the pulse width of the gate signal is controlled by PWM control up to the minimum pulse width narrowed by PWM control, and the pulse width shorter than the minimum pulse width is controlled by phase shift control (PS control).
- PS control phase shift control
- phase difference control between control signals by the power control section has a plurality of modes of first to third modes.
- the power control unit compares the output power feedback value FWD_FB of the high-frequency pulse output with the output power command value FWD_ref * to generate a pair of control signals to be input to each amplifier. Phase difference control is performed to obtain a control signal phase difference command value ⁇ d * between control signals.
- the power control unit sets the control signal phase difference command value ⁇ d * between the pair of control signals in each amplifier based on the comparison of the amplifier output of each amplifier. Adjust and provide phase difference control to balance the amplifier outputs of the two amplifiers.
- the power control unit includes, in each of the two amplifiers, a first inter-control-signal phase difference ⁇ da between a pair of control signals input to one of the amplifiers, and Phase difference control for adjusting the control signal phase difference command values ⁇ da * and ⁇ db * such that the second control signal phase difference ⁇ db between the pair of control signals input to the other amplifier is the same phase difference amount. conduct.
- phase difference control section performs phase shift control to generate a control signal having a phase difference ⁇ s based on a phase difference command value ⁇ s * between control signal sets.
- Control mode of PWM control PWM control includes a plurality of control modes of a first control mode to a third control mode. include.
- phase shift control In phase shift control, control between two sets of control signals based on a comparison between the output power feedback value FWD_FB of the high frequency pulse output and the output power command value FWD_ref * A phase difference command value ⁇ s * between signal sets is obtained.
- control signal is in the form of a differential signal whose phases are opposite to each other, so that noise immunity is enhanced in driving the switching elements of the amplifier.
- differential signals operation using single-ended signals is not excluded.
- FIG. 3 is a schematic diagram of control of the present invention
- FIG. 5 is a diagram showing how to properly use DC voltage control and phase difference control according to the present invention
- FIG. 4 is a diagram for explaining the relationship between power control and output power according to the present invention
- FIG. 4 is a diagram for explaining the relationship between power control and output power according to the present invention
- It is a figure for demonstrating the relationship between duty ratio Duty and an output voltage.
- FIG. 4 is a diagram for explaining the relationship between PWM control and output power
- 4 is a flow chart for explaining an aspect of a high-frequency power output control method according to the present invention
- It is a figure for demonstrating the structural example of the high frequency power supply device of this invention.
- FIG. 4 is a diagram for explaining a configuration example of a main part of a power control unit of the present invention;
- FIG. 4 is a signal diagram for explaining control signals, gate signals, etc. of the high-frequency power supply device of the present invention;
- FIG. 4 is a signal diagram for explaining control signals, gate signals, etc. of the high-frequency power supply device of the present invention;
- FIG. 4 is a signal diagram for explaining control signals, gate signals, etc. of the high-frequency power supply device of the present invention;
- FIG. 4 is a signal diagram for explaining control signals, gate signals, etc. of the high-frequency power supply device of the present invention;
- FIG. 4 is a signal diagram for explaining an example of parallel connection of the high-frequency power supply device of the present invention;
- FIG. 1 The outline of the control according to the present invention will be described below with reference to FIGS. 1 and 2.
- FIG. Regarding power control according to the present invention, the relationship between the power control according to the present invention and output power will be described using FIGS. 3 and 4, the relationship between internal loss and output power will be described using FIG. 5, and FIG. to explain the relationship between PWM control and output power.
- the aspect of the high-frequency power output control method of the present invention will be described using the flowchart of FIG. 7, and the configuration example of the high-frequency power supply device of the present invention will be described using FIGS. Furthermore, a configuration example of a main part of the power control unit will be described with reference to FIG. 11 . 12 to 14 are signal diagrams of control signals, gate signals, etc. of the high-frequency power supply device of the present invention. Further, in the high-frequency power supply device of the present invention, a configuration example in which a plurality of sets of the configuration example shown in FIG. 8 are used and connected in parallel will be described with reference to FIG.
- FIG. 1 is a schematic diagram for explaining control according to the present invention
- FIG. 2 is a diagram for explaining proper use of DC voltage control and phase difference control according to the present invention
- FIG. 2(b) and 2(c) show a case where the power output is controlled by phase difference control (CNTL2).
- FIG. 2(b) shows a case where phase difference control (CNTL2) is performed by PWM control
- FIG. 2(c) shows a case where phase difference control (CNTL2) is performed by phase shift control.
- the high-frequency power output control selectively uses DC voltage control (CNTL1) and phase difference control (CNTL2) according to the output level.
- the phase difference control (CNTL2) of the present invention is applied to a configuration in which the amplifier outputs of the two amplifiers 2 (2A, 2B) are combined by the combiner 5 to output the output power.
- the configuration that combines the amplifier outputs of two amplifiers 2 (2A, 2B) to generate output power is based on the phase difference ⁇ s between the two control signal sets input to the amplifier. This configuration is applied to power control by phase shift control for controlling the phase difference ⁇ s amp between amplifier outputs and controlling the output power.
- the output power when controlling the output power in the high output level range, the output power is controlled by the DC voltage control (CNTL1), and when controlling the output power in the low output level range, the phase difference control (CNTL2 ) to control the output power.
- the DC voltage control CTL1
- the phase difference control CTL2
- the output level threshold that distinguishes between the high output level range and the low output level range can be arbitrarily determined in consideration of the DC voltage control configuration, main circuit system, power conversion efficiency, or the like.
- DC voltage control (CNTL1)
- the DC voltage Vdc supplied to the amplifier is made variable in the high output level range.
- the phase difference command value ⁇ * is fixed so that the phase difference ⁇ of the phase difference control is fixed, and the DC voltage Vdc supplied to the pair of amplifiers 2 (2A, 2B) is changed to the DC voltage command value Vref *. to control each output power and control the combined output power. Note that the DC voltage command value Vref * is not shown in FIG.
- phase difference ⁇ of phase difference control is fixed, and the output power is varied only by DC voltage control.
- the phase difference ⁇ is fixed by fixing the phase difference of both the control signal phase difference ⁇ d between the control signals and the phase difference ⁇ s between the control signal sets. Stop variable output power by
- the output level range to which the DC voltage control of the present invention is applied can be limited to an arbitrary high output level range. As a result, the size and weight of the high-frequency power supply can be reduced.
- high output power indicated by High is output by DC voltage control
- low output power indicated by Low 1 is output by phase difference control of PWM control
- low output power indicated by phase shift control (PS control) is indicated by Low 2.
- a lower output level of low output power is output.
- Solid line arrows, dashed line arrows, and dashed line arrows in FIG. 1 indicate control states of DC voltage control, phase difference control of PWM control, and phase difference control of phase shift control (PS control), respectively. .
- FIG. 2(a) shows the control mode of power output by DC voltage control (CNTL1)
- the left side of the horizontal axis in the figure shows the control mode in the control signal
- the right side shows the control mode in the amplifier.
- the vertical axis in FIG. 2 indicates the output power
- the area above the dashed line indicates the high output level range
- the area below the dashed line indicates the low output level range.
- the output power is made variable only by DC voltage control in the control mode of the amplifier.
- the high output level range is defined by a maximum DC voltage value Vdc_max and a minimum DC voltage value Vdc_min.
- the maximum value Vdc_max of the DC voltage is set according to the specifications of a device that generates a DC voltage, such as an AC/DC converter that outputs a DC voltage.
- the minimum value Vdc_min of the DC voltage is arbitrarily determined depending on the control system and main circuit system of the device that generates the DC voltage, power conversion efficiency, and the like.
- phase difference control In DC voltage control, by fixing the phase difference ⁇ d between control signals for PWM control of phase difference control and the phase difference ⁇ s between control signal sets for phase shift control, output power is not controlled by phase difference control.
- the output power is controlled by varying only the DC voltage Vdc.
- the inter-control signal phase difference ⁇ d and inter-control signal set phase difference ⁇ s can be fixed by fixing inter-control signal phase difference command value ⁇ d * and inter-control signal set phase difference command value ⁇ s * . can.
- phase difference control (CNTL2)
- the control signal used for the phase difference control of the present invention can be a single-ended signal or a differential signal.
- a differential signal with high noise resistance is suitable for accurately transmitting phase difference and duty information.
- control signals based on differential signals will be described. Note that the differential signal is two signals whose phases are opposite to each other, and can be converted into a single-ended signal by the difference between the two signals.
- Control of output power by phase difference control limits the output level range for control to a low output level range. As a result, the internal loss due to the dummy resistance of the high-frequency power supply is reduced, and the efficiency is improved.
- a pair of control signals are input to each one amplifier.
- a pair of control signals Sig1a and Sig2a are input to the amplifier 2A, and a pair of control signals Sig1b and Sig2b are input to the amplifier 2B.
- each of the control signals Sig1a, Sig2a, Sig1b, and Sig2b is a differential signal
- two pairs of control signals are input to each amplifier when two differential signals are regarded as a pair of signals. Therefore, the number of signals included in the two pairs of control signals is four.
- phase difference between two pairs of control signals input to one amplifier is the phase difference between control signals ⁇ d
- phase difference between the two pairs of control signals (Sig1a, Sig2a) input to the amplifier 2A is
- the phase difference between the control signals is represented by ⁇ da
- the phase difference between the two pairs of control signals (Sig1b, Sig2b) input to the amplifier 2B is represented by the phase difference between control signals ⁇ db.
- the two pairs of control signals (Sig1a, Sig2a) input to the amplifier 2A and the two pairs of control signals (Sig1b, Sig2b) input to the amplifier 2B constitute sets of control signals, respectively.
- the phase difference between the control signal sets is represented by the phase difference ⁇ s between the control signal sets.
- the phase difference control includes two controls, the first phase difference control (CNTL2d) and the second phase difference control (CNTL2s).
- the first phase difference control (CNTL2d) is PWM control that modulates the pulse width by the phase difference ⁇ d between control signals, and the duty ratio (Duty) of the pulse signal that drives the switching element based on the PWM-controlled control signal. is variable.
- the second phase difference control (CNTL2s) is a phase shift control (PS control) that shifts the inter-control signal set phase difference ⁇ s between a pair of control signal sets, and the degree of overlap of the output powers of the two amplifiers. to control the output power.
- the control of the output power by PWM control is highly efficient because there is no internal loss due to the dummy resistance of the high-frequency power supply.
- CNTL2d indicates PWM control in which the pulse width is modulated by the phase difference ⁇ d ( ⁇ da, ⁇ db) between the control signals of two pairs of control signals
- CNTL2s indicates the phase difference between the control signal sets between the pair of control signal sets.
- Phase shift control (PS control) for shifting the phase difference ⁇ s is shown.
- phase difference between the two pairs of control signals Sig1a and Sig2a input to the amplifier 2A is controlled to be the phase difference ⁇ da between the control signals.
- phase difference between the pair of control signals Sig1b and Sig2b is controlled to be the inter-control-signal phase difference ⁇ db.
- a control signal Sig1a and a control signal Sig2a which are two pairs of differential signals having a phase difference ⁇ da between the control signals, are input to the amplifier 2A, and the duty ratio of the gate signal of the switching element is determined based on the phase difference ⁇ da between the control signals. (Duty) is controlled, and the output power of the high-frequency pulse output is controlled by the duty ratio (Duty).
- control signal Sig1b and the control signal Sig2b which are two pairs of differential signals having a phase difference ⁇ db between the control signals, are input to the amplifier 2B, and the gate signal of the switching element is input based on the phase difference ⁇ db between the control signals. is controlled, and the output power of the high-frequency pulse output is controlled by the duty ratio (Duty).
- DutyA DutyA based on the phase difference ⁇ da between the control signals
- DutyB DutyB based on the phase difference ⁇ db between the control signals
- Phase difference control divides the low output level range into high output level and low output level, (i) A mode of applying PWM control of the first phase difference control for high output levels (ii) A mode of applying phase shift control (PS control) of the second phase difference control to low output levels can do.
- FIG. 2(b) shows a control mode of power output by only PWM control of the first phase difference control in the control of output power by phase difference control (CNTL2).
- the left side of the dashed line shows the control mode of the control signal
- the right side shows the control mode of the amplifier.
- the vertical axis in the figure indicates the output power, with the lower dashed line as the boundary, the upper side indicates the high output level side, and the lower side indicates the low output level side.
- the output power is made variable by the phase difference control of PWM control (CNTL2d) in the control mode of the control signal, and in the control mode of the amplifier,
- the output power is made variable by duty control based on the phase difference ⁇ d ( ⁇ da, ⁇ db) between PWM-controlled control signals.
- the duty ratio Duty (DutyA, DutyB) of the gate signals for driving the amplifier is obtained based on the phase difference ⁇ d ( ⁇ da, ⁇ db) between the control signals.
- the high output level side within the low output level range is defined by the maximum duty ratio Duty_max at which the duty ratio reaches its maximum value and the minimum duty ratio Duty_min at which the duty ratio reaches its minimum value.
- the maximum duty ratio Duty_max is determined as the minimum required dead time DT_min from the balance between the output power of the switching element and the power conversion efficiency, and the power output obtained at this time matches the minimum output during DC voltage control.
- the minimum duty ratio Duty_min is determined depending on the response speed of the switching elements included in the amplifier, and is set by the pulse width corresponding to the fastest response speed of the switching elements.
- the DC voltage Vdc for performing DC voltage control and the phase difference ⁇ s between control signal sets for performing phase shift control are fixed, and the phase difference between control signals for performing PWM control is fixed.
- the output power is controlled by varying only ⁇ d.
- the fixed values of the DC voltage Vdc and the phase difference ⁇ s between control signal sets can be determined arbitrarily.
- the phase difference between control signals is The control width of the output power can be controlled in the PWM control performed by making the phase difference ⁇ d variable.
- FIG. 2(c) shows power output control only by the phase shift control of the second phase difference control in the control of the output power by the phase difference control (CNTL2). It shows the mode.
- the left side of the dashed line shows the control mode of the control signal
- the right side shows the control mode of the amplifier.
- the vertical axis in the figure indicates the output power, with the lower dashed line as the boundary, the upper side indicates the high output level side, and the lower side indicates the low output level side.
- phase shift control is applied instead of PWM control.
- the inter-control signal set phase difference ⁇ s between sets of control signals for driving and controlling the amplifier is varied in the range of 0 [deg] to 180 [deg].
- the output power when the phase difference ⁇ s between the control signal sets is 0 [deg] corresponds to the output power when the duty ratio Duty is the minimum duty ratio Duty_min in the PWM control.
- the output power when the phase difference ⁇ s between control signal sets is 180 [deg] corresponds to power zero.
- the output power is made variable by the phase shift control (CNTL2s) of the phase difference control in the control mode of the control signal, and in the control mode of the amplifier
- the switching element is driven by the gate signal of the inter-amplifier phase difference ⁇ s amp based on the inter-amplifier phase difference ⁇ s of the phase-shift controlled control signals to make the output power variable.
- the range of the phase difference ⁇ s between control signal sets for performing phase shift control is 0 [deg] to 180 [deg].
- the phase shift control when the phase difference ⁇ s between the control signal sets is 0 [deg], the maximum output power in the phase shift control is obtained, and when the phase difference ⁇ s between the control signal sets is 180 [deg], the phase shift is Minimum output power in control is obtained.
- the output power can be varied continuously.
- the pulse width controlled by PWM control defines the pulse width of the gate signal. Since the pulse width of the gate signal is limited by the operating characteristics of the switching element, the minimum pulse width of the pulse width narrowed by PWM control is also limited, and PWM control with a pulse width shorter than the minimum pulse width may cause problems. .
- the pulse width of the gate signal is controlled by PWM control up to the minimum pulse width of the pulse width narrowed by PWM control, and the pulse width shorter than the minimum pulse width is controlled by phase shift control (PS control).
- PWM control enables control even in a low level range, which is difficult to control, and enables control of the output power up to an arbitrary low level range.
- phase difference control may be performed only by PWM control without applying phase shift control (PS control).
- Phase shift control has a problem of low power conversion efficiency due to internal loss consumed inside the power supply. , the amount of internal loss can be made smaller than when phase shift control (PS control) is applied even on the high level side. As a result, the internal loss is reduced in the entire range of output levels, and efficiency is improved.
- the output power is continuously variable within each output level range, and the control is switched from DC voltage control to phase difference control or from phase difference control to DC voltage control.
- the output power of the output level can be made continuously variable over the entire range without being discontinuous.
- the present invention can arbitrarily set the change characteristics of the output power in each of the high output voltage range and the low output voltage range.
- 3 and 4 show examples of change characteristics. Here, an example of four output voltage ranges of high output voltage High, low output voltages Low1 and Low2, and zero output voltage is shown.
- FIG. 3 shows an example of a mode in which output power is kept constant by a constant output voltage within each output voltage range.
- the phase differences ⁇ da and ⁇ db between the control signals and the phase difference ⁇ s between the control signal sets are fixed, and the DC voltage Vdc is variable. Control power. At this time, the output power is made constant by keeping the DC voltage Vdc constant.
- the output power is controlled by PWM control in which the DC voltage Vdc and the phase difference ⁇ s between the control signal sets are fixed, and the phase differences ⁇ da and ⁇ db between the control signals are variable. At this time, the output power is made constant by making the phase differences ⁇ da and ⁇ db between the control signals constant.
- the output power is controlled by phase shift control in which the DC voltage Vdc and the phase differences ⁇ da and ⁇ db between the control signals are fixed, and the phase difference ⁇ s between the control signal sets is variable. At this time, the output power is made constant by setting the phase difference ⁇ s between the control signal sets to a constant phase difference.
- the output voltage is set to zero output voltage by DC voltage control or phase difference control, and variable control of the output voltage is not performed. According to this constant output power mode, the output power changes stepwise between each output voltage range.
- FIG. 4(a) shows an example of aspect in which the output power is linearly variable within each output voltage range.
- the phase differences ⁇ da and ⁇ db between the control signals and the phase difference ⁇ s between the control signal sets are fixed, and the DC voltage Vdc is made variable.
- Output power is controlled by DC voltage control.
- the DC voltage Vdc is made variable in a root function (square root function) manner with respect to the linear change in the output power so that the output power is linearly variable.
- the relationship between the change in the inter-control-signal-set phase difference ⁇ s and the change in the output power does not necessarily have a linear relationship. adjust for changes in
- DC voltage control or phase difference control is set so that the output voltage becomes zero output voltage, and variable control of the output voltage is not performed.
- FIG. 4(b) shows an example of a mode in which the output power is exponentially variable within each output voltage range.
- the phase differences ⁇ da and ⁇ db between the control signals and the phase difference ⁇ s between the control signal sets are fixed, and the DC voltage Vdc is made variable.
- the output power is controlled by DC voltage control. At this time, the DC voltage Vdc is variable so that the output power is exponentially variable.
- the DC voltage Vdc and the phase differences ⁇ da and ⁇ db between the control signals are fixed, and the phase difference ⁇ s between the control signal sets is variable.
- Control power since the change in the phase difference ⁇ s between the control signal sets and the change in the output power do not necessarily have a linear relationship, the phase difference between the control signal sets is adjusted so that the output power becomes exponentially variable. Adjust for changes in ⁇ s. In the case of zero output voltage, the output voltage is set to zero output voltage by DC voltage control or phase difference control, and variable control of the output voltage is not performed.
- FIG. 5 shows output voltage waveforms during PWM control of push-pull amplifiers based on D-, F-, and EF-class switching modes.
- the output voltage waveform Vdd indicates the drain-to-drain voltage.
- the output voltage waveform Vdd is a square waveform with an amplitude equal to the drain-source voltage Vds.
- harmonic components other than the fundamental wave are removed by an output filter, and only the fundamental wave is output. Therefore, if the output voltage waveform Vdd is equivalently calculated as a sine wave voltage Vac of only the fundamental wave component, it is represented by the following equation (3).
- the duty ratio Duty is normalized by a half cycle of 180 [deg].
- Vac (4/.pi.).Vds.sin ⁇ (.pi./2).Duty ⁇ .sin( .omega.s.t ) (3)
- Vds voltage between drain and source
- Duty duty ratio
- ⁇ s angular frequency of fundamental wave
- FIG. 6 is a diagram of the output power P out in the case of PWM control with a variable duty ratio Duty in the high-frequency power supply, obtained based on the equation (3).
- the horizontal axis indicates the duty ratio Duty [%]
- the vertical axis indicates the power of Pout .
- high efficiency is achieved by providing a dead time DT to the gate signal voltage Vgs.
- Vac shown in Equation (3) has a duty ratio Duty term in the sine function, it becomes a function that draws an S-shaped curve.
- the duty ratio Duty is in the range of 20% to 80%, which exhibits a substantially linear linear characteristic. In the range of , the slope becomes gentle, and the nonlinear characteristics strongly appear. From such output characteristics of the sine wave voltage Vac, in the PWM control of the high-frequency power supply, the duty ratio vs. output power gain changes extremely low outside the range of 20% to 80%, and the duty ratio Duty makes the output It becomes difficult to adjust the power gain, and the controllability deteriorates.
- the rated duty in PWM control is selected in the vicinity of 80% in order to avoid a duty ratio duty range in which controllability is low.
- the duty ratio Duty near 80% corresponds to 140 [deg] to 160 [deg] when converted to the phase differences ⁇ da and ⁇ db between the control signals.
- the output power will be about 1/10 of the rated output. If the range of the duty ratio Duty is selected in this way from 20% to 80% and the region determined by the range of this duty ratio Duty is the PWM control region, the output power will be 10% of the rated output at the minimum duty ratio Duty_min. reduced.
- the output power range in the PWM control region is represented as P_high and P_low.
- phase shift control is applied instead of PWM control.
- the phase difference ⁇ s between control signal sets which is the phase difference between amplifiers, is varied within the range of 0 [deg] to 180 [deg].
- the output power when the phase difference ⁇ s between the control signal sets is 0 [deg] corresponds to the output power when the duty ratio Duty is the minimum duty ratio Duty_min in the PWM control.
- the output power when the phase difference ⁇ s between control signal sets is 180 [deg] corresponds to power 0.
- the maximum internal loss of phase shift control is when the phase difference ⁇ s between control signal sets is 180 [deg]. match.
- the phase difference ⁇ s between control signal sets of 180 [deg] corresponds to the output power with the minimum duty ratio Duty_min, so the internal loss is reduced to about 1/10. .
- the internal loss is equivalent to 10% of the rated power, the internal loss is improved by about 90% compared to output power control only by phase shift control.
- the outline of the high-frequency power output control according to the present invention is to selectively use DC voltage control and phase difference control according to the output power level, thereby reducing the internal loss due to the dummy resistance of the high-frequency power supply.
- FIG. 7(a) is a flowchart for explaining the outline of output control.
- S1 When there is a change in the output power (S1), it is determined whether the level of the output power is in a preset High level range (high output level range) or in a Low level range (low output level range). Determine (S2).
- S3 When the output power level is within the High level range, DC voltage control is performed (S3), and when the output power level is within the Low level range, phase difference control is performed (S4).
- FIG. 7(b) is a flow chart showing the detailed flow of the phase difference control, and the process of S4 in the flow chart shown in FIG. 7(a) is enclosed by a dashed line.
- S2 Low level range
- S4a preset minimum duty ratio Duty_min
- the phase difference command values ⁇ da * and ⁇ db * between the control signals are obtained by calculating the phase difference of the phase difference control, and the calculated phase difference between the control signals is calculated.
- control signals having inter-control signal phase differences ⁇ da and ⁇ db are generated (S4b1).
- the duty ratios DutyA and DutyB of the driving signals are determined based on the generated phase differences ⁇ da and ⁇ db between the control signals, and the switching elements of the amplifier are PWM-controlled by the determined duty ratios DutyA and DutyB (S4b2).
- the phase difference calculation of the phase difference control determines the inter-control signal set command value phase difference ⁇ s, which is the phase difference between the control signal sets. Ask for * .
- a control signal having an inter-control signal set phase difference ⁇ s is generated based on the determined inter-control signal set phase difference command value ⁇ s * (S4c1), and phase shift control is performed on the switching elements of the amplifier (S4c2).
- either one of the PWM control and the phase shift control is selected in the phase difference control. It is also possible to adopt a mode in which shift control is executed simultaneously.
- phase difference control inter-control signal phase difference command values ⁇ da * and ⁇ db * and inter-control signal set phase difference command values ⁇ s * are obtained by calculation, and respective command values ⁇ da * and ⁇ db * related to the obtained phase differences are calculated.
- ⁇ s * control signals having respective phase differences ⁇ da, ⁇ db, and ⁇ s are generated, and PWM control (S4b) and phase shift control (PS control) are performed (S4c).
- phase difference control when the PWM control (S4b) and the phase shift control (S4c) are performed simultaneously, the internal loss increases compared to when both controls are performed individually. For example, when the duty ratio Duty is 50% and the phase difference ⁇ s between control signal sets is 90 [deg], the internal loss is 25% of the rated output. However, this internal loss is superior to the conventional method because the loss is reduced to 1/4 compared to the output power control only by phase shift control.
- High-Frequency Power Supply A configuration example of the high-frequency power supply of the present invention will be described with reference to FIGS. 8 to 10.
- Configuration example 1 Configuration Example 1 will be described with reference to FIG.
- a high-frequency power supply 1 includes a pair of amplifiers 2A and 2B, and a combiner 5 that combines the amplifier outputs of the amplifiers 2A and 2B to generate a high-frequency pulse output.
- the amplifiers 2A and 2B are class D, class F, or class EF switching mode power amplifiers, and include an AD/DC converter as a component constituting a DC power supply that supplies a DC voltage Vdc to the power amplifiers.
- FIG. 8 shows, as an example, a configuration in which two LDMOS or one-package switching elements, an output transformer, and a low-pass filter are connected in series. A DC voltage Vdc is applied from the DC power supply of the AC/DC converter 6 to the middle point of the output transformer.
- Gate signals Gsig1a and Gsig2a and gate signals Gsig1b and Gsig2b which are drive signals from the drive circuits 3A and 3B, are input to the gate terminals of two switching elements provided in the amplifiers 2A and 2B, respectively. Signal driven.
- the amplifier outputs of amplifiers 2A and 2B are input to combiner 5 via circulators/isolators 4A and 4B.
- a combiner 5 combines the outputs of the amplifiers 2A and 2B and outputs a high frequency pulse output.
- Dummy resistors are connected to the circulators/isolators 4A and 4B. The output of the amplifier output that has not been combined by the combiner 5 is consumed in the dummy resistor and becomes an internal loss.
- the high-frequency power supply 1 includes a configuration for performing DC voltage control as a configuration for controlling the output power of the amplifiers 2A and 2B, and a configuration for performing phase difference control.
- the phase difference control is composed of the power controller 10 and the control signal generator 12 .
- the power control unit 10 calculates a command value for controlling the output power, and the control signal generation unit 12 generates a control signal for phase control difference control based on the phase difference control command value obtained by the calculation of the power control unit 10. to generate
- the power control unit 10 switches between DC voltage control and phase difference control according to the output level of the high frequency pulse output from the high frequency power supply 1, and when the output level is in the high output level range, the DC voltage command value is controlled by the DC voltage control.
- Vref * is calculated, and when the output level is in the low output level range, the phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) is calculated by phase difference control, and the DC voltage command value Vref * is sent to the DC voltage control unit 11, A phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) is sent to the control signal generator 12 .
- the DC voltage command value Vref * and the phase difference command value ⁇ * ( ⁇ d * , ⁇ s * ) are obtained by performing calculations based on the difference between the output power command value FWD_ref * and the output power feedback value FWD_FB.
- the power control unit 10 includes a DC voltage calculation unit 10a for calculating a DC voltage command value Vref * for controlling the output power by DC voltage control, and a phase difference command value ⁇ * for controlling the output power by phase difference control.
- a phase difference calculator 10b for calculating ( ⁇ d * , ⁇ s * ) is provided.
- the DC voltage calculation unit 10a calculates a DC voltage command value Vref * for matching the output power with the output power command value FWD_ref * based on the difference between the output power command value FWD_ref * and the output power feedback value FWD_FB.
- the DC voltage command value Vref * can be calculated by feedback control that makes the difference between the output power command value FWD_ref * and the output power feedback value FWD_FB zero. For example, when the difference (FWD_ref * )-(FWD_FB) is a positive value, the output power feedback value FWD_FB is smaller than the output power command value FWD_ref * . Bring the output power feedback value FWD_FB closer to the output power command value FWD_ref * . Conversely, when the difference (FWD_ref * ) ⁇ (FWD_FB) is a negative value, the output power feedback value FWD_FB is greater than the output power command value FWD_ref * , so the output power command value Vref * must be decreased. brings the output power feedback value FWD_FB closer to the output power command value FWD_ref * .
- the DC voltage command value Vref * is used in the DC voltage control unit 11 to calculate the manipulated variable ⁇ for controlling the DC voltage Vdc supplied to the pair of amplifiers 2A and 2B.
- phase difference calculator 10b calculates a phase difference command value ⁇ * for phase difference control of the output power based on the difference between the output power command value FWD_ref * and the output power feedback value FWD_FB.
- the phase difference command value ⁇ * includes inter-control-signal phase-difference command values ⁇ da * and ⁇ db * for PWM control and inter-control-signal-set phase-difference command value ⁇ s * for phase-difference control (PS control),
- the control signal generator 12 generates a control signal having a phase difference ⁇ ( ⁇ da, ⁇ db, ⁇ s) based on the phase difference command value ⁇ * ( ⁇ da * , ⁇ db * , ⁇ s * ).
- the high-frequency power supply 1 has a DC voltage control unit 11 that controls the output power, and a phase difference command that the power control unit 10 calculates the phase difference ⁇ ( ⁇ d, ⁇ s) between the control signals input to the pair of amplifiers 2A and 2B. and a control signal generator 12 for generating a differential signal based on the value ⁇ * ( ⁇ d * , ⁇ s * ) and controlling the output power.
- a DC voltage command value Vref * used for DC voltage control, inter-control-signal phase differences ⁇ da and ⁇ db used for phase-difference control, and inter-control-signal-set phase difference ⁇ s are obtained by calculation of the power control unit 10 .
- a DC voltage control unit 11 is provided as a configuration for performing DC voltage control.
- the DC voltage control unit 11 generates the manipulated variable ⁇ based on the DC voltage command value Vref * .
- An AC/DC converter 6 constituting a DC power supply is controlled based on the manipulated variable ⁇ , and supplies an output voltage of a DC voltage Vdc corresponding to the DC voltage command value Vref * to the amplifiers 2A and 2B.
- DC voltage control unit 11 compares feedback voltage Vdc_FB fed back from amplifiers 2A and 2B with DC voltage command value Vref * , and performs feedback control so that DC voltage Vdc matches DC voltage command value Vref * .
- a control signal generator 12 is provided as a configuration for performing phase difference control.
- the control signal generator 12 includes phase difference control function units 12Aa and 12Ab that perform PWM control, and a phase difference control function unit 12B that performs phase shift control.
- phase differences ⁇ da and ⁇ db between the control signals of the phase difference control function units 12Aa and 12Ab for PWM control and the phase difference ⁇ s between the control signal sets of the phase difference control function unit 12B for phase shift control are calculated by the arithmetic processing of the power control unit 10. It is generated based on the obtained phase command value.
- phase difference control function units 12Aa and 12Ab responsible for PWM control generate control signals Sig1a and Sig2a for controlling the amplifier 2A and control signals Sig1b and Sig2b for controlling the amplifier 2B, respectively.
- control signals Sig1a, Sig2a, Sig1b, and Sig2b are composed of differential signals whose phases are opposite to each other, two pairs of control signals including a pair of differential signals are input to each amplifier.
- control signals Sig1a and Sig2a input to the amplifier 2A form a set signal Siga consisting of two pairs of control signals including a pair of differential signals
- control signals Sig1b and Sig2b input to the amplifier 2B also Similarly, a set signal Sigb is composed of two pairs of control signals including a pair of differential signals. Therefore, the number of signals included in the set signal Siga and the set signal Sigb is four.
- the inter-control-signal phase difference ⁇ da between the control signal Sig1a and the control signal Sig2a is generated based on the inter-control-signal phase difference command value ⁇ da * .
- the pulse widths of the gate signals Gsig1a and Gsig2a output from the driving circuit 3A are PWM-controlled.
- the inter-control signal phase difference ⁇ db between the control signals Sig1b and Sig2b becomes the inter-control signal phase difference command value ⁇ db * .
- the pulse widths of the gate signals Gsig1b and Gsig2b output from the driving circuit 3B are PWM-controlled.
- the drive circuit 3A outputs an amplifier output corresponding to the inter-control signal phase difference ⁇ da
- the drive circuit 3B outputs an amplifier output corresponding to the inter-control signal phase difference ⁇ db.
- PWM control is performed with the inter-control-signal phase difference ⁇ da and the inter-control-signal phase difference ⁇ db as the same phase difference.
- the inter-control-signal phase difference command value ⁇ d * can be calculated by feedback control to zero the difference between the output power command value FWD_ref * and the output power feedback value FWD_FB. For example, when the difference (FWD_ref * ) ⁇ (FWD_FB) is a positive value, the output power feedback value FWD_FB is smaller than the output power command value FWD_ref * . By bringing the duty ratio Duty that widens the pulse width closer to the maximum duty ratio Duty_max, the output power feedback value FWD_FB is brought closer to the output power command value FWD_ref * .
- phase difference control function unit 12B responsible for phase shift control has a control signal between the set signal Siga of the control signals Sig1a and Sig2a for controlling the amplifiers 2A and 2B and the set signal Sigb of the control signals Sig1b and Sig2b.
- An inter-set phase difference ⁇ s is given.
- the phase difference ⁇ s between the control signal sets gives a phase difference ⁇ s between the signal set of the gate signals Gsig1a and Gsig2a output by the drive circuit 3A and the set signal of the gate signals Gsig1b and Gsig2b output by the drive circuit 3B. It is used for phase shift control for controlling the overlap of phases in which the amplifier output of the drive circuit 3A and the amplifier output of the drive circuit 3B are output simultaneously.
- the inter-amplifier output phase difference ⁇ s amp between the amplifier output of the drive circuit 3A and the amplifier output of the drive circuit 3B is the inter-control signal set phase difference ⁇ s of the control signal generated by the inter-control signal set phase difference command value ⁇ s * . is phase shift controlled based on.
- the inter-control-signal-set phase difference command value ⁇ s * can be calculated by feedback control that makes the difference between the output power command value FWD_ref * and the output power feedback value FWD_FB zero. For example, when the difference (FWD_ref * ) ⁇ (FWD_FB) is a positive value, the output power feedback value FWD_FB is smaller than the output power command value FWD_ref * . deg] brings the output power feedback value FWD_FB closer to the output power command value FWD_ref * .
- the inter-control signal set phase difference ⁇ s is set to 180 [deg]. brings the output power feedback value FWD_FB closer to the output power command value FWD_ref * .
- phase difference control function units 12Aa and 12Ab for PWM control and the phase difference control function unit 12B for phase shift control use the control signal phase difference command values ⁇ da * and ⁇ db * obtained by the arithmetic processing of the power control unit 10 and the control Control signals Sig1a and Sig2a and control signals Sig1b and Sig2b of differential signals based on the clock signal (CLK signal) are generated based on the inter-signal-set phase difference command value ⁇ s * .
- phase difference control function units 12Aa and 12Ab for PWM control and the phase difference control function unit 12B for phase shift control are each a signal oscillator that makes the frequency/phase of DDS (direct digital synthesis) variable, or an FPGA. (Filed Programmable Gate Way) integrated circuit or the like.
- the DC voltage command value Vref * is indicated by a circled numeral 1
- the control signal phase difference command value ⁇ d * ( ⁇ da * , ⁇ db * ) is indicated by a circled numeral 2
- the phase difference between the control signal sets A circled number 3 indicates the command value ⁇ s * .
- Configuration example 2 determines whether or not the inter-control-signal phase difference ⁇ d generated by the control-signal generating unit 12 matches the inter-control-signal phase difference command value ⁇ d * obtained by the calculation of the power control unit 10. If they do not match, the control signal phase difference ⁇ d generated by the control signal generator 12 is adjusted so as to match the control signal phase difference command value ⁇ d * .
- the adjustment of the inter-control signal phase difference ⁇ d In the adjustment of the inter-control signal phase difference ⁇ d, the adjustment of the inter-control signal phase difference ⁇ da between the control signals Sig1a and Sig2a and the adjustment of the inter-control signal phase difference ⁇ db between the control signals Sig1b and Sig2b are performed separately. conduct.
- circled symbols a1 and a2 feed back the control signals Sig1a and Sig2a output from the control signal generator 12 to the power controller 10, and A route for obtaining the phase difference ⁇ da is shown, and symbols b1 and b2 with circles feed back the control signals Sig1b and Sig2b output from the control signal generation unit 12 to the power control unit 10, and the control signals Sig1b and Sig2b are fed back to the power control unit 10. shows a path for obtaining the inter-control-signal phase difference ⁇ db.
- the phase difference calculation unit 10b compares the inter-control-signal phase difference command value ⁇ da * obtained by the calculation with the inter-control-signal phase difference ⁇ da obtained by feedback, and the inter-control-signal phase difference ⁇ da is the inter-control-signal phase difference command value.
- the command value to be commanded to the control signal generator 12 is adjusted so as to match the value ⁇ da * .
- the control signal phase difference command value ⁇ db * obtained by the calculation and the control signal phase difference ⁇ db obtained by feedback are compared, and the control signal phase difference ⁇ db becomes the control signal phase difference command value ⁇ db * .
- the command value to be commanded to the control signal generator 12 is adjusted so as to match.
- the control signal generator 12 adjusts the phase differences ⁇ da and ⁇ db between the control signals based on the adjusted command value.
- Configuration example 3 Configuration Example 3 will be described with reference to FIG. In configuration example 3, it is determined whether or not there is a difference between the amplifier outputs generated by the amplifiers 2A and 2B. adjust.
- circled symbols c and d denote paths for feeding back the amplifier outputs of the amplifiers 2A and 2B to the power control unit 10 to obtain the inter-control signal set phase difference ⁇ s.
- the phase difference calculation unit 10b compares the inter-control signal set phase difference command value ⁇ s * obtained by the calculation with the inter-control signal set phase difference ⁇ s obtained by feedback.
- the command value to be commanded to the control signal generator 12 is adjusted so as to match the phase difference command value ⁇ s * .
- the control signal generator 12 adjusts the inter-control signal set phase difference ⁇ s based on the adjusted command value.
- FIG. 11 shows a configuration example of a main part of the power control unit. Here, an example is shown in which the output power feedback value FWD_FB has two output levels of High output and Low output.
- the power controller 10a1 power-amplifies this difference to calculate the DC voltage command value Vref * .
- the DC voltage command value Vref * is converted into the manipulated variable ⁇ by the power controller 10a1, and controls the AC/DC converter of the DC power supply 6.
- a DC power supply 6 AC-DC-converts AC power from an AC power supply to DC and outputs a DC voltage Vdc.
- the Low output is sampled (held) by the Low_hold signal, and the difference between the sampled Low output and the Low side output power command value FWD_ref * (L) is calculated.
- the power controller 10b1 power-amplifies this difference, each phase difference data of the control signal phase difference command value ⁇ d * and the control signal set phase difference command value ⁇ s * are calculated.
- FIG. 12 shows an outline of the signal of each part of the high frequency power supply device of the present invention, and is an example of the outline signal when DC voltage control is performed in the high output level range.
- phase difference command value ⁇ d * between control signals and the phase difference command value ⁇ s * between control signal sets are fixed, and variable control of the output power is performed by DC voltage control using DC voltage Vdc.
- FIGS. 12(a) and (b) show control signals Sig1a and Sig2a on the amplifier (AMP_UNITA) side
- FIGS. 12(c) and (d) show control signals Sig1b and Sig2b on the amplifier (AMP_UNITB) side.
- Each signal shows an example of a differential signal whose phases indicated by symbols P and N are opposite to each other.
- the signal P is indicated by a solid line
- the signal N is indicated by a broken line.
- FIG. 12E shows the inter-control signal set phase difference command value ⁇ s * between the set signal of the control signal Sig1a and the control signal Sig2a and the set signal of the control signal Sig1b and the control signal Sig2b. This indicates that the command value ⁇ s * is in a fixed state.
- the inter-control-signal-set phase difference command value ⁇ s * can be a fixed value of 0 [deg], for example, but may be a phase difference other than 0 [deg].
- FIG. 12(f) shows that the control signal phase difference command value ⁇ da * between the control signals Sig1a and control signals Sig2a and the control signal phase difference ⁇ db * between the control signals Sig1b and Sig2b are fixed. showing. Since the control signal phase difference command values ⁇ da * and ⁇ db * are fixed, the duty ratio Duty of the gate signal for driving the amplifier is also fixed (FIG. 12(g)).
- the fixed values of the control signal phase difference command values ⁇ da * and ⁇ db * are recommended to be 140 [deg]-160 [deg] in consideration of high efficiency. is set as the rated duty.
- FIGS. 12(h) and (i) are gate signal voltages Vgs1a and Vgs2a on the amplifier (AMP_UNITA) side
- FIGS. 12(j) and (k) are gate signal voltages Vgs1b and Vgs2b on the amplifier (AMP_UNITB) side
- Each pulse width is determined by the duty ratios DutyA and DutyB in FIG. 12(g).
- DTA is dead time provided between gate signal voltage Vgs1a and gate signal voltage Vgs2a
- DTB is dead time provided between gate signal voltage Vgs1b and gate signal voltage Vgs2b.
- FIG. 12(l) is the DC voltage Vdc determined by the manipulated variable ⁇ by the DC voltage control.
- the phase difference between the gate signal voltage Vgs1a and the gate signal voltage Vgs1b is the phase difference ⁇ s amp between the amplifier outputs of the amplifiers 2A and 2B, and corresponds to the phase difference ⁇ s between the control signal sets.
- the control signal set phase difference command value ⁇ s * is fixed at a fixed value of 0 [deg]
- the amplifier output phase difference ⁇ s amp is 0 [deg].
- FIG. 13 shows an outline of the signal of each part of the high-frequency power supply device of the present invention, and is an example of an outline signal when performing phase difference control by PWM control in the low output level range.
- FIGS. 13(a) and (b) show control signals Sig1a and Sig2a on the amplifier (AMP_UNITA) side
- FIGS. 13(c) and (d) show control signals Sig1b and Sig2b on the amplifier (AMP_UNITB) side.
- Each signal shows an example of a differential signal whose phases indicated by symbols P and N are opposite to each other.
- the signal P is indicated by a solid line
- the signal N is indicated by a broken line.
- FIG. 13E shows the inter-control signal set phase difference command value ⁇ s * between the set signal of the control signal Sig1a and the control signal Sig2a and the set signal of the control signal Sig1b and the control signal Sig2b. This indicates that the command value ⁇ s * is in a fixed state.
- FIG. 13F shows that the inter-control-signal phase difference ⁇ da between the control signals Sig1a and Sig2a and the inter-control-signal phase difference command value ⁇ db * between the control signals Sig1b and Sig2b are variable. ing. By making the phase difference command values ⁇ da * and ⁇ db * between the control signals variable, the duty ratio Duty of the gate signal for driving the amplifier becomes variable (FIG. 13(g)).
- FIGS. 13(h) and (i) are gate signal voltages Vgs1a and Vgs2a on the amplifier (AMP_UNITA) side
- FIGS. 13(j) and (k) are gate signal voltages Vgs1b and Vgs2b on the amplifier (AMP_UNITB) side
- Each pulse width is variable by the duty ratios DutyA and DutyB in FIG. 13(g).
- DTA is the dead time provided between the gate signal voltage Vgs1a and the gate signal voltage Vgs2a
- DTB is the dead time provided between the gate signal voltage Vgs1b and the gate signal voltage Vgs2b
- the duty ratios DutyA and DutyB are made variable so as to reduce the output power below the rated duty set at the high output level.
- FIG. 13(l) is the DC voltage Vdc determined by the manipulated variable ⁇ by the DC voltage control, which is fixed because the DC voltage control is not performed.
- the phase difference between the gate signal voltage Vgs1a and the gate signal voltage Vgs1b is the phase difference ⁇ s amp between the amplifier outputs of the amplifiers 2A and 2B, and corresponds to the phase difference ⁇ s between the control signal sets.
- the control signal set phase difference command value ⁇ s * is fixed at a fixed value of 0 [deg]
- the amplifier output phase difference ⁇ s amp is 0 [deg].
- PWM control varies the phase difference ⁇ d between control signals within the range from the rated duty set at the time of high output level to the minimum duty ratio Duty_min. , to apply phase shift control.
- FIG. 14 shows an outline of the signal of each part of the high frequency power supply device of the present invention, and is an example of the outline signal when performing phase difference control by phase shift control in the low output level range. .
- Phase shift control is applied when the output power cannot be lowered even if the pulse width is reduced to the minimum duty ratio Duty_min by PWM control.
- the DC voltage command value Vdc * and the control signal phase difference command value ⁇ d * are fixed, and the output power is variably controlled by phase shift control in which the phase difference ⁇ s between the control signal sets is variable. conduct.
- FIGS. 14(a) and (b) show control signals Sig1a and Sig2a on the amplifier (AMP_UNITA) side
- FIGS. 14(c) and (d) show control signals Sig1b and Sig2b on the amplifier (AMP_UNITB) side.
- Each signal shows an example of a differential signal whose phases indicated by symbols P and N are opposite to each other.
- the signal P is indicated by a solid line
- the signal N is indicated by a broken line.
- FIG. 14E shows the inter-control signal set phase difference command value ⁇ s * between the set signal of the control signal Sig1a and the control signal Sig2a and the set signal of the control signal Sig1b and the control signal Sig2b. This indicates that the command value ⁇ s * is variable.
- control signal phase difference command value ⁇ da * between the control signals Sig1a and control signals Sig2a and the control signal phase difference command value ⁇ db * between the control signals Sig1b and Sig2b are in a fixed state. It is shown that.
- the duty ratio Duty of the gate signal for driving the amplifier becomes a fixed value (FIG. 14(g)).
- FIGS. 14(h) and (i) are gate signal voltages Vgs1a and Vgs2a on the amplifier (AMP_UNITA) side
- FIGS. 14(j) and (k) are gate signal voltages Vgs1b and Vgs2b on the amplifier (AMP_UNITB) side
- Each pulse width is in a fixed state at the fixed values of the duty ratios DutyA and DutyB in FIG. 14(g).
- DTA is dead time provided between gate signal voltage Vgs1a and gate signal voltage Vgs2a
- DTB is dead time provided between gate signal voltage Vgs1b and gate signal voltage Vgs2b.
- phase differences ⁇ da and ⁇ db between the control signals are fixed at the minimum duty ratio Duty_min that the driver board can supply the duty ratio DutyA of the gate signal voltages Vgs1a and Vgs2a and the duty ratio DutyB of the gate signal voltages Vgs1b and Vgs2b applied to the amplifier. value.
- FIG. 14(l) shows the DC voltage Vdc determined by the manipulated variable ⁇ by the DC voltage control, which is fixed because the DC voltage control is not performed.
- the phase difference between the gate signal voltage Vgs1a and the gate signal voltage Vgs1b is the phase difference ⁇ s amp between the amplifier outputs of the amplifiers 2A and 2B, and corresponds to the phase difference ⁇ s between the control signal sets.
- the phase difference ⁇ s amp between amplifier outputs is an angle corresponding to the variable value of the phase difference command value ⁇ s * between control signal sets.
- FIG. 15 shows a configuration in which the high-frequency power supply device shown in FIG. 1 is taken as one unit and a plurality of units are connected in parallel.
- the configuration example shown in FIG. 15 is a configuration in which a plurality of high-frequency power supply devices of unit A to unit N are connected in parallel.
- Each unit AN includes a drive circuit 3, an amplifier 2, and a circulator/isolator 4, similar to the configuration shown in FIG.
- the control signals Sig1a, Sig2a, Sig1b, and Sig2b generated by the control signal generator 12 are distributed by the signal distributor 7 and supplied to the units A to N.
- the control of unit A-unit N is performed in the same manner as the control mode described above.
- the phase difference ⁇ s amp between the amplifier outputs of the two amplifiers output from each unit of unit A to unit N is a phase difference corresponding to the phase difference command value ⁇ s * between the control signal sets.
- the synthesizer 5 further synthesizes the amplifier outputs obtained by synthesizing in each unit and obtaining through phase shift control, and outputs a final high-frequency pulse output.
- the high-frequency power supply and the high-frequency pulse output control method of the present invention are applied to industrial equipment using pulse output with an output of 1 kw or more and a frequency range of 27 MHz to 100 MHz, such as semiconductor manufacturing equipment and flat panel displays (liquid crystal panels). , organic panel) manufacturing equipment, solar panel manufacturing equipment, CO2 laser processing machine and other industrial applications.
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Abstract
Description
位相シフト制御では、2つ増幅器の出力を合成器で合成する際、2つの増幅器間の位相差φを可変とすることにより出力電力を調整している。このとき、電源内部の合成器に実装されたダミー抵抗により内部損失が発生する。
第1の位相差制御は、制御信号間の位相差である制御信号間位相差φdによりパルス幅を変調するPWM制御である。PWM制御によりスイッチング素子を駆動するパルス信号のデューティ比(Duty)を可変とする。この第1の位相差制御(PWM制御)では、高周波電源装置のダミー抵抗による内部損失が無いため、高効率化が図られる。
本発明の高周波電源装置の態様は、一対の増幅器と、一対の増幅器の増幅器出力を合成して高周波パルスの出力電力を生成する合成器とを備える。出力電力を制御する制御部は、一対の増幅器に供給する直流電圧Vdcを制御する直流電圧制御により出力電力を制御する第1制御部と、一対の増幅器の増幅器出力を制御する制御信号の位相差φ(φd、φs)により出力電力を位相差制御する第2制御部とを備える。出力電力の出力レベルに応じて、第1制御部による直流電圧制御と第2制御部による位相差制御とを切り替える。
(a)高出力レベル範囲に対して、直流電圧制御の直流電圧指令値Vref*を演算し、
(b)低出力レベル範囲に対して、位相差制御の位相差指令値φ*(φd*、φs*)を演算し、出力電力の出力レベルに応じて直流電圧制御と位相差制御とを切り替えて出力電力を制御する。
電力制御部は、出力電力指令値に基づいて出力電力の出力レベルを判定し、出力レベルの高低に応じて直流電圧制御あるいは位相差制御の何れの制御を適用するかを判定し、出力レベルが高出力レベル範囲にあるか、あるいは低出力レベル範囲にあるかにより直流電圧制御と位相差制御とを切り替える。
直流電圧制御部は、高出力レベル範囲において、電力制御部の直流電圧制御により得られた直流電圧指令値Vref*に基づいて増幅器に供給する直流電圧Vdcを可変とし、これにより増幅器の出力電力を制御する。
制御信号生成部は、低出力レベル範囲において、電力制御部の位相差制御により得られた位相差指令値φ*(φd*、φs*)に基づいて、2つの増幅器に入力する一対の制御信号の位相差φ(φd、φs)を制御する。制御信号の位相差φ(φd、φs)は、電力制御部の位相差制御により得られた位相差指令値φ*(φd*、φs*)に対応している。
(a)位相差制御の第1の制御態様
位相差制御の第1の制御態様は、PWM制御(デューティ制御)による制御態様である。低出力レベル範囲の内、高出力レベル側の出力電力に対しては、PWM制御により制御信号間位相差指令値φd*を用いてPWM制御により制御信号間位相差φdを有する制御信号を生成し、出力電力を制御する。
位相差制御の第2の制御態様は、位相シフト制御(PS制御)による制御態様である。
低出力レベル範囲の低出力レベル側の出力電力に対しては、制御信号セット間位相差指令値φs*を用いて位相シフト制御により制御信号セット間位相差φsを有する制御信号を生成して出力電力を制御する。
位相差制御の第3の制御態様は、第1の制御態様のPWM制御(デューティ制御)と第2の制御態様の位相シフト制御(PS制御)とからなる制御態様である。
本発明の高周波電力の出力制御方法の態様は、一対の増幅器を制御し、高周波パルス出力の出力電力を可変とする高周波電力の制御方法であり、出力レベルに応じて直流電圧制御と位相差制御とを切り替える。
(b)出力レベルが低出力レベル範囲では、一対の増幅器に入力する複数の制御信号の位相差φ(φd、φs)を制御する位相差制御により出力電力を制御する。
直流電圧制御は、高出力レベル範囲において直流電圧指令値Vref*を求め、求めた直流電圧指令値Vref*に基づいて増幅器に供給する直流電圧Vdcを可変とし、これにより増幅器の出力電力を制御する。
位相差制御は低出力レベル範囲に適用される。低出力レベル範囲を高出力レベル側と低出力レベル側とに区分し、高出力レベル側の出力電力については、制御信号間位相差φdを用いたPWM制御(デューティ制御)で制御し、低出力レベル側の出力電力については、制御信号セット間位相差φsを用いた位相シフト制御(PS制御)で制御する。
第1の制御態様において、位相差φは増幅器に入力する制御信号の制御信号間位相差φdであり、位相差制御は、パルス幅を制御信号間位相差φdにより制御し、増幅器のスイッチング素子のゲート信号のデューティ比(Duty)を制御するPWM制御により高周波パルス出力の出力電力を制御する。
第2の制御態様において、位相差φは増幅器に入力する制御信号の制御信号セット間位相差φsであり、位相差制御は、位相シフト制御(PS制御)による制御態様である。
位相差制御の第3の制御態様は、第1の制御態様のPWM制御(デューティ制御)と第2の制御態様の位相シフト制御(PS制御)とからなる制御態様である。
電力制御部による制御信号間の位相差制御は第1の形態-第3の形態の複数形態を備える。
第1形態において、電力制御部は、高周波パルス出力の出力電力フィードバック値FWD_FBと出力電力指令値FWD_ref*との比較に基づいて、各増幅器に入力する制御信号の一対の制御信号間の制御信号間位相差指令値φd*を求める位相差制御を行う。
第2形態において、電力制御部は、各増幅器の増幅器出力の比較に基づいて、各増幅器において、制御信号の一対の信号間の制御信号間位相差指令値φd*を調整し、2つの増幅器の増幅器出力を均衡化する位相差制御を行う。
第3形態において、電力制御部は、2つの増幅器の各増幅器において、一方の増幅器に入力する一対の制御信号の信号間の第1の制御信号間位相差φda、及び他方の増幅器に入力する一対の制御信号の信号間の第2の制御信号間位相差φdbを同一の位相差量とする制御信号間位相差指令値φda*及びφdb*を調整する位相差制御を行う。
電力制御部は、高周波パルス出力の出力電力フィードバック値FWD_FBと出力電力指令値FWD_ref*との比較に基づいて、2つの信号セット間の位相差指令値φs*を求める。位相差制御部は、制御信号セット間の位相差指令値φs*に基づいて、位相差φsを有する制御信号を生成する位相シフト制御を行う。
(1)PWM制御の制御態様
PWM制御は第1の制御態様-第3の制御態様の複数の制御態様を含む。
PWM制御の第1の制御態様において、高周波パルス出力の出力電力フィードバック値FWD_FBと出力電力指令値FWD_ref*との比較に基づいて、各増幅器に入力する制御信号の一対の信号間の制御信号間位相差指令値φd*を求める。
PWM制御の第2の制御態様において、各増幅器の増幅器出力の比較に基づいて、各増幅器において、制御信号の一対の信号間の制御信号間位相差指令値φd*を調整し、一対の増幅器の増幅器出力を均衡化する。
PWM制御の第3の制御態様において、一対の増幅器の各増幅器において、一方の増幅器に入力する一対の制御信号の信号間の第1の制御信号間位相差φda、及び他方の増幅器に入力する一対の制御信号の信号間の第2の制御信号間位相差φdbを同一の位相差量とする制御信号間位相差指令値φda*及びφdb*を調整する位相差制御を行う。
位相シフト制御において、高周波パルス出力の出力電力フィードバック値FWD_FBと出力電力指令値FWD_ref*との比較に基づいて、2つの制御信号のセット間の制御信号セット間位相差指令値φs*を求める。
本発明において、制御信号は位相が互いに逆相の位相関係にある差動信号の形態を用いることにより、増幅器のスイッチング素子の駆動において、耐ノイズ性が高まる。本発明では、制御信号として差動信号を用いることが望ましいが、シングルエンド信号を用いた動作を除くものではない。
1-1.制御概要
本発明の制御概要を図1、図2を用いて説明する。図1は本発明による制御を説明するための概要図であり、図2は本発明による直流電圧制御と位相差制御の使い分けを説明するための図であり、図2(a)は直流電圧制御(CNTL1)により電力出力を制御する場合を示し、図2(b)及び図2(c)は位相差制御(CNTL2)により電力出力を制御する場合を示している。また、図2(b)は位相差制御(CNTL2)をPWM制御により行う場合であり、図2(c)は位相差制御(CNTL2)を位相シフト制御により行う場合である。
直流電圧制御による出力電力の制御では、高出力レベル範囲において、増幅器に供給する直流電圧Vdcを可変とする。
本発明の位相差制御に用いる制御信号は、シングルエンド信号あるいは差動信号を用いることができるが、出力が1kw以上で周波数範囲が27MHz~100MHzの高周波のパルス出力に適用される高周波電源装置及び高周波電力の出力制御では、位相差やデューティ情報を正確に伝送するためには耐ノイズ性が高い差動信号が好適である。以後の説明では差動信号による制御信号について説明する。なお、差動信号は、位相が互いに逆相関係にある2つの信号であり、2つの信号の差分によりシングルエンド信号に変換することができる。
DutyA=φda/180[deg] …(1)
DutyB=φdb/180[deg] …(2)
で表される。
(i)高出力レベルに対して第1の位相差制御のPWM制御を適用する態様
(ii)低出力レベルに対して第2の位相差制御の位相シフト制御(PS制御)を適用する態様
とすることができる。
図2(b)は、位相差制御(CNTL2)による出力電力の制御において、第1の位相差制御のPWM制御のみによる電力出力の制御態様を示し、図中の横軸において一点鎖線を挟んで左方は制御信号における制御態様を示し、右方は増幅器における制御態様を示している。また図中の縦軸は出力電力を示し、下側の破線を境に上方は高出力レベル側を示し、下方は低出力レベル側を示している。
図2(c)は、位相差制御(CNTL2)による出力電力の制御において、第2の位相差制御の位相シフト制御のみによる電力出力の制御態様を示している。図中の横軸において一点鎖線を挟んで左方は制御信号における制御態様を示し、右方は増幅器における制御態様を示している。また図中の縦軸は出力電力を示し、下側の破線を境に上方は高出力レベル側を示し、下方は低出力レベル側を示している。
本発明は、高出力電圧範囲及び低出力電圧範囲の各出力電圧範囲において、出力電力の変化特性を任意に設定することができる。図3、4は変化特性例を示している。ここでは、高出力電圧High、低出力電圧Low1、Low2、零出力電圧の4つの出力電圧範囲の例を示している。
図3は各出力電圧範囲内において一定の出力電圧により出力電力を一定とする態様例である。高出力電圧範囲において、Highの一定出力電力を出力する場合には、制御信号間位相差φda、φdb、制御信号セット間位相差φsを固定し、直流電圧Vdcを可変とする直流電圧制御により出力電力を制御する。このとき直流電圧Vdcを一定電圧とすることにより出力電力を一定とする。
この一定出力電力の態様によれば、各出力電圧範囲間において出力電力は階段状の電力変化となる。
図4(a)は各出力電圧範囲内において出力電力を線形的に可変とする態様例である。
高出力電圧範囲において、Highのレベルで出力電力を線形的に可変とする場合には、制御信号間位相差φda、φdb、制御信号セット間位相差φsを固定し、直流電圧Vdcを可変とする直流電圧制御により出力電力を制御する。このとき出力電力が線形的に可変となるように、直流電圧Vdcは出力電力の線形変化に対してルート関数的(平方根関数的)に可変とする。
図4(b)は各出力電圧範囲内において出力電力を指数関数的に可変とする態様例である。高出力電圧範囲において、Highのレベルで出力電力を指数関数的に可変とする場合には、制御信号間位相差φda、φdb、制御信号セット間位相差φsを固定し、直流電圧Vdcを可変とする直流電圧制御により出力電力を制御する。このとき直流電圧Vdcは出力電力が指数関数的に可変となるように可変とする。
零出力電圧の場合には、直流電圧制御、あるいは位相差制御により出力電圧が零出力電圧となるように設定しておき、出力電圧の可変制御は行わない。
図5はD級、F級、EF級のスイッチングモード方式によるプッシュプル増幅器のPWM制御時における出力電圧波形を示している。出力電圧波形Vddは、ドレイン-ドレイン間電圧を示している。
Vac=(4/π)・Vds・sin{(π/2)・Duty}・sin(ωs・t) …(3)
Vac:正弦波電圧
Vds:ドレイン-ソース間電圧
Duty:デューティ比
ωs:基本波の角周波数
本発明の高周波電力の出力制御方法を図7のフローチャートを用いて説明する。以下のフローチャートではSの符号を用いて各工程の流れを表している。
図8~図10を用いて本発明の高周波電源装置の構成例を説明する。
3-1.構成例1
構成例1を図8に基づいて説明する。高周波電源装置1は、一対の増幅器2A、2Bと、増幅器2A、2Bの増幅器出力を合成して高周波パルス出力を生成する合成器5とを備える。
電力制御部10は出力電力を制御するための指令値を演算し、制御信号生成部12は電力制御部10の演算で求めた位相差制御指令値に基づいて位相制御差制御のための制御信号を生成する。
直流電圧演算部10aは、出力電力指令値FWD_ref*と出力電力フィードバック値FWD_FBとの差分に基づいて出力電力を出力電力指令値FWD_ref*に一致させるための直流電圧指令値Vref*を演算する。
位相差演算部10bは、出力電力指令値FWD_ref*と出力電力フィードバック値FWD_FBとの差分に基づいて出力電力を位相差制御するための位相差指令値φ*を演算する。位相差指令値φ*は、PWM制御のための制御信号間位相差指令値φda*、φdb*、及び位相差制御(PS制御)のための制御信号セット間位相差指令値φs*を含み、制御信号生成部12は位相差指令値φ*(φda*、φdb*、φs*)に基づいて位相差φ(φda、φdb、φs)を備えた制御信号を生成する。
高周波電源装置1は、出力電力を制御する直流電圧制御部11と、一対の増幅器2A、2Bに入力する制御信号の位相差φ(φd、φs)を、電力制御部10が演算する位相差指令値φ*(φd*、φs*)に基づいて差動信号を生成し、出力電力を制御する制御信号生成部12とを備える。
直流電圧制御を行う構成として直流電圧制御部11を備える。直流電圧制御部11は、直流電圧指令値Vref*に基づいて操作量αを生成する。直流電源を構成するAC/DCコンバータ6は操作量αに基づいて制御され、直流電圧指令値Vref*に応じた直流電圧Vdcの出力電圧を増幅器2A、2Bに供給する。
位相差制御を行う構成として制御信号生成部12を備える。制御信号生成部12は、PWM制御を担う位相差制御機能部12Aa、12Ab、及び位相シフト制御を担う位相差制御機能部12Bを備える。
PWM制御を担う位相差制御機能部12Aa、12Abは、それぞれ増幅器2Aを制御するための制御信号Sig1a、Sig2a、及び増幅器2Bを制御するための制御信号Sig1b、Sig2bを生成する。制御信号Sig1a、Sig2a、Sig1b、Sig2bを位相が互いに逆相関係にある差動信号により構成される場合には、各増幅器には一対の差動信号を含む二対の制御信号が入力される。これにより、増幅器2Aに入力される制御信号Sig1a、Sig2aは、一対の差動信号を含む二対の制御信号からなるセット信号Sigaを構成し、増幅器2Bに入力される制御信号Sig1b、Sig2bにおいても同様に、一対の差動信号を含む二対の制御信号からなるセット信号Sigbを構成する。したがって、セット信号Siga及びセット信号Sigbに含まれる信号数は4信号となる。
例えば、差分(FWD_ref*)-(FWD_FB)が正の値であるときには、出力電力フィードバック値FWD_FBが出力電力指令値FWD_ref*よりも小さいことから、制御信号間位相差指令値φd*を増加させ、パルス幅を広げるデューティ比Dutyを最大デューティ比Duty_maxに近づけることにより出力電力フィードバック値FWD_FBを出力電力指令値FWD_ref*に近づける。
位相シフト制御を担う位相差制御機能部12Bは、それぞれ増幅器2A、2Bを制御するための制御信号Sig1a、Sig2aのセット信号Sigaと制御信号Sig1b、Sig2bのセット信号Sigbとのセット信号間に制御信号セット間位相差φsを付与する。
例えば、差分(FWD_ref*)-(FWD_FB)が正の値であるときには、出力電力フィードバック値FWD_FBが出力電力指令値FWD_ref*よりも小さいことから、制御信号セット間位相差指令値φs*を0[deg]に近づけることにより出力電力フィードバック値FWD_FBを出力電力指令値FWD_ref*に近づける。
構成例2を図9に基づいて説明する。構成例2は、制御信号生成部12で生成した制御信号間位相差φdが、電力制御部10の演算で得られた制御信号間位相差指令値φd*と一致しているか否かを判定し、不一致の場合には制御信号生成部12で生成する制御信号間位相差φdが制御信号間位相差指令値φd*と一致するように調整する。
構成例3を図10に基づいて説明する。構成例3は、増幅器2A、2Bで生成した増幅器出力間に差異が発生しているか否かを判定し、不一致の場合には、制御信号生成部12で生成する制御信号セット間位相差φsを調整する。図10において、丸印付きの符号c、符号dは、増幅器2A、増幅器2Bの増幅器出力を電力制御部10にフィードバックして制御信号セット間位相差φsを求める経路を示している。
図11は電力制御部の要部の構成例を示している。ここでは、出力電力フィードバック値FWD_FBがHigh出力とLow出力の2段階の出力レベルである例を示している。
3-5a.高出力レベル(直流電圧制御)の信号例
図12は本発明の高周波電源装置の各部の信号の概略を示し、高出力レベル範囲において直流電圧制御を行う際の概略信号例である。
図13は本発明の高周波電源装置の各部の信号の概略を示し、低出力レベル範囲においてPWM制御による位相差制御を行う際の概略信号例である。
図14は本発明の高周波電源装置の各部の信号の概略を示し、低出力レベル範囲において位相シフト制御による位相差制御を行う際の概略信号例である。
ゲート信号電圧Vgs1aとゲート信号電圧Vgs1bとの位相差は増幅器2Aと増幅器2Bの増幅器出力間位相差φsampであり、制御信号セット間位相差φsに対応している。増幅器出力間位相差φsampは、制御信号セット間位相差指令値φs*が可変値に応じた角度なる。
図15の構成例は、図1で示した高周波電源装置を1ユニットとし、複数ユニットを並列接続する構成を示している。
2 増幅器
2、2A、2B 増幅器
3、3A、3B 駆動回路
4、4A、4B サーキュレータ/アイソレータ
5 合成器
6 直流電源
7 信号分配器
10 電力制御部
10a 直流電圧演算部
10a1、10b1 電力コントローラ
10b 位相差演算部
11 直流電圧制御部
12 制御信号生成部
12Aa、12Ab、12B 位相差制御機能部
A-N ユニット
DT_min 最小必要デットタイム
DT、DTA、DTB デットタイム
Duty_max 最大デューティ比
Duty_min 最小デューティ比
Duty、DutyA、DutyB デューティ比
FWD_ref* 出力電力指令値
FWD_FB 出力電力フィードバック値
FWD 出力電力
Gsig1a、Gsig2a ゲート信号
Gsig1b、Gsig2b ゲート信号
P,N 差動信号
Pout 出力電力
Sig1a、Sig2a 制御信号
Sig1b、Sig2b 制御信号
Siga、Sigb セット信号
Vac 正弦波電圧
Vdc 直流電圧
Vdc_FB フィードバック電圧
Vdc_max 最大値
Vdc_min 最小値
Vdc* 直流電圧指令値
Vdd 出力電圧波形
Vds ドレイン-ソース間電圧
Vgs ゲート信号電圧
Vgs1a、Vgs2a ゲート信号電圧
Vgs1b、Vgs2b ゲート信号電圧
Vref* 直流電圧指令値
α 操作量
φ 位相差
φ* 位相差指令値
φd 制御信号間位相差
φd* 制御信号間位相差指令値
φda 制御信号間位相差
φda* 制御信号間位相差指令値
φdb 制御信号間位相差
φdb* 制御信号間位相差指令値
φs 制御信号セット間位相差
φs* 制御信号セット間位相差指令値
φsamp 増幅器出力間位相差
Claims (20)
- 一対の増幅器と、
前記一対の増幅器の増幅器出力を合成して高周波パルスの出力電力を生成する合成器と、
を備え、
前記一対の増幅器に供給する直流電圧Vdcを制御する直流電圧制御により前記出力電力を制御する第1制御部と、
前記一対の増幅器の増幅器出力を制御する制御信号の位相差φにより前記出力電力を位相差制御する第2制御部と、
を備え、
前記出力電力の出力レベルに応じて、前記第1制御部による直流電圧制御と前記第2制御部による位相差制御とを切り替える、
高周波電源装置。 - 一対の増幅器と、
前記一対の増幅器の各増幅器出力を合成して高周波パルスの出力電力を生成する合成器と、
高周波パルス出力の出力電力の制御において、直流電圧制御に用いる直流電圧指令値Vref*、及び位相差制御に用いる位相差指令値φ*を演算する電力制御部と、
前記一対の増幅器に供給する直流電圧Vdcを前記直流電圧指令値Vref*に基づいて直流電圧制御する直流電圧制御部と、
前記一対の増幅器を前記位相差指令値φ*に基づいて位相差制御する制御信号を生成する制御信号生成部と、
を備え、
前記電力制御部は、前記出力電力の出力レベルにおいて、
(a)高出力レベル範囲に対して、前記直流電圧制御の直流電圧指令値Vref*を演算し、
(b)低出力レベル範囲に対して、前記位相差制御の位相差指令値φ*を演算し、
前記出力電力の出力レベルに応じて前記直流電圧制御と前記位相差制御とを切り替えて出力電力を制御する、
高周波電源装置。 - 前記各増幅器に入力する制御信号は、位相が互いに逆相の位相関係にある差動信号である、請求項2に記載の高周波電源装置。
- 前記位相差φは、前記一対の増幅器の各増幅器に入力する各二対の制御信号の信号間の制御信号間位相差φdであり、
前記電力制御部は、前記制御信号間の位相差指令値φd*を演算し、
前記制御信号生成部は、
制御信号位相差制御により、各増幅器に対して、前記位相差指令値φd*に基づいて制御信号間位相差φdの各二対の制御信号を生成し、
前記制御信号位相差制御された制御信号により、各増幅器のスイッチング素子のゲート信号のデューティ比を制御するPWM制御により高周波パルス出力の出力電力を制御する、
請求項3に記載の高周波電源装置。 - 前記位相差φは、前記一対の増幅器の各増幅器に入力する各二対の制御信号の信号間の制御信号間位相差φd、及び各増幅器に入力する二対の前記制御信号を信号セットとして、各増幅器に入力する信号セット間の制御信号セット間位相差φsを含み、
前記電力制御部は、前記制御信号間の位相差指令値φd*、及び制御信号セット間位相差指令値φs*を演算し、
前記制御信号生成部は、前記低出力レベル範囲において高出力レベル側と低出力レベル側とで制御を切り替え、
(a)前記高出力レベル側では、制御信号位相差制御により、各増幅器に対して、前記位相差指令値φd*に基づいて制御信号間位相差φdの各二対の制御信号を生成し、
前記制御信号位相差制御された制御信号により、各増幅器のスイッチング素子のゲート信号のデューティ比を制御するPWM制御により高周波パルス出力の出力電力を制御し、 (b)前記低出力レベル側では、位相シフト制御により、一対の増幅器間において、前記制御信号セット間位相差指令値φs*に基づいて制御信号セット間位相差φsの二対の制御信号の信号セットを生成し、位相シフト制御された二対の制御信号の信号セットにより、一対の増幅器間のゲート信号の位相差を制御し、前記ゲート信号の位相差により高周波パルス出力の出力電力を制御し、
(c)前記制御信号位相差制御及び位相シフト制御により生成された前記一対の増幅器の増幅器出力を合成して高周波パルス出力を生成する
請求項3に記載の高周波電源装置。 - 前記電力制御部は、
高周波パルス出力の出力電力フィードバック値FWD_FBと出力電力指令値FWD_ref*との比較に基づいて、各増幅器に入力する二対の制御信号の信号間の制御信号間位相差指令値φd*を求める、
請求項4又は5に記載の高周波電源装置。 - 前記電力制御部は、前記各増幅器の増幅器出力の比較に基づいて、各増幅器において、二対の制御信号の信号間の制御信号間位相差指令値φd*を調整し、一対の増幅器の増幅器出力を均衡化する、
請求項4又は5に記載の高周波電源装置。 - 前記電力制御部は、前記一対の増幅器の各増幅器において、一方の増幅器に入力する二対の制御信号の信号間の第1の制御信号間位相差φda、及び他方の増幅器に入力する二対の制御信号の信号間の第2の制御信号間位相差φdbを同一の位相差量とする制御信号間位相差指令値φda*及びφda*を調整する、
請求項4又は5に記載の高周波電源装置。 - 前記電力制御部は、高周波パルス出力の出力電力フィードバック値FWD_FBと出力電力指令値FWD_ref*との比較に基づいて、前記信号セット間の制御信号セット間位相差指令値φs*を求める、
請求項5に記載の高周波電源装置。 - 前記直流電圧制御部は、前記増幅器に供給される直流電圧のフィードバック電圧Vdc_FBと直流電圧指令値Vref*との差に基づいて得られる操作量αによりAD/DCコンバータの直流出力電圧を制御する、
請求項2に記載の高周波電源装置。 - 前記増幅器は、スイッチングモード方式による電力増幅器であり、前記制御信号により位相差を有して動作する2つのスイッチング素子の直列回路である、
請求項1から9の何れか一つに記載の高周波電源装置。 - 一対の増幅器を制御し、高周波パルス出力の出力電力を可変とする高周波電力の出力制御方法であり、
出力レベルに応じて直流電圧制御と位相差制御(CNTL2)とを切り替え、
(a)出力レベルが高出力レベル範囲では、前記一対の増幅器に供給する直流電圧Vdcを制御する直流電圧制御により出力電力を制御し、
(b)出力レベルが低出力レベル範囲では、前記一対の増幅器に入力する制御信号の位相差φを制御する位相差制御により出力電力を制御する、
高周波電力の出力制御方法。 - 前記各増幅器に入力する制御信号は、位相が互いに逆相の位相関係にある差動信号である、
請求項12に記載の高周波電力の出力制御方法。 - 前記位相差φは、前記一対の増幅器の各増幅器に入力する各二対の制御信号の信号間の制御信号間位相差φdであり、
前記位相差制御は、
パルス幅を前記制御信号間位相差φdとする制御信号を生成し、
前記制御信号により、各増幅器のスイッチング素子のゲート信号のデューティ比を制御するPWM制御により高周波パルス出力の出力電力を制御する、
請求項13に記載の高周波電力の出力制御方法。 - 前記位相差φは、前記各増幅器に入力する二対の前記制御信号の信号間の制御信号間位相差φd、及び各増幅器に入力する二対の前記制御信号を信号セットとして、一対の増幅器に入力する信号セット間の制御信号セット間位相差φsであり、
前記位相差制御は、前記低出力レベル範囲において高出力レベル側と低出力レベル側とで制御を切り替え、
(a)前記高出力レベル側では、パルス幅を前記制御信号間位相差φdとする制御信号を生成し、前記制御信号により、各増幅器のスイッチング素子のゲート信号のデューティ比を制御するPWM制御により高周波パルス出力の出力電力を制御し、
(b)前記低出力レベル側では、制御信号の信号セット間の制御信号セット間位相差φsを有する制御信号を生成し、前記制御信号により、前記一対の増幅器のゲート信号の位相差を位相シフト制御して高周波パルス出力の出力電力を制御し、
(c)前記一対の増幅器の増幅器出力を合成して高周波パルス出力を生成する、
請求項13に記載の高周波電力の出力制御方法。 - 前記位相差制御において、高周波パルス出力の出力電力フィードバック値FWD_FBと出力電力指令値FWD_ref*との比較に基づいて、各増幅器に入力する制御信号の二対の信号間の制御信号間位相差指令値φd*を求める、
請求項14又は15に記載の高周波電力の出力制御方法。 - 前記位相差制御において、前記各増幅器の増幅器出力の比較に基づいて、各増幅器において、制御信号の二対の信号間の制御信号間位相差指令値φd*を調整し、一対の増幅器の増幅器出力を均衡化する、
請求項14又は15に記載の高周波電力の出力制御方法。 - 前記位相差制御において、
前記一対の増幅器の各増幅器において、一方の増幅器に入力する二対の制御信号の信号間の第1の制御信号間位相差φda、及び他方の増幅器に入力する二対の制御信号の信号間の第2の制御信号間位相差φdbを同一の位相差量とする制御信号間位相差指令値φda*及びφda*を調整する、
請求項14に記載の高周波電力の出力制御方法。 - 前記位相シフト制御において、高周波パルス出力の出力電力フィードバック値FWD_FBと出力電力指令値FWD_ref*との比較に基づいて、前記信号セット間の制御信号セット間位相差指令値φs*を求める、
請求項15に記載の高周波電力の出力制御方法。 - 前記直流電圧制御は、前記増幅器に供給される直流電圧のフィードバック電圧Vdc_FBと直流電圧指令値Vref*との差に基づいて出力電圧を制御する、請求項12に記載の高周波電力の出力制御方法。
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JPH0637375A (ja) | 1992-07-15 | 1994-02-10 | Amada Co Ltd | レーザ発振器の高周波電源 |
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