WO2023087363A1 - 存储器件及其制造方法及包括存储器件的电子设备 - Google Patents

存储器件及其制造方法及包括存储器件的电子设备 Download PDF

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Publication number
WO2023087363A1
WO2023087363A1 PCT/CN2021/133337 CN2021133337W WO2023087363A1 WO 2023087363 A1 WO2023087363 A1 WO 2023087363A1 CN 2021133337 W CN2021133337 W CN 2021133337W WO 2023087363 A1 WO2023087363 A1 WO 2023087363A1
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layer
source
drain layer
drain
substrate
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PCT/CN2021/133337
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English (en)
French (fr)
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王琪
朱慧珑
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北京超弦存储器研究院
中国科学院微电子研究所
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Publication of WO2023087363A1 publication Critical patent/WO2023087363A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Definitions

  • the present disclosure relates to the field of semiconductors, and more particularly, to memory devices, methods of manufacturing the same, and electronic equipment including the memory devices.
  • an object of the present disclosure is at least in part to provide a memory device capable of securing on-current while suppressing leakage current, a method of manufacturing the same, and an electronic device including the memory device.
  • a memory device comprising: a substrate; a plurality of word lines extending on the substrate along a first direction; and a plurality of word lines extending on the substrate along a second direction perpendicular to the first direction bit lines; and a memory cell array on the substrate, including a plurality of memory cells electrically connected to corresponding word lines and corresponding bit lines, respectively.
  • Each memory cell may include: an active region extending along a third direction inclined relative to the first direction and including a vertical stack of a first source/drain layer, a channel layer, and a second source/drain layer; and
  • the gate stack is vertically interposed between the first source/drain layer and the second source/drain layer, and is arranged on opposite sides of the channel layer in a fourth direction perpendicular to the third direction to sandwich the channel layer.
  • a respective word line of each memory cell extends across the memory cell in a first direction to contact and electrically connect to the gate stacks on opposite sides of the memory cell.
  • a method of manufacturing a memory device comprising: providing a vertical stack extending along a third direction between the first direction and the second direction on a substrate, the vertical stack comprising successively The stacked first source/drain layer, channel layer and second source/drain layer, the first direction and the second direction are perpendicular to each other; the vertical stack is divided into a plurality of segments along the third direction; based on the multiple segments to define a plurality of memory cells; a plurality of word lines extending in a first direction are formed on the substrate, each word line extends across a corresponding one of the plurality of memory cells in the first direction, and electrically connected to the gate stack of the corresponding memory cell; and forming a plurality of bit lines extending along the second direction on the substrate, each bit line electrically connected to a corresponding memory cell of the plurality of memory cells.
  • an electronic device including the above storage device.
  • the memory cell is fabricated based on the vertical device, which can reduce the occupied area and suppress the leakage current compared with the horizontal device.
  • the conduction current can be increased.
  • FIG. 1(a) to 23 schematically illustrate some stages in the flow of manufacturing a memory device according to an embodiment of the present disclosure, in these figures:
  • Figures 1(a), 2(a), 3(a), 8(a), 12, 13(a), 14, 15(a), 16(a), 18, 19(a), 20(a) ), 21(a), 22(a), and 23 are plan views, wherein, the position of AA' line is shown in Fig. 2(a), the position of BB' line is shown in Fig. 13(a), and Fig. 15 (a) shows the position of CC' line, Fig. 19(a) shows the position of DD' line and EE' line, Fig. 20(a) shows the position of FF' line, Fig. 22( a) shows the position of the GG' line;
  • Fig. 1 (b) is a sectional view on the vertical direction
  • Figures 2(b), 3(b), 4 to 7, 8(b), 9 to 11, 13(b), 16(b), 17 are cross-sectional views along the line AA';
  • Fig. 13 (c) is a sectional view along BB' line
  • Figure 15(b) is a sectional view along line CC';
  • Fig. 19 (b) is a sectional view along DD' line
  • Fig. 19 (c) is a sectional view along EE' line
  • Fig. 20 (b), 21 (b) are the sectional views along FF ' line;
  • Fig. 22(b) is a cross-sectional view along line GG'.
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on” another layer/element in one orientation, the layer/element can be located “below” the other layer/element when the orientation is reversed.
  • a memory device is based on vertical metal oxide field effect transistors (MOSFETs).
  • MOSFETs vertical metal oxide field effect transistors
  • the vertical MOSFET can have a smaller occupied area and smaller leakage current, but the conduction current is relatively small.
  • the on-current of the vertical MOSFET can be optimized by its orientation, such as the angle with respect to the word line (or bit line), and thus the on-current can be ensured while suppressing the leakage current.
  • the conduction current of the vertical MOSFET may be in a vertical direction (eg, a direction substantially perpendicular to the surface of the substrate).
  • a vertical MOSFET may include a vertical stack of a first source/drain layer, a channel layer, and a second source/drain layer.
  • a gate stack may be disposed opposite the channel layer to define a channel region in the channel layer.
  • Source/drain regions may be respectively formed in the first source/drain layer and the second source/drain layer, and may be electrically communicated with each other through the channel region.
  • One of the source/drain regions may be electrically connected to a data storage structure, such as a capacitor, and thus form a memory cell (available in a Dynamic Random Access Memory (DRAM) configuration).
  • the other of the source/drain regions may be electrically connected to a bit line (BL), and the gate stack may be electrically connected to a word line (WL). Through word lines and bit lines, memory cells can be addressed.
  • the orientation of the vertical stack (especially the channel layer therein) can be optimized to increase the on-current.
  • the vertical stack can be tilted with respect to WL (or BL), eg, at an angle of about 30-80 degrees, to increase the channel width and thus the on-current.
  • the orientation of the vertical stack, especially the channel layer therein may be along a specific crystal plane where charge carriers may have increased mobility, eg, electrons on the (100) crystal plane.
  • WL may extend along a first direction
  • BL may extend along a second direction crossing (eg, perpendicular to) the first direction
  • the vertical stack (especially the channel layer therein) may extend along the first direction and the second direction.
  • a third direction extends between the two directions.
  • the gate stacks can be arranged on opposite sides of the channel layer (in a fourth direction orthogonal to the third direction), so that a double gate configuration can be obtained.
  • the WL may extend across the vertical stack in a first direction and may contact and thus be electrically connected to the gate stack on opposite sides.
  • the gate stack (the gate conductor layer in it) and the WL may be integrally formed to save process steps and thus reduce costs.
  • each pair of memory cells adjacent in the third direction may share the same BL contact plug to save area.
  • the respective first source/drain layers of the pair of memory cells extend toward each other to be integrated, and a common BL contact plug may land on the first source/drain layer region between them.
  • the channel layer may include a single crystal semiconductor material.
  • the first source/drain layer and the second source/drain layer may also include single crystal semiconductor material.
  • they can all be formed by epitaxial growth.
  • Such a semiconductor device can be manufactured, for example, as follows.
  • a vertical active region such as a vertical stack of a first source/drain layer, a channel layer, and a second source/drain layer, may be provided on the substrate.
  • the vertical stack may extend along a third direction between the first direction (eg, WL direction) and the second direction (eg, BL direction).
  • first direction eg, WL direction
  • second direction eg, BL direction
  • such vertical stacking can be formed by partition wall pattern transfer techniques.
  • the vertical stack may be divided into segments along a third direction, and storage cells may be defined based on the segments. Each memory cell may be electrically connected to a corresponding WL and a corresponding BL.
  • two storage units may be defined based on a single segment.
  • the second source/drain layer and the channel layer may be removed to expose the first source/drain layer in the middle region of each segment in the third direction.
  • Portions of the segment located on opposite sides of the central region in the third direction may each define a storage unit.
  • a corresponding bit line BL may be electrically connected to the two memory cells through a common contact plug disposed on the first source/drain layer in the middle region.
  • a single storage unit may be defined based on a single segment.
  • the WL may be integrated with the gate stack (especially the gate conductor layer therein).
  • the respective first source/drain layer and second source/drain layer of each memory cell may define therebetween recessed portions on opposite sides of the channel layer in a fourth direction perpendicular to the third direction.
  • a gate dielectric layer and a gate conductor layer can be sequentially formed, which can be filled into the recess to form a gate stack (thus self-aligning to the channel layer).
  • the gate conductor layer may be patterned as WL extending in the first direction. The patterning may not substantially affect the gate conductor layer filled in the recess.
  • the thickness and gate length of the channel layer are mainly determined by epitaxial growth, rather than by etching or photolithography, so it can have good channel size/thickness and Grid length control.
  • the disclosure can be presented in various forms, some examples of which are described below.
  • the selection of various materials is involved.
  • the selection of materials also considers etching selectivity.
  • the desired etch selectivity may or may not be indicated. It should be clear to those skilled in the art that when it is mentioned below that a certain material layer is etched, if it is not mentioned that other layers are also etched or it is not shown in the figure that other layers are also etched, then such etching It may be selective, and the layer of material may be etch-selective relative to other layers exposed to the same etch formulation.
  • FIG. 1 to 23 schematically illustrate some stages in the flow of manufacturing a memory device according to an embodiment of the present disclosure.
  • a substrate 1001 is provided.
  • the substrate 1001 may be various types of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrate is used as an example for description.
  • SOI semiconductor-on-insulator
  • a silicon wafer is provided as a substrate 1001 .
  • a well region may be formed. If a p-type device is to be formed, the well region can be an n-type well; if an n-type device is to be formed, the well region can be a p-type well.
  • a p-type well can be formed, for example, by implanting a p-type dopant such as boron (B) in the substrate 1001, and then performing thermal annealing.
  • the ion implantation energy may be about 30K-300K eV
  • the implantation dose may be about 1E12-1E14/cm 2
  • the implantation angle may be about 0-15 degrees.
  • n-type device is taken as an example for description. It is clear to those skilled in the art that the following description is also applicable to p-type devices, for example by appropriately adjusting the conductivity type of the doping.
  • a first source/drain layer 1003, a channel defining layer 1005, and a second source/drain layer 1007 may be formed by, for example, epitaxial growth.
  • the first source/drain layer 1003 can be used to define the position of the lower source/drain part, and its thickness is, for example, about 50nm-300nm.
  • the channel defining layer 1005 can be used to define the position of the channel, and the thickness is, for example, about 30nm-150nm.
  • the second source/drain layer 1005 can be used to define the position of the upper source/drain part, and its thickness is, for example, about 50nm-250nm.
  • Adjacent layers among the first source/drain layer 1003 , the channel defining layer 1005 and the second source/drain layer 1007 may have etch selectivity with respect to each other.
  • the first source/drain layer 1003 may include Si
  • the channel defining layer 1005 may include SiGe (eg, Ge atomic percentage is about 10%-40%)
  • the second source/drain layer 1007 may include Si.
  • the first source/drain layer 1003 and the second source/drain layer 1007 may be in-situ doped during growth to (at least partially) define the doping characteristics of the source/drain portion.
  • an n-type dopant such as phosphorus (P) may be doped at a concentration of about 1E19-1E21/cm 3 .
  • an active region may be defined from the first source/drain layer 1003 , the channel defining layer 1005 and the second source/drain layer 1007 .
  • a spacer pattern transfer technique is used in the following composition.
  • a mandrel may be formed.
  • a layer 1011 for a mandrel pattern may be formed on the second source/drain layer 1007 by, for example, deposition such as chemical vapor deposition (CVD).
  • the layer 1011 for the mandrel pattern may include amorphous silicon or polycrystalline silicon with a thickness of about 50nm-400nm.
  • the etch stop layer 1009 may be formed first by, for example, deposition such as CVD.
  • etch stop layer 1009 may include oxide (eg, silicon oxide) with a thickness of about 5nm-30nm.
  • a hard mask layer 1013 may be formed by, for example, deposition such as CVD.
  • the hard mask layer 1013 may include oxide and have a thickness of about 50nm-400nm.
  • the layer 1011 for the core pattern may be patterned into the core pattern.
  • a patterned photoresist (not shown) can be formed on the hard mask layer 1013 by photolithography (the layout critical dimension (CD) can be about 20nm-60nm). Shows).
  • the photoresist that can be patterned is used as an etching mask, and the hard mask layer 1013, the layer 1011 for the core pattern, and the etch stop layer 1009 are sequentially etched selectively by, for example, reactive ion etching (RIE).
  • RIE reactive ion etching
  • the RIE can be performed in the vertical direction, the RIE on the layer 1011 of the mandrel pattern can be stopped at the etch stop layer 1009 , and the RIE on the etch stop layer 1009 can be stopped at the second source/drain layer 1007 . Afterwards, the photoresist can be removed.
  • the transverse directions x, y and the vertical direction z are schematically shown in Fig. 2(a).
  • the x and y directions may be parallel to the top surface of the substrate 1001 , and may intersect each other, eg, be perpendicular; the z direction may be substantially perpendicular to the top surface of the substrate 1001 .
  • the y-direction may correspond to a longitudinally extending direction of a subsequently formed word line (WL) (which may be referred to as a "first direction”), and the x-direction may correspond to a longitudinally extending direction of a subsequently formed bit line (BL) (which may be referred to as a "first direction”).
  • WL subsequently formed word line
  • BL bit line
  • Second Direction Second Direction
  • the core pattern (for convenience, still marked with 1011 ) includes a series of line segments extending substantially in parallel. These line segments may be inclined (ie, at non-orthogonal angles) with respect to the y-direction.
  • the longitudinal extension direction of the line segment (which may be referred to as the "third direction") may form an angle of about 30°-80° with respect to the y-direction.
  • the longitudinal extension direction of the line segment can be along a specific crystal plane, such as the (100) crystal plane, so as to increase the mobility of carriers (electrons in the case of n-type devices).
  • partition walls 1015 may be formed on side walls of the mandrel pattern 1011 .
  • oxide can be deposited in a substantially conformal manner and then anisotropically etched, such as RIE, along the z-direction of the deposited oxide layer to remove its lateral extension and leave its vertical extension, thereby Get Partition 1015.
  • Partition walls 1015 can then be used to define the location of the device's active area.
  • the thickness of the partition wall 1015 (in the lateral direction) may be about 30nm-200nm.
  • the second source/drain layer 1007, the channel defining layer 1005, and the first source/drain layer 1003 can be patterned as parallel strips to the core pattern 1011 by using the hard mask layer 1013 and the partition walls 1015.
  • the hard mask layer 1013 and the partition wall 1015 can be used as an etching mask, and each layer is selectively etched sequentially by, for example, RIE in the z direction, so as to transfer the pattern to the underlying layer.
  • a certain space can be released between the first source/drain layer 1003 and the second source/drain layer 1007, so that the subsequently formed gate stack can be (at least partially) disposed in the space so as to be self-aligned to the channel formed by the channel.
  • the channel portion defined by the definition layer 1005 is defined.
  • the channel-defining layer 1005 can be selectively etched so that its sidewalls are perpendicular to the third direction (the direction perpendicular to the paper in FIG. 5) in the lateral direction.
  • the fourth direction horizontal direction in the paper plane in FIG. 5 ), it is relatively concave to form a concave portion.
  • selective etching can use CF 4 :O 2 :He mixed gas (dry etching) with a (volume) ratio such as 4:1:5, or a (volume) ratio such as 1:2:4.
  • HF 6% aqueous solution
  • the amount of lateral etching can be about 10nm-100nm.
  • the sidewalls of the channel-defining layer 1005 are still substantially vertical after etching.
  • the sidewall of the channel defining layer 1005 after etching may be in a curved shape, such as a C shape.
  • the active layer 1017 may be formed on the sidewall of the ridge structure by, for example, selective epitaxial growth. Due to selective epitaxial growth, no active layer 1017 may be formed on the surfaces of the hard mask layer 1013 and the partition wall 1015 . The portion of the active layer 1017 on the sidewalls of the channel defining layer 1005 then faces the gate stack and thus defines the channel portion.
  • the channel portion extends substantially in the vertical direction, so the active layer 1017 (in particular its part on the sidewalls of the channel defining layer 1005 ) may also be referred to as a (vertical) channel layer.
  • the thickness of the active layer 1017 (defining the channel portion) can be determined by an epitaxial growth process (for example, about 5 nm-50 nm), so the thickness of the channel portion can be better controlled.
  • the material of the active layer 1017 can be appropriately selected according to the performance requirements of the design for the device.
  • the active layer 1017 may include various semiconductor materials, such as elemental semiconductor materials such as Si, Ge, etc., or compound semiconductor materials such as SiGe, InP, GaAs, InGaAs, etc.
  • the active layer 1017 may include Si, which is the same as the first source/drain layer and the second source/drain layer.
  • the active layer 1017 can be in-situ (lightly) doped during growth, so as to form a certain doping distribution in the channel portion, so as to adjust the threshold voltage (Vt) of the device.
  • a gate stack may subsequently be formed.
  • a position maintaining layer 1019 may be formed in the recess.
  • nitride eg, silicon nitride
  • the deposited nitride is etched back by, for example, RIE in the z direction to form a position holding layer 1019 filled in the concave portion.
  • Portions of the active layer 1017 outside the recesses may also be removed (or, may be removed by additional RIE).
  • the first source/drain layer 1003 and the second source/drain layer 1007 may be doped, to achieve the desired source/drain doping characteristics.
  • This doping can be achieved by ion implantation or a solid-phase dopant source layer.
  • a solid-phase dopant source layer (not shown) may be formed on the structure shown in FIG. 7 in a substantially conformal manner by deposition.
  • the solid-phase dopant source layer may be, for example, an oxide containing a dopant.
  • the solid-phase dopant source layer may contain n-type dopants, such as PSG (phosphosilicate glass).
  • the solid-phase dopant source layer may contain p-type dopants, such as BSG (borosilicate glass).
  • the dopants in the solid-phase dopant source layer can be driven into the first source/drain layer 1003 and the second source/drain layer 1007 by annealing, such as laser rapid annealing at about 700° C.-1100° C. Form the desired source/drain doping characteristics.
  • the conditions (for example, time) of the annealing process can be controlled, so that the dopant is driven into the first source/drain layer 1003 and the second source/drain layer 1007 mainly in the lateral direction (suppressing the dopant in the vertical direction). diffused from the first source/drain layer 1003 and the second source/drain layer 1007 into the channel portion). Afterwards, the solid-phase dopant source layer may be removed.
  • partition wall 1015 can be used to complete the definition of the active area.
  • a dielectric layer 1021 may be formed on a substrate 1001 .
  • the oxide may be deposited to a thickness (eg, about 300nm-1000nm) sufficient to completely cover the ridge structures.
  • the deposited oxide is planarized, such as chemical mechanical polishing (CMP), to remove the hard mask layer 1013 and thus expose the core pattern 1011 .
  • CMP chemical mechanical polishing
  • the position holding layer 1019 can also be removed by selective etching.
  • the dielectric layer 1021 also enters into the concave portion.
  • the dielectric layer 1021 helps to expose the mandrel pattern 1011 by planarization, and (a part of it) can then also act as an isolation layer.
  • the core pattern 1011 can be removed by selective etching such as wet etching using a TMAH solution (stopping at the etch stop layer 1009). This leaves a partition wall 1015 in the form of a closed ring on the ridge structure.
  • the partition wall 1015 can be used as an etching mask, and the etch stop layer 1009, the second source/drain layer 1007, the channel defining layer 1005, and the second etch stop layer 1009, the second source/drain layer 1007, the channel defining layer 1005, and the A source/drain layer 1003.
  • the partition walls 1015 and the etch stop layer 1009 are both oxides, since the etch stop layer 1009 is thin, it is possible to remove the etch stop layer 1009 while leaving the partition walls 1015 .
  • the first source/drain layer 1003, the channel defining layer 1005, the second source/drain layer 1007 and the active layer 1017 form a closed ring corresponding to the partition wall 1015 to define source area.
  • the depth of the overcut is, for example, about 10 nm-100 nm (the overcut may be approximately the same on the inner and outer sides of the partition wall 1015 ).
  • the active layer 1017 is covered on the inside by the channel-defining layer 1005 .
  • the channel defining layer 1005 In this example SiGe), leaving space for the gate stack inside the active layer 1017 as shown in FIG. 11 .
  • the active region extends continuously in a closed ring. Isolation may be performed to divide a continuously extending active region into corresponding active regions of different devices.
  • a photoresist 1023 can be formed on the substrate 1001 and patterned by photolithography (the minimum CD of the layout can be about 20nm-100nm) to expose the region to be isolated.
  • the device is formed with long sides of each annular shape substantially parallel to each other so as to form a regular array of memory cells.
  • the photoresist 1023 can expose the end of each ring in the longitudinal direction (the end where the short side is located, not used to form a device), and on the other hand, can expose a local area on the long side to divide the long side for several paragraphs.
  • These segments may have substantially the same longitudinal extension length (i.e., the distance between two adjacent openings of the photoresist 1023 on the same long side), so that devices subsequently formed based thereon may have substantially the same size ( Except near the end, due to the inclined layout, there may be some segments of non-uniform length near the end, which may be dummy and not used to form the device).
  • the following openings are formed in the photoresist 1023: a larger rectangle at the ends, and a smaller rectangle between the ends.
  • the smaller rectangles can be arranged in columns in the y direction that are spaced apart in the x direction.
  • each segment includes a vertical stack of first source/drain layer 1003, active layer 1017 and second source/drain layer 1007 (with a partition wall 1015 on top).
  • the first source/drain layer 1003 may be partially exposed to facilitate subsequent formation of electrical contacts from the BL to the exposed portion.
  • two devices may be formed, and the two devices may share the same BL contact plug.
  • the first source/drain layer 1003 may be exposed approximately in the middle of each segment.
  • a photoresist 1025 can be formed on the substrate 1001, and it is patterned to expose the first source/drain layer 1003 that needs to be exposed by photolithography (the minimum CD of the layout can be, for example, about 20nm-100nm). Area.
  • the photoresist 1025 may expose approximately the middle of each segment in the longitudinal direction (so that each segment may be divided into two sub-segments).
  • the openings in the photoresist 1025 may be located between the openings in the previously formed photoresist 1023 that are adjacent in the lengthwise direction, so that the subsections may have substantially the same longitudinal extension.
  • rectangular openings may be formed in the photoresist 1025 . Considering the formation of the following BL, the rectangular openings can be arranged in rows in the x-direction, which are spaced apart in the y-direction.
  • the partition wall 1015 (and partially the dielectric layer 1021), the second source/drain layer 1007 and the active layer 1017.
  • the upper portion of the first source/drain layer 1003 may also be removed.
  • the first source/drain layer 1003 may be etched away by about 10%-50% of its thickness. In this way, as shown in Figure 15(b), in the area exposed by the opening in the photoresist 1025, there is no active layer on the top of the first source/drain layer 1003, which facilitates the subsequent formation of Electrical contacts to the source/drain layer 1003 .
  • each sub-segment in each segment can be used to form a single switching device, and a storage unit can be formed based on each switching device (for example, a switching device+data storage structure).
  • each sub-segment of the segments can be used as an active area of a switching device.
  • the present disclosure is not limited thereto.
  • each segment can be used as the active area of a switching device.
  • a part of the first source/drain layer can be exposed at one end of each segment in the longitudinal extension direction by a method similar to that described in conjunction with FIGS.
  • a BL contact plug is formed on the exposed portion of the first source/drain layer.
  • An isolation layer for electrical isolation may be formed on the substrate.
  • an oxide may be formed on the substrate to a thickness (eg, about 300nm-1000nm) sufficient to cover the active region by deposition such as CVD.
  • planarization such as CMP, is performed on the deposited oxide.
  • the planarized oxide and the previously formed partition wall 1015 and dielectric layer 1021 which are both oxides
  • a certain thickness of oxide is left as the isolation layer 1029 .
  • the top surface of the isolation layer 1029 may be about 10nm-150nm below the bottom of the channel portion (or, the top surface of the first source/drain layer 1003).
  • the isolation layer 1029 is not shown for clarity.
  • a plurality of device active regions (corresponding to the above-mentioned "subsections") extending linearly are formed on the substrate, which are inclined with respect to the y direction.
  • the respective first source/drain layers of each pair of device active regions adjacent in the longitudinal extension direction may be connected to each other (thereby corresponding to the above-mentioned "segment"), and exposed in the middle (the darker color in Fig. 16(a) , defined by the aforementioned photoresist 1025).
  • the isolation between pairs of device active regions in the direction of longitudinal extension may be defined by the above-mentioned photoresist 1023 .
  • Gate stacks may be formed on the isolation layer 1029 . According to an embodiment of the present disclosure, a gate stack may be formed together with the WL to save process steps and thus reduce costs.
  • a gate dielectric layer 1031 can be formed on the isolation layer 1029 in a substantially conformal manner by deposition, and a gate conductor layer 1033 can be formed on the gate dielectric layer 1031 .
  • the gate dielectric layer 1031 may include a high-k gate dielectric such as HfO 2 , with a thickness of, for example, about 1 nm-10 nm.
  • an interfacial layer may also be formed, for example, an oxide formed by an oxidation process or deposition such as atomic layer deposition (ALD).
  • the gate conductor layer 1033 may include a work function adjusting metal such as TiN with a thickness of about 1 nm-10 nm and a gate conductive metal such as W with a thickness of about 100 nm-800 nm.
  • the gate conductor layer 1033 may be planarized, such as CMP, and may fill spaces between active regions of each device.
  • the gate stack thus formed (gate dielectric layer 1031 + gate conductor layer 1033 ) can be embedded between the first source/drain layer 1003 and the second source/drain layer 1007 and surround the channel layer 1017 .
  • interconnect structures such as WL, BL, and data storage structures (eg, capacitors) may be formed.
  • the WL may be formed based on the gate stack, especially the gate conductor layer 1033 therein.
  • a photoresist 1035 can be formed on the gate conductor layer 1033, and patterned into a pattern corresponding to WL (in this example, a series of lines in the y direction). These lines may extend in the y-direction to pass through the above-mentioned gaps between the segments (corresponding to the openings in the photoresist 1023), and may be spaced apart in the x-direction so that each device active area (corresponding to each a sub-segment above) intersects a single line (corresponding to a single WL).
  • the gate conductor layer 1033 can be selectively etched by using the photoresist 1035 as an etching mask, for example, by RIE in the z direction, To pattern it into WL corresponding to the pattern of photoresist 1035.
  • the etching can stop at the gate dielectric layer 1031 .
  • the gate conductor layer 1033 can be left in the gap between the first source/drain layer 1003 and the second source/drain layer 1007, and thus can be self-aligned on the channel layer 1017.
  • the inner and outer sides of the grid thus forming a double gate configuration.
  • the top surface of the gate conductor layer 1033 is higher than the top surface of the active region of the device (that is, the top surface of the second source/drain layer 1007), so that The gate stacks on the inner and outer sides of the channel layer 1017 are electrically connected to each other.
  • a single device corresponding to a sub-segment
  • the gate conductor layer of the device is integral with the corresponding WL.
  • the gate dielectric layer 1031 is not shown in black as in the cross-sectional view of FIG. 19( b ).
  • the WL is formed as a gate conductor layer here, the present disclosure is not limited thereto.
  • the gate conductor layer 1033 may be selectively etched, such as RIE in the z direction, without additionally forming an etching mask. In this way, the gate conductor layer 1033 may be left only in the gap between the first source/drain layer 1003 and the second source/drain layer 1007 .
  • a conductive layer may be additionally formed and patterned using a photoresist 1035 to form a WL.
  • the WL may extend across the respective sub-section and may contact and thus be electrically connected to the gate stacks on opposite sides of the sub-section.
  • the memory cell may include a first source/drain layer 1003, a channel layer 1017 and a second source/drain layer stacked in sequence in the vertical direction Layer 1007.
  • the channel layer 1017 may be in the shape of nanosheets or nanowires.
  • the gate stack is vertically interposed between the first source/drain layer 1003 and the second source/drain layer 1007, and sandwiches the channel layer 1017 from opposite sides of the channel layer 1017 (in the fourth direction). .
  • the active region (the stack of the first source/drain layer 1003, the channel layer 1017 and the second source/drain layer 1007), especially the channel layer 1017 therein, can ) extends in the oblique third direction, so that the channel width and thus the on-current can be increased.
  • an interlayer dielectric layer 1035 may be formed on the isolation layer 1029 .
  • an oxide of about 50nm-100nm may be deposited such as by CVD, and a planarization treatment such as CMP may be performed on the deposited oxide to form the interlayer dielectric layer 1035 .
  • a nitride liner layer (not shown), eg, about 10 nm-30 nm, may be formed first.
  • a BL contact hole 1037 can be formed by photolithography.
  • the BL contact hole 1037 is set between the active regions of each device (corresponding to the position between the two sub-segments in the above-mentioned same segment, defined by the opening in the photoresist 1025), to expose The first source/drain layer 1003 .
  • the top surface of the first source/drain layer 1003 at a position between two sub-segments in each segment is shown flush with the top surface of the isolation layer 1029 . But this is only schematically shown for the convenience of illustration. Depending on the amount of etching, the top surface of the first source/drain layer 1003 may protrude or be recessed relative to the top surface of the isolation layer 1029 .
  • a conductive material may be filled in the BL contact hole to form a BL contact plug.
  • BL 1039 may be formed on interlayer dielectric layer 1035 by depositing and then etching a conductive material.
  • the BLs 1039 can extend in the x-direction and can be spaced apart in the y-direction so that each BL contact plug is electrically connected to a single BL. It can be seen that two devices adjacent in the direction of longitudinal extension (corresponding to two sub-segments of the same segment) may share the same BL contact plug and thus be electrically connected to the same BL. This can reduce the number of BL contact plugs.
  • each BL contact plug small square on the BL is shown for clarity, which is actually hidden from view by the BL.
  • capacitor contact holes 1041 can be formed by photolithography. Capacitive contact holes 1041 can be provided above the active regions of each device (corresponding to the above-mentioned sub-sections, that is, the above-mentioned regions where the long sides are between the openings in the photoresist 1023 and the openings in the photoresist 1025) , to expose the second source/drain layer 1007.
  • a conductive material may be filled in the capacitive contact hole 1041 to form a capacitive contact plug 1043 .
  • the capacitive contact plug 1043 may electrically connect a capacitor (not shown) subsequently formed on the interlayer dielectric layer 1035 to the second source/drain layer 1007 of each device.
  • a WL contact hole can be formed by photolithography, and a conductive material can be filled therein to form a WL contact plug 1045 .
  • Each WL contact plug 1045 is positioned over the WL to make contact with the WL and thus be electrically connected to the WL.
  • the above etching performed in the interlayer dielectric layer 1035 for forming the BL contact hole, the capacitor contact hole, and the WL contact hole is performed separately because their respective etching depths are different. Their processing order may differ from that described above.
  • a memory device may be applied to various electronic devices.
  • an electronic device may include a memory device and a processor.
  • Storage devices can store data required for the operation of electronic equipment or obtained during operation.
  • the processor can operate based on data and/or applications stored in the memory device.
  • Such electronic devices include smart phones, computers, tablet computers (PCs), wearable smart devices, artificial intelligence devices, mobile power supplies, and the like.

Abstract

一种存储器件及其制造方法及包括存储器件的电子设备。存储器件可以包括：衬底；衬底上沿第一方向延伸的多条字线；衬底上沿与第一方向垂直的第二方向延伸的多条位线；以及衬底上的存储单元阵列，包括分别电连接到相应字线和相应位线的多个存储单元。每个存储单元可以包括：有源区，沿着相对于第一方向倾斜的第三方向延伸，且包括第一源/漏层、沟道层和第二源/漏层的竖直堆叠；以及栅堆叠，在竖直方向上介于第一源/漏层与第二源/漏层之间，且设于沟道层在与第三方向正交的第四方向上的相对两侧以夹着沟道层。每个存储单元的相应字线在第一方向上跨过该存储单元延伸，以接触并电连接到该存储单元的相对两侧上的栅堆叠。

Description

存储器件及其制造方法及包括存储器件的电子设备
相关申请的引用
本申请要求于2021年11月19日递交的题为“存储器件及其制造方法及包括存储器件的电子设备”的中国专利申请202111381851.1的优先权，其内容一并于此用作参考。
技术领域
本公开涉及半导体领域，更具体地，涉及存储器件及其制造方法及包括存储器件的电子设备。
背景技术
为满足对更大存储容量的需求，存储器件的集成度越来越高，且存储单元尺寸进一步缩减。这种尺寸缩减伴随着漏电流的增大，特别是对于水平器件。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种能够在抑制漏电流的同时保证导通电流的存储器件及其制造方法及包括存储器件的电子设备。
根据本公开的一个方面，提供了一种存储器件，包括：衬底；衬底上沿第一方向延伸的多条字线；衬底上沿与第一方向垂直的第二方向延伸的多条位线；以及衬底上的存储单元阵列，包括分别电连接到相应字线和相应位线的多个存储单元。每个存储单元可以包括：有源区，沿着相对于第一方向倾斜的第三方向延伸，且包括第一源/漏层、沟道层和第二源/漏层的竖直堆叠；以及栅堆叠，在竖直方向上介于第一源/漏层与第二源/漏层之间，且设于沟道层在与第三方向正交的第四方向上的相对两侧以夹着沟道层。每个存储单元的相应字线在第一方向上跨过该存储单元延伸，以接触并电连接到该存储单元的相对两侧上的栅堆叠。
根据本公开的另一方面，提供了一种制造存储器件的方法，包括：在衬底上设置沿第一方向和第二方向之间的第三方向延伸的竖直堆叠，竖直堆叠包括 依次叠置的第一源/漏层、沟道层和第二源/漏层，第一方向和第二方向彼此垂直；将竖直堆叠沿着第三方向分为多个段；基于所述多个段来限定多个存储单元；在衬底上形成沿第一方向延伸的多条字线，每条字线在第一方向上跨过所述多个存储单元中的相应存储单元延伸，并电连接到相应存储单元的栅堆叠；在衬底上形成沿第二方向延伸的多条位线，每条位线电连接到所述多个存储单元中的相应存储单元。
根据本公开的另一方面，提供了一种电子设备，包括上述存储器件。
根据本公开的实施例，基于竖直器件来制作存储单元，相比于水平器件可以减小占用面积以及抑制漏电流。另外，通过优化器件有源区特别是沟道层的取向，可以增大导通电流。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1(a)至23示意性示出了根据本公开实施例的制造存储器件的流程中的一些阶段，在这些附图中：
图1(a)、2(a)、3(a)、8(a)、12、13(a)、14、15(a)、16(a)、18、19(a)、20(a)、21(a)、22(a)、23是俯视图，其中，图2(a)中示出了AA′线的位置，图13(a)中示出了BB′线的位置，图15(a)中示出了CC′线的位置，图19(a)中示出了DD′线、EE′线的位置，图20(a)中示出了FF′线的位置，图22(a)中示出了GG′线的位置；
图1(b)是竖直方向上的截面图；
图2(b)、3(b)、4至7、8(b)、9至11、13(b)、16(b)、17是沿AA′线的截面图；
图13(c)是沿BB′线的截面图；
图15(b)是沿CC′线的截面图；
图19(b)是沿DD′线的截面图；
图19(c)是沿EE′线的截面图；
图20(b)、21(b)是沿FF′线的截面图；
图22(b)是沿GG′线的截面图。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。附图并非一定是按比例绘制的，特别是为清楚起见，截面图的绘制比例不同于俯视图的绘制比例。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
根据本公开的实施例，提供了一种存储器件。该存储器件基于竖直型金属氧化物场效应晶体管(MOSFET)。相比于水平型MOSFET，竖直型MOSFET可以具有较小的占用面积和较小的漏电流，但是导通电流相对较小。根据本发明构思，可以通过竖直型MOSFET的取向，例如相对于字线(或者位线)的角度，来优化其导通电流，并因此可以在抑制漏电流的同时保证导通电流。
竖直型MOSFET的导通电流可以在竖直方向(例如，大致垂直于衬底表面的方向)上。例如，竖直型MOSFET可以包括第一源/漏层、沟道层和第二源/漏层的竖直堆叠。栅堆叠可以设置为与沟道层相对，以在沟道层中限定沟道区。源/漏区可以分别形成于第一源/漏层和第二源/漏层中，并可以通过沟道区而彼此电气连通。源/漏区之一可以电连接到数据存储结构如电容器，并因 此形成存储单元(可以得到动态随机存取存储器(DRAM)配置)。源/漏区中另一个可以电连接到位线(BL)，栅堆叠可以电连接到字线(WL)。通过字线和位线，可以寻址存储单元。
如上所述，可以优化竖直堆叠(特别是其中的沟道层)的取向，以增大导通电流。例如，竖直堆叠可以相对于WL(或BL)倾斜，例如成约30度至80度的角度，以增大沟道宽度，并因此增大导通电流。另外，竖直堆叠特别是其中的沟道层的取向可以沿着特定晶面，载流子在该特定晶面上可以具有增大的迁移率，例如，(100)晶面上的电子。
根据实施例，WL可以沿第一方向延伸，BL可以沿与第一方向交叉(例如，垂直)的第二方向延伸，竖直堆叠(特别是其中的沟道层)可以沿第一方向与第二方向之间的第三方向延伸。
栅堆叠可以设置在沟道层(在与第三方向正交的第四方向上)的相对两侧，从而可以得到双栅配置。WL可以在第一方向上跨过竖直堆叠延伸，并可以接触并与因此电连接到相对两侧上的栅堆叠。根据实施例，栅堆叠(中的栅导体层)与WL可以一体形成，以节省工艺步骤并因此降低成本。
根据实施例，在第三方向上相邻的每对存储单元可以共享相同的BL接触插塞，以节省面积。例如，该对存储单元各自的第一源/漏层向着彼此延伸从而成一体，公共的BL接触插塞可以着落于它们之间的第一源/漏层区域上。
沟道层可以包括单晶半导体材料。当然，第一源/漏层和第二源/漏层也可以包括单晶半导体材料。例如，它们都可以通过外延生长来形成。
这种半导体器件例如可以如下制造。
可以在衬底上设置竖直有源区，例如第一源/漏层、沟道层和第二源/漏层的竖直堆叠。如上所述，竖直堆叠可以沿着第一方向(例如，WL方向)与第二方向(例如，BL方向)之间的第三方向延伸。可以存在彼此平行的多个这样的竖直堆叠。如下所述，这种竖直堆叠可以通过隔墙图形转移技术来形成。可以将竖直堆叠沿着第三方向分为多个段，可以基于这些段来限定存储单元。每个存储单元可以电连接到相应的WL和相应的BL。
根据本公开的实施例，可以基于单个段来限定两个存储单元。例如，可以在每个段在第三方向上的中部区域，去除第二源/漏层和沟道层，并露出第一 源/漏层。该段在第三方向上位于中部区域相对两侧的部分可以各自限定一个存储单元。相应的位线BL可以通过设置在中部区域中第一源/漏层上的公共接触插塞电连接到这两个存储单元。当然，本公开不限于此。例如，可以基于单个段来限定单个存储单元。
根据本公开的实施例，WL可以与栅堆叠(特别是其中的栅导体层)一体。例如，每个存储单元各自的第一源/漏层与第二源/漏层可以在它们之间限定分别处于沟道层在与第三方向正交的第四方向上相对两侧的凹入部。可以依次形成栅介质层和栅导体层，它们可以填充到凹入部中形成栅堆叠(因此自对准于沟道层)。可以将栅导体层构图为沿第一方向延伸的WL。该构图可以实质上不影响凹入部中填充的栅导体层。
根据本公开的实施例，沟道层(纳米片或纳米线)的厚度以及栅长主要由外延生长确定，而不是通过刻蚀或光刻来确定，因此可以具有良好的沟道尺寸/厚度和栅长控制。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
图1至23示意性示出了根据本公开实施例的制造存储器件的流程中的一些阶段。
如图1(a)和1(b)所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在此，提供硅晶片作为衬底1001。
在衬底1001中，可以形成阱区。如果要形成p型器件，则阱区可以是n型阱；如果要形成n型器件，则阱区可以是p型阱。一般地，在DRAM中，存储单元基于n型器件。因此，例如可以通过在衬底1001中注入p型掺杂剂 如硼(B)，且随后进行热退火来形成p型阱。例如，离子注入的能量可以为约30K-300K eV，注入剂量可以为约1E12-1E14/cm 2，注入角度可以为约0-15度。
以下，以形成n型器件为例进行描述。本领域技术人员清楚，例如通过适当调整掺杂的导电类型，以下描述同样适用于p型器件。
在衬底1001上，可以通过例如外延生长，形成第一源/漏层1003、沟道限定层1005和第二源/漏层1007。第一源/漏层1003可以用来限定下端源/漏部的位置，厚度例如为约50nm-300nm。沟道限定层1005可以用来限定沟道的位置，厚度例如为约30nm-150nm。第二源/漏层1005可以用来限定上端源/漏部的位置，厚度例如为约50nm-250nm。
第一源/漏层1003、沟道限定层1005和第二源/漏层1007中相邻的层相对于彼此可以具有刻蚀选择性。例如，第一源/漏层1003可以包括Si，沟道限定层1005可以包括SiGe(例如，Ge原子百分比为约10％-40％)，第二源/漏层1007可以包括Si。
第一源/漏层1003和第二源/漏层1007在生长时可以被原位掺杂，以(至少部分地)限定源/漏部的掺杂特性。例如，可以约1E19-1E21/cm 3的浓度掺杂n型掺杂剂如磷(P)。
随后，可以从第一源/漏层1003、沟道限定层1005和第二源/漏层1007来限定有源区。为避免光刻限制，根据本公开的实施例，在以下构图中使用了隔墙(spacer)图形转移技术。为形成隔墙，可以形成芯模图案(mandrel)。例如，可以在第二源/漏层1007上，通过例如淀积如化学气相淀积(CVD)，形成用于芯模图案的层1011。例如，用于芯模图案的层1011可以包括非晶硅或多晶硅，厚度为约50nm-400nm。另外，为了更好的刻蚀控制，可以通过例如淀积如CVD，先形成刻蚀停止层1009。例如，刻蚀停止层1009可以包括氧化物(例如，氧化硅)，厚度为约5nm-30nm。
在用于芯模图案的层1011上，可以通过例如淀积如CVD，形成硬掩模层1013。例如，硬掩模层1013可以包括氧化物，厚度为约50nm-400nm。
可以将用于芯模图案的层1011构图为芯模图案。
例如，如图2(a)和2(b)所示，可以通过光刻(版图关键尺寸(CD)可以 为约20nm-60nm)，在硬掩模层1013上形成构图的光刻胶(未示出)。可以构图的光刻胶作为刻蚀掩模，通过例如反应离子刻蚀(RIE)依次对硬掩模层1013、用于芯模图案的层1011和刻蚀停止层1009进行选择性刻蚀。RIE可以沿竖直方向进行，对芯模图案的层1011的RIE可以停止于刻蚀停止层1009，对刻蚀停止层1009的RIE可以停止于第二源/漏层1007。之后，可以去除光刻胶。
图2(a)中示意性示出了横向方向x、y和竖直方向z。x、y方向可以平行于衬底1001的顶面，并且可以彼此相交例如垂直；z方向可以基本上垂直于衬底1001的顶面。y方向可以对应于随后形成的字线(WL)的纵向延伸方向(可称为“第一方向”)，x方向可以对应于随后形成的位线(BL)的纵向延伸方向(可称为“第二方向”)。
在此，为形成存储单元阵列，芯模图案(为方便起见，仍以1011标示)包括一系列实质上平行延伸的线段。这些线段可以相对于y方向倾斜(即，成非正交的角度)。例如，线段的纵向延伸方向(可称为“第三方向”)相对于y方向可以成约30°-80°的角度。另外，线段的纵向延伸方向可以沿着特定的晶面，例如(100)晶面，以提升载流子(在n型器件的情况下，电子)的迁移率。
如图3(a)和3(b)所示，可以在芯模图案1011的侧壁上，形成隔墙1015。例如，可以以大致共形的方式淀积氧化物，然后沿z方向对淀积的氧化物层进行各向异性刻蚀如RIE，以去除其横向延伸部分而留下其竖直延伸部分，从而得到隔墙1015。隔墙1015随后可以用来限定器件有源区的位置。隔墙1015(横向上)的厚度可以为约30nm-200nm。
如图4所示，可以利用硬掩模层1013和隔墙1015，将第二源/漏层1007、沟道限定层1005和第一源/漏层1003构图为与芯模图案1011的平行条形图案相对应的脊状结构。例如，可以硬掩模层1013和隔墙1015作为刻蚀掩模，通过例如z方向上的RIE依次对各层进行选择性刻蚀，将图案转移到下方的层中。在此，可以存在对衬底1001的过刻，过刻深度例如为约10nm-100nm。
可以在第一源/漏层1003与第二源/漏层1007之间释放一定的空间，从而随后形成的栅堆叠(可以至少部分地)设置于该空间中，以便自对准于由沟道 限定层1005限定的沟道部。例如，如图5所示，可以对沟道限定层1005进行选择性刻蚀，以使其侧壁在横向上，例如，在与第三方向(图5中垂直于纸面的方向)正交的第四方向(图5中纸面内的水平方向)上，相对凹入，以形成凹入部。例如，选择性刻蚀可以采用(体积)比例例如为4∶1∶5的CF 4∶O 2∶He混合气体(干法刻蚀)，或者采用(体积)比例例如为1∶2∶4的HF(浓度为6％的水溶液)∶H 2O 2(浓度为30％的水溶液)∶CH 3COOH(浓度为99.8％的水溶液)混合溶液(湿法刻蚀)，横向刻蚀量可以为约10nm-100nm。
在图5的示例中，刻蚀后沟道限定层1005的侧壁仍然大致在竖直方向上。取决于刻蚀的工艺条件，刻蚀后沟道限定层1005的侧壁可以呈弯曲形状，例如C形。
如图6所示，可以通过例如选择性外延生长，在脊状结构的侧壁上形成有源层1017。由于选择性外延生长，硬掩模层1013、隔墙1015的表面上可以没有形成有源层1017。有源层1017在沟道限定层1005侧壁上的部分随后面对栅堆叠，并因此限定沟道部。沟道部基本上在竖直方向上延伸，因此有源层1017(特别是其在沟道限定层1005的侧壁上的部分)也可以称作(竖直)沟道层。根据本公开的实施例，有源层1017(限定沟道部)的厚度可以通过外延生长工艺决定(例如为约5nm-50nm)，因此可以更好地控制沟道部的厚度。
尽管在此使用了选择性外延生长，但是非选择性外延生长也适用。
可以根据设计对器件的性能要求，适当选择有源层1017的材料。例如，有源层1017可以包括各种半导体材料，例如元素半导体材料如Si、Ge等，或者化合物半导体材料如SiGe、InP、GaAs、InGaAs等。在该示例中，有源层1017可以包括Si，与第一源/漏层和第二源/漏层相同。
另外，有源层1017在生长时可以被原位(轻)掺杂，从而在沟道部中形成一定的掺杂分布，以调整器件的阈值电压(Vt)。
在凹入部中，随后可以形成栅堆叠。为防止后继处理在该凹入部中留下不必要的材料或者影响有源层1017，如图7所示，可以在该凹入中形成位置保持层1019。例如，可以采用台阶覆盖能力较好的低压CVD，淀积厚度为约10nm-100nm的氮化物(例如，氮化硅)。然后，可以硬掩模层1013和隔墙1015作为刻蚀掩模，通过例如z方向的RIE，来回蚀淀积的氮化物，以形成填充在 凹入部中的位置保持层1019。有源层1017位于凹入部之外的部分也可以被去除(或者，可以通过另外的RIE去除)。
作为以上对第一源/漏层1003和第二源/漏层1007进行的原位掺杂的补充或替代，可以对第一源/漏层1003和第二源/漏层1007进行掺杂，以实现所需的源/漏掺杂特性。这种掺杂可以通过离子注入或固相掺杂剂源层来实现。例如，可以通过淀积，以大致共形的方式，在图7所示的结构上形成固相掺杂剂源层(未示出)。固相掺杂剂源层可以是例如包含掺杂剂的氧化物。对于n型器件，固相掺杂剂源层可以包含n型掺杂剂，例如PSG(磷硅玻璃)。对于p型器件，固相掺杂剂源层可以包含p型掺杂剂，例如BSG(硼硅玻璃)。可以通过退火，例如在约700℃-1100℃下的激光快速退火，将固相掺杂剂源层中的掺杂剂驱入第一源/漏层1003和第二源/漏层1007中以形成所需的源/漏掺杂特性。可以控制退火工艺的条件(例如，时间)，使得掺杂剂向第一源/漏层1003和第二源/漏层1007中的驱入主要发生在横向上(抑制掺杂剂在竖直方向上从第一源/漏层1003和第二源/漏层1007扩散到沟道部中)。之后，可以去除固相掺杂剂源层。
在第一源/漏层1003和第二源/漏层1007生长时的原位掺杂满足器件性能要求的情况下，也可以不再另外进行掺杂。
接下来，可以利用隔墙1015来完成有源区的限定。
如图8(a)和8(b)所示，可以在衬底1001上形成电介质层1021。例如，可以通过淀积，形成厚度(例如，为约300nm-1000nm)足以完全覆盖脊状结构的氧化物。然后，对淀积的氧化物进行平坦化如化学机械抛光(CMP)，以去除硬掩模层1013并因此露出芯模图案1011。在淀积氧化物之前，还可以通过选择性刻蚀，去掉位置保持层1019。于是，电介质层1021也进入到凹入部中。电介质层1021有助于通过平坦化来露出芯模图案1011，而且(其一部分)随后也可以充当隔离层。
在图中，为了清楚地示出隔墙1015的位置(以方便读者理解有源区所在的区域)，仍然示出了其与电介质层1021之间的界面。当然，在该示例中，由于它们均为氧化物，因此它们之间的界面实际上可能并不清晰。
如图9所示，可以通过选择性刻蚀如采用TMAH溶液的湿法刻蚀(停止 于刻蚀停止层1009)，去除芯模图案1011。这样，在脊状结构上留下了呈闭合环形的隔墙1015。
如图10所示，可以利用隔墙1015作为刻蚀掩模，通过例如z方向上的RIE，依次选择性刻蚀刻蚀停止层1009、第二源/漏层1007、沟道限定层1005以及第一源/漏层1003。在此，尽管隔墙1015和刻蚀停止层1009均为氧化物，但是由于刻蚀停止层1009较薄，因此保留隔墙1015而去除刻蚀停止层1009是可能的。这样，在隔墙1015下方，第一源/漏层1003、沟道限定层1005、第二源/漏层1007以及有源层1017形成了与隔墙1015相对应的闭合环形，用以限定有源区。在此，同样地，可以存在对衬底1001的过刻，过刻深度例如为约10nm-100nm(在隔墙1015的内外两侧，过刻可以大致相同)。
当前，有源层1017在内侧被沟道限定层1005覆盖。可以相对于衬底1001、第一源/漏层1003、有源层1017和第二源/漏层1007(在该示例中均为Si)，通过选择性刻蚀，去除沟道限定层1005(在该示例中为SiGe)，从而在有源层1017的内侧留下用于栅堆叠的空间，如图11所示。
当前，有源区呈闭合环形连续延伸。可以进行隔离，以将连续延伸的有源区分为不同器件的相应有源区。例如，如图12所示，可以在衬底1001上形成光刻胶1023，并通过光刻(版图最小CD可以为约20nm-100nm)将其构图为露出需要隔离的区域。在此，利用各环形形状的彼此实质上平行的长边来形成器件，以便形成规则的存储单元阵列。因此，光刻胶1023一方面可以露出各环形在纵向方向上的端部(短边所在的端部，不用来形成器件)，另一方面可以露出长边上的局部区域，以将长边划分为若干段。这些段可以具有实质上相同的纵向延伸长度(即，光刻胶1023在同一条长边上两个相邻开口之间的距离)，从而随后基于此形成的器件可以具有基本上相同的尺寸(除了在靠近端部处，由于倾斜布局，靠近端部处可能存在一些长度不一致的段，这些段可以是虚设的，不用来形成器件)。在该示例中，光刻胶1023中形成有如下开口：在端部处的较大矩形，以及在端部之间的较小矩形。考虑到以下WL的形成，较小矩形可以排列成y方向上的列，这些列在x方向上间隔开。
如图13(a)、13(b)和13(c)所示，可以通过选择性刻蚀如z方向上的RIE，去除由光刻胶1023中的开口露出的区域中的隔墙1015(以及电介质层1021)、 第二源/漏层1007、有源层1017、第一源/漏层1003。同样地，可以存在对衬底1001的过刻，过刻深度例如为约10nm-100nm。这样，如图13(c)所示，在由光刻胶1023中的开口露出的区域中，各条长边被断开，从而分离为彼此隔开的段。如图13(b)所示，各段包括第一源/漏层1003、有源层1017和第二源/漏层1007的竖直堆叠(顶部设有隔墙1015)。
对于各段，可以部分地露出第一源/漏层1003，以便于随后形成从BL到露出部分的电接触。根据本公开的实施例，为节省面积，基于同一段，可以形成两个器件，这两个器件可以共享同一BL接触插塞。有鉴于此，可以在各段的大致中部露出第一源/漏层1003。
例如，如图14所示，可以在衬底1001上形成光刻胶1025，并通过光刻(版图最小CD可以为例如约20nm-100nm)将其构图为露出需要露出第一源/漏层1003的区域。在此，光刻胶1025可以露出各段在纵向方向上的大致中部(从而可以将各段划分为两个子段)。例如，光刻胶1025中的开口可以位于之前形成的光刻胶1023中的开口中在长边方向上相邻的开口之间，从而这些子段可以具有实质上相同的纵向延伸长度。类似地，光刻胶1025中可以形成矩形开口。考虑到以下BL的形成，矩形开口可以排列成x方向上的行，这些行在y方向上间隔开。
如图15(a)和15(b)所示，可以通过选择性刻蚀如z方向上的RIE，去除由光刻胶1025中的开口露出的区域中的隔墙1015(以及部分地去除电介质层1021)、第二源/漏层1007和有源层1017。另外，第一源/漏层1003的上部也可以被去除。例如，第一源/漏层1003可以被刻蚀掉约10％-50％的厚度。这样，如图15(b)所示，在由光刻胶1025中的开口露出的区域中，第一源/漏层1003的顶部上不存在有源层，有利于随后形成从BL到第一源/漏层1003的电接触。
至此，已经限定了各器件的有源区。具体地，各段中的每一子段可以分别用来形成单个开关器件，并可以以各开关器件为基础形成存储单元(例如，开关器件+数据存储结构)。在此，各段中的每个子段可以用作一个开关器件的有源区。但是，本公开不限于此。例如，每个段可以用作一个开关器件的有源区。在这种情况下，可以通过类似于结合图14、15(a)和15(b)描述的方法，在 各段在纵向延伸方向上的一端露出第一源/漏层的一部分，随后可以在第一源/漏层的露出部分上制作BL接触插塞。
可以在衬底上形成用于电隔离的隔离层。例如，如图16(a)和16(b)所示，可以通过淀积如CVD，在衬底上形成厚度(例如，为约300nm-1000nm)足以覆盖有源区的氧化物。然后，对淀积的氧化物进行平坦化如CMP。可以通过湿法刻蚀(例如，使用HF酸)或干法刻蚀，回蚀平坦化的氧化物(以及之前形成的同为氧化物的隔墙1015、电介质层1021)，在衬底1001上留下一定厚度的氧化物作为隔离层1029。例如，隔离层1029的顶面可以在沟道部的底部(或者，第一源/漏层1003的顶面)以下约10nm-150nm处。
在图16(a)的俯视图中，为了清楚起见，并未示出隔离层1029。如图16(a)清楚所示，在衬底上形成了呈线形延伸的多个器件有源区(对应于上述的“子段”)，它们相对于y方向倾斜。在纵向延伸方向上相邻的每对器件有源区各自的第一源/漏层可以彼此连接(从而对应于上述的“段”)，且在中部显露(图16(a)中较深色的部分，通过上述光刻胶1025限定)。纵向延伸方向上各对器件有源区之间的隔离(各段之间的间隔)可以通过上述光刻胶1023限定。
可以在隔离层1029上形成栅堆叠。根据本公开的实施例，栅堆叠可以与WL一起形成，以节省工艺步骤并因此降低成本。
例如，如图17所示，可以在隔离层1029上，通过淀积，以大致共形的方式形成栅介质层1031，并在栅介质层1031上形成栅导体层1033。例如，栅介质层1031可以包括高k栅介质如HfO 2，厚度例如为约1nm-10nm。在形成高k栅介质之前，还可以形成界面层，例如通过氧化工艺或淀积如原子层淀积(ALD)形成的氧化物。栅导体层1033可以包括厚度例如为约1nm-10nm的功函数调节金属如TiN等以及厚度例如为约100nm-800nm的栅导电金属如W等。栅导体层1033可以被平坦化如CMP，并可以填充各器件的有源区之间的空间。如此形成的栅堆叠(栅介质层1031+栅导体层1033)可以嵌入到第一源/漏层1003与第二源/漏层1007之间，并围绕沟道层1017。
至此，已基本上完成了存储单元中开关器件的制作。接下来，可以形成各种互连结构如WL、BL以及数据存储结构(例如，电容器)。
可以基于栅堆叠特别是其中的栅导体层1033来形成WL。
例如，如图18所示，可以在栅导体层1033上形成光刻胶1035，并通过光刻(版图CD尺寸最小可以为约10nm-50nm)将其构图为与WL相对应的图案(在该示例中，一系列y方向上的线条)。这些线条可以在y方向上延伸以穿过上述段与段之间的间隙(对应于光刻胶1023中的开口)，并可以在x方向上间隔开排列使得各器件有源区(对应于每一上述子段)与单个线条(对应于单条WL)相交。
如图19(a)、19(b)和19(c)所示，可以利用光刻胶1035作为刻蚀掩模，通过例如z方向上的RIE，对栅导体层1033进行选择性刻蚀，以将其构图为与光刻胶1035的图案相对应的WL。刻蚀可以停止于栅介质层1031。如图19(c)所示，栅导体层1033可以留于第一源/漏层1003与第二源/漏层1007之间的间隙中，并因此可以自对准地设置于沟道层1017的内外两侧，从而形成双栅配置。在此，如图19(b)所示，在WL处，栅导体层1033的顶面高于器件有源区的顶面(即，第二源/漏层1007的顶面)，从而可以将沟道层1017内外两侧的栅堆叠彼此电连接。于是，单个器件(对应于子段)可以电连接到单条WL(事实上，该器件的栅导体层与相应的WL一体)。
在图19(a)的俯视图中，为清楚起见，栅介质层1031并未如图19(b)中的截面图那样以黑色来表示。
尽管在此以栅导体层来形成WL，但是本公开不限于此。例如，可以在不另外形成刻蚀掩模的情况下，对栅导体层1033进行选择性刻蚀如z方向上的RIE。这样，栅导体层1033可以仅留于第一源/漏层1003与第二源/漏层1007之间的间隙中。然后，可以另外形成导电层，并利用光刻胶1035对该导电层进行构图以形成WL。WL可以跨过相应的子段延伸，并可以接触并因此电连接至子段的相对两侧的栅堆叠。
如图19(a)、19(b)和19(c)所示，存储单元可以包括在竖直方向上依次叠置的第一源/漏层1003、沟道层1017和第二源/漏层1007。沟道层1017可以呈纳米片或纳米线的形状。栅堆叠在竖直方向上介于第一源/漏层1003和第二源/漏层1007之间，并从沟道层1017(在第四方向上)的相对两侧夹着沟道层1017。有源区(第一源/漏层1003、沟道层1017和第二源/漏层1007的叠层)，特别是其中的沟道层1017，可以在相对于第一方向(WL的延伸方向)倾斜的第三 方向上延伸，从而可以增大沟道宽度并因此增大导通电流。
如图20(a)和20(b)所示，在隔离层1029上，可以形成层间电介质层1035。例如，可以淀积如CVD约50nm-100nm的氧化物，并对淀积的氧化物进行平坦化处理如CMP，来形成层间电介质层1035。在形成氧化物的层间电介质层1035之前，可以先形成例如约10nm-30nm的氮化物衬层(未示出)。在层间电介质层1035中，可以通过光刻，形成BL接触孔1037。如图20(b)所示，BL接触孔1037设于各器件有源区之间(对应于上述同一段中两个子段之间的位置，由光刻胶1025中的开口限定)，以露出第一源/漏层1003。
在图20(b)中，在各段中两个子段之间的位置处的第一源/漏层1003的顶面被示出为与隔离层1029的顶面齐平。但这仅仅是为了图示的方便而示意性示出的。取决于刻蚀量，第一源/漏层1003的顶面相对于隔离层1029的顶面可以突出或凹进。
如图21(a)和21(b)所示，可以在BL接触孔中填充导电材料，以形成BL接触插塞。另外，在层间电介质层1035上可以通过淀积且然后刻蚀导电材料的方法，形成BL 1039。BL 1039可以在x方向上延伸，并可以在y方向上间隔开排列，从而各BL接触插塞与单条BL电连接。可以看到，在纵向延伸方向上相邻的两个器件(对应于同一段的两个子段)可以共享相同的BL接触插塞，并因此电连接到相同的BL。这可以减少BL接触插塞的数量。
在图21(a)的俯视图中，为清楚起见，示出了各BL接触插塞(BL上的小方块)，其事实上被BL所遮挡而不可见。
另外，如图22(a)和22(b)所示，在层间电介质层1035中，可以通过光刻，形成电容接触孔1041。电容接触孔1041可以设于各器件有源区(对应于上述各子段，也即，上述各条长边在光刻胶1023中的开口与光刻胶1025中的开口之间的区域)上方，以露出第二源/漏层1007。
如图23所示，可以在电容接触孔1041中填充导电材料，以形成电容接触插塞1043。电容接触插塞1043可以将随后在层间电介质层1035上形成的电容器(未示出)电连接至各器件的第二源/漏层1007。
类似地，在层间电介质层1035中，可以通过光刻，形成WL接触孔，并在其中填充导电材料以形成WL接触插塞1045。各WL接触插塞1045位于 WL上方，以与WL相接触并因此电连接到WL。
注意，以上为形成BL接触孔、电容接触孔和WL接触孔而在层间电介质层1035中进行的刻蚀分别进行，这是因为它们各自的刻蚀深度不同。它们的处理顺序可以不同于以上描述的顺序。
随后，可以进行后段工艺，在此不再赘述。
根据本公开实施例的存储器件可以应用于各种电子设备。例如，电子设备可以包括存储器件和处理器。存储器件可以存储电子设备操作所需或运行过程中得到的数据。处理器可以基于存储器件中存储的数据和/或应用而运行。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、人工智能设备、移动电源等。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (18)

  1. 一种存储器件，包括：
    衬底；
    所述衬底上沿第一方向延伸的多条字线；
    所述衬底上沿与所述第一方向垂直的第二方向延伸的多条位线；以及
    所述衬底上的存储单元阵列，包括分别电连接到所述多条字线中的相应字线以及所述多条位线中的相应位线的多个存储单元，
    其中，每个所述存储单元包括：
    有源区，沿着相对于所述第一方向倾斜的第三方向延伸，且包括第一源/漏层、沟道层和第二源/漏层的竖直堆叠；以及
    栅堆叠，在竖直方向上介于所述第一源/漏层与所述第二源/漏层之间，且设于所述沟道层在与所述第三方向正交的第四方向上的相对两侧以夹着所述沟道层，
    其中，每个所述存储单元的相应字线在所述第一方向上跨过该存储单元延伸，以接触并电连接到该存储单元的所述相对两侧上的栅堆叠。
  2. 根据权利要求1所述的存储器件，其中，所述第三方向相对于所述第一方向成约30度至80度的角度。
  3. 根据权利要求1所述的存储器件，其中，所述栅堆叠包括栅介质层和所述栅介质层上的栅导体层，其中，所述栅导体层与相应字线成一体。
  4. 根据权利要求3所述的存储器件，还包括：
    所述衬底上的隔离层，所述栅堆叠设于所述隔离层上，
    其中，所述栅介质层延伸到所述隔离层、所述第一源/漏层和所述第二源/漏层的表面上。
  5. 根据权利要求1所述的存储器件，其中，在所述存储单元阵列中，所述多个存储单元沿着彼此平行的、在所述第三方向上延伸的线排列。
  6. 根据权利要求5所述的存储器件，其中，所述第三方向上相邻的每对存储单元各自的第一源/漏层成一体，
    所述存储器件还包括：各对存储单元之间的区域中设置在所述第一源/漏 层上的位线接触插塞，所述位线接触插塞接触并电连接到相应的位线。
  7. 根据权利要求6所述的存储器件，其中，在所述存储单元阵列中，各对存储单元中的两个存储单元分别排列在相应的位线在所述第一方向上的相对两侧。
  8. 根据权利要求1所述的存储器件，其中，所述第一源/漏层与所述第二源/漏层各自在所述第四方向上的宽度为约30nm至200nm，所述沟道层在所述第四方向上的厚度为约5nm至50nm。
  9. 根据权利要求1所述的存储器件，其中，所述第三方向沿着特定晶面。
  10. 根据权利要求9所述的存储器件，其中，所述晶面包括(100)晶面。
  11. 一种制造存储器件的方法，包括：
    在衬底上设置沿第一方向和第二方向之间的第三方向延伸的竖直堆叠，所述竖直堆叠包括依次叠置的第一源/漏层、沟道层和第二源/漏层，所述第一方向和所述第二方向彼此垂直；
    将所述竖直堆叠沿着所述第三方向分为多个段；
    基于所述多个段来限定多个存储单元；
    在所述衬底上形成沿所述第一方向延伸的多条字线，每条所述字线在所述第一方向上跨过所述多个存储单元中的相应存储单元延伸，并电连接到相应存储单元的栅堆叠；
    在所述衬底上形成沿所述第二方向延伸的多条位线，每条所述位线电连接到所述多个存储单元中的相应存储单元。
  12. 根据权利要求11所述的方法，其中，基于所述多个段来限定多个存储单元包括：
    在所述多个段中的每个段在所述第三方向上的中部区域，去除所述第二源/漏层和所述沟道层，以露出所述第一源/漏层，
    其中，每个段在所述第三方向上位于所述中部区域相对两侧的部分各自限定一个存储单元。
  13. 根据权利要求12所述的方法，还包括：
    在所述中部区域中形成到所述第一源/漏层的位线接触插塞，
    其中，所述位线接触插塞从所述第一源/漏层延伸到所述多条位线中的相 应位线。
  14. 根据权利要求12所述的方法，其中，
    每个所述存储单元各自的所述第一源/漏层与所述第二源/漏层在它们之间限定了分别处于所述沟道层在与所述第三方向正交的第四方向上相对两侧的凹入部，
    形成沿所述第一方向延伸的多条字线包括：
    依次形成栅介质层和栅导体层，其中，所述栅介质层和所述栅导体层填充到所述凹入部中形成所述栅堆叠；以及
    将所述栅导体层构图为沿所述第一方向延伸的字线，
    其中，每个所述存储单元的所述凹入部中的栅导体层与相应的字线连续。
  15. 根据权利要求11所述的方法，其中，所述第三方向相对于所述第一方向成约30度至80度的角度。
  16. 根据权利要求11所述的方法，其中，在衬底上设置竖直堆叠包括：
    在所述衬底上形成第一源/漏层、沟道限定层和第二源/漏层的叠层；
    在所述叠层上形成沿所述第三方向延伸的芯模图案；
    在所述芯模图案的侧壁上形成隔墙；
    以所述芯模图案和所述隔墙作为刻蚀掩模，将所述叠层构图为沿所述第三方向的脊状结构；
    对所述沟道限定层进行选择性刻蚀，以使其在横向上相对于所述第一源/漏层和所述第二源/漏层凹入；
    通过外延生长，在所述沟道限定层的侧壁上形成沟道层；
    去除所述芯模图案，并以所述隔墙各刻蚀掩模，将所述叠层构图为线状；以及
    去除所述沟道限定层。
  17. 一种电子设备，包括如权利要求1至10中任一项所述的存储器件。
  18. 根据权利要求17所述的电子设备，包括智能电话、计算机、平板电脑、可穿戴智能设备、人工智能设备、移动电源。
PCT/CN2021/133337 2021-11-19 2021-11-26 存储器件及其制造方法及包括存储器件的电子设备 WO2023087363A1 (zh)

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