WO2022213530A1 - 半导体结构及半导体结构的形成方法 - Google Patents

半导体结构及半导体结构的形成方法 Download PDF

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Publication number
WO2022213530A1
WO2022213530A1 PCT/CN2021/115297 CN2021115297W WO2022213530A1 WO 2022213530 A1 WO2022213530 A1 WO 2022213530A1 CN 2021115297 W CN2021115297 W CN 2021115297W WO 2022213530 A1 WO2022213530 A1 WO 2022213530A1
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Prior art keywords
substrate
region
forming
semiconductor structure
bit line
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PCT/CN2021/115297
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English (en)
French (fr)
Inventor
华文宇
何波涌
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芯盟科技有限公司
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Priority claimed from CN202110373396.4A external-priority patent/CN115188761A/zh
Priority claimed from CN202110374507.3A external-priority patent/CN115172278A/zh
Application filed by 芯盟科技有限公司 filed Critical 芯盟科技有限公司
Priority to US18/554,367 priority Critical patent/US20240196588A1/en
Publication of WO2022213530A1 publication Critical patent/WO2022213530A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the semiconductor structure.
  • DRAM Dynamic Random Access Memory
  • main function is to use the amount of stored charge in a capacitor to represent whether a binary bit (bit) is 1 or 0.
  • the basic memory cell of dynamic random access memory consists of a transistor and a storage capacitor, while the memory array consists of multiple memory cells. Therefore, the size of the memory chip area depends on the area size of the basic memory cell.
  • the technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, so as to improve the performance of the dynamic random access memory.
  • the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first surface and a second surface opposite to each other, and the substrate includes a plurality of mutually discrete source regions, a plurality of the active regions are arranged along a first direction, and a plurality of the active regions are parallel to the second direction, and the first direction and the second direction are perpendicular to each other; a plurality of first directions are formed in the substrate grooves, the first grooves extend from the first surface to the second surface, a plurality of the first grooves are arranged along a second direction, and the first grooves pass through a plurality of the active regions along the first direction;
  • An initial word line gate structure is formed within the first recess, the initial word line gate structure includes opposing first and second side regions, the first and second side regions being respectively opposite to the The active region is adjacent; the first side region and a portion of the active region adjacent to the first side region are removed to form
  • the word line gate structure includes a gate dielectric layer on the sidewall surface and the bottom surface of the first groove and a gate layer on the surface of the gate dielectric layer.
  • the depth of the first isolation structure is greater than or equal to the depth of the word line gate structure.
  • the material of the gate layer includes polysilicon or metal, and the metal includes tungsten.
  • the gate layer includes a first subsection located at the bottom of the first groove and a second subsection located on the first subsection, and the materials of the first subsection and the second subsection are different.
  • the material of the first subsection includes polysilicon or metal, and the metal includes tungsten; the material of the second subsection includes polysilicon or metal, and the metal includes tungsten.
  • the method for forming several bit line structures on the second surface of the substrate includes: thinning the second surface of the substrate until the second surface of the substrate is exposed. Isolate the surface of the structure; perform ion implantation on the active region exposed on the second surface of the substrate after thinning, and form a second doping region in the active region; form a number of bit line structures on the second doping region, each bit line
  • the structures are respectively electrically connected with a column of a plurality of second doping regions arranged along the second direction.
  • the depth of the second doped region is greater than or equal to the distance between the word line gate structure and the second surface of the substrate.
  • the method before forming a plurality of bit line structures on the second doped region, the method further includes: forming a bit line plug on the second doped region, the bit line plug electrically connecting the bit line structure and the the second doped region.
  • the method further includes: removing part of the bottom of the word line gate structure. until the surface of the gate dielectric layer is exposed, a fifth groove is formed in the active region, and several discrete second doping regions are formed in the active region on the second surface of the substrate.
  • the method for forming the bit line structure includes: forming a first dielectric layer on the exposed active region on the second surface of the substrate and on the second isolation structure, and the first dielectric layer has a plurality of third a groove, the third groove exposes the surface of the active region; the bit line structure is formed in the third groove.
  • the bit line structure includes a barrier layer on the sidewall surface and the bottom surface of the third groove, and a bit line layer on the barrier layer.
  • the method for forming the capacitor structure includes: forming a second dielectric layer on the first isolation structure and on the active area of the first surface of the substrate; forming a fourth groove in the second dielectric layer, the fourth The groove exposes part of the surface of the active region; and a capacitor structure is formed in the fourth groove.
  • the method for thinning the second surface of the substrate includes: providing a base, and the surface of the base is bonded to the surface of the second dielectric layer; turning the base and the substrate, and the second surface of the substrate is The surface is thinned.
  • the process of thinning the second surface of the substrate includes a chemical mechanical polishing process.
  • the method further includes: exposing the first side of the substrate. Ion implantation is performed in the active region, and a first doping region is formed in the active region; each capacitor structure is electrically connected to a first doping region respectively.
  • the projection of the capacitor structure on the first surface of the substrate at least coincides with a part of the first doped region.
  • the method further includes: forming capacitor plugs on the first doped region, the The capacitive plug electrically connects the capacitive structure and the first doped region.
  • a top surface of the word line gate structure facing the first side of the substrate is higher than a bottom plane of the first doped region facing the first side of the substrate.
  • the process of removing the first side region and the part of the active region adjacent to the first side region includes a dry etching process.
  • each of the capacitor structures is located on an active region adjacent to the second side region.
  • the technical solution of the present invention also provides a semiconductor structure, comprising: a substrate, the substrate includes a first surface and a second surface opposite to each other, the substrate includes a plurality of mutually discrete active regions, A plurality of the active regions are arranged along a first direction, and a plurality of the active regions are parallel to a second direction, and the first direction and the second direction are perpendicular to each other; a plurality of first grooves located in the substrate, The first groove extends from the first surface to the second surface, a plurality of the first grooves are arranged along the second direction, and the first grooves pass through a plurality of the active regions along the first direction; a wordline gate structure within a recess, the wordline gate structure comprising opposing first and second side regions, the second side region adjoining the active region; located within the first recess
  • the first isolation structure is adjacent to the first side region of the word line gate structure, the first isolation structure is located between the word line gate structure and the active region
  • the word line gate structure includes a gate dielectric layer on the sidewall surface and the bottom surface of the first groove and a gate layer on the surface of the gate dielectric layer.
  • the depth of the first isolation structure is greater than or equal to the depth of the word line gate structure.
  • the material of the gate layer includes polysilicon or metal, and the metal includes tungsten.
  • the gate layer includes a first subsection located at the bottom of the first groove and a second subsection located on the first subsection, and the materials of the first subsection and the second subsection are different.
  • the material of the first subsection includes polysilicon or metal, and the metal includes tungsten; the material of the second subsection includes polysilicon or metal, and the metal includes tungsten.
  • the active region on the second side of the substrate also exposes the bottom surface of the gate dielectric layer.
  • the method further includes: a first doped region located in the active region exposed on the first surface of the substrate; each capacitor structure is electrically connected to one of the first doped regions.
  • the projection of the capacitor structure on the first surface of the substrate at least coincides with a part of the first doped region.
  • it further includes: a capacitor plug located between the capacitor structure and the first doped region, the capacitor plug electrically connecting the capacitor structure and the first doped region.
  • a top surface of the word line gate structure facing the first side of the substrate is higher than a bottom surface of the first doped region facing the first side of the substrate.
  • the method further includes: a second doped region located in the active region exposed on the second surface of the substrate; each bit line structure is electrically connected to a column of several second doped regions arranged along the second direction.
  • the depth of the second doped region is greater than or equal to the distance between the word line gate structure and the second surface of the substrate.
  • the method further includes: a bit line plug located between the bit line structure and the second doping region, the bit line plug electrically connecting the bit line structure and the second doping region.
  • the second isolation structure is exposed on the second surface of the substrate.
  • it further includes: a first dielectric layer located on the second surface of the substrate and on the second isolation structure, wherein the first dielectric layer has a third groove, and the third groove exposes the active region surface; the bit line structure is located in the third groove.
  • the bit line structure includes a barrier layer on the sidewall surface and the bottom surface of the third groove, and a bit line layer on the barrier layer.
  • the material of the second isolation structure includes a dielectric material, and the dielectric material includes silicon oxide.
  • the material of the first isolation structure includes a dielectric material, and the dielectric material includes silicon oxide.
  • the method further includes: a second dielectric layer located on the first isolation structure and the first surface of the active region; the capacitor structure is located in the second dielectric layer.
  • each of the capacitor structures is located on an active region adjacent to the second side region.
  • the bit line structure is located on the second side of the substrate, and the capacitor structure is located on the first side of the substrate, thereby greatly simplifying the difficulty and cost of the manufacturing process;
  • the word line gate The pole structure is located in the substrate, and the channel controlled by the word line gate structure is perpendicular to the surface of the substrate, so that the area in the horizontal direction of the substrate can be saved, and the density of the memory array unit can be improved;
  • first doped region and the second doped region are respectively located on two sides of the substrate, thereby saving the area in the horizontal direction of the substrate, thereby increasing the density of the memory array units.
  • the gate layer includes a first subsection and a second subsection located on the first subsection, the material of the first subsection includes polysilicon or a metal, and the metal includes tungsten; the second subsection The materials include polysilicon or metals including tungsten.
  • the material of the gate layer is not pure polysilicon or metal, so that the resistance improvement performance and the leakage current improvement performance of the gate layer are balanced.
  • a capacitor plug located between the capacitor structure and the first doped region, the capacitor structure and the first doped region are electrically connected through the capacitor plug, so as to form a process for forming the capacitor structure and the capacitor plug
  • the window can be enlarged.
  • the active region on the second side of the substrate also exposes the bottom surface of the gate dielectric layer.
  • the active regions on the second side of the substrate are separated from each other, so that after the bit line structure is formed on the active regions on the second side of the substrate, the generated capacitance is reduced.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in an embodiment
  • FIGS. 2 to 24 are schematic structural diagrams of a process of forming a semiconductor structure in an embodiment of the present invention.
  • 25 to 27 are schematic structural diagrams of a semiconductor structure forming process in another embodiment of the present invention.
  • 28 and 29 are schematic structural diagrams of a semiconductor structure formation process in another embodiment of the present invention.
  • FIG. 30 and FIG. 31 are schematic structural diagrams of a process of forming a semiconductor structure in another embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure in an embodiment.
  • FIG. 1 which includes: a substrate 100 ; a word line gate structure 101 located in the substrate 100 ; a source doped region 103 and a drain doped region 102 located in the substrate 100 on both sides of the word line gate structure 101 ;
  • the bit line structure 105 is electrically connected to the source doped region 103 through the source plug 104 ;
  • the capacitor structure 107 is electrically connected to the drain doped region 102 through the capacitor plug 106 .
  • the formation process of the semiconductor structure is as follows: firstly, the source doped region 103 and the drain doped region 102 are formed, then the word line gate structure 101 is formed in the substrate 100 , then the source plug 104 and the bit line structure 105 are formed, and then the word line gate structure 101 is formed in the substrate 100 .
  • the capacitor plug 106 is formed, and finally the capacitor structure 107 is formed.
  • the channel of the semiconductor structure is U-shaped, and the source doped region 103 and the drain doped region 102 are on horizontal sides of the word line gate structure 101 .
  • the bit line structure 105 and the capacitor structure 107 are on the same side of the transistor, and both are located above the substrate in the process.
  • the capacitor plug 106 of the capacitor structure 107 needs to pass through the bit line structure 105 , which makes the overall process complexity relatively high, and has extremely high requirements on the photolithography process and alignment.
  • the technical solution of the present invention forms a new semiconductor structure.
  • the capacitor structure is located on the first side of the substrate, and the bit line structure is located on the second side of the substrate, thereby greatly simplifying the difficulty and complexity of the manufacturing process.
  • the word line gate structure is located in the substrate, thereby saving space in the direction perpendicular to the surface of the substrate and increasing the density of the memory array units; on the other hand, the word line gate structure is similar to There is a first isolation structure between the active regions, the second side region of the word line gate structure is adjacent to the active region, and the first side region of the word line gate structure is adjacent to the first isolation structure, so that the The first isolation structure can isolate the first side region and the active region of the word line gate structure, so as to prevent the word line gate structure from being in contact with the active regions on both adjacent sides at the same time to generate two channels to form parasitic devices , so that the transistor is not easy to turn off. Therefore, the leakage current can be reduced, and the performance of the semiconductor structure can be improved.
  • FIGS. 2 to 24 are schematic structural diagrams of a process of forming a semiconductor structure in an embodiment of the present invention.
  • FIG. 3 is a top view of the first surface 300 of the substrate of FIG. 2, and FIG. 2 is a schematic cross-sectional structure diagram of FIG. 3 along the section line AA1.
  • the substrate 200 is provided. On one side 300 and the second side 400, the substrate 200 includes a plurality of mutually discrete active regions 201, a plurality of the active regions 201 are arranged along the first direction X, and a plurality of the active regions 201 are parallel to the second Direction Y, the first direction X and the second direction Y are perpendicular to each other.
  • the material of the substrate 200 is silicon.
  • the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of Group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI).
  • the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.
  • a second isolation structure 202 is provided between adjacent active regions 201 .
  • the material of the second isolation structure 202 includes dielectric materials including silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon nitride carbide and nitrogen A combination of one or more of silicon oxycarbide.
  • the material of the second isolation structure 202 includes silicon oxide.
  • FIG. 6 is a top view of the first surface 300 of the substrate shown in FIGS. 5 and 4
  • FIG. 4 is a schematic cross-sectional structural diagram of FIG. 6 along the section line BB1
  • FIG. 5 is a cross-sectional view of FIG. 6
  • a schematic cross-sectional structure diagram in the direction of line CC1 a plurality of first grooves 203 are formed in the substrate 200, the first grooves 203 extend from the first surface 300 to the second surface 400, and a plurality of the first grooves 203 are formed.
  • the first grooves 203 are arranged along the second direction Y, and the first grooves 203 pass through a plurality of the active regions 201 along the first direction X.
  • the method for forming the first groove 203 includes: forming a patterned mask layer (not shown) on the first surface 300 of the substrate, and the patterned mask layer exposes part of the active region 201 surface; using the patterned mask layer as a mask to etch the active region 201 to form the first groove 203 in the substrate.
  • the bottom plane of the first groove 203 facing the second surface 400 of the substrate is higher than the bottom plane of the second isolation structure 202 facing the second surface 400 of the substrate.
  • a physical space is reserved for the subsequent formation of the second doped region on the second surface 400 of the substrate.
  • FIG. 8 is a top view of the first surface 300 of the substrate of FIG. 7
  • FIG. 7 is a schematic cross-sectional structure diagram of FIG. structure
  • the initial word line gate structure includes an opposite first side region (not marked) and a second side region (not marked), the first side region and the second side region are respectively connected with the active region 201 adjacency.
  • the initial word line gate structure includes an initial gate dielectric layer 204 located on the sidewall surface and bottom surface of the first groove 203 and an initial gate dielectric layer 205 located on the surface of the initial gate dielectric layer 204 .
  • the top surface of the initial word line gate structure toward the first surface 300 of the substrate is lower than the surface of the first surface 300 of the substrate, so as to provide a physical space for the subsequent formation of the first doped region on the first surface 300 of the active region 201 .
  • the method for forming the initial word line gate structure includes: forming a gate dielectric material layer (not shown) on the sidewall surface and bottom surface of the first groove 203 and the surface of the active region 201 of the first surface 300 of the substrate; A gate material layer (not shown) is formed on the dielectric material layer; the gate material layer and the gate dielectric material layer are planarized until the surface of the active region 201 is exposed to form a transition initial word line gate structure; etch back The initial word line gate structure is transitioned until a part of the sidewall of the first recess 203 is exposed to form the initial word line gate structure.
  • the material of the initial gate dielectric layer 204 includes silicon oxide or a low-K (K less than 3.9) material; the material of the initial gate layer 205 includes polysilicon.
  • the material of the initial gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material includes aluminum oxide or hafnium oxide ;
  • the material of the initial gate layer includes metal, and the metal includes tungsten.
  • the initial word line gate structure further includes an initial work function layer located between the initial gate dielectric layer and the initial gate layer.
  • the material of the initial work function layer includes an N-type work function material or a P-type work function material, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.
  • the initial gate layer includes a first subsection at the bottom of the first groove and a second subsection on the first subsection, and the materials of the first subsection and the second subsection are different.
  • FIG. 10 is a top view of the first surface 300 of the substrate of FIG. 9, and FIG. 9 is a schematic cross-sectional structure diagram of FIG. 10 along the section line EE1.
  • the substrate Ion implantation is performed on the surface of the active region 201 exposed by the first surface 300 of the bottom 200 to form a first doped region 206 in the active region 201 .
  • the top surface of the initial word line gate structure facing the first side 300 of the substrate is higher than the bottom plane of the first doped region 206 facing the first side 300 of the substrate.
  • it can ensure that the first doped region 206 can be in contact with the initial gate dielectric layer 204, so as to ensure that the first doped region 206 is conductive with the channel and the second doped region formed subsequently;
  • the initial word line gate structure is directed toward the top surface of the first side 300 of the substrate, and the surface of the first side 300 of the first substrate 200, thereby also reducing the possibility that the channel formed in the active region 201 of the subsequent word line gate structure will not
  • the first doped regions 206 are excessively overlapped to prevent the performance of the first doped regions 206 from being affected.
  • the first doping region 206 has doping ions, and the doping ions are N-type or P-type; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions ions, boron fluoride ions or indium ions.
  • FIG. 11 is a schematic structural diagram based on FIG. 9 .
  • the first side region and the part of the active region 201 adjacent to the first side region are removed to form a word line gate structure.
  • a second groove 207 is formed between the word line gate structure and the active region 201 .
  • the word line gate structure includes a gate dielectric layer 208 located on a part of the sidewall surface and the bottom surface of the first groove 203 and a gate dielectric layer 209 located on the surface of the gate dielectric layer 208 .
  • the word line gate structure is located in the substrate, and the channel controlled by the word line gate structure is perpendicular to the surface of the substrate, so that the area in the horizontal direction of the substrate can be saved, and the density of the memory array unit can be improved.
  • the first side region and the part of the active region 201 adjacent to the first side region are removed, so that only the second side of the word line gate structure is in contact with the active region 201, so that a trench is generated during operation channel, so that the transistor meets the performance requirements, and the turn-on and turn-off are easily controlled, so that the leakage current can be reduced.
  • the depth of the second groove 207 is greater than or equal to the depth of the word line gate structure. Therefore, the isolation function of the first isolation structure formed in the second groove 207 can be ensured, so that the channel of the first side region of the word line gate structure can be completely turned off, and the leakage current can be reduced.
  • the process of removing the first side region and the part of the active region 201 adjacent to the first side region includes a dry etching process.
  • the dry etching process can easily control the depth and dimensional accuracy of the formed second grooves 207 .
  • FIG. 13 is a top view of FIG. 12
  • FIG. 12 is a schematic cross-sectional view of FIG. 13 along the section line FF1 .
  • a first isolation structure 210 is formed in the second groove 207 .
  • the first isolation structure 210 is also located on the top surface of the word line gate structure.
  • the first isolation structure 210 is located between the word line gate structure and the active region 201, and the second side region of the word line gate structure is adjacent to the active region 201, so that the first isolation structure 210 can isolate
  • the first side region and the active region 201 of the word line gate structure prevent the word line gate structure from being in contact with the active regions 201 on both adjacent sides at the same time to generate two channels to form parasitic devices, making it difficult for transistors turn-off condition, thereby reducing leakage current.
  • the method for forming the first isolation structure 210 includes: forming an isolation material layer (not shown) in the second groove 207, on the top of the word line gate structure and on the surface of the active region 201; and planarizing the isolation material layer, Until the surface of the active region 201 is exposed, the first isolation structure 210 is formed.
  • the material of the first isolation structure 210 includes dielectric materials including silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon nitride carbide and nitrogen A combination of one or more of silicon oxycarbide.
  • the material of the first isolation structure 210 includes silicon oxide.
  • the depth of the first isolation structure 210 is greater than or equal to the depth of the word line gate structure. Therefore, the isolation function of the first isolation structure 210 enables the channel of the first side region of the word line gate structure to be completely turned off, thereby reducing leakage current.
  • FIG. 15 is a top view of the first surface 300 of the substrate in FIG. 14
  • FIG. 14 is a schematic cross-sectional structure diagram of FIG. 15 along the section line GG1 .
  • a plurality of capacitor structures 212 are formed on the region 201 , and each capacitor structure 212 is electrically connected to a first doped region 206 respectively.
  • Each of the capacitor structures 212 is located on the active region 201 adjacent to the second side region, and the projection of the capacitor structure 212 on the first surface of the active region 201 is at least partially the same as that of the first doped region 206 coincide.
  • the method further includes: forming a capacitor plug 211 on the first doped region 206 , the capacitor plug 211 electrically connecting the capacitor structure 212 and the first doped region 206 .
  • the method for forming the capacitor plug 211 and the capacitor structure 212 includes: forming a second dielectric layer (not shown) on the first isolation structure 210 and the active region 201 of the first surface 300 of the substrate; A fourth groove (not shown) is formed in the layer; an opening (not shown) is formed in the fourth groove, and the opening exposes part of the surface of the first doped region 206; a capacitor plug 211 is formed in the opening, A capacitor structure 212 is formed in the fourth groove.
  • the method for forming the capacitor plug 211 and the capacitor structure 212 is to form a fourth groove in the second dielectric layer, form an opening in the fourth groove, form a capacitor plug in the opening, and then form a capacitor in the fourth groove structure.
  • the process window is large, the process is relatively simple, and the production efficiency can be improved.
  • the capacitor structure 212 includes: a first electrode layer (not shown), a second electrode layer (not shown), and a dielectric layer (not shown) located between the first electrode layer and the second electrode layer.
  • the shape of the dielectric layer includes: planar or "U" shape.
  • the surface of the first electrode layer is flat, and the surface of the second electrode layer is flat.
  • the surface of the first electrode layer is an uneven surface
  • the surface of the second electrode layer is an uneven surface
  • the material of the first electrode layer includes: metal or metal nitride; the material of the second electrode layer includes: metal or metal nitride; the metal includes: copper, aluminum, tungsten, cobalt, nickel and tantalum A combination of one or more; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
  • the material of the capacitor plug 211 includes: metal or metal nitride; the metal includes: one or a combination of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes nitride A combination of one or more of tantalum and titanium nitride.
  • the capacitive plug may not be formed, and the capacitive structure is electrically connected to the first doped region in direct contact.
  • the method for forming the capacitor structure includes: forming a second dielectric layer on the first isolation structure and on the active area of the first surface of the substrate; forming a fourth groove in the second dielectric layer, the fourth groove Part of the surface of the first doped region is exposed; and a capacitor structure is formed in the fourth groove.
  • bit line structures 215 are formed on the second surface 400 of the substrate, the plurality of the bit line structures 215 are arranged along the first direction X, and the plurality of the bit line structures 215 are parallel to the second direction Y. Please refer to FIG. 16 to FIG. 24 for the formation process of the bit line structure 215 .
  • FIG. 18 is a top view of the second surface 400 of the substrate shown in FIGS. 16 and 17
  • FIG. 16 is a schematic cross-sectional structure diagram of FIG. 18 taken along the section line HH1
  • FIG. 17 is a cross-sectional view of FIG.
  • a schematic diagram of the cross-sectional structure along the line JJ1 the second surface 400 of the substrate is thinned until the surface of the second isolation structure 202 is exposed.
  • the method for thinning the second surface 400 of the substrate includes: providing a base (not shown), and the surface of the base is bonded to the surface of the second dielectric layer; The second side 400 is thinned.
  • the process of thinning the second surface 400 of the substrate includes a chemical mechanical polishing process.
  • FIG. 21 is a top view of the second surface 400 of the substrate shown in FIGS. 19 and 20
  • FIG. 19 is a schematic cross-sectional structural diagram of FIG. 21 along the section line KK1
  • FIG. 20 is a cross-sectional view of FIG. 21
  • the first doped region 206 and the second doped region 213 are located on two sides of the substrate 200 respectively, thereby saving the area of the substrate 200 in the horizontal direction, thereby increasing the density of the memory array units.
  • the depth of the second doped region 213 is greater than or equal to the distance between the word line gate structure and the second surface 400 of the substrate 200, so as to ensure that the second doped region 213 can be connected to the gate dielectric layer 208 contact to ensure that the second doping region 213 is connected to the channel and the first doping region 206 .
  • the second doping region 213 has doping ions, and the doping ions are N-type or P-type; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions ions, boron fluoride ions or indium ions.
  • the conductivity type of the dopant ions in the second doping region 213 is the same as the conductivity type of the dopant ions in the first doping region 206 .
  • FIGS. 22 , 23 and 24 are a top view of the second surface 400 of the substrate shown in FIGS. 22 and 23
  • FIG. 22 is a schematic cross-sectional structure diagram of FIG. 24 along the section line MM1
  • FIG. 23 is a cross-sectional view of FIG.
  • the method for forming the bit line structure 215 includes: forming a first dielectric layer 214 on the active region 201 of the second surface 400 of the substrate and on the second isolation structure 202, and the first dielectric layer 214 has a plurality of third recesses in it. A groove (not shown), the third groove exposes the surface of the second doping region 213; the bit line structure 215 is formed in the third groove.
  • the bit line structure 215 includes a barrier layer (not shown) on the sidewall surface and the bottom surface of the third groove, and a bit line layer (not shown) on the barrier layer.
  • the material of the barrier layer includes metal nitride; the material of the bit line layer includes metal or metal nitride; the metal includes: one or a combination of copper, aluminum, tungsten, cobalt, nickel and tantalum ; The metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.
  • the method further includes: forming a bit line plug on the second doped region, the bit line plug electrically connecting the bit line structure and the second doped region.
  • the capacitor structure 212 is formed on the first side 300 of the substrate, and the bit line structure 215 is formed on the second side 400 of the substrate, thereby greatly simplifying the difficulty and cost of the manufacturing process;
  • the word line gate structure is located in the substrate, and the channel controlled by the word line gate structure is perpendicular to the surface of the substrate, so that the area in the horizontal direction of the substrate can be saved, and the density of the memory array unit can be improved;
  • the structure 210 can isolate the first side region of the word line gate structure and the active region 201, so as to prevent the word line gate structure from being in contact with the active regions 201 on both adjacent sides at the same time to generate two channels to form parasitic devices , so that the transistor is not easy to turn off. Therefore, the leak
  • an embodiment of the present invention also provides a semiconductor structure, please continue to refer to FIG. 22 , FIG. 23 and FIG. 24 , including:
  • the substrate 200 includes a first surface 300 and a second surface 400 opposite to each other, the substrate 200 includes a plurality of mutually discrete active regions 201, and the plurality of the active regions 201 are arranged along the first direction X , and several of the active regions 201 are parallel to the second direction Y, and the first direction X and the second direction Y are perpendicular to each other;
  • a wordline gate structure located in the first recess, the wordline gate structure comprising an opposing first side region and a second side region, the second side region adjoining the active region 201;
  • capacitor structures 212 located on the second surface 400 of the substrate 200, the capacitor structures 212 are electrically connected to the active region 201;
  • a plurality of bit line structures 215 located on the second surface 400 of the substrate 200 are arranged along the first direction X, and a plurality of the bit line structures 215 are parallel to the second direction Y.
  • the word line gate structure includes a gate dielectric layer 208 located on the sidewall surface and the bottom surface of the first groove, and a gate dielectric layer 209 located on the surface of the gate dielectric layer 208 .
  • the depth of the first isolation structure 210 is greater than or equal to the depth of the word line gate structure.
  • the material of the gate layer 209 includes polysilicon or metal, and the metal includes tungsten.
  • each capacitor structure 212 is electrically connected to one of the first doped regions 206 respectively.
  • the projection of the capacitor structure 212 on the first surface 300 of the substrate 200 at least coincides with a part of the first doped region 206 .
  • a capacitor plug 211 located between the capacitor structure 212 and the first doped region 206 is further included, and the capacitor plug 211 is electrically connected to the capacitor structure 212 and the first doped region 206 .
  • the top surface of the word line gate structure facing the first side 300 of the substrate 200 is higher than the bottom surface of the first doped region 206 facing the first side 300 of the substrate 200 .
  • it further includes: a second doped region 213 located in the active region 201 exposed from the second surface 400 of the substrate 200; the bit line structures 215 are respectively connected with a column of a plurality of second doped regions arranged along the second direction Y.
  • the doped regions 213 are electrically connected.
  • the depth of the second doped region 213 is greater than or equal to the distance between the word line gate structure and the second surface 400 of the substrate 200 .
  • the method further includes: a bit line plug located between the bit line structure and the second doping region, the bit line plug electrically connecting the bit line structure and the second doping region .
  • second isolation structures 202 between adjacent active regions; the second isolation structures 202 are exposed from the second surface 400 of the substrate.
  • it further includes: a first dielectric layer 214 located on the second surface 400 of the substrate 200 and on the second isolation structure 202 , the first dielectric layer 214 has a third groove therein, and the third The recess exposes the surface of the active region 201; the bit line structure 215 is located in the third recess.
  • the bit line structure 215 includes a barrier layer on the sidewall surface and the bottom surface of the third groove, and a bit line layer on the barrier layer.
  • the material of the second isolation structure 202 includes a dielectric material, and the dielectric material includes silicon oxide.
  • the material of the first isolation structure 210 includes a dielectric material, and the dielectric material includes silicon oxide.
  • it further includes: a second dielectric layer located on the first isolation structure 210 and the first surface 300 of the substrate; the capacitor structure is located in the second dielectric layer.
  • each of the capacitor structures 212 is located on the active region 201 adjacent to the second side region.
  • FIG. 25 to FIG. 27 are schematic structural diagrams of a semiconductor structure forming process in another embodiment of the present invention.
  • FIG. 25 is a schematic structural diagram based on FIG. 19, FIG. 26 is a structural schematic diagram based on FIG. 21, FIG. 26 is a top view of the second surface 400 of the substrate in FIG. 25, and FIG. 26.
  • a plurality of discrete second doped regions 313 are formed in the active region 201 of the second surface 200 .
  • FIG. 27 is a schematic structural diagram based on FIG. 25 .
  • a first dielectric layer 314 is formed in the fifth groove 301 , on the active region 201 of the second surface 400 of the substrate, and on the second isolation structure 202 .
  • the first dielectric layer 314 has a plurality of third grooves (not shown), and the third grooves expose the surface of the second doped region 313 ; bit line structures 315 are formed in the third grooves.
  • the active regions 201 of the second surface 400 of the substrate are separated from each other, so that after the bit line structure 315 is formed on the second doped region 313, the resulting capacitance is reduced.
  • an embodiment of the present invention further provides a semiconductor structure. Please continue to refer to FIG. 27 .
  • the difference between the structure of FIG. 27 and the structure of FIG. 22 is that the gate dielectric is exposed in the active region of the second surface 400 of the substrate. layer 208 surface.
  • it further includes: a fifth groove (not shown) located in the active region 201 at the bottom of the word line gate structure, the fifth groove extending from the second surface 400 of the substrate to the first surface 300 extends, and the fifth groove exposes the surface of the gate dielectric layer 208, the first dielectric layer 314 is also located in the fifth groove; a plurality of second doped regions located in the second surface 400 of the active region 201 313 , a plurality of the second doping regions 313 are separated from each other, and the fifth recess is located between adjacent second doping regions 313 .
  • the active regions 201 of the second surface 400 of the substrate are separated from each other, so that after the bit line structure 215 is formed on the second doped region 313, the resulting capacitance is reduced.
  • FIG. 28 and FIG. 29 are schematic structural diagrams of a process of forming a semiconductor structure in another embodiment of the present invention.
  • FIG. 28 is a schematic view of the structure based on FIG. 4 .
  • An initial word line gate structure is formed in the first recess 203 , and the initial word line gate structure includes opposite first side regions (not marked). ) and a second side region (not indicated), the first side region and the second side region are respectively adjacent to the active region 201 .
  • the initial word line gate structure includes an initial gate dielectric layer 404 on the sidewall surface and bottom surface of the first groove 203 and an initial gate layer on the surface of the initial gate dielectric layer 404 .
  • the initial gate layer includes a first subsection 405 located at the bottom of the first groove 203 and a second subsection 406 located on the first subsection 405.
  • the first subsection 405 and the first subsection 406 The materials of the two subsections 406 are different.
  • the material of the first subsection 405 includes metal or polysilicon, and the metal includes tungsten; the material of the second subsection 406 includes metal or polysilicon, and the metal includes tungsten.
  • the material of the gate layer is not pure polysilicon or metal, so that the performance of improving the resistance of the gate layer and the performance of improving the leakage current are balanced, avoiding the resistance of the gate layer when the material of the gate layer is polysilicon. In the larger case, it also avoids the situation that leakage is likely to occur when the material of the gate layer is metal, thereby improving the performance of the semiconductor structure.
  • the material of the first subsection 405 includes polysilicon; the material of the second subsection 406 includes tungsten.
  • the material of the first subsection includes tungsten; the material of the second subsection includes polysilicon.
  • the method for forming the initial word line gate structure includes: forming an initial gate dielectric material layer (not shown) on the sidewall surface and bottom surface of the first groove 203 and the top surface of the active region 201 on the first surface 300 of the substrate ; forming an initial first subsection (not shown) on the initial gate dielectric layer; etching back the initial first subsection until the top surface of the initial first subsection is lower than the first surface 300 of the substrate A first subsection 405 is formed on the top surface of the active region 201 and a part of the initial gate dielectric material layer on the sidewall of the first groove 201 is exposed; an initial second subsection (not shown) is formed on the first subsection 405 ; planarize the initial second subsection and the initial gate dielectric material layer on the top of the active region 201 on the first side 300 of the substrate until the top surface of the active region 201 on the first side 300 of the substrate is exposed to form an initial gate
  • the dielectric layer 404 and the transition second subsection (not shown); the transition second subsection is etched back to form the second subsection 406
  • ion implantation is performed on the active region 201 of the first surface 300 of the substrate 200 to form a first doped region 206 in the active region 201;
  • the first side region and the part of the active region 201 adjacent to the first side region form a word line gate structure, and a second groove is formed between the word line gate structure and the active region 201; in A first isolation structure 410 is formed in the second groove; a plurality of capacitor structures 212 are formed on each of the active regions 201 on the first surface 300 of the substrate 200 , and each capacitor structure 212 is electrically connected to a first doped region 206 respectively ; Ion implantation is performed on the active region 201 of the second surface 400 of the substrate 200, and a second doped region 213 is formed in the active region 201; 215 are respectively electrically connected to a row of second doped regions 213 arranged along the second direction Y.
  • the first isolation structure 210 For the formation process of the first doped region 206 , the first isolation structure 210 , the capacitor structure 212 , the second doped region 213 and the bit line structure 215 , please refer to FIGS. 9 to 24 , which will not be repeated here.
  • an embodiment of the present invention further provides a semiconductor structure.
  • the gate layer includes a first subsection 405 located at the bottom of the first groove and a first subsection 405 located at the bottom of the first groove.
  • a second subsection 406 on a subsection 405, the first subsection 405 and the second subsection 406 are of different materials.
  • the material of the first subsection 405 includes metal
  • the metal includes tungsten
  • the material of the second subsection 406 includes polysilicon.
  • the material of the first subsection includes polysilicon
  • the material of the second subsection includes a metal
  • the metal includes tungsten
  • FIG. 30 and FIG. 31 are schematic structural diagrams of a process of forming a semiconductor structure in another embodiment of the present invention.
  • FIG. 30 is a schematic structural diagram based on FIG. 28 .
  • ion implantation is performed on the active region 201 of the first surface 300 of the substrate 200 .
  • a second groove is formed between the source regions 201;
  • a first isolation structure 410 is formed in the second groove;
  • a plurality of capacitor structures 212 are formed on each of the active regions 201 on the first surface 300 of the substrate 200, and each capacitor structure 212 are respectively electrically connected to a first doped region 206 ;
  • ion implantation is performed on the active region 201 of the second surface 400 of the substrate 200 to form a second doped region 613 in the active region 201 .
  • the first isolation structure 210 For the formation process of the first doped region 206 , the first isolation structure 210 , the capacitor structure 212 and the second doped region 613 , please refer to FIG. 9 to FIG. 21 , and details are not repeated here.
  • a first dielectric layer 214 is formed in the fifth groove 601 , on the active region 201 of the second surface 400 of the substrate and on the second isolation structure 202 , and the first dielectric layer 214 has a plurality of third A groove (not shown), the third groove exposes the surface of the second doped region 613; the bit line structure 215 is formed in the third groove.
  • the active regions 201 of the second surface 400 of the substrate are separated from each other, so that after the bit line structure 215 is formed on the second doped region 613, the resulting capacitance is reduced.
  • an embodiment of the present invention also provides a semiconductor structure. Please continue to refer to FIG. 31 .
  • the difference between the structure of FIG. 31 and the structure of FIG. 22 is that the gate is exposed from the active region 201 of the second surface 400 of the substrate.
  • the surface of the dielectric layer 208; the gate layer includes a first subsection 405 located at the bottom of the first groove and a second subsection 406 located on the first subsection 405, the first subsection 405 and the second subsection 406
  • the material of the 406 is different.
  • the material of the first subsection 405 includes metal
  • the metal includes tungsten
  • the material of the second subsection 406 includes polysilicon.
  • the material of the first subsection includes polysilicon
  • the material of the second subsection includes a metal
  • the metal includes tungsten
  • it further includes: a fifth groove (not shown) located in the active region 201 at the bottom of the word line gate structure, the fifth groove extending from the second surface 400 of the substrate to the first surface 300 extends, and the fifth groove exposes the surface of the gate dielectric layer 208, the first dielectric layer 214 is also located in the fifth groove; a plurality of second doping regions located in the second surface 400 of the active region 201 613 , a plurality of the second doping regions 613 are separated from each other, and the fifth recess is located between adjacent second doping regions 613 .
  • a fifth groove (not shown) located in the active region 201 at the bottom of the word line gate structure, the fifth groove extending from the second surface 400 of the substrate to the first surface 300 extends, and the fifth groove exposes the surface of the gate dielectric layer 208, the first dielectric layer 214 is also located in the fifth groove; a plurality of second doping regions located in the second surface 400 of the active region 201 613 , a plurality of the
  • the active regions 201 of the second surface 400 of the substrate are separated from each other, so that after the bit line structure 215 is formed on the second doped region 613, the resulting capacitance is reduced.

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Abstract

一种半导体结构及其形成方法，结构包括：衬底，包括相对的第一面和第二面，衬底包括若干沿第一方向且平行于第二方向排列的有源区，第一方向与第二方向垂直；位于衬底内的若干自第一面向第二面延伸的第一凹槽，若干第一凹槽沿第二方向排列且沿第一方向贯穿若干有源区；位于第一凹槽内的字线栅极结构，字线栅极结构包括相对的第一侧区和与有源区邻接的第二侧区；位于第一凹槽内与字线栅极结构第一侧区邻接的第一隔离结构，第一隔离结构位于字线栅极结构与有源区之间以及位于部分有源区内；位于衬底第二面上的若干与有源区电连接的电容结构；位于衬底第二面上的若干沿第一方向排列且平行于第二方向的位线结构。所述半导体结构的单位面积较小。

Description

半导体结构及半导体结构的形成方法
本申请要求2021年04月07日提交中国专利局、申请号为2021103733964、发明名称为“半导体结构”，以及要求2021年04月07日提交中国专利局、申请号为2021103745073、发明名称为“半导体结构的形成方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构及半导体结构的形成方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是一种半导体存储器，主要的作用原理是利用电容内存储电荷的多寡来代表一个二进制比特(bit)是1还是0。
动态随机存取存储器(DRAM)的基本存储单元由一个晶体管和一个存储电容组成，而存储阵列由多个存储单元组成。因此，存储器芯片面积的大小就取决于基本存储单元的面积大小。
现有的动态随机存取存储器还有待改善。
发明内容
本发明解决的技术问题是提供一种半导体结构及半导体结构的形成方法，以提升动态随机存取存储器的性能。
为解决上述技术问题，本发明技术方案提供一种半导体结构的形成方法，包括：提供衬底，所述衬底包括相对的第一面和第二面，所述衬底包括若干相互分立的有源区，若干所述有源区沿第一方向排列，且若干所述有源区平行于第二方向，所述第一方向与第二方向相 互垂直；在所述衬底内形成若干第一凹槽，所述第一凹槽自第一面向第二面延伸，若干所述第一凹槽沿第二方向排列，且所述第一凹槽沿第一方向贯穿若干所述有源区；在第一凹槽内形成初始字线栅极结构，所述初始字线栅极结构包括相对的第一侧区和第二侧区，所述第一侧区和第二侧区分别与所述有源区邻接；去除所述第一侧区以及与第一侧区邻接的部分所述有源区，形成字线栅极结构，并在所述字线栅极结构和有源区之间形成第二凹槽；在第二凹槽内形成第一隔离结构；在衬底的第一面上形成若干电容结构，各所述电容结构与各所述有源区电连接；在衬底第二面上形成若干位线结构，若干所述位线结构沿第一方向排列，且若干所述位线结构平行于第二方向。
可选的，所述字线栅极结构包括位于第一凹槽侧壁表面和底部表面的栅介质层以及位于栅介质层表面的栅极层。
可选的，所述第一隔离结构的深度大于或等于所述字线栅极结构的深度。
可选的，所述栅极层的材料包括多晶硅或金属，所述金属包括钨。
可选的，所述栅极层包括位于第一凹槽底部的第一分部和位于第一分部上的第二分部，所述第一分部和第二分部的材料不同。
可选的，所述第一分部的材料包括多晶硅或金属，所述金属包括钨；所述第二分部的材料包括多晶硅或金属，所述金属包括钨。
可选的，相邻有源区之间具有第二隔离结构；在衬底第二面上形成若干位线结构的方法包括：对所述衬底第二面进行减薄，直至暴露出第二隔离结构表面；对减薄后衬底第二面暴露出的有源区进行离子注入，在有源区内形成第二掺杂区；在第二掺杂区上形成若干位线结构，各位线结构分别与沿第二方向排列的一列若干第二掺杂区电连接。
可选的，所述第二掺杂区的深度大于或等于所述字线栅极结构与衬底第二面之间的间距。
可选的，在第二掺杂区上形成若干位线结构之前，还包括：在第二掺杂区上形成位线插塞，所述位线插塞电连接所述位线结构与所述第二掺杂区。
可选的，对减薄后的衬底第二面暴露出的有源区进行离子注入之后，在第二掺杂区上形成若干位线结构之前，还包括：去除部分字线栅极结构底部的有源区，直至暴露出栅介质层表面，在有源区内形成第五凹槽，在衬底第二面有源区内形成若干分立的第二掺杂区。
可选的，所述位线结构的形成方法包括：在衬底第二面暴露出的有源区上和第二隔离结构上形成第一介质层，所述第一介质层内具有若干第三凹槽，所述第三凹槽暴露出有源区表面；在第三凹槽内形成所述位线结构。
可选的，所述位线结构包括位于第三凹槽侧壁表面和底部表面的阻挡层，以及位于阻挡层上的位线层。
可选的，形成电容结构的方法包括：在第一隔离结构上和衬底第一面的有源区上形成第二介质层；在第二介质层内形成第四凹槽，所述第四凹槽暴露出部分有源区表面；在所述第四凹槽内形成电容结构。
可选的，对所述衬底第二面进行减薄的方法包括：提供基底，所述基底表面与第二介质层表面键合；翻转所述基底和衬底，对所述衬底第二面进行减薄。
可选的，对所述衬底第二面进行减薄的工艺包括化学机械抛光工艺。
可选的，形成初始字线栅极结构之后，去除所述第一侧区以及与第一侧区邻接的部分所述有源区之前，还包括：对所述衬底第一面暴露出的有源区进行离子注入，在有源区内形成第一掺杂区；各电容结构分别与一个第一掺杂区电连接。
可选的，所述电容结构在衬底的第一面上的投影至少与部分所述 第一掺杂区重合。
可选的，形成第一隔离结构之后，在衬底第一面暴露出的各所述有源区上形成若干电容结构之前，还包括：在第一掺杂区上形成电容插塞，所述电容插塞电连接所述电容结构和第一掺杂区。
可选的，所述字线栅极结构朝向衬底第一面的顶部表面高于所述第一掺杂区朝向衬底第一面的底部平面。
可选的，去除所述第一侧区以及与第一侧区邻接的部分所述有源区的工艺包括干法刻蚀工艺。
可选的，各所述电容结构位于与所述第二侧区邻接的有源区上。
为解决上述技术问题，本发明技术方案还提供一种半导体结构，包括：衬底，所述衬底包括相对的第一面和第二面，所述衬底包括若干相互分立的有源区，若干所述有源区沿第一方向排列，且若干所述有源区平行于第二方向，所述第一方向与第二方向相互垂直；位于所述衬底内的若干第一凹槽，所述第一凹槽自第一面向第二面延伸，若干所述第一凹槽沿第二方向排列，且所述第一凹槽沿第一方向贯穿若干所述有源区；位于第一凹槽内的字线栅极结构，所述字线栅极结构包括相对的第一侧区和第二侧区，所述第二侧区与所述有源区邻接；位于第一凹槽内的第一隔离结构，所述第一隔离结构与字线栅极结构第一侧区邻接，所述第一隔离结构位于字线栅极结构与有源区之间，所述第一隔离结构还位于部分有源区内；位于衬底第二面上的若干电容结构，所述电容结构与所述有源区电连接；位于衬底第二面上的若干位线结构，若干所述位线结构沿第一方向排列，且若干所述位线结构平行于第二方向。
可选的，所述字线栅极结构包括位于第一凹槽侧壁表面和底部表面的栅介质层以及位于栅介质层表面的栅极层。
可选的，所述第一隔离结构的深度大于或等于所述字线栅极结构的深度。
可选的，所述栅极层的材料包括多晶硅或金属，所述金属包括钨。
可选的，所述栅极层包括位于第一凹槽底部的第一分部和位于第一分部上的第二分部，所述第一分部和第二分部的材料不同。
可选的，所述第一分部的材料包括多晶硅或金属，所述金属包括钨；所述第二分部的材料包括多晶硅或金属，所述金属包括钨。
可选的，所述衬底第二面的有源区还暴露出栅介质层底部表面。
可选的，还包括：位于衬底第一面暴露出的有源区内的第一掺杂区；各电容结构分别与一个第一掺杂区电连接。
可选的，所述电容结构在衬底的第一面上的投影至少与部分所述第一掺杂区重合。
可选的，还包括：位于电容结构和第一掺杂区之间的电容插塞，所述电容插塞电连接所述电容结构和第一掺杂区。
可选的，所述字线栅极结构朝向衬底第一面的顶部表面高于所述第一掺杂区朝向衬底第一面的底部表面。
可选的，还包括：位于衬底第二面暴露出的有源区内的第二掺杂区；各位线结构分别与沿第二方向排列的一列若干第二掺杂区电连接。
可选的，所述第二掺杂区的深度大于或等于所述字线栅极结构与衬底第二面之间的间距。
可选的，还包括：位于位线结构与所述第二掺杂区之间的位线插塞，所述位线插塞电连接所述位线结构与所述第二掺杂区。
可选的，相邻有源区之间具有第二隔离结构；所述衬底第二面暴露出所述第二隔离结构。
可选的，还包括：位于衬底第二面上和第二隔离结构上的第一介质层，所述第一介质层内具有第三凹槽，所述第三凹槽暴露出有源区 表面；所述位线结构位于所述第三凹槽内。
可选的，所述位线结构包括位于第三凹槽侧壁表面和底部表面的阻挡层，以及位于阻挡层上的位线层。
可选的，所述第二隔离结构的材料包括介电材料，所述介电材料包括氧化硅。
可选的，所述第一隔离结构的材料包括介电材料，所述介电材料包括氧化硅。
可选的，还包括：位于第一隔离结构上和有源区第一面上的第二介质层；所述电容结构位于第二介质层内。
可选的，各所述电容结构位于与所述第二侧区邻接的有源区上。
与现有技术相比，本发明的技术方案具有以下有益效果：
本发明的半导体结构，一方面，所述位线结构位于衬底第二面，电容结构位于衬底第一面，从而大大简化了制造工艺的难度和成本；另一方面，所述字线栅极结构位于衬底内，所述字线栅极结构控制的沟道垂直于衬底表面，从而能够节省衬底水平方向上的面积，能够提高存储阵列单元的密度；再一方面，所述字线栅极结构与有源区之间具有第一隔离结构，所述字线栅极结构的第二侧区与有源区邻接，所述字线栅极结构第一侧区与第一隔离结构邻接，从而所述第一隔离结构能够隔离所述字线栅极结构第一侧区和有源区，避免所述字线栅极结构同时与相邻两侧的有源区都接触产生两个沟道形成寄生器件，使得晶体管不易关断的情况。从而能够减少漏电流，提升半导体结构的性能。
进一步，所述第一掺杂区和第二掺杂区分别位于衬底的两面，从而节省了衬底水平方向上的面积，从而能够增加存储阵列单元的密度。
进一步，所述栅极层包括第一分部和位于第一分部上的第二分 部，所述第一分部的材料包括多晶硅或金属，所述金属包括钨；所述第二分部的材料包括多晶硅或金属，所述金属包括钨。所述栅极层的材料不是纯粹的多晶硅或金属，从而所述栅极层的电阻改善的性能和漏电流改善的性能得到均衡。
进一步，还包括：位于电容结构和第一掺杂区之间的电容插塞，所述电容结构与所述第一掺杂区通过电容插塞电连接，从而形成电容结构和电容插塞的工艺窗口能够增大。
进一步，所述衬底第二面的有源区还暴露出栅介质层底部表面。所述衬底第二面的有源区是相互分立的，从而在衬底第二面的有源区上形成位线结构之后，产生的电容减小。
附图说明
图1是一实施例中半导体结构的结构示意图；
图2至图24是本发明一实施例中半导体结构形成过程的结构示意图；
图25至图27是本发明另一实施例中半导体结构形成过程的结构示意图；
图28和图29是本发明另一实施例中半导体结构形成过程的结构示意图；
图30和图31是本发明另一实施例中半导体结构形成过程的结构示意图。
具体实施方式
如背景技术所述，现有的动态随机存取存储器还有待改善。现结合具体的实施例进行分析说明。
图1是一实施例中半导体结构的结构示意图。
请参考图1，包括：衬底100；位于衬底100内的字线栅极结构 101；位于字线栅极结构101两侧衬底100内的源掺杂区103和漏掺杂区102；通过源插塞104与源掺杂区103电连接的位线结构105；通过电容插塞106与漏掺杂区102电连接的电容结构107。
所述半导体结构的形成过程为：先形成源掺杂区103和漏掺杂区102，再在衬底100内形成字线栅极结构101，然后形成源插塞104和位线结构105，再形成电容插塞106，最后形成电容结构107。所述半导体结构的沟道为U型，源掺杂区103和漏掺杂区102在字线栅极结构101的水平两侧。位线结构105和电容结构107在晶体管的同侧，在加工工艺上都位于衬底的上方。电容结构107的电容插塞106需要穿过位线结构105，使得整体的工艺复杂度较高，对于光刻工艺和对准度有极高的要求。
为了解决上述问题，本发明技术方案形成一种新的半导体结构，一方面，所述电容结构位于衬底第一面，位线结构位于衬底第二面，从而大大简化了制造工艺的难度和成本；另一方面，所述字线栅极结构位于衬底内，从而能够节省垂直衬底表面方向上的空间，能够提高存储阵列单元的密度；再一方面，所述字线栅极结构与有源区之间具有第一隔离结构，所述字线栅极结构的第二侧区与有源区邻接，所述字线栅极结构第一侧区与第一隔离结构邻接，从而所述第一隔离结构能够隔离所述字线栅极结构第一侧区和有源区，避免所述字线栅极结构同时与相邻两侧的有源区都接触产生两个沟道形成寄生器件，使得晶体管不易关断的情况。从而能够减少漏电流，提升半导体结构的性能。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图2至图24是本发明实施例中半导体结构形成过程的结构示意图。
请参考图2和图3，图3为图2衬底第一面300的俯视图，图2为图3沿剖面线AA1方向的剖面结构示意图，提供衬底200，所述 衬底包括相对的第一面300和第二面400，所述衬底200包括若干相互分立的有源区201，若干所述有源区201沿第一方向X排列，且若干所述有源区201平行于第二方向Y，所述第一方向X与第二方向Y相互垂直。
在本实施例中，所述衬底200的材料为硅。
在其他实施例中，所述衬底的材料包括碳化硅、硅锗、Ⅲ-Ⅴ族元素构成的多元半导体材料、绝缘体上硅(SOI)或者绝缘体上锗(GOI)。其中，Ⅲ-Ⅴ族元素构成的多元半导体材料包括InP、GaAs、GaP、InAs、InSb、InGaAs或者InGaAsP。
在本实施例中，相邻有源区201之间具有第二隔离结构202。
所述第二隔离结构202的材料包括介电材料，所述介电材料包括氧化硅、氮化硅、碳化硅、碳氧化硅、氮氧化硅、氧化铝、氮化铝、氮碳化硅和氮碳氧化硅中的一种或多种的组合。
在本实施例中，所述第二隔离结构202的材料包括氧化硅。
请参考图4、图5和图6，图6为图5和图4衬底第一面300的俯视图，图4为图6沿剖面线BB1方向的剖面结构示意图，图5为图6沿剖面线CC1方向的剖面结构示意图，在所述衬底200内形成若干第一凹槽203，所述第一凹槽203自第一面300向第二面400延伸，若干所述第一凹槽203沿第二方向Y排列，且所述第一凹槽203沿第一方向X贯穿若干所述有源区201。
所述第一凹槽203的形成方法包括：在衬底第一面300上形成图形化的掩膜层(未图示)，所述图形化的掩膜层暴露出部分所述有源区201表面；以所述图形化的掩膜层为掩膜刻蚀所述有源区201，在衬底内形成所述第一凹槽203。
在本实施例中，所述第一凹槽203朝向衬底第二面400的底部平面高于所述第二隔离结构202朝向衬底第二面400的底部平面。为后续在衬底第二面400形成第二掺杂区留有物理空间。
请参考图7和图8，图8为图7衬底第一面300的俯视图，图7为图8沿剖面线DD1方向的剖面结构示意图，在第一凹槽203内形成初始字线栅极结构，所述初始字线栅极结构包括相对的第一侧区(未标示)和第二侧区(未标示)，所述第一侧区和第二侧区分别与所述有源区201邻接。
所述初始字线栅极结构包括位于第一凹槽203侧壁表面和底部表面的初始栅介质层204以及位于初始栅介质层204表面的初始栅极层205。
所述初始字线栅极结构朝向衬底第一面300的顶部表面低于所述衬底第一面300表面，为后续在有源区201第一面300形成第一掺杂区提供物理空间。
所述初始字线栅极结构的形成方法包括：在第一凹槽203侧壁表面和底部表面、衬底第一面300有源区201表面形成栅介质材料层(未图示)；在栅介质材料层上形成栅极材料层(未图示)；平坦化所述栅极材料层和栅介质材料层，直至暴露出有源区201表面，形成过渡初始字线栅极结构；回刻蚀所述过渡初始字线栅极结构，直至暴露出部分所述第一凹槽203侧壁，形成所述初始字线栅极结构。
在本实施例中，所述初始栅介质层204的材料包括氧化硅或低K(K小于3.9)材料；所述初始栅极层205的材料包括多晶硅。
在另一实施例中，所述初始栅介质层的材料包括高介电常数材料，所述高介电常数材料的介电常数大于3.9，所述高介电常数的材料包括氧化铝或氧化铪；所述初始栅极层的材料包括金属，所述金属包括钨。
在另一实施例中，所述初始字线栅极结构还包括初始功函数层，所述初始功函数层位于所述初始栅介质层和初始栅极层之间。所述初始功函数层的材料包括N型功函数材料或P型功函数材料，所述N型功函数材料包括钛铝，所述P型功函数材料包括氮化钛或氮化钽。
在其他实施例中，所述初始栅极层包括位于第一凹槽底部的第一分部和位于第一分部上的第二分部，所述第一分部和第二分部的材料不同。
请参考图9和图10，图10为图9衬底第一面300的俯视图，图9为图10沿剖面线EE1方向的剖面结构示意图，形成初始字线栅极结构之后，对所述衬底200第一面300暴露出的有源区201表面进行离子注入，在有源区201内形成第一掺杂区206。
所述初始字线栅极结构朝向衬底第一面300的顶部表面高于所述第一掺杂区206朝向衬底第一面300的底部平面。一方面，能够保证所述第一掺杂区206能够与初始栅介质层204接触，以保证第一掺杂区206与沟道以及后续形成的第二掺杂区导通；另一方面，所述初始字线栅极结构朝向衬底第一面300的顶部表面第一衬底200第一面300表面，从而也减少后续字线栅极结构在有源区201内形成的沟道不会与第一掺杂区206过度重合，避免第一掺杂区206的性能受到影响。
所述第一掺杂区206内具有掺杂离子，所述掺杂离子的类型为N型或P型；所述N型离子包括磷离子、砷离子或锑离子；所述P型离子包括硼离子、硼氟离子或铟离子。
请参考图11，图11为在图9基础上的结构示意图，去除所述第一侧区以及与第一侧区邻接的部分所述有源区201，形成字线栅极结构，并在所述字线栅极结构和有源区201之间形成第二凹槽207。
所述字线栅极结构包括位于第一凹槽203部分侧壁表面和底部表面的栅介质层208以及位于栅介质层208表面的栅极层209。所述字线栅极结构位于衬底内，所述字线栅极结构控制的沟道垂直于衬底表面，从而能够节省衬底水平方向上的面积，能够提高存储阵列单元的密度。
去除所述第一侧区以及与第一侧区邻接的部分所述有源区201， 从而使得所述字线栅极结构只有第二侧与有源区201都接触，从而工作时产生一个沟道，使得所述晶体管满足性能要求，开启和关断容易控制，从而能够减少漏电流。
在本实施例中，所述第二凹槽207的深度大于或等于所述字线栅极结构的深度。从而能够确保后续在第二凹槽207内形成的第一隔离结构的隔离作用使得字线栅极结构第一侧区的沟道能够完全关断，能够减少漏电流。
在本实施例中，去除所述第一侧区以及与第一侧区邻接的部分所述有源区201的工艺包括干法刻蚀工艺。所述干法刻蚀工艺容易控制形成的第二凹槽207的深度和尺寸精度。
请参考图12和图13，图13为图12的俯视图，图12为图13沿剖面线FF1方向的剖面结构示意图，在第二凹槽207内形成第一隔离结构210。
所述第一隔离结构210还位于字线栅极结构顶部表面。
所述第一隔离结构210位于字线栅极结构与有源区201之间，所述字线栅极结构的第二侧区与有源区201邻接，从而所述第一隔离结构210能够隔离所述字线栅极结构第一侧区和有源区201，避免所述字线栅极结构同时与相邻两侧的有源区201都接触产生两个沟道形成寄生器件，使得晶体管不易关断的情况，从而能够减少漏电流。
所述第一隔离结构210的形成方法包括：在第二凹槽207内、字线栅极结构顶部以及有源区201表面形成隔离材料层(未图示)；平坦化所述隔离材料层，直至暴露出有源区201表面，形成所述第一隔离结构210。
所述第一隔离结构210的材料包括介电材料，所述介电材料包括氧化硅、氮化硅、碳化硅、碳氧化硅、氮氧化硅、氧化铝、氮化铝、氮碳化硅和氮碳氧化硅中的一种或多种的组合。
在本实施例中，所述第一隔离结构210的材料包括氧化硅。
在本实施例中，所述第一隔离结构210的深度大于或等于所述字线栅极结构的深度。从而所述第一隔离结构210的隔离作用使得字线栅极结构第一侧区的沟道能够完全关断，能够减少漏电流。
请参考图14和图15，图15为图14衬底第一面300的俯视图，图14为图15沿剖面线GG1方向的剖面结构示意图，在衬底第一面300的各所述有源区201上形成若干电容结构212，各电容结构212分别与一个第一掺杂区206电连接。
各所述电容结构212位于与所述第二侧区邻接的有源区201上，所述电容结构212在有源区201的第一面上的投影至少与部分所述第一掺杂区206重合。
在本实施例中，还包括：在第一掺杂区206上形成电容插塞211，所述电容插塞211电连接所述电容结构212和第一掺杂区206。
所述电容插塞211和电容结构212的形成方法包括：在第一隔离结构210上和衬底第一面300的有源区201上形成第二介质层(未图示)；在第二介质层内形成第四凹槽(未图示)；在第四凹槽内形成开口(未图示)，所述开口暴露出部分第一掺杂区206表面；在开口内形成电容插塞211，在第四凹槽内形成电容结构212。
形成电容插塞211和电容结构212的方法，在第二介质层内形成第四凹槽，在第四凹槽内形成开口，在开口内形成电容插塞，再在第四凹槽内形成电容结构。所述工艺窗口较大，工艺较简单，能够提升生产效率。
所述电容结构212包括：第一电极层(未图示)、第二电极层(未图示)和位于第一电极层与第二电极层之间的介电层(未图示)。
所述介电层的形状包括：平面型或“U”型。
当所述介电层的形状为平面型时，所述第一电极层的表面平整，所述第二电极层的表面平整。
当所述介电层的形状为“U”型时，所述第一电极层的表面为不平整的表面，所述第二电极层的表面为不平整的表面。
所述第一电极层的材料包括：金属或金属氮化物；所述第二电极层的材料包括：金属或金属氮化物；所述金属包括：铜、铝、钨、钴、镍和钽中的一种或多种的组合；所述金属氮化物包括氮化钽和氮化钛中的一种或多种的组合。
所述电容插塞211的材料包括：金属或金属氮化物；所述金属包括：铜、铝、钨、钴、镍和钽中的一种或多种的组合；所述金属氮化物包括氮化钽和氮化钛中的一种或多种的组合。
在另一实施例中，能够不形成所述电容插塞，所述电容结构与第一掺杂区直接接触电连接。
所述电容结构的形成方法包括：在第一隔离结构上和衬底第一面的有源区上形成第二介质层；在第二介质层内形成第四凹槽，所述第四凹槽暴露出部分第一掺杂区表面；在所述第四凹槽内形成电容结构。
接下来，在衬底第二面400上形成若干位线结构215，若干所述位线结构215沿第一方向X排列，且若干所述位线结构215平行于第二方向Y。所述位线结构215的形成过程请参考图16至图24。
请参考图16、图17和图18，图18为图16和图17衬底第二面400的俯视图，图16为图18沿剖面线HH1方向的剖面结构示意图，图17为图18沿剖面线JJ1方向的剖面结构示意图，对所述衬底第二面400进行减薄，直至暴露出第二隔离结构202表面。
对所述衬底第二面400进行减薄的方法包括：提供基底(未图示)，所述基底表面与第二介质层表面键合；翻转所述基底和衬底，对所述衬底第二面400进行减薄。
对所述衬底第二面400进行减薄的工艺包括化学机械抛光工艺。
请参考图19、图20和图21，图21为图19和图20衬底第二面400的俯视图，图19为图21沿剖面线KK1方向的剖面结构示意图，图20为图21沿剖面线LL1方向的剖面结构示意图，对减薄后的衬底第二面400的有源区201进行离子注入，在有源区201内形成第二掺杂区213。
所述第一掺杂区206和第二掺杂区213分别位于衬底200的两面，从而节省了衬底200水平方向上的面积，从而能够增加存储阵列单元的密度。
所述第二掺杂区213的深度大于或等于所述字线栅极结构与衬底200第二面400之间的间距，从而能够保证所述第二掺杂区213能够与栅介质层208接触，以保证第二掺杂区213与沟道以及第一掺杂区206导通。
所述第二掺杂区213内具有掺杂离子，所述掺杂离子的类型为N型或P型；所述N型离子包括磷离子、砷离子或锑离子；所述P型离子包括硼离子、硼氟离子或铟离子。
在本实施例中，所述第二掺杂区213内的掺杂离子导电类型与第一掺杂区206内掺杂离子的导电类型相同。请参考图22、图23和图24，图24为图22和图23衬底第二面400的俯视图，图22为图24沿剖面线MM1方向的剖面结构示意图，图23为图24沿剖面线NN1方向的剖面结构示意图，在第二掺杂区213上形成若干位线结构215，各位线结构分别与沿第二方向Y排列的一列第二掺杂区213电连接。
所述位线结构215的形成方法包括：在衬底第二面400有源区201上和第二隔离结构202上形成第一介质层214，所述第一介质层214内具有若干第三凹槽(未图示)，所述第三凹槽暴露出第二掺杂区213表面；在第三凹槽内形成所述位线结构215。
所述位线结构215包括位于第三凹槽侧壁表面和底部表面的阻挡层(未图示)，以及位于阻挡层上的位线层(未图示)。
所述阻挡层的材料包括金属氮化物；所述位线层的材料包括金属或金属氮化物；所述金属包括：铜、铝、钨、钴、镍和钽中的一种或多种的组合；所述金属氮化物包括氮化钽和氮化钛中的一种或多种的组合。
在另一实施例中，还包括：在第二掺杂区上形成位线插塞，所述位线插塞电连接所述位线结构与所述第二掺杂区。
至此，形成的半导体结构，一方面，所述电容结构212形成于衬底第一面300，位线结构215形成于衬底第二面400，从而大大简化了制造工艺的难度和成本；另一方面，所述字线栅极结构位于衬底内，所述字线栅极结构控制的沟道垂直于衬底表面，从而能够节省衬底水平方向上的面积，能够提高存储阵列单元的密度；再一方面，所述字线栅极结构与有源区201之间具有第一隔离结构210，所述字线栅极结构的第二侧区与有源区201邻接，从而所述第一隔离结构210能够隔离所述字线栅极结构第一侧区和有源区201，避免所述字线栅极结构同时与相邻两侧的有源区201都接触产生两个沟道形成寄生器件，使得晶体管不易关断的情况。从而能够减少漏电流，提升半导体结构的性能。
相应地，本发明实施例还提供一种半导体结构，请继续参考图22、图23和图24，包括：
衬底200，所述衬底200包括相对的第一面300和第二面400，所述衬底200包括若干相互分立的有源区201，若干所述有源区201沿第一方向X排列，且若干所述有源区201平行于第二方向Y，所述第一方向X与第二方向Y相互垂直；
位于所述衬底200内的若干第一凹槽，所述第一凹槽自第一面300向第二面400延伸，若干所述第一凹槽沿第二方向Y排列，且所述第一凹槽沿第一方向X贯穿若干所述有源区201；
位于第一凹槽内的字线栅极结构，所述字线栅极结构包括相对的 第一侧区和第二侧区，所述第二侧区与所述有源区201邻接；
位于第一凹槽内的第一隔离结构210，所述第一隔离结构210与字线栅极结构第一侧区邻接，所述第一隔离结构210位于字线栅极结构与有源区201之间，所述第一隔离结构210还位于部分有源区201内；
位于衬底200第二面400上的若干电容结构212，所述电容结构212与所述有源区201电连接；
位于衬底200第二面400上的若干位线结构215，若干所述位线结构215沿第一方向X排列，且若干所述位线结构215平行于第二方向Y。
在本实施例中，所述字线栅极结构包括位于第一凹槽侧壁表面和底部表面的栅介质层208以及位于栅介质层208表面的栅极层209。
在本实施例中，所述第一隔离结构210的深度大于或等于所述字线栅极结构的深度。
在本实施例中，所述栅极层209的材料包括多晶硅或金属，所述金属包括钨。
在本实施例中，还包括：位于衬底200第一面300暴露出的有源区201内的第一掺杂区206；各电容结构212分别与一个第一掺杂区206电连接。
在本实施例中，所述电容结构212在衬底200第一面300上的投影至少与部分所述第一掺杂区206重合。
在本实施例中，还包括：位于电容结构212和第一掺杂区206之间的电容插塞211，所述电容插塞211电连接所述电容结构212和第一掺杂区206。
在本实施例中，所述字线栅极结构朝向衬底200第一面300的顶部表面高于所述第一掺杂区206朝向衬底200第一面300的底部表 面。
在本实施例中，还包括：位于衬底200第二面400暴露出的有源区201内的第二掺杂区213；各位线结构215分别与沿第二方向Y排列的一列若干第二掺杂区213电连接。
在本实施例中，所述第二掺杂区213的深度大于或等于所述字线栅极结构与衬底200第二面400之间的间距。
在其他实施例中，还包括：位于位线结构与所述第二掺杂区之间的位线插塞，所述位线插塞电连接所述位线结构与所述第二掺杂区。
在本实施例中，相邻有源区之间具有第二隔离结构202；所述衬底第二面400暴露出所述第二隔离结构202。
在本实施例中，还包括：位于衬底200第二面400上和第二隔离结构202上的第一介质层214，所述第一介质层214内具有第三凹槽，所述第三凹槽暴露出有源区201表面；所述位线结构215位于所述第三凹槽内。
在本实施例中，所述位线结构215包括位于第三凹槽侧壁表面和底部表面的阻挡层，以及位于阻挡层上的位线层。
在本实施例中，所述第二隔离结构202的材料包括介电材料，所述介电材料包括氧化硅。
在本实施例中，所述第一隔离结构210的材料包括介电材料，所述介电材料包括氧化硅。
在本实施例中，还包括：位于第一隔离结构210上和衬底第一面300上的第二介质层；所述电容结构位于第二介质层内。
在本实施例中，各所述电容结构212位于与所述第二侧区邻接的有源区201上。
图25至图27是本发明另一实施例中半导体结构形成过程的结构 示意图。
请参考图25和图26，图25为在图19基础上的结构示意图，图26为在图21基础上的结构示意图，图26为图25衬底第二面400的俯视图，图25为图26沿剖面线OO1方向的剖面结构示意图，去除部分字线栅极结构底部的有源区201，直至暴露出栅介质层208表面，在有源区201内形成第五凹槽301，在衬底200第二面400有源区201内形成若干分立的第二掺杂区313。
请参考图27，图27为在图25基础上的结构示意图，在第五凹槽301内、衬底第二面400有源区201上和第二隔离结构202上形成第一介质层314，所述第一介质层314内具有若干第三凹槽(未图示)，所述第三凹槽暴露出第二掺杂区313表面；在第三凹槽内形成位线结构315。
所述衬底第二面400的有源区201是相互分立的，从而在第二掺杂区313上形成位线结构315之后，产生的电容减小。
相应地，本发明实施例还提供一种半导体结构，请继续参考图27，图27的结构与图22结构的区别在于：所述衬底第二面400的有源区暴露出所述栅介质层208表面。
在本实施例中，还包括：位于字线栅极结构底部的有源区201内的第五凹槽(未图示)，所述第五凹槽从衬底第二面400向第一面300延伸，且所述第五凹槽暴露出栅介质层208表面，所述第一介质层314还位于第五凹槽内；位于有源区201第二面400内的若干第二掺杂区313，若干所述第二掺杂区313相互分立，且所述第五凹槽位于相邻第二掺杂区313之间。
所述衬底第二面400的有源区201是相互分立的，从而在第二掺杂区313上形成位线结构215之后，产生的电容减小。
图28和图29是本发明另一实施例中半导体结构形成过程的结构示意图。
请参考图28，图28为在图4基础上的结构示意图，在第一凹槽203内形成初始字线栅极结构，所述初始字线栅极结构包括相对的第一侧区(未标示)和第二侧区(未标示)，所述第一侧区和第二侧区分别与所述有源区201邻接。
所述初始字线栅极结构包括位于第一凹槽203侧壁表面和底部表面的初始栅介质层404以及位于初始栅介质层404表面的初始栅极层。
在本实施例中，所述初始栅极层包括位于第一凹槽203底部的第一分部405和位于第一分部405上的第二分部406，所述第一分部405和第二分部406的材料不同。
所述第一分部405的材料包括金属或多晶硅，所述金属包括钨；所述第二分部406的材料包括金属或多晶硅，所述金属包括钨。
所述栅极层的材料不是纯粹的多晶硅或金属，从而所述栅极层的电阻改善的性能和漏电流改善的性能得到均衡，避免了栅极层的材料是多晶硅时使得栅极层的电阻较大的情况，也避免了栅极层的材料是金属时容易发生漏电的情况，从而提升了半导体结构的性能。
在本实施例中，所述第一分部405的材料包括多晶硅；所述第二分部406的材料包括钨。
在另一实施例中，所述第一分部的材料包括钨；所述第二分部的材料包括多晶硅。
所述初始字线栅极结构的形成方法包括：在第一凹槽203侧壁表面和底部表面以及衬底第一面300的有源区201顶部表面形成初始栅介质材料层(未图示)；在初始栅介质层上形成初始第一分部(未图示)；回刻蚀所述初始第一分部，直至所述初始第一分部顶部表面低于所述衬底第一面300的有源区201顶部表面且暴露出第一凹槽201侧壁的部分初始栅介质材料层，形成第一分部405；在第一分部405上形成初始第二分部(未图示)；平坦化所述初始第二分部和衬底第 一面300的有源区201顶部的初始栅介质材料层，直至暴露出衬底第一面300的有源区201顶部表面，形成初始栅介质层404和过渡第二分部(未图示)；回刻蚀所述过渡第二分部，形成所述第二分部406。
请参考图29，形成初始字线栅极结构之后，对所述衬底200第一面300的有源区201进行离子注入，在有源区201内形成第一掺杂区206；去除所述第一侧区以及与第一侧区邻接的部分所述有源区201，形成字线栅极结构，并在所述字线栅极结构和有源区201之间形成第二凹槽；在第二凹槽内形成第一隔离结构410；在衬底200第一面300的各所述有源区201上形成若干电容结构212，各电容结构212分别与一个第一掺杂区206电连接；对衬底200第二面400的有源区201进行离子注入，在有源区201内形成第二掺杂区213；在第二掺杂区213上形成若干位线结构215，各位线结构215分别与沿第二方向Y排列的一列第二掺杂区213电连接。
所述第一掺杂区206、第一隔离结构210、电容结构212、第二掺杂区213和位线结构215的形成过程请参考图9至图24，在此不再赘述。
相应地，本发明实施例还提供一种半导体结构，请继续参考图29，图29与图22的区别在于：所述栅极层包括位于第一凹槽底部的第一分部405和位于第一分部405上的第二分部406，所述第一分部405和第二分部406的材料不同。
在本实施例中，所述第一分部405的材料包括金属，所述金属包括钨，所述第二分部406的材料包括多晶硅。
在其他实施例中，所述第一分部的材料包括多晶硅，所述第二分部的材料包括金属，所述金属包括钨。
图30和图31是本发明另一实施例中半导体结构形成过程的结构示意图。
请参考图30，图30为在图28基础上的结构示意图，形成初始 字线栅极结构之后，对所述衬底200第一面300的有源区201进行离子注入，在有源区201内形成第一掺杂区206；去除所述第一侧区以及与第一侧区邻接的部分所述有源区201，形成字线栅极结构，并在所述字线栅极结构和有源区201之间形成第二凹槽；在第二凹槽内形成第一隔离结构410；在衬底200第一面300的各所述有源区201上形成若干电容结构212，各电容结构212分别与一个第一掺杂区206电连接；对衬底200第二面400的有源区201进行离子注入，在有源区201内形成第二掺杂区613。
所述第一掺杂区206、第一隔离结构210、电容结构212和第二掺杂区613的形成过程请参考图9至图21，在此不再赘述。
请继续参考图30，去除部分字线栅极结构底部的有源区201，直至暴露出栅介质层404表面，在有源区201内形成第五凹槽601，在衬底200第二面400有源区201内形成若干分立的第二掺杂区613。
请参考图31，在第五凹槽601内、衬底第二面400有源区201上和第二隔离结构202上形成第一介质层214，所述第一介质层214内具有若干第三凹槽(未图示)，所述第三凹槽暴露出第二掺杂区613表面；在第三凹槽内形成位线结构215。
所述衬底第二面400的有源区201是相互分立的，从而在第二掺杂区613上形成位线结构215之后，产生的电容减小。
相应地，本发明实施例还提供一种半导体结构，请继续参考图31，图31的结构与图22结构的区别在于：所述衬底第二面400的有源区201暴露出所述栅介质层208表面；所述栅极层包括位于第一凹槽底部的第一分部405和位于第一分部405上的第二分部406，所述第一分部405和第二分部406的材料不同。
在本实施例中，所述第一分部405的材料包括金属，所述金属包括钨，所述第二分部406的材料包括多晶硅。
在其他实施例中，所述第一分部的材料包括多晶硅，所述第二分 部的材料包括金属，所述金属包括钨。
在本实施例中，还包括：位于字线栅极结构底部的有源区201内的第五凹槽(未图示)，所述第五凹槽从衬底第二面400向第一面300延伸，且所述第五凹槽暴露出栅介质层208表面，所述第一介质层214还位于第五凹槽内；位于有源区201第二面400内的若干第二掺杂区613，若干所述第二掺杂区613相互分立，且所述第五凹槽位于相邻第二掺杂区613之间。
所述衬底第二面400的有源区201是相互分立的，从而在第二掺杂区613上形成位线结构215之后，产生的电容减小。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (42)

  1. 一种半导体结构的形成方法，其特征在于，包括：
    提供衬底，所述衬底包括相对的第一面和第二面，所述衬底包括若干相互分立的有源区，若干所述有源区沿第一方向排列，且若干所述有源区平行于第二方向，所述第一方向与第二方向相互垂直；
    在所述衬底内形成若干第一凹槽，所述第一凹槽自第一面向第二面延伸，若干所述第一凹槽沿第二方向排列，且所述第一凹槽沿第一方向贯穿若干所述有源区；
    在第一凹槽内形成初始字线栅极结构，所述初始字线栅极结构包括相对的第一侧区和第二侧区，所述第一侧区和第二侧区分别与所述有源区邻接；
    去除所述第一侧区以及与第一侧区邻接的部分所述有源区，形成字线栅极结构，并在所述字线栅极结构和有源区之间形成第二凹槽；
    在第二凹槽内形成第一隔离结构；
    在衬底第一面上形成若干电容结构，各所述电容结构与各所述有源区电连接；
    在衬底第二面上形成若干位线结构，若干所述位线结构沿第一方向排列，且若干所述位线结构平行于第二方向。
  2. 如权利要求1所述半导体结构的形成方法，其特征在于，所述字线栅极结构包括位于第一凹槽侧壁表面和底部表面的栅介质层以及位于栅介质层表面的栅极层。
  3. 如权利要求2所述半导体结构的形成方法，其特征在于，所述第一隔离结构的深度大于或等于所述字线栅极结构的深度。
  4. 如权利要求3所述半导体结构的形成方法，其特征在于，所述栅极层的材料包括多晶硅或金属，所述金属包括钨。
  5. 如权利要求3所述半导体结构的形成方法，其特征在于，所述栅极层包括位于第一凹槽底部的第一分部和位于第一分部上的第二分部，所述第一分部和第二分部的材料不同。
  6. 如权利要求5所述半导体结构的形成方法，其特征在于，所述第一分部的材料包括多晶硅或金属，所述金属包括钨；所述第二分部的材料包括多晶硅或金属，所述金属包括钨。
  7. 如权利要求2所述半导体结构的形成方法，其特征在于，相邻有源区之间具有第二隔离结构；在衬底第二面上形成若干位线结构的方法包括：对所述衬底第二面进行减薄，直至暴露出第二隔离结构表面；对减薄后的衬底第二面暴露出的有源区进行离子注入，在有源区内形成第二掺杂区；在第二掺杂区上形成若干位线结构，各位线结构分别与沿第二方向排列的一列若干第二掺杂区电连接。
  8. 如权利要求7所述半导体结构的形成方法，其特征在于，所述第二掺杂区的深度大于或等于所述字线栅极结构与衬底第二面之间的间距。
  9. 如权利要求7所述半导体结构的形成方法，其特征在于，在第二掺杂区上形成若干位线结构之前，还包括：在第二掺杂区上形成位线插塞，所述位线插塞电连接所述位线结构与所述第二掺杂区。
  10. 如权利要求7所述半导体结构的形成方法，其特征在于，对减薄后的衬底第二面暴露出的有源区进行离子注入之后，在第二掺杂区上形成若干位线结构之前，还包括：去除部分字线栅极结构底部的有源区，直至暴露出栅介质层表面，在有源区内形成第五凹槽，在衬底第二面有源区内形成若干分立的第二掺杂区。
  11. 如权利要求7所述半导体结构的形成方法，其特征在于，所述位线结构的形成方法包括：在衬底第二面暴露出的有源区上和第二隔离结构上形成第一介质层，所述第一介质层内具有若干第三凹 槽，所述第三凹槽暴露出有源区表面；在第三凹槽内形成所述位线结构。
  12. 如权利要求11所述半导体结构的形成方法，其特征在于，所述位线结构包括位于第三凹槽侧壁表面和底部表面的阻挡层，以及位于阻挡层上的位线层。
  13. 如权利要求7所述半导体结构的形成方法，其特征在于，形成电容结构的方法包括：在第一隔离结构上和衬底第一面的有源区上形成第二介质层；在第二介质层内形成第四凹槽，所述第四凹槽暴露出部分有源区表面；在所述第四凹槽内形成电容结构。
  14. 如权利要求13所述半导体结构的形成方法，其特征在于，对所述衬底第二面进行减薄的方法包括：提供基底，所述基底表面与第二介质层表面键合；翻转所述基底和衬底，对所述衬底第二面进行减薄。
  15. 如权利要求7所述半导体结构的形成方法，其特征在于，对所述衬底第二面进行减薄的工艺包括化学机械抛光工艺。
  16. 如权利要求1所述半导体结构的形成方法，其特征在于，形成初始字线栅极结构之后，去除所述第一侧区以及与第一侧区邻接的部分所述有源区之前，还包括：对所述衬底第一面暴露出的有源区进行离子注入，在有源区内形成第一掺杂区；各电容结构分别与一个第一掺杂区电连接。
  17. 如权利要求16所述半导体结构的形成方法，其特征在于，所述电容结构在衬底第一面上的投影至少与部分所述第一掺杂区重合。
  18. 如权利要求16所述半导体结构的形成方法，其特征在于，形成第一隔离结构之后，在衬底第一面暴露出的各所述有源区上形成若干电容结构之前，还包括：在第一掺杂区上形成电容插塞，所述电容插塞电连接所述电容结构和第一掺杂区。
  19. 如权利要求16所述半导体结构的形成方法，其特征在于，所述字 线栅极结构朝向衬底第一面的顶部表面高于所述第一掺杂区朝向衬底第一面的底部平面。
  20. 如权利要求1所述半导体结构的形成方法，其特征在于，去除所述第一侧区以及与第一侧区邻接的部分所述有源区的工艺包括干法刻蚀工艺。
  21. 如权利要求1所述半导体结构的形成方法，其特征在于，各所述电容结构位于与所述第二侧区邻接的有源区上。
  22. 一种半导体结构，其特征在于，包括：
    衬底，所述衬底包括相对的第一面和第二面，所述衬底包括若干相互分立的有源区，若干所述有源区沿第一方向排列，且若干所述有源区平行于第二方向，所述第一方向与第二方向相互垂直；
    位于所述衬底内的若干第一凹槽，所述第一凹槽自第一面向第二面延伸，若干所述第一凹槽沿第二方向排列，且所述第一凹槽沿第一方向贯穿若干所述有源区；
    位于第一凹槽内的字线栅极结构，所述字线栅极结构包括相对的第一侧区和第二侧区，所述第二侧区与所述有源区邻接；
    位于第一凹槽内的第一隔离结构，所述第一隔离结构与字线栅极结构第一侧区邻接，所述第一隔离结构位于字线栅极结构与有源区之间，所述第一隔离结构还位于部分有源区内；
    位于衬底第二面上的若干电容结构，所述电容结构与所述有源区电连接；
    位于衬底第二面上的若干位线结构，若干所述位线结构沿第一方向排列，且若干所述位线结构平行于第二方向。
  23. 如权利要求22所述的半导体结构，其特征在于，所述字线栅极结构包括位于第一凹槽侧壁表面和底部表面的栅介质层以及位于栅介质层表面的栅极层。
  24. 如权利要求23所述的半导体结构，其特征在于，所述第一隔离结构的深度大于或等于所述字线栅极结构的深度。
  25. 如权利要求23所述的半导体结构，其特征在于，所述栅极层的材料包括多晶硅或金属，所述金属包括钨。
  26. 如权利要求23所述的半导体结构，其特征在于，所述栅极层包括位于第一凹槽底部的第一分部和位于第一分部上的第二分部，所述第一分部和第二分部的材料不同。
  27. 如权利要求26所述的半导体结构，其特征在于，所述第一分部的材料包括多晶硅或金属，所述金属包括钨；所述第二分部的材料包括多晶硅或金属，所述金属包括钨。
  28. 如权利要求23所述的半导体结构，其特征在于，所述衬底第二面的有源区还暴露出栅介质层底部表面。
  29. 如权利要求22所述的半导体结构，其特征在于，还包括：位于衬底第一面暴露出的有源区内的第一掺杂区；各电容结构分别与一个第一掺杂区电连接。
  30. 如权利要求29所述的半导体结构，其特征在于，所述电容结构在衬底第一面上的投影至少与部分所述第一掺杂区重合。
  31. 如权利要求29所述的半导体结构，其特征在于，还包括：位于电容结构和第一掺杂区之间的电容插塞，所述电容插塞电连接所述电容结构和第一掺杂区。
  32. 如权利要求29所述的半导体结构，其特征在于，所述字线栅极结构朝向衬底第一面的顶部表面高于所述第一掺杂区朝向衬底第一面的底部表面。
  33. 如权利要求22所述的半导体结构，其特征在于，还包括：位于衬底第二面暴露出的有源区内的第二掺杂区；各位线结构分别与沿第二方向排列的一列若干第二掺杂区电连接。
  34. 如权利要求33所述的半导体结构，其特征在于，所述第二掺杂区的深度大于或等于所述字线栅极结构与衬底第二面之间的间距。
  35. 如权利要求33所述的半导体结构，其特征在于，还包括：位于位线结构与所述第二掺杂区之间的位线插塞，所述位线插塞电连接所述位线结构与所述第二掺杂区。
  36. 如权利要求22所述的半导体结构，其特征在于，相邻有源区之间具有第二隔离结构；所述衬底第二面暴露出所述第二隔离结构。
  37. 如权利要求36所述的半导体结构，其特征在于，还包括：位于衬底第二面上和第二隔离结构上的第一介质层，所述第一介质层内具有第三凹槽，所述第三凹槽暴露出有源区表面；所述位线结构位于所述第三凹槽内。
  38. 如权利要求37所述的半导体结构，其特征在于，所述位线结构包括位于第三凹槽侧壁表面和底部表面的阻挡层，以及位于阻挡层上的位线层。
  39. 如权利要求36所述的半导体结构，其特征在于，所述第二隔离结构的材料包括介电材料，所述介电材料包括氧化硅。
  40. 如权利要求22所述的半导体结构，其特征在于，所述第一隔离结构的材料包括介电材料，所述介电材料包括氧化硅。
  41. 如权利要求22所述的半导体结构，其特征在于，还包括：位于第一隔离结构上和有源区第一面上的第二介质层；所述电容结构位于第二介质层内。
  42. 如权利要求22所述半导体结构，其特征在于，各所述电容结构位于与所述第二侧区邻接的有源区上。
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