WO2023102965A1 - 垂直mosfet器件及其制备方法 - Google Patents

垂直mosfet器件及其制备方法 Download PDF

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WO2023102965A1
WO2023102965A1 PCT/CN2021/137863 CN2021137863W WO2023102965A1 WO 2023102965 A1 WO2023102965 A1 WO 2023102965A1 CN 2021137863 W CN2021137863 W CN 2021137863W WO 2023102965 A1 WO2023102965 A1 WO 2023102965A1
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layer
source
drain
channel
gate
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PCT/CN2021/137863
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English (en)
French (fr)
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朱慧珑
肖忠睿
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北京超弦存储器研究院
中国科学院微电子研究所
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Publication of WO2023102965A1 publication Critical patent/WO2023102965A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to the field of semiconductors, in particular to a vertical MOSFET device and a manufacturing method thereof.
  • MOSFETs planar metal-oxide field-effect transistors
  • Source, gate, and drain are all arranged in the horizontal direction.
  • Vertical MOSFET devices have an advantage over horizontal MOSFET devices because the source, gate, and drain are perpendicular to the scaling direction.
  • an object of the present disclosure is at least in part to provide a vertical MOSFET device with self-aligned sidewalls and a method for fabricating the same.
  • a vertical MOSFET device comprising: a substrate; an active region including a first source/drain layer, a channel layer, and a second source/drain layer vertically stacked on the substrate in sequence; drain layer, the periphery of the channel layer is recessed relative to the periphery of the first source/drain layer and the second source/drain layer; the spacer layer includes an upper spacer layer and a lower spacer layer, wherein the upper spacer layer is formed in the channel The lower surface of the second source/drain layer exposed due to the recessed layer, the lower spacer layer is formed on the upper surface of the first source/drain layer exposed due to the recessed channel layer, and both the upper spacer layer and the lower spacer layer are connected to the channel layer.
  • the side surfaces of the channel layer are in contact with each other; the gate stack is at least formed on the lateral periphery of the channel layer and embedded in the groove space between the upper spacer layer and the lower spacer layer.
  • a method for fabricating a vertical MOSFET device comprising: sequentially forming a structure comprising a first source/drain layer, a channel layer and a second source/drain layer on a substrate along a vertical direction;
  • the outer periphery of the channel layer has a concave portion relative to the outer periphery of the first source/drain layer and the second source/drain layer;
  • the outer surface of the active region is covered with a dummy structure layer, and the dummy structure layer is selectively etched , so that the lower surface of the first source/drain layer and the upper surface of the second source/drain layer respectively retain a second part of the dummy structure layer, and the second part of the dummy structure layer sandwiches the channel layer from opposite sides of the channel layer ; grow a dummy gate structure layer in the groove space formed by the inner wall of the second part of the dummy structure layer and the outer periphery of the channel layer, and replace
  • an electronic device including the above-mentioned vertical MOSFET device.
  • the vertical MOSFET device and its preparation method provided by the present disclosure have at least the following beneficial effects: the vertical MOSFET device has the function of self-aligned side walls, and utilizes the characteristics of different epitaxial growth rates on different crystal planes to A false sidewall structure is formed, and the rate of epitaxial growth in the channel direction is relatively high.
  • FIG. 1 to 12 schematically show cross-sectional views of a method for fabricating a storage device according to an embodiment of the present disclosure at different stages in sequence.
  • FIG. 1 to 12 schematically show cross-sectional views of a method for fabricating a storage device according to an embodiment of the present disclosure at different stages in sequence.
  • Figure 1 schematically shows a cross-sectional view of a stack disposed on a substrate
  • Fig. 2 schematically shows a cross-sectional view of etching a first source/drain layer on the stack
  • Figure 3 schematically shows a cross-sectional view of a channel layer formed by selective etching
  • Fig. 4 schematically shows a cross-sectional view covering the outer surface of the active region with a dummy structure layer
  • Fig. 5 schematically shows a cross-sectional view of the initial selective etching of the dummy structure layer
  • Fig. 6 schematically shows a cross-sectional view of selectively etching the dummy structure layer again
  • FIG. 7 schematically shows a cross-sectional view of growing a dummy gate structure layer in a groove space
  • Figure 8 schematically shows a cross-sectional view of a replaced spacer layer
  • FIG. 10 schematically shows a cross-sectional view of forming a gate dielectric layer and a gate conductor layer
  • Figure 11 (a) schematically shows a cross-sectional view of spin-coating photoresist on the gate conductor layer
  • Figure 11(b) schematically shows a cross-sectional view of etching the gate conductor layer
  • Figure 12 schematically shows a cross-sectional view of forming a metal contact
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be intervening layers/elements in between. element. Additionally, if a layer/element is "on” another layer/element in one orientation, the layer/element can be located “below” the other layer/element when the orientation is reversed.
  • the disclosure can be presented in various forms, some examples of which are described below.
  • the selection of various materials is involved.
  • the selection of materials also considers etching selectivity.
  • the desired etch selectivity may or may not be indicated. It should be clear to those skilled in the art that when it is mentioned below that a certain material layer is etched, if it is not mentioned that other layers are also etched or it is not shown in the figure that other layers are also etched, then such etching It may be selective, and the layer of material may be etch-selective relative to other layers exposed to the same etch formulation.
  • An embodiment of the present disclosure provides a vertical MOSFET device.
  • Embodiments of the present disclosure provide a vertical MOSFET device.
  • a vertical MOSFET device means that its active region (especially the channel region) extends in a vertical direction relative to the substrate (eg, a direction perpendicular or substantially perpendicular to the surface of the substrate).
  • the active region can be made of single crystal semiconductor material to improve device performance.
  • a gate stack may be formed around the outside of the middle portion of the active region.
  • the vertical MOSFET device may be based on a vertical metal oxide field effect transistor (MOSFET). Compared with the horizontal MOSFET, the vertical MOSFET can have a smaller occupied area and smaller leakage current, but the conduction current is relatively small.
  • MOSFET vertical metal oxide field effect transistor
  • the vertical MOSFET device includes: a substrate; an active region including a first source/drain layer 1003, a channel layer 200 and a second source/drain layer 1007 vertically stacked on the substrate in sequence , the outer periphery of the channel layer 200 is recessed relative to the outer periphery of the first source/drain layer 1003 and the second source/drain layer 1007; the spacer layer 3001 includes an upper spacer layer and a lower spacer layer, wherein the upper spacer layer is formed due to The lower surface of the second source/drain layer 1007 exposed by the recess of the channel layer 200, the lower spacer layer is formed on the upper surface of the first source/drain layer 1003 exposed by the recess of the channel layer 200, the upper spacer layer and The lower spacer layers are in contact with the side surfaces of the channel layer 200 and are not connected; the gate stack is at least formed on the lateral periphery of the channel layer 200 and embedded in the groove space between the upper spacer layer and the
  • the thicknesses of the first source/drain layer 1003 , the channel layer 200 and the second source/drain layer 1007 are all 10 nm ⁇ 100 nm.
  • the gate stack includes a gate dielectric layer 3002 and a gate conductor layer 5001
  • the gate conductor layer 5001 includes a work function adjusting metal and a gate conductive metal disposed on the work function adjusting metal.
  • the vertical MOSFET device further includes: a first dielectric layer 4001 disposed on the first source/drain layer 1003 .
  • the height of the first dielectric layer 4001 is higher than the bottom surface of the channel layer 200 and lower than the top surface of the lower spacer layer adjacent to the bottom surface of the channel layer 200 .
  • gate dielectric layer 3002 and the gate conductor layer 5001 are partially disposed on the first dielectric layer 4001 .
  • the vertical MOSFET device further includes: a second dielectric layer 4002 disposed on the upper surface of the gate dielectric layer 3002 and the gate conductor layer 5001, the materials of the second dielectric layer 4002 and the first dielectric layer 4001 same.
  • the lateral outer edges of the spacer layer 3001 relative to the first source/drain layer 1003 and the second source/drain layer 1007 are aligned with each other.
  • the vertical MOSFET device further includes: metal contacts embedded in the first source/drain layer 1003 , the gate conductor layer 5001 and the second source/drain layer 1007 respectively.
  • an embodiment of the present disclosure also provides a method for fabricating a vertical MOSFET device, including:
  • Step S1 sequentially forming an active region including a first source/drain layer 1003, a channel layer 200 and a second source/drain layer 1007 on the substrate along the vertical direction, the outer periphery of the channel layer 200 is opposite to the first source
  • the outer peripheries of the /drain layer 1003 and the second source/drain layer 1007 have recesses;
  • Step S2 cover the dummy structure layer 1009 on the outer surface of the active region, and selectively etch the dummy structure layer 1009, so that the lower surface of the first source/drain layer 1003 and the upper surface of the second source/drain layer 1007 respectively retain
  • the second part of the dummy structure layer 10092, the second part of the dummy structure layer 10092 sandwiches the channel layer 200 from opposite sides of the channel layer 200;
  • Step S3 growing a dummy gate structure layer 2001 in the groove space formed by the inner wall of the second part of the dummy structure layer 10092 and the outer periphery of the channel layer 200, and replacing the second part of the dummy structure layer 10092 with a spacer layer 3001;
  • Step S4 forming a first dielectric layer 4001 on the first source/drain layer 1003, removing the dummy gate structure layer 2001, and forming a gate dielectric layer 3002 and a gate conductor layer 5001 on the groove space and the first dielectric layer 4001; as well as
  • Step S5 selectively etching the gate conductor layer 5001 to form metal contacts on the first source/drain layer 1003 , the gate conductor layer 5001 and the second source/drain layer 1007 .
  • the dummy structure layer 1009 Since the function of the dummy structure layer 1009 is to fill and occupy a certain space in the concave part of the channel layer 200, and to facilitate the subsequent replacement with the spacer layer 3001, the dummy structure layer 1009 can also be called a "dummy structure layer", "position keeping layer” or "sacrificial layer”.
  • FIGS. 1 to 12 schematically show flow charts of different stages of a manufacturing method of a storage device according to an embodiment of the present disclosure.
  • FIG. 1 schematically shows a cross-sectional view of stacking layers disposed on a substrate.
  • a substrate 1001 is provided.
  • the substrate 1001 may be various types of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like.
  • bulk Si substrate is used as an example for description.
  • SOI semiconductor-on-insulator
  • a silicon wafer is provided as a substrate 1001 .
  • a well region may be formed. If a p-type device is to be formed, the well region can be an n-type well; if an n-type device is to be formed, the well region can be a p-type well.
  • a p-type well can be formed, for example, by implanting a p-type dopant such as boron (B) in the substrate 1001, and then performing thermal annealing.
  • boron (B) may be about 1E19 ⁇ 1E21/cm ⁇ 3 .
  • n-type device is taken as an example for description. It is clear to those skilled in the art that the following description is also applicable to p-type devices, for example by appropriately adjusting the conductivity type of the doping.
  • a first source/drain layer 1003, a channel defining layer 1005, and a second source/drain layer 1007 may be formed by, for example, epitaxial growth.
  • the first source/drain layer 1003 can be used to define the position of the lower source/drain part, and its thickness is, for example, about 10 nm ⁇ 100 nm.
  • the channel defining layer 1005 can be used to define the position of the channel, and its thickness is, for example, about 10 nm ⁇ 100 nm.
  • the second source/drain layer 1005 can be used to define the position of the upper source/drain part, and its thickness is, for example, about 10 nm ⁇ 100 nm.
  • Adjacent layers among the first source/drain layer 1003 , the channel defining layer 1005 and the second source/drain layer 1007 may have etch selectivity with respect to each other.
  • the first source/drain layer 1003 may include Si
  • the channel defining layer 1005 may include SiGe (for example, the composition of Ge is about 10%-40%)
  • the second source/drain layer 1007 may include Si.
  • the first source/drain layer 1003 and the second source/drain layer 1007 can adopt a low-temperature epitaxy process, and the growth temperature should be lower than 900° C. to avoid impurity diffusion. In other embodiments, other doping methods can also be used, such as implantation or gas phase diffusion technology. In addition, the first source/drain layer 1003 and the second source/drain layer 1007 may be in-situ doped during growth to (at least partially) define the doping characteristics of the source/drain portion.
  • transverse directions x, y and the vertical direction z are schematically shown in FIG. 1 .
  • the x and y directions may be parallel to the top surface of the substrate 1001 , and may intersect each other, eg, be perpendicular; the z direction may be substantially perpendicular to the top surface of the substrate 1001 .
  • the substrate is a (110) crystal plane
  • the channel layer is a (001) crystal plane.
  • Fig. 2 schematically shows a cross-sectional view of etching a first source/drain layer on the stack.
  • a photoresist (not shown) is formed on the laminated layer formed by the first source/drain layer 1003, the channel defining layer 1005 and the second source/drain layer 1007, by photolithography (exposure and developing) to pattern the photoresist into the desired shape.
  • the second source/drain layer 1007, the channel defining layer 1005 and the first source/drain layer 1003 are sequentially etched such as reactive ion etching (Reactive ion etching, RIE). The etching proceeds to the middle of the first source/drain layer 1003 , but not to the bottom surface of the first source/drain layer 1003 .
  • the etched second source/drain layer 1007, the upper part of the channel defining layer 1005 and the first source/drain layer 1003 form a columnar shape.
  • RIE can be performed in a direction approximately perpendicular to the surface of the substrate 1001 , so that the columnar shape is also approximately perpendicular to the surface of the substrate 1001 .
  • the photoresist can be removed.
  • the active region of the vertical MOSFET device is thus defined, and the active region includes the etched upper portion of the first source/drain layer 1003 , the channel defining layer 1005 and the second source/drain layer 1007 .
  • sidewalls are formed on the outer peripheries of opposite sides of the channel defining layer 1005 along the x-direction, and the sidewalls are crystal planes in the x-direction.
  • FIG. 3 schematically shows a cross-sectional view of a channel layer formed by selective etching.
  • the channel defining layer 1005 is selectively etched so that the outer periphery of the channel defining layer 1005 is recessed relative to the outer periphery of the first source/drain layer 1003 and the second source/drain layer 1007 to form a channel layer 200.
  • etching can be performed along the outer circumference of the channel defining layer 1005 toward the middle, and the middle part of the channel defining layer 1005 is retained, thereby forming an approximately cylindrical channel layer 200 .
  • the concave portion thus formed may be self-aligned to the channel layer 200 .
  • the selective etching can use wet etching or atomic layer etching (ALE).
  • ALE atomic layer etching
  • Fig. 4 schematically shows a cross-sectional view of covering the outer surface of the active region with a dummy structure layer.
  • a dummy structure layer 1009 is epitaxially grown on the surfaces of the second source/drain layer 1007 , the channel layer 200 and the first source/drain layer 1003 .
  • the material of the dummy structure layer 1009 may be SiGe, and the composition of Ge is about 20%-70%. Therefore, the composition of Ge in the dummy structure layer 1009 is higher than that in the channel layer 200 .
  • the dummy structure layer 1009 covers the outer surfaces of the second source/drain layer 1007 , the channel layer 200 and the first source/drain layer 1003 . It should be noted that since the epitaxial growth rate in the y direction is higher than that in the x direction, during the epitaxial growth process, the dummy structure layer 1009 along the x direction in FIG. 4 is thicker than the dummy structure layer 1009 along the y direction. Therefore, the dummy structure layer 1009 is formed using the characteristic that different crystal planes have different growth rates.
  • FIG. 5 schematically shows a cross-sectional view of the initial selective etching of the dummy structure layer.
  • the dummy structure layer 1009 is partially etched by an atomic layer etching (ALE) method, and the first part of the dummy structure layer 10091 along the y direction is reserved.
  • ALE atomic layer etching
  • the atomic layer etching can be performed with a material having etching selectivity to the SiGe material of the channel layer 200 .
  • this partial etching may include: etching away the dummy structure layers located on the opposite sides of the surface of the second source/drain layer 1007, the channel layer 200 and the first source/drain layer 1003 along the x direction along the x direction, leaving The first part of the virtual structure layer 10091 along the y direction.
  • the first part of the dummy structure layer 10091 can retain roughly the same thickness, but the roughly the same thickness is smaller than the thickness of the dummy structure layer 1009 epitaxially grown along the y direction in FIG. 4 .
  • FIG. 6 schematically shows a cross-sectional view of selectively etching the dummy structure layer again.
  • the first part of the dummy structure layer 10091 is partially etched by reactive ion etching method, and the second part of the dummy structure layer 10092 in the concave part of the channel layer 200 is reserved.
  • the second part of the dummy structure layer 10092 is respectively located on the lower surface of the first source/drain layer 1003 and the upper surface of the second source/drain layer 1007, and horizontally sandwiches the channel from opposite sides of the channel layer 200.
  • Layer 200, the middle part of the channel layer 200 does not retain the second part of the dummy structure layer 10092.
  • FIG. 7 schematically shows a cross-sectional view of growing a dummy gate structure layer in the groove space.
  • a dummy gate structure layer 2001 is deposited and grown in the groove space formed by the inner wall of the second part of the dummy structure layer 10092 and the outer periphery of the channel layer 200 .
  • the material of the dummy gate structure layer 2001 may be SiC.
  • the redundant dummy gate structure layer 2001 In order to control the deposition growth size, it is also necessary to etch away the redundant dummy gate structure layer 2001 at the edge of the second part of the dummy structure layer 10092 by reactive ion etching, so as to form the second source/drain layer 1007 and the first source/drain layer 1007.
  • the dummy gate structure layer 2001 is filled to fill the groove space where the channel layer 200 is located.
  • Figure 8 schematically shows a cross-sectional view of a spacer layer after replacement.
  • the second part of the dummy structure layer 10092 is selectively etched away, and a growth spacer layer 3001 is deposited on the corresponding position of the second part of the dummy structure layer 10092 .
  • the second part of the dummy structure layer 10092 is replaced by the spacer layer 3001 .
  • the spacer layer 3001 includes an upper spacer layer and a lower spacer layer, wherein the upper spacer layer is formed on the lower surface of the second source/drain layer 1007 exposed due to the recess of the channel layer 200, and the lower spacer layer is formed on On the upper surface of the first source/drain layer 1003 exposed due to the recess of the channel layer 200 , both the upper spacer layer and the lower spacer layer are in contact with and not connected to the side surfaces of the channel layer 200 .
  • the spacer layer 3001 can be made of a dielectric material with a low dielectric constant or SiN material.
  • the deposition growth method may adopt atomic layer deposition or chemical vapor deposition.
  • FIG. 9 schematically shows a cross-sectional view of forming a first dielectric layer.
  • a first dielectric layer 4001 is deposited and grown on the first source/drain layer 1003 , and then the first dielectric layer 4001 is etched back to a preset height. Before the etch back, chemical mechanical polishing (CMP) may be performed on the surface of the deposited and grown first dielectric layer 4001 .
  • CMP chemical mechanical polishing
  • the material of the first dielectric layer 4001 may be silicon oxide.
  • the predetermined height of the first dielectric layer 4001 is higher than the bottom surface of the channel layer 200 and lower than the top surface of the lower spacer layer adjacent to the bottom surface of the channel layer 200 .
  • the setting of the height of the first dielectric layer 4001 helps to form a self-aligned gate structure between the first source/drain layer 1003 and the second source/drain layer 1007 after removing the dummy gate structure layer 2001 .
  • the so-called “self-alignment” does not necessarily mean complete alignment.
  • Self-aligned refers to a relative position between structures that is substantially unaffected by process fluctuations, especially lithographic fluctuations. This self-aligned structure is detectable. For example, there may be a plurality of such devices in an integrated circuit (IC), and if it is a self-aligned structure, the positional relationship of the low-k dielectric layer and the spacer with respect to the end of the channel region in each device can remain substantially If it is not a self-aligned structure, there may be process fluctuations in this relative position relationship between devices.
  • IC integrated circuit
  • FIG. 10 schematically shows a cross-sectional view of forming a gate dielectric layer and a gate conductor layer.
  • the dummy gate structure layer 2001 is removed, a gate dielectric layer 3002 is deposited on the groove space and the first dielectric layer 4001 , and a gate conductor layer 5001 is deposited on the surface of the gate dielectric layer 3002 .
  • the gate dielectric layer 3002 can be made of a dielectric material with a high dielectric constant, such as HfO 2 , with a thickness of about 1 nm ⁇ 5 nm.
  • the gate conductor layer 5001 can be deposited on the surface of the gate dielectric layer 3002 in a substantially conformal manner, so as to extend along the surface of the gate dielectric layer 3002 .
  • an interfacial layer (not shown in the figure) of silicon oxide material with a thickness of about 0.3nm-1.5nm may also be formed.
  • the gate conductor layer 5001 may include a work function adjusting metal and a gate conductive metal.
  • the work function adjusting metal may include, for example, a TiN material with a thickness of, for example, about 1 nm ⁇ 10 nm.
  • the gate conductive metal may include, for example, a W material with a thickness of about 100 nm ⁇ 800 nm.
  • the gate conductor layer 5001 can fill the space between the active regions of the respective devices.
  • the gate stack formed in this way (including the gate dielectric layer 3002 and the gate conductor layer 5001) can be embedded between the first source/drain layer 1003 and the second source/drain layer 1007, and the gate stack is formed at least on the lateral periphery of the channel layer 200 And embedded in the groove space between the upper interval layer and the lower interval layer. In order to control the etching depth, it is necessary to etch back the formed gate stack at last.
  • Fig. 11(a) schematically shows a cross-sectional view of spin-coating photoresist on the gate conductor layer.
  • Fig. 11(b) schematically shows a cross-sectional view of etching the gate conductor layer.
  • a photoresist 500 is spin-coated on the gate conductor layer 5001 to form a gate pattern.
  • the photoresist 500 is, for example, patterned by photolithography to cover a part of the gate conductor layer 5001 exposed outside the groove space where the channel layer 200 is located (in this example, the left half of the figure), and expose the gate conductor layer 5001 is exposed to another part (in this example, the right half of the figure) outside the groove space where the channel layer 200 is located.
  • the gate conductor layer 5001 is etched such as RIE. RIE can be performed along the vertical direction, and then the photoresist 500 is removed.
  • the portion blocked by the photoresist 500 is also retained.
  • Fig. 12 schematically shows a cross-sectional view of forming a metal contact.
  • a second dielectric layer 4002 is deposited on the exposed upper surfaces of the gate dielectric layer 3002 and the gate conductor layer 5001 and subjected to chemical mechanical polishing, respectively on the first source/drain layer 1003 and the gate conductor layer 5001
  • a metal contact portion is formed on the second source/drain layer 1007 .
  • These metal contacts can be formed by etching holes in the second dielectric layer 4002 and the first dielectric layer 4001 and filling them with conductive material such as metal.
  • the second dielectric layer 4002 can be the same as the first dielectric layer 4001, that is, the material of the second dielectric layer 4002 can also be silicon oxide.
  • the metal contacts include: a first source/drain contact 6001 formed on the first source/drain layer 1003, a gate contact 6002 formed on the gate conductor layer 5001, and a second source/drain layer 1007 A second source/drain contact 6003 is formed.
  • the first source/drain contact portion 6001 , the gate contact portion 6002 and the second source/drain contact portion 6003 can be formed using conventional processes.
  • the gate contact portion 6002 can be easily formed. Meanwhile, since there is no gate conductor layer 5001 over at least a part of the first source/drain layer 1003 , the first source/drain contact portion 6001 can be easily formed.
  • the vertical MOSFET device of the embodiment of the present disclosure is prepared.
  • the vertical MOSFET device in this embodiment has the function of self-aligned sidewalls, and uses the characteristics of different epitaxial growth rates on different crystal planes to form a false sidewall structure, and the epitaxial growth rate in the channel direction is relatively high.
  • an electronic device may include a vertical MOSFET device and a processor.
  • Vertical MOSFET devices can store data required for the operation of electronic equipment or obtained during operation.
  • the processor can operate based on data and/or applications stored in the vertical MOSFET devices.
  • Such electronic devices include smart phones, computers, tablet computers (PCs), wearable smart devices, artificial intelligence devices, mobile power supplies, and the like.

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Abstract

本公开提供一种垂直MOSFET器件及其制备方法，涉及半导体技术领域。该垂直MOSFET器件包括：衬底；有源区，包括依次竖直叠置于衬底上的第一源/漏层、沟道层和第二源/漏层，沟道层的外周相对于第一源/漏层和第二源/漏层的外周凹入；间隔层，包括上间隔层和下间隔层，其中，上间隔层形成于因沟道层凹入而露出的第二源/漏层的下表面，下间隔层形成于因沟道层凹入而露出的第一源/漏层的上表面，上间隔层和下间隔层均与沟道层的侧面接触且不连通；栅堆叠，至少形成于沟道层的横向外周且嵌于上间隔层和下间隔层之间的凹槽空间。

Description

垂直MOSFET器件及其制备方法 技术领域
本公开涉及半导体领域，具体涉及一种垂直MOSFET器件及其制备方法。
背景技术
目前，平面型金属氧化物场效应晶体管(MOSFET)由于源极、栅极和漏极均沿水平方向排列，因此尺寸不易缩小。垂直MOSFET器件由于源极、栅极和漏极垂直于缩放方向，比水平型MOSFET器件更具优势。
然而，现有的垂直MOSFET器件仍旧存在难以克服的技术缺陷。例如，垂直MOSFET器件的栅极长度的控制比较困难，尤其是对于单晶沟道材料。另外，如果沟道材料为多晶，则沟道电阻比单晶体高得多，此时由于总电阻太高，很难将多个垂直器件进行堆叠。
发明内容
有鉴于此，本公开的目的至少部分地在于提供一种具有自对准侧墙的垂直MOSFET器件及其制备方法。
根据本公开的一个方面，提供了一种垂直MOSFET器件，包括：衬底；有源区，包括依次竖直叠置于衬底上的第一源/漏层、沟道层和第二源/漏层，沟道层的外周相对于第一源/漏层和第二源/漏层的外周凹入；间隔层，包括上间隔层和下间隔层，其中，上间隔层形成于因沟道层凹入而露出的第二源/漏层的下表面，下间隔层形成于因沟道层凹入而露出的第一源/漏层的上表面，上间隔层和下间隔层均与沟道层的侧面接触且不连通；栅堆叠，至少形成于沟道层的横向外周且嵌于上间隔层和下间隔层之间的凹槽空间。
根据本公开的另一方面，提供了一种垂直MOSFET器件的制备方法， 包括：在衬底上沿竖直方向依次形成包括第一源/漏层、沟道层和第二源/漏层的有源区，使沟道层的外周相对于第一源/漏层和第二源/漏层的外周具有凹入部；在有源区的外表面覆盖虚拟结构层，选择性刻蚀虚拟结构层，使第一源/漏层的下表面和第二源/漏层的上表面分别保留有第二部分虚拟结构层，第二部分虚拟结构层从沟道层的相对两侧夹着沟道层；在第二部分虚拟结构层内壁与沟道层外周构成的凹槽空间生长假栅结构层，将第二部分虚拟结构层替换为间隔层；在第一源/漏层上形成第一介电层，去除假栅结构层，在凹槽空间和第一介电层上形成栅介质层和栅导体层；选择性刻蚀栅导体层，分别在第一源/漏层、栅导体层和第二源/漏层上形成金属接触部。
根据本公开的另一方面，提供了一种电子设备，包括上述垂直MOSFET器件。
与现有技术相比，本公开提供的垂直MOSFET器件及其制备方法，至少具有以下有益效果：该垂直MOSFET器件具有自对准侧墙的功能，利用不同晶面上外延生长速率不同的特点来形成假侧墙结构，在沟道方向上外延生长的速率相对较高。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1至12示意性示出了根据本公开实施例的存储器件的制备方法依次处于不同阶段的截面图，在这些附图中：
图1示意性示出了在衬底上设置叠层的截面图；
图2示意性示出了在叠层上刻蚀第一源/漏层的截面图；
图3示意性示出了选择性刻蚀形成沟道层的截面图；
图4示意性示出了在有源区的外表面覆盖虚拟结构层的截面图；
图5示意性示出了初次选择性刻蚀虚拟结构层的截面图；
图6示意性示出了再次选择性刻蚀虚拟结构层的截面图；
图7示意性示出了在凹槽空间生长假栅结构层的截面图；
图8示意性示出了替换后的间隔层的截面图；
图9示意性示出了形成第一介电层的截面图；
图10示意性示出了形成栅介质层和栅导体层的截面图；
图11(a)示意性示出了在栅导体层上旋涂光刻胶的截面图；
图11(b)示意性示出了刻蚀栅导体层的截面图；
图12示意性示出了形成金属接触部的截面图；
附图标记说明：
1001-衬底；1003-第一源/漏层；1005-沟道限定层；
1007-第二源/漏层；200-沟道层；1009-虚拟结构层；
10091-第一部分虚拟结构层；10092-第二部分虚拟结构层；
2001-假栅结构层；3001-间隔层；3002-栅介质层；
4001-第一介电层；4002-第二介电层；500-光刻胶；
5001-栅导体层；6001-第一源/漏极接触部；6002-栅极接触部；
6003-第二源/漏极接触部。
贯穿附图，相同或相似的附图标记表示相同或相似的部件。附图并非一定是按比例绘制的，特别是为清楚起见，截面图的绘制比例不同于俯视图的绘制比例。
具体实施方式
以下，将参照附图来描述本公开的实施例。但是应该理解，这些描述只是示例性的，而并非要限制本公开的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差 或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。
本公开可以各种形式呈现，以下将描述其中一些示例。在以下的描述中，涉及各种材料的选择。材料的选择除了考虑其功能(例如，半导体材料用于形成有源区，电介质材料用于形成电隔离)之外，还考虑刻蚀选择性。在以下的描述中，可能指出了所需的刻蚀选择性，也可能并未指出。本领域技术人员应当清楚，当以下提及对某一材料层进行刻蚀时，如果没有提到其他层也被刻蚀或者图中并未示出其他层也被刻蚀，那么这种刻蚀可以是选择性的，且该材料层相对于暴露于相同刻蚀配方中的其他层可以具备刻蚀选择性。
本公开实施例提供了一种垂直MOSFET器件。本公开的实施例提供一种垂直MOSFET器件。垂直MOSFET器件，是指其有源区(特别是沟道区)相对于衬底在竖直方向(例如，垂直于或实质上垂直于衬底表面的方向)上延伸。有源区可以由单晶半导体材料制成，以改善器件性能。绕有源区的中间部分的外部可以形成栅堆叠。该垂直MOSFET器件可以基于竖直型的金属氧化物场效应晶体管(MOSFET)。相比于水平型MOSFET，竖直型MOSFET可以具有较小的占用面积和较小的漏电流，但是导通电流相对较小。
本公开实施例提供的垂直MOSFET器件，包括：衬底；有源区，包括依次竖直叠置于衬底上的第一源/漏层1003、沟道层200和第二源/漏层1007，沟道层200的外周相对于第一源/漏层1003和第二源/漏层1007的外周凹入；间隔层3001，包括上间隔层和下间隔层，其中，上间隔层形成于因沟道层200凹入而露出的第二源/漏层1007的下表面，下间隔层形成于因沟道层200凹入而露出的第一源/漏层1003 的上表面，上间隔层和下间隔层均与沟道层200的侧面接触且不连通；栅堆叠，至少形成于沟道层200的横向外周且嵌于上间隔层和下间隔层之间的凹槽空间。
根据本公开的实施例，第一源/漏层1003、沟道层200和第二源/漏层1007的厚度均为10nm～100nm。
根据本公开的实施例，栅堆叠包括栅介质层3002和栅导体层5001，栅导体层5001包括功函数调节金属和设置于功函数调节金属上的栅导电金属。
根据本公开的实施例，该垂直MOSFET器件还包括：第一介电层4001，设置于第一源/漏层1003上。
进一步地，第一介电层4001高度高于沟道层200的底面且低于紧邻沟道层200底面的下间隔层的顶面。
进一步地，栅介质层3002和栅导体层5001还部分设置于第一介电层4001上。
进一步地，栅导体层5001露于凹槽空间之外的一部分，且露出凹槽空间之外的另一部分。
根据本公开的实施例，该垂直MOSFET器件还包括：第二介电层4002，设置于栅介质层3002和栅导体层5001上表面，第二介电层4002与第一介电层4001的材料相同。
根据本公开的实施例，间隔层3001相对于第一源/漏层1003和第二源/漏层1007的横向外边缘相互齐整。
根据本公开的实施例，该垂直MOSFET器件还包括：金属接触部，分别嵌入于第一源/漏层1003、栅导体层5001和第二源/漏层1007。
需要说明的是，装置部分的实施例方式与方法部分的实施例方式对应类似，并且所达到的技术效果也对应类似，具体细节请参照一下方法部分的实施例方式，在此不再赘述。
基于同一发明构思，本公开实施例还提供了一种垂直MOSFET器件的制备方法，包括：
步骤S1，在衬底上沿竖直方向依次形成包括第一源/漏层1003、沟道层200和第二源/漏层1007的有源区，沟道层200的外周相对于第一源/漏层1003和第二源/漏层1007的外周具有凹入部；
步骤S2，在有源区的外表面覆盖虚拟结构层1009，选择性刻蚀虚拟结构层1009，使第一源/漏层1003的下表面和第二源/漏层1007的上表面分别保留有第二部分虚拟结构层10092，第二部分虚拟结构层10092从沟道层200的相对两侧夹着沟道层200；
步骤S3，在第二部分虚拟结构层10092内壁与沟道层200外周构成的凹槽空间生长假栅结构层2001，将第二部分虚拟结构层10092替换为间隔层3001；
步骤S4，在第一源/漏层1003上形成第一介电层4001，去除假栅结构层2001，在凹槽空间和第一介电层4001上形成栅介质层3002和栅导体层5001；以及
步骤S5，选择性刻蚀栅导体层5001，分别在第一源/漏层1003、栅导体层5001和第二源/漏层1007上形成金属接触部。
由于虚拟结构层1009的作用是为了填充以占据沟道层200凹入部的一定空间，方便后续替换成间隔层3001，由此，虚拟结构层1009也可以称为“dummy结构层”、“位置保持层”或“牺牲层”。
图1至12示意性示出了根据本公开实施例的存储器件的制备方法处于不同阶段的流程图。其中，图1示意性示出了在衬底上设置叠层的截面图。
如图1所示，提供衬底1001。该衬底1001可以是各种形式的衬底，包括但不限于体半导体材料衬底如体Si衬底、绝缘体上半导体(SOI)衬底、化合物半导体衬底如SiGe衬底等。在以下的描述中，为方便说明，以体Si衬底为例进行描述。在此，提供硅晶片作为衬底1001。
在衬底1001中，可以形成阱区。如果要形成p型器件，则阱区可以是n型阱；如果要形成n型器件，则阱区可以是p型阱。一般地， 在DRAM中，存储单元基于n型器件。因此，例如可以通过在衬底1001中注入p型掺杂剂如硼(B)，且随后进行热退火来形成p型阱。例如，硼(B)的掺杂浓度可以为约1E19～1E21/cm -3。
以下，以形成n型器件为例进行描述。本领域技术人员清楚，例如通过适当调整掺杂的导电类型，以下描述同样适用于p型器件。
在衬底1001上，可以通过例如外延生长，形成第一源/漏层1003、沟道限定层1005和第二源/漏层1007。第一源/漏层1003可以用来限定下端源/漏部的位置，厚度例如为约10nm～100nm。沟道限定层1005可以用来限定沟道的位置，厚度例如为约10nm～100nm。第二源/漏层1005可以用来限定上端源/漏部的位置，厚度例如为约10nm～100nm。
第一源/漏层1003、沟道限定层1005和第二源/漏层1007中相邻的层相对于彼此可以具有刻蚀选择性。例如，第一源/漏层1003可以包括Si，沟道限定层1005可以包括SiGe(例如，Ge的组分为约10％～40％)，
第二源/漏层1007可以包括Si。
第一源/漏层1003和第二源/漏层1007可以采用低温外延工艺，生长温度要小于900℃以避免发生杂质扩散的现象。在其他实施例中，还可以使用其他的掺杂方法，例如注入或者气相扩散技术。另外，第一源/漏层1003和第二源/漏层1007在生长时可以被原位掺杂，以(至少部分地)限定源/漏部的掺杂特性。
还需要说明的是，图1中示意性示出了横向方向x、y和竖直方向z。x、y方向可以平行于衬底1001的顶面，并且可以彼此相交例如垂直；z方向可以基本上垂直于衬底1001的顶面。
衬底为(110)晶面，沟道层为(001)晶面。
图2示意性示出了在叠层上刻蚀第一源/漏层的截面图。
如图2所示，在第一源/漏层1003、沟道限定层1005和第二源/漏层1007构成的叠层上形成光刻胶(图中未示出)，通过光刻(曝光和显影)将光刻胶构图为所需形状。以构图后的光刻胶为掩模，依次 对第二源/漏层1007、沟道限定层1005和第一源/漏层1003进行刻蚀如反应离子刻蚀(Reactive ion etching，RIE)。刻蚀进行到第一源/漏层1003中部，但并未进行到第一源/漏层1003的底面。于是，刻蚀后的第二源/漏层1007、沟道限定层1005和第一源/漏层1003的上部形成柱状。RIE可以按大致垂直于衬底1001表面的方向进行，从而该柱状也大致垂直于衬底1001表面。之后，可以去除光刻胶。
由此限定该垂直MOSFET器件的有源区，该有源区包括刻蚀后的第一源/漏层1003的上部、沟道限定层1005和第二源/漏层1007。此时，沟道限定层1005沿x向的相对两侧外周形成侧墙，该侧墙为x向晶面。
图3示意性示出了选择性刻蚀形成沟道层的截面图。
如图3所示，选择性刻蚀沟道限定层1005，使沟道限定层1005的外周相对于第一源/漏层1003和第二源/漏层1007的外周凹入，形成沟道层200。
具体地，本发明可沿着沟道限定层1005的外周向中间进行刻蚀，并保留中间部分的沟道限定层1005，由此形成近似圆柱形的沟道层200。如此形成的凹入部可以自对准于沟道层200。
为更好地控制刻蚀深度，该选择性刻蚀可以采用湿法刻蚀或者原子层刻蚀(ALE)。由此，本实施例可以在衬底1001上形成具有凹入部的沟道层200。
图4示意性示出了在有源区的外表面覆盖虚拟结构层的截面图。
如图4所示，在第二源/漏层1007、沟道层200和第一源/漏层1003表面外延生长虚拟结构层1009。其中，虚拟结构层1009的材料可以为SiGe，Ge的组分约为20％～70％。由此，虚拟结构层1009中的Ge的组分要高于沟道层200。
由此，虚拟结构层1009覆盖第二源/漏层1007、沟道层200和第一源/漏层1003的外表面。需要注意的是，由于y方向的外延生长速度要高于x方向，因此在外延生长过程中，图4中的沿x方向的虚拟 结构层1009厚度比沿y方向的虚拟结构层1009更厚。因此，虚拟结构层1009利用不同晶面的生长速率不同的特点形成。
图5示意性示出了初次选择性刻蚀虚拟结构层的截面图。
如图5所示，采用原子层刻蚀(ALE)方法部分刻蚀虚拟结构层1009，保留沿y方向上的第一部分虚拟结构层10091。其中，该原子层刻蚀可以选用与沟道层200的SiGe材料具有刻蚀选择性的材料进行。
具体地，该部分刻蚀可以包括：沿x方向刻蚀掉位于第二源/漏层1007、沟道层200和第一源/漏层1003表面沿x向相对两侧的虚拟结构层，保留沿y方向上的第一部分虚拟结构层10091。
经过原子层刻蚀并控制刻蚀深度，第一部分虚拟结构层10091可以保留大致相同的厚度，但是该大致相同的厚度小于图4中沿y方向外延生长的虚拟结构层1009的厚度。
图6示意性示出了再次选择性刻蚀虚拟结构层的截面图。
如图6所示，利用反应离子刻蚀方法部分刻蚀第一部分虚拟结构层10091，保留沟道层200凹入部的第二部分虚拟结构层10092。
具体地，该第二部分虚拟结构层10092分别位于第一源/漏层1003的下表面和第二源/漏层1007的上表面，并从沟道层200的相对两侧水平夹着沟道层200，该沟道层200的中部并未保留有第二部分虚拟结构层10092。
图7示意性示出了在凹槽空间生长假栅结构层的截面图。
如图7所示，在第二部分虚拟结构层10092内壁与沟道层200外周构成的凹槽空间淀积生长假栅结构层2001。其中，假栅结构层2001的材料可以为SiC。
为控制淀积生长尺寸，还需通过反应离子刻蚀来刻蚀掉位于第二部分虚拟结构层10092边缘的多余假栅结构层2001，以形成与第二源/漏层1007和第一源/漏层1003的外边缘相互齐整的假栅结构层2001。由此填充假栅结构层2001，以充满沟道层200所在的凹槽空 间。
图8示意性示出了替换后的间隔层的截面图。
如图8所示，选择性刻蚀掉第二部分虚拟结构层10092，在第二部分虚拟结构层10092的对应位置淀积生长间隔层3001。由此，将第二部分虚拟结构层10092替换为间隔层3001。具体地，该间隔层3001，包括上间隔层和下间隔层，其中，上间隔层形成于因沟道层200凹入而露出的第二源/漏层1007的下表面，下间隔层形成于因沟道层200凹入而露出的第一源/漏层1003的上表面，上间隔层和下间隔层均与沟道层200的侧面接触且不连通。
该间隔层3001可以选用具有低介电常数的介电材料或者SiN材料。该淀积生长方法可以采用原子层淀积或者化学气相淀积。
需要说明的是，为控制淀积生长尺寸，还需通过反应离子刻蚀来刻蚀掉位于第二部分虚拟结构层10092的对应位置外边缘多余的间隔层3001，以形成与第二源/漏层1007和第一源/漏层1003的横向外边缘相互齐整的间隔层3001。
图9示意性示出了形成第一介电层的截面图。
如图9所示，在第一源/漏层1003上淀积生长第一介电层4001，然后将第一介电层4001回刻到预设高度。在回刻之前，可以对淀积生长的第一介电层4001表面进行化学机械抛光(Chemical Mechanical Polishing，CMP)。
其中，第一介电层4001的材料可以为氧化硅。该第一介电层4001的预设高度高于沟道层200的底面且低于紧邻沟道层200底面的下间隔层的顶面。
由此，第一介电层4001的高度设置有助于在去除假栅结构层2001后，在第一源/漏层1003与第二源/漏层1007之间形成自对准的栅极结构。
本公开实施例中，所谓“自对准”，并不一定意味着完全对准。“自对准”是指结构之间的相对位置，基本上不受工艺波动特别是光刻波 动的影响。这种自对准的结构是可检测的。例如，在集成电路(IC)中可以存在多个这样的器件，如果是自对准的结构，则各器件中低k电介质层和侧墙相对于沟道区端部的位置关系可以保持实质上不变；而如果不是自对准的结构，则这种相对位置关系在器件之间可以存在工艺波动。
图10示意性示出了形成栅介质层和栅导体层的截面图。
如图10所示，去除假栅结构层2001，在凹槽空间和第一介电层4001上表面淀积一层栅介质层3002，在栅介质层3002表面淀积栅导体层5001。
其中，栅介质层3002可以选用具有高介电常数的介电材料，例如HfO 2，厚度为约1nm～5nm。栅导体层5001可以大致共形的方式淀积形成于栅介质层3002表面，从而沿着栅介质层3002的表面延伸。另外，在淀积栅介质层3002之前，还可以形成例如氧化硅材料且厚度约为0.3nm～1.5nm的界面层(图中未示出)。
栅导体层5001可以包括功函数调节金属和栅导电金属。其中，功函数调节金属例如可以包括厚度例如为约1nm～10nm的TiN材料。栅导电金属例如可以包括厚度为约100nm～800nm的W材料。
由此，栅导体层5001可以填充各器件的有源区之间的空间。如此形成的栅堆叠(包括栅介质层3002和栅导体层5001)可以嵌入到第一源/漏层1003与第二源/漏层1007之间，栅堆叠至少形成于沟道层200的横向外周且嵌于上间隔层和下间隔层之间的凹槽空间。为控制刻蚀深度，最后还需对形成的栅堆叠进行回刻。
图11(a)示意性示出了在栅导体层上旋涂光刻胶的截面图。图11(b)示意性示出了刻蚀栅导体层的截面图。
如图11(a)所示，在栅导体层5001旋涂光刻胶500，形成栅极图形。
其中，光刻胶500例如通过光刻构图为覆盖栅导体层5001露于沟道层200所在的凹槽空间之外的一部分(在该示例中为图中左半 部)，且露出栅导体层5001露于沟道层200所在的凹槽空间之外的另一部分(在该示例中为图中右半部)。
然后，如11(b)所示，以构图后的光刻胶500为掩模，对栅导体层5001进行刻蚀如RIE，RIE可以沿竖直方向进行，然后去除光刻胶500。
由此，栅导体层5001除了保留于凹槽空间之内的部分之外，被光刻胶500遮挡的部分也得以保留。
图12示意性示出了形成金属接触部的截面图。
如图12所示，在栅介质层3002和栅导体层5001暴露于外的上表面上沉积第二介电层4002并进行化学机械抛光，分别在第一源/漏层1003、栅导体层5001和第二源/漏层1007上形成金属接触部。这些金属接触部可以通过在第二介电层4002以及第一介电层4001中刻蚀孔洞，并在其中填充导电材料例如金属来形成。
具体来说，第二介电层4002可以同第一介电层4001相同，也即第二介电层4002的材料也可以为氧化硅。金属接触部包括：在第一源/漏层1003上形成的第一源/漏极接触部6001，在栅导体层5001上形成的栅极接触部6002，以及在第二源/漏层1007上形成的第二源/漏极接触部6003。可以采用常规工艺来形成第一源/漏极接触部6001、栅极接触部6002和第二源/漏极接触部6003。
另外，由于栅导体层5001延伸超出有源区外周，从而可以容易地形成栅极接触部6002。同时，由于第一源/漏层1003的至少一部分上方并不存在栅导体层5001，从而可以容易地形成第一源/漏极接触部6001。
由此，制备完成本公开实施例的垂直MOSFET器件。本实施例的垂直MOSFET器件具有自对准侧墙的功能，利用不同晶面上外延生长速率不同的特点来形成假侧墙结构，在沟道方向上外延生长的速率相对较高。
根据本公开实施例的垂直MOSFET器件可以应用于各种电子设 备。例如，电子设备可以包括垂直MOSFET器件和处理器。垂直MOSFET器件可以存储电子设备操作所需或运行过程中得到的数据。处理器可以基于垂直MOSFET器件中存储的数据和/或应用而运行。这种电子设备例如智能电话、计算机、平板电脑(PC)、可穿戴智能设备、人工智能设备、移动电源等。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (24)

  1. 一种垂直MOSFET器件，包括：
    衬底；
    有源区，包括依次竖直叠置于所述衬底上的第一源/漏层(1003)、沟道层(200)和第二源/漏层(1007)，所述沟道层(200)的外周相对于第一源/漏层(1003)和第二源/漏层(1007)的外周凹入；
    间隔层(3001)，包括上间隔层和下间隔层，其中，所述上间隔层形成于因所述沟道层(200)凹入而露出的第二源/漏层(1007)的下表面，所述下间隔层形成于因所述沟道层(200)凹入而露出的所述第一源/漏层(1003)的上表面，所述上间隔层和所述下间隔层均与所述沟道层(200)的侧面接触且不连通；
    栅堆叠，至少形成于所述沟道层(200)的横向外周且嵌于所述上间隔层和所述下间隔层之间的凹槽空间。
  2. 根据权利要求1所述的垂直MOSFET器件，其中，所述第一源/漏层(1003)、沟道层(200)和第二源/漏层(1007)的厚度均为10nm～100nm。
  3. 根据权利要求1所述的垂直MOSFET器件，其中，所述栅堆叠包括栅介质层(3002)和栅导体层(5001)，所述栅导体层(5001)包括功函数调节金属和设置于所述功函数调节金属上的栅导电金属。
  4. 根据权利要求1所述的垂直MOSFET器件，还包括：
    第一介电层(4001)，设置于所述第一源/漏层(1003)上。
  5. 根据权利要求4所述的垂直MOSFET器件，其中，所述第一介电层(4001)高度高于所述沟道层(200)的底面且低于紧邻所述沟道层(200)底面的下间隔层的顶面。
  6. 根据权利要求4所述的垂直MOSFET器件，其中，所述栅介质层(3002)和栅导体层(5001)还部分设置于所述第一介电层(4001)上。
  7. 根据权利要求6所述的垂直MOSFET器件，其中，所述栅导体层(5001)露于所述凹槽空间之外的一部分，且露出所述凹槽空间之外的另一部分。
  8. 根据权利要求4所述的垂直MOSFET器件，还包括：
    第二介电层(4002)，设置于所述栅介质层(3002)和栅导体层(5001)上表面，所述第二介电层(4002)与第一介电层(4001)的材料相同。
  9. 根据权利要求1所述的垂直MOSFET器件，其中，所述间隔层(3001)相对于所述第一源/漏层(1003)和第二源/漏层(1007)的横向外边缘相互齐整。
  10. 根据权利要求1所述的垂直MOSFET器件，还包括：
    金属接触部，分别嵌入于所述第一源/漏层(1003)、栅导体层(5001)和第二源/漏层(1007)。
  11. 根据权利要求1所述的垂直MOSFET器件，其中，所述衬底为(110)晶面，所述沟道层为(001)晶面。
  12. 一种垂直MOSFET器件的制备方法，包括：
    在衬底上沿竖直方向依次形成包括第一源/漏层(1003)、沟道层(200)和第二源/漏层(1007)的有源区，所述沟道层(200)的外周相对于第一源/漏层(1003)和第二源/漏层(1007)的外周具有凹入部；
    在所述有源区的外表面覆盖虚拟结构层(1009)，选择性刻蚀所述虚拟结构层(1009)，使第一源/漏层(1003)的下表面和第二源/漏层(1007)的上表面分别保留有第二部分虚拟结构层(10092)，所述第二部分虚拟结构层(10092)从沟道层(200)的相对两侧夹着沟道层(200)；
    在第二部分虚拟结构层(10092)内壁与沟道层(200)外周构成的凹槽空间生长假栅结构层(2001)，将所述第二部分虚拟结构层(10092)替换为间隔层(3001)；
    在第一源/漏层(1003)上形成第一介电层(4001)，去除假栅结构层(2001)，在所述凹槽空间和第一介电层(4001)上形成栅介质层(3002)和栅导体层(5001)；
    选择性刻蚀栅导体层(5001)，分别在第一源/漏层(1003)、栅导体层(5001)和第二源/漏层(1007)上形成金属接触部；
    其中，所述虚拟结构层(1009)利用不同晶面的生长速率不同的特点形成。
  13. 根据权利要求12所述的制备方法，其中，设置所述有源区包括：
    在衬底上依次竖直形成包括第一源/漏层(1003)、沟道限定层(1005)和第二源/漏层(1007)的叠层；
    在所述叠层上形成光刻胶，以构图后的光刻胶为掩模，依次对所述叠层进行刻蚀，刻蚀停止于所述第一源/漏层(1003)中部；
    选择性刻蚀沟道限定层(1005)，使沟道限定层(1005)的外周相对于第一源/漏层(1003)和第二源/漏层(1007)的外周凹入，形成沟道层(200)。
  14. 根据权利要求12所述的制备方法，其中，所述第一源/漏层(1003)和第二源/漏层(1007)采用外延工艺，所述外延工艺的温度小于900℃。
  15. 根据权利要求12所述的制备方法，其中，所述虚拟结构层(1009)与沟道层(200)的材料均为SiGe，所述虚拟结构层(1009)中的Ge的组分高于所述沟道层(200)。
  16. 根据权利要求12所述的制备方法，其中，所述使第一源/漏层(1003)的下表面和第二源/漏层(1007)的上表面分别保留有第二部分虚拟结构层(10092)，包括：
    选择性刻蚀所述虚拟结构层(1009)，保留沿竖直方向上的第一部分虚拟结构层(10091)；
    选择性刻蚀所述第一部分虚拟结构层(10091)，保留所述沟道 层(200)凹入部的第二部分虚拟结构层(10092)。
  17. 根据权利要求12所述的制备方法，其中，所述假栅结构层(2001)的材料为SiC，所述间隔层(3001)为具有低介电常数的介电材料。
  18. 根据权利要求12所述的制备方法，其中，所述第一介电层(4001)的材料为氧化硅，所述在第一源/漏层(1003)上形成第一介电层(4001)，还包括：
    对所述第一介电层(4001)表面进行化学机械抛光；
    将所述第一介电层(4001)回刻到预设高度。
  19. 根据权利要求18所述的制备方法，其中，所述预设高度高于所述沟道层(200)的底面且低于紧邻所述沟道层(200)底面的间隔层(3001)的顶面。
  20. 根据权利要求12所述的制备方法，其中，所述在所述凹槽空间和第一介电层(4001)上形成栅介质层(3002)和栅导体层(5001)，包括：
    在所述凹槽空间和第一介电层(4001)上表面淀积栅介质层(3002)；
    在所述栅介质层(3002)表面淀积栅导体层(5001)；
    其中，所述栅介质层(3002)为具有高介电常数的介电材料，所述栅导体层(5001)包括功函数调节金属和栅导电金属。
  21. 根据权利要求12所述的制备方法，其中，所述选择性刻蚀栅导体层(5001)，包括：
    在所述栅导体层(5001)旋涂光刻胶(500)，所述光刻胶(500)通过光刻构图为覆盖所述栅导体层(5001)露于所述凹槽空间之外的一部分，且露出所述栅导体层(5001)露于所述凹槽空间之外的另一部分；
    以构图后的光刻胶(500)为掩模，对栅导体层(5001)进行刻蚀。
  22. 根据权利要求12所述的制备方法，其中，所述分别在第一源/漏层(1003)、栅导体层(5001)和第二源/漏层(1007)上形成金属接触部之前，还包括：
    在所述栅介质层(3002)和栅导体层(5001)上表面沉积第二介电层(4002)，所述第二介电层(4002)与第一介电层(4001)的材料相同；
    对第二介电层(4002)表面进行化学机械抛光。
  23. 一种电子设备，包括如权利要求1至11中任一项所述的垂直MOSFET器件。
  24. 根据权利要求23所述的电子设备，其中，所述电子设备包括智能电话、计算机、平板电脑、可穿戴智能设备、人工智能设备、移动电源。
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