WO2023087346A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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Publication number
WO2023087346A1
WO2023087346A1 PCT/CN2021/132868 CN2021132868W WO2023087346A1 WO 2023087346 A1 WO2023087346 A1 WO 2023087346A1 CN 2021132868 W CN2021132868 W CN 2021132868W WO 2023087346 A1 WO2023087346 A1 WO 2023087346A1
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WIPO (PCT)
Prior art keywords
auxiliary
signal lead
array substrate
common electrode
wiring
Prior art date
Application number
PCT/CN2021/132868
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English (en)
French (fr)
Inventor
刘倩
Original Assignee
Tcl华星光电技术有限公司
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Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to JP2021572924A priority Critical patent/JP2024503152A/ja
Publication of WO2023087346A1 publication Critical patent/WO2023087346A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133302—Rigid substrates, e.g. inorganic substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136272—Auxiliary lines

Definitions

  • the present application relates to the field of display technology, in particular to an array substrate and a liquid crystal display panel.
  • the common electrode and the pixel electrode jointly form a horizontal electric field, thereby realizing display.
  • the part where the pixel is used as the display area and allows the backlight to pass through to generate the three primary colors of red, green, and blue is called the opening area.
  • the electrodes for deflecting the liquid crystal in the opening area are usually designed in stripes.
  • the common electrode is arranged in a stripe shape and the pixel electrode is arranged in a stripe shape; when one electrode is designed in a stripe shape, the other electrode is designed to cover the entire surface of the opening area.
  • the display effect will be improved.
  • a new layer of auxiliary wiring is added on the common electrode.
  • the auxiliary wiring is easy to break, which affects the stability of the common electrode signal and further affects the display effect.
  • the present application provides an array substrate and a liquid crystal display panel, which can maintain the stability of the common electrode signal, thereby improving the display effect.
  • an array substrate which includes:
  • the common electrode is a planar electrode
  • the auxiliary wiring is arranged on the common electrode and contacts the common electrode;
  • a signal lead the signal lead includes a first signal lead and a second signal lead, the first signal lead is connected to the auxiliary wiring, and the second signal lead is connected to the common electrode.
  • the auxiliary routing includes a plurality of first auxiliary routings and a second auxiliary routing; the plurality of first auxiliary routings are arranged at intervals along the first direction, and each of the auxiliary routings The first auxiliary wiring extends along the second direction; each of the first auxiliary wiring is connected to the second auxiliary wiring, and the second auxiliary wiring is connected to the first signal lead.
  • the second auxiliary routing includes a first routing segment and a second routing segment
  • the first auxiliary routing includes a first end and a second end, the first end is connected to the first routing segment, and the second end is connected to the second routing segment.
  • the second auxiliary routing further includes a third routing segment and a fourth routing segment, and the first routing segment, the third routing segment, the second routing segment and The fourth routing segment is connected end to end in sequence.
  • the auxiliary routings further include a plurality of third auxiliary routings, and the plurality of third auxiliary routings are arranged at intervals along the second direction;
  • the third routing segment is connected to the first auxiliary routing adjacent to the third routing segment through a plurality of third auxiliary routings.
  • the auxiliary wirings further include a plurality of fourth auxiliary wirings, and the plurality of fourth auxiliary wirings are arranged at intervals along the second direction;
  • the fourth routing segment is connected to the first auxiliary routing adjacent to the fourth routing segment through a plurality of fourth auxiliary routings.
  • the second signal leads include a plurality of first sub-signal leads and a second sub-signal lead;
  • a plurality of the first sub-signal leads are arranged at intervals along the second direction, each of the first sub-signal leads extends along the first direction; each of the first sub-signal leads is connected to the The second sub signal lead is connected.
  • the second sub-signal lead includes a first part, a second part, a third part and a fourth part, and the first part, the third part, the second part and the The fourth part is connected end to end in sequence, and surrounds a plurality of the first sub-signal leads.
  • the array substrate includes a substrate sequentially stacked, a first metal layer including the first signal lead and the second signal lead, a first insulating layer, a second metal layer, A second insulating layer, a flat layer, a common electrode layer including the common electrode, an auxiliary wiring layer including the auxiliary wiring, a third insulating layer and a pixel electrode layer.
  • the array substrate is provided with a first via hole, a second via hole and a third via hole, the first via hole penetrates through the first insulating layer, and the second via hole penetrating through the third insulating layer, the third via hole penetrating through the third insulating layer, the auxiliary wiring layer, the common electrode layer, the planar layer and the second insulating layer;
  • the second metal layer includes a first connection metal, and the first connection metal extends into the first via hole;
  • the pixel electrode layer includes a first connection electrode, and the first connection electrode extends into the first via hole.
  • the auxiliary trace is connected to the first signal lead through the first connection electrode and the first connection metal.
  • the array substrate is provided with a fourth via hole, a fifth via hole and a sixth via hole, the fourth via hole penetrates through the first insulating layer, and the fifth via hole penetrating through the third insulating layer and the auxiliary wiring layer, the sixth via hole passing through the third insulating layer, the auxiliary wiring layer, the common electrode layer, the planar layer and the first Two insulating layers;
  • the second metal layer includes a second connection metal, and the second connection metal extends into the fourth via hole;
  • the pixel electrode layer includes a second connection electrode, and the second connection electrode extends into the first via hole.
  • the common electrode is connected to the second signal lead through the second connection electrode and the second connection metal.
  • the present application also provides a liquid crystal display panel, which includes:
  • a color filter substrate, the color filter substrate is arranged opposite to the array substrate;
  • liquid crystal layer is arranged between the array substrate and the color filter substrate;
  • the array substrate includes:
  • the common electrode is a planar electrode
  • the auxiliary wiring is arranged on the common electrode and contacts the common electrode;
  • a signal lead the signal lead includes a first signal lead and a second signal lead, the first signal lead is connected to the auxiliary wiring, and the second signal lead is connected to the common electrode.
  • the auxiliary wiring includes a plurality of first auxiliary wiring and a second auxiliary wiring; the plurality of first auxiliary wiring are arranged at intervals along the first direction, each The first auxiliary wiring extends along the second direction; each of the first auxiliary wiring is connected to the second auxiliary wiring, and the second auxiliary wiring is connected to the first signal lead .
  • the second auxiliary routing includes a first routing segment and a second routing segment
  • the first auxiliary routing includes a first end and a second end, the first end is connected to the first routing segment, and the second end is connected to the second routing segment.
  • the second auxiliary routing further includes a third routing segment and a fourth routing segment, and the first routing segment, the third routing segment, and the second routing segment and the fourth routing segment are connected end to end in sequence.
  • the auxiliary wirings further include a plurality of third auxiliary wirings, and the plurality of third auxiliary wirings are arranged at intervals along the second direction;
  • the third routing segment is connected to the first auxiliary routing adjacent to the third routing segment through a plurality of third auxiliary routings.
  • the auxiliary wirings further include a plurality of fourth auxiliary wirings, and the plurality of fourth auxiliary wirings are arranged at intervals along the second direction;
  • the fourth routing segment is connected to the first auxiliary routing adjacent to the fourth routing segment through a plurality of fourth auxiliary routings.
  • the second signal lead includes a plurality of first sub-signal leads and a second sub-signal lead;
  • a plurality of the first sub-signal leads are arranged at intervals along the second direction, each of the first sub-signal leads extends along the first direction; each of the first sub-signal leads is connected to the The second sub signal lead is connected.
  • the second sub-signal lead includes a first part, a second part, a third part and a fourth part, the first part, the third part, the second part and The fourth part is connected end to end in turn, and surrounds a plurality of the first sub-signal leads.
  • the array substrate includes a substrate sequentially stacked, a first metal layer including the first signal lead and the second signal lead, a first insulating layer, and a second metal layer. , a second insulating layer, a flat layer, a common electrode layer including the common electrode, an auxiliary wiring layer including the auxiliary wiring, a third insulating layer, and a pixel electrode layer.
  • the common electrode signal is only transmitted to the common electrode through a signal lead, and then the common electrode signal is transmitted to the auxiliary wiring through the common electrode;
  • Two signal leads, the common electrode signal is transmitted to the auxiliary wiring through the first signal lead and to the common electrode through the second signal lead; that is, the common electrode signal is transmitted to the auxiliary wiring and the common electrode through the unused signal lead respectively , can form multiple identical common electrode signal loops; when the auxiliary wiring is disconnected, the common electrode signal can be maintained through multiple paths, thereby ensuring the stability of the common electrode signal and improving the display effect.
  • FIG. 1 is a schematic diagram of the structure of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a first arrangement of auxiliary traces and first signal leads on an array substrate provided by an embodiment of the present application;
  • FIG. 3 is a schematic diagram of the arrangement of the second signal leads on the array substrate provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of a second arrangement of auxiliary wiring and first signal leads on the array substrate provided by the embodiment of the present application;
  • FIG. 5 is a schematic diagram of a third arrangement of auxiliary traces and first signal leads on the array substrate provided by the embodiment of the present application;
  • FIG. 6 is a schematic diagram of a structure of a liquid crystal display panel provided by an embodiment of the present application.
  • FIG. 1 is a schematic diagram of the structure of the array substrate provided by the embodiment of the present application.
  • the array substrate 100 of the embodiment of the present application includes a substrate 101 , a first metal layer 102 , a first insulating layer 103 , a second metal layer 104 , a second insulating layer 105 , a flat layer 106 , and a common electrode layer 107 , an auxiliary wiring layer 108 , a third insulating layer 109 and a pixel electrode layer 110 .
  • the substrate 101, the first metal layer 102, the first insulating layer 103, the second metal layer 104, the second insulating layer 105, the flat layer 106, the common electrode layer 107, the auxiliary wiring layer 108, the third insulating layer 109 and The pixel electrode layers 110 are stacked in sequence.
  • the first metal layer 102 includes a gate, a scan line, a first signal lead 1021 and a second signal lead 1022 .
  • the first metal layer 102 can be deposited on the substrate 101 through a deposition process, and then the gate, the scan line, the first signal lead 1021 and the second signal lead 1022 can be formed through a patterning process.
  • the first signal lead wire 1021 and the second signal lead wire 1022 in the embodiment of the present application are both used to access the common electrode signal.
  • the second metal layer 104 includes a source electrode, a drain electrode, a data line, a first connection metal 1041 and a second connection metal 1042 .
  • the second metal layer 104 can be deposited on the first insulating layer 103 through a deposition process, and then the source electrode, the drain electrode, the data line, the first connection metal 1041 and the second connection metal 1042 can be formed through a patterning process. .
  • the common electrode layer 107 includes a common electrode 1071 .
  • the common electrode layer 107 may be deposited on the planarization layer 106 through a deposition process.
  • the common electrode 1071 is a planar electrode provided on the entire surface. In the liquid crystal display panel, the common electrode and the pixel electrode jointly form a horizontal electric field, thereby realizing display. It should be noted that, in the case where the pixel electrodes are arranged in stripes and the common electrode 1071 is arranged to cover the entire opening area, in order to reduce the resistance of the common electrode 1071 and reduce the coupling effect caused by the signal disturbance of the scanning line and the data line, The auxiliary wiring 1081 is arranged on the common electrode 1071, so that the display effect can be improved.
  • the auxiliary wiring layer 108 includes auxiliary wiring 1081 .
  • the auxiliary wiring layer 108 can be deposited on the common electrode layer 107 through a deposition process, and then the auxiliary wiring 1081 can be formed through a patterning process. It can be understood that no insulating layer is provided between the auxiliary wiring layer 108 and the common electrode layer 107, and the auxiliary wiring layer 108 is in contact with the common electrode layer 107; The common electrode 1071 is in contact.
  • the pixel electrode layer 110 includes a pixel electrode, a first connection electrode 1101 and a second connection electrode 1102 .
  • the pixel electrode layer 110 can be deposited on the third insulating layer 109 through a deposition process, and then the pixel electrode, the first connection electrode 1101 and the second connection electrode 1102 can be formed through a patterning process.
  • the array substrate is provided with a first via hole 111 , a second via hole 112 , a third via hole 113 , a fourth via hole 114 , a fifth via hole 115 and a sixth via hole 116 .
  • the first via hole 111 penetrates through the first insulating layer 103 , and the first via hole 111 is correspondingly disposed directly above the first signal lead 1021 .
  • the second via hole 112 penetrates through the third insulating layer 109 , and the second via hole 112 is correspondingly disposed directly above the auxiliary trace 1081 .
  • the third via hole 113 runs through the third insulating layer 109, the auxiliary wiring layer 108, the common electrode layer 107, the planar layer 106 and the second insulating layer 105, and the third via hole 113 is correspondingly arranged directly above the first connecting metal 1041 .
  • the fourth via hole 114 penetrates through the first insulating layer 103 , and the fourth via hole 114 is correspondingly disposed directly above the second signal lead 1022 .
  • the fifth via hole 115 penetrates through the third insulating layer 109 and the auxiliary wiring layer 108 , and the fifth via hole 115 is correspondingly disposed directly above the common electrode 1071 .
  • the sixth via hole 116 runs through the third insulating layer 109 , the auxiliary wiring layer 108 , the common electrode layer 107 , the planar layer 106 and the second insulating layer 105 , and the sixth via hole 116 is correspondingly arranged directly above the second connecting metal 1042 .
  • the first connecting metal 1041 extends into the first via hole 111 .
  • the first connection electrode 1101 extends into the second via hole 112 and the third via hole 113 .
  • the auxiliary trace 1081 is connected to the first signal lead 1021 through the first connection electrode 1101 and the first connection metal 1041 .
  • the second connection metal 1042 extends into the fourth via hole 114 .
  • the second connection electrode 1102 extends into the fifth via hole 115 and the sixth via hole 116 .
  • the common electrode 1071 is connected to the second signal lead 1022 through the second connection electrode 1102 and the second connection metal 1042 .
  • the existing array substrate only transmits the common electrode signal to the common electrode through a signal lead, and then transmits the common electrode signal to the auxiliary wiring through the common electrode; that is, the existing array substrate transmits the common electrode signal to the auxiliary wiring. Only one path is provided to the common electrode and the auxiliary trace.
  • the array substrate 100 provided by the embodiment of the present application transmits the common electrode signal to the auxiliary wiring 1081 through the first signal lead 1021, and transmits the common electrode signal to the common electrode 1071 through the second signal lead 1022; that is, the present application In the array substrate 100 of the embodiment, there are two paths for transmitting the common electrode signal to the common electrode 1071 and the auxiliary wiring 1081 .
  • the paths for the array substrate 100 in the embodiment of the present application to transmit the common electrode signal to the common electrode 1071 and the auxiliary wiring 1081 include a first path and a second path.
  • the common electrode signal is transmitted to the auxiliary wiring 1081 and the common electrode 1071 respectively through different signal leads, and multiple identical common electrode signal loops can be formed; when the auxiliary wiring 1081 is disconnected, the common The electrode signal can be maintained through multiple paths to ensure the stability of the common electrode signal and improve the display effect.
  • FIG. 2 is a schematic diagram of a first arrangement of auxiliary traces and first signal leads on the array substrate provided by the embodiment of the present application.
  • the auxiliary wires 1081 include multiple first auxiliary wires 10811 , one second auxiliary wire 10812 , multiple third auxiliary wires 10813 and multiple fourth auxiliary wires 10814 .
  • a plurality of first auxiliary wires 10811 are arranged at intervals along the first direction, and each first auxiliary wire 10811 extends along the second direction.
  • Each first auxiliary wiring 10811 is connected to a second auxiliary wiring 10812 , and the second auxiliary wiring 10812 is connected to the first signal lead 1021 .
  • a plurality of third auxiliary wires 10813 are arranged at intervals along the second direction.
  • a plurality of fourth auxiliary wires 10814 are arranged at intervals along the second direction.
  • the first signal wire 1021 is connected to the auxiliary wire 1081 .
  • the second auxiliary routing 10812 includes a first routing segment 10812A, a second routing segment 10812B, a third routing segment 10812C and a fourth routing segment 10812D.
  • the first routing segment 10812A is opposite to the second routing segment 10812B.
  • the third routing segment 10812C is opposite to the fourth routing segment 10812D.
  • the first routing segment 10812A, the third routing segment 10812B, the second routing segment 10812C and the fourth routing segment 10812D are connected end to end in sequence.
  • Each first auxiliary wire 10811 includes a first end A and a second end B oppositely disposed.
  • the first end A is connected to the first routing segment 10812A, and the second end B is connected to the second routing segment 10812B.
  • the third routing segment 10812C is connected to the first auxiliary routing 10811 close to the third routing segment 10812C through a plurality of third auxiliary routings 10813 .
  • the fourth routing segment 10812D is connected to the first auxiliary routing 10811 close to the fourth routing segment 10812D through a plurality of fourth auxiliary routings 10814 .
  • auxiliary wiring 1081 and the first signal wiring 1021 are located on different layers, via holes need to be provided on the array substrate 100, so that the auxiliary wiring 1081 and the first signal wiring can be connected through the via holes.
  • Signal leads 1021 Those skilled in the art can reasonably arrange via holes on the array substrate according to needs, so as to connect the auxiliary wiring 1081 and the first signal lead 1021 .
  • FIG. 3 is a schematic diagram of the arrangement of the second signal leads on the array substrate provided by the embodiment of the present application.
  • the second signal lead 1022 includes a plurality of first sub-signal leads 10221 and a second sub-signal lead 10222 .
  • a plurality of first sub-signal leads 10221 are arranged at intervals along the second direction, and each first sub-signal lead 10221 extends along the first direction; each first sub-signal lead 10221 is connected to a second sub-signal lead 10222 .
  • the second sub signal lead 10222 is connected to the common electrode 1071 .
  • the second sub-signal lead 10222 includes a first part 10222A, a second part 10222B, a third part 10222C and a fourth part 10222D.
  • the first part 10222A, the third part 10222B, the second part 10222C and the fourth part 10222D are sequentially connected end to end, and are arranged around a plurality of first sub-signal leads 10221 .
  • a via hole needs to be provided on the array substrate 100, so that the common electrode 1071 and the second signal lead can be connected through the via hole.
  • Lead 1022 Those skilled in the art can properly arrange via holes on the array substrate 100 according to needs, so as to connect the common electrode 1071 and the second signal lead 1022 .
  • FIG. 4 is a schematic diagram of a second arrangement of the auxiliary traces and the first signal leads on the array substrate provided by the embodiment of the present application.
  • the difference between the array substrate 100 shown in FIG. 4 and the array substrate 100 shown in FIG. 2 is that the second auxiliary wiring 10812 on the array substrate 100 shown in FIG. 2 includes a first wiring segment 10812A, a second wiring segment 10812B, a third routing segment 10812C, and a fourth routing segment 10812D; the second auxiliary routing 10812 on the array substrate 100 shown in FIG. 4 includes a first routing segment 10812A and a second routing segment 10812B.
  • the array substrate 100 shown in FIG. 4 does not need to set the third wiring segment 10812C on the premise that the plurality of first auxiliary wiring lines 10811 are all connected to the second auxiliary wiring lines 10812 and the fourth wiring segment 10812D, so that the wiring space of the array substrate 100 can be improved.
  • FIG. 5 is a schematic diagram of a third arrangement of the auxiliary traces and the first signal leads on the array substrate provided by the embodiment of the present application.
  • the difference between the array substrate 100 shown in FIG. 5 and the array substrate 100 shown in FIG. 2 is that the auxiliary wiring 1081 on the array substrate 100 shown in FIG. Auxiliary wiring 10812, multiple third auxiliary wiring 10813 and multiple fourth auxiliary wiring 10814; the auxiliary wiring 1081 on the array substrate 100 shown in FIG. Auxiliary wiring 10812 and multiple third auxiliary wiring 10813.
  • the array substrate 100 shown in FIG. 5 can increase the wiring space of the array substrate 100 .
  • the common electrode signal is transmitted to the auxiliary wiring through the first signal lead and transmitted to the common electrode through the second signal lead; that is, the The common electrode signal is transmitted to the auxiliary wiring and the common electrode through unused signal leads, and multiple identical common electrode signal loops can be formed; when the auxiliary wiring is disconnected, the common electrode signal can be maintained through multiple paths, thereby Ensure the stability of the common electrode signal and improve the display effect.
  • FIG. 6 is a schematic diagram of the structure of the liquid crystal display panel provided by the embodiment of the present application.
  • the liquid crystal display panel 1000 provided in the embodiment of the present application includes an array substrate 1001 , and the array substrate 1001 includes the above-mentioned array substrate, a color filter substrate 1002 and a liquid crystal layer 1003 .
  • the liquid crystal layer 1003 is disposed between the array substrate 1001 and the color filter substrate 1002 .
  • the details of the array substrate 1001 can be referred to above.
  • the common electrode signal is transmitted to the auxiliary wiring through the first signal lead and transmitted to the common electrode through the second signal lead; that is, The common electrode signal is transmitted to the auxiliary wiring and the common electrode through unused signal leads, and multiple identical common electrode signal loops can be formed; when the auxiliary wiring is disconnected, the common electrode signal can be maintained through multiple paths. In this way, the stability of the common electrode signal is ensured, and the display effect is improved.

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Abstract

阵列基板(100)及液晶显示面板(1000)，通过设置第一信号引线(1021)及第二信号引线(1022)，将公共电极信号通过第一信号引线(1021)传至辅助走线(1081)及通过第二信号引线(1022)传至公共电极(1071)；当辅助走线(1081)断线时，公共电极信号可通过多条路径进行信号维持。

Description

阵列基板及液晶显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板及液晶显示面板。
 背景技术
在液晶显示面板中，公共电极与像素电极共同形成水平电场，从而实现显示。在像素作为显示区域、让背光通过从而产生红、绿、蓝三原色的部分称作开口区。为改善视角及提升显示效率，通常将开口区内让液晶偏转的电极设计成条纹状。通常有公共电极设置成条纹状、像素电极设置成条纹状两种设计情况；当一种电极为条纹状设计时，另一种电极为开口区整面性覆盖设计。
在像素电极设置成条纹状、公共电极为开口区整面性覆盖设计的情况，为降低公共电极的电阻、减小扫描线、数据线的信号扰动造成的耦合作用，从而提升显示效果，会在公共电极上新增一层辅助走线。然而，辅助走线容易断线，从而影响公共电极信号的稳定性，进而影响显示效果。
 技术问题
本申请提供一种阵列基板及液晶显示面板，可以维持公共电极信号的稳定性，从而提升显示效果。
 技术解决方案
第一方面，本申请提供一种阵列基板，其包括：
公共电极，所述公共电极为面状电极；
辅助走线，所述辅助走线设置在所述公共电极上，并与所述公共电极接触；
信号引线，所述信号引线包括第一信号引线及第二信号引线，所述第一信号引线与所述辅助走线连接，所述第二信号引线与所述公共电极连接。
在本申请提供的阵列基板中，所述辅助走线包括多条第一辅助走线及一第二辅助走线；多条所述第一辅助走线沿着第一方向间隔设置，每条所述第一辅助走线沿着第二方向延伸；每条所述第一辅助走线均与所述第二辅助走线连接，且所述第二辅助走线与所述第一信号引线连接。
在本申请提供的阵列基板中，所述第二辅助走线包括第一走线段及第二走线段；
所述第一辅助走线包括第一端部和第二端部，所述第一端部与所述第一走线段连接，所述第二端部与所述第二走线段连接。
在本申请提供的阵列基板中，所述第二辅助走线还包括第三走线段及第四走线段，且所述第一走线段、所述第三走线段、所述第二走线段及所述第四走线段首尾依次连接。
在本申请提供的阵列基板中，所述辅助走线还包括多条第三辅助走线，多条所述第三辅助走线沿着所述第二方向间隔设置；
所述第三走线段通过多条所述第三辅助走线与靠近所述第三走线段的所述第一辅助走线连接。
在本申请提供的阵列基板中，所述辅助走线还包括多条第四辅助走线，多条所述第四辅助走线沿着所述第二方向间隔设置；
所述第四走线段通过多条所述第四辅助走线与靠近所述第四走线段的所述第一辅助走线连接。
在本申请提供的阵列基板中，所述第二信号引线包括多条第一子信号引线及一第二子信号引线；
多条所述第一子信号引线沿着所述第二方向间隔设置，每条所述第一子信号引线沿着所述第一方向延伸；每条所述第一子信号引线均与所述第二子信号引线连接。
在本申请提供的阵列基板中，所述第二子信号引线包括第一部分、第二部分、第三部分及第四部分，所述第一部分、所述第三部分、所述第二部分及所述第四部分首尾依次连接，且围绕多条所述第一子信号引线。
在本申请提供的阵列基板中，所述阵列基板包括依次层叠设置的基板、包括所述第一信号引线和所述第二信号引线的第一金属层、第一绝缘层、第二金属层、第二绝缘层、平坦层、包括所述公共电极的公共电极层、包括所述辅助走线的辅助走线层、第三绝缘层及像素电极层。
在本申请提供的阵列基板中，所述阵列基板设置有第一过孔、第二过孔及第三过孔，所述第一过孔贯穿所述第一绝缘层，所述第二过孔贯穿所述第三绝缘层，所述第三过孔贯穿所述第三绝缘层、所述辅助走线层、所述公共电极层、所述平坦层及所述第二绝缘层；
所述第二金属层包括第一连接金属，所述第一连接金属延伸至所述第一过孔内；所述像素电极层包括第一连接电极，所述第一连接电极延伸至所述第二过孔及所述第三过孔内；所述辅助走线通过所述第一连接电极及所述第一连接金属与所述第一信号引线连接。
在本申请提供的阵列基板中，所述阵列基板设置有第四过孔、第五过孔及第六过孔，所述第四过孔贯穿所述第一绝缘层，所述第五过孔贯穿所述第三绝缘层及所述辅助走线层，所述第六过孔贯穿所述第三绝缘层、所述辅助走线层、所述公共电极层、所述平坦层及所述第二绝缘层；
所述第二金属层包括第二连接金属，所述第二连接金属延伸至所述第四过孔内；所述像素电极层包括第二连接电极，所述第二连接电极延伸至所述第五过孔及所述第六过孔内；所述公共电极通过所述第二连接电极及所述第二连接金属与所述第二信号引线连接。
第二方面，本申请还提供一种液晶显示面板，其包括：
阵列基板；
彩膜基板，所述彩膜基板与所述阵列基板相对设置；及
液晶层，所述液晶层设置在所述阵列基板与所述彩膜基板之间；
所述阵列基板包括：
公共电极，所述公共电极为面状电极；
辅助走线，所述辅助走线设置在所述公共电极上，并与所述公共电极接触；
信号引线，所述信号引线包括第一信号引线及第二信号引线，所述第一信号引线与所述辅助走线连接，所述第二信号引线与所述公共电极连接。
在本申请提供的液晶显示面板中，所述辅助走线包括多条第一辅助走线及一第二辅助走线；多条所述第一辅助走线沿着第一方向间隔设置，每条所述第一辅助走线沿着第二方向延伸；每条所述第一辅助走线均与所述第二辅助走线连接，且所述第二辅助走线与所述第一信号引线连接。
在本申请提供的液晶显示面板中，所述第二辅助走线包括第一走线段及第二走线段；
所述第一辅助走线包括第一端部和第二端部，所述第一端部与所述第一走线段连接，所述第二端部与所述第二走线段连接。
在本申请提供的液晶显示面板中，所述第二辅助走线还包括第三走线段及第四走线，且所述第一走线段、所述第三走线段、所述第二走线段及所述第四走线段首尾依次连接。
在本申请提供的液晶显示面板中，所述辅助走线还包括多条第三辅助走线，多条所述第三辅助走线沿着所述第二方向间隔设置；
所述第三走线段通过多条所述第三辅助走线与靠近所述第三走线段的所述第一辅助走线连接。
在本申请提供的液晶显示面板中，所述辅助走线还包括多条第四辅助走线，多条所述第四辅助走线沿着所述第二方向间隔设置；
所述第四走线段通过多条所述第四辅助走线与靠近所述第四走线段的所述第一辅助走线连接。
在本申请提供的液晶显示面板中，所述第二信号引线包括多条第一子信号引线及一第二子信号引线；
多条所述第一子信号引线沿着所述第二方向间隔设置，每条所述第一子信号引线沿着所述第一方向延伸；每条所述第一子信号引线均与所述第二子信号引线连接。
在本申请提供的液晶显示面板中，所述第二子信号引线包括第一部分、第二部分、第三部分及第四部分，所述第一部分、所述第三部分、所述第二部分及所述第四部分首尾依次连接，且围绕多条所述第一子信号引线。
在本申请提供的液晶显示面板中，所述阵列基板包括依次层叠设置的基板、包括所述第一信号引线和所述第二信号引线的第一金属层、第一绝缘层、第二金属层、第二绝缘层、平坦层、包括所述公共电极的公共电极层、包括所述辅助走线的辅助走线层、第三绝缘层及像素电极层。
 有益效果
现有技术仅仅通过一条信号引线将公共电极信号传至公共电极，再通过公共电极将公共电极信号传至辅助走线；本申请提供的阵列基板及液晶显示面板，通过设置第一信号引线及第二信号引线，将公共电极信号通过第一信号引线传至辅助走线及通过第二信号引线传至公共电极；也即，将公共电极信号通过不用的信号引线分别传至辅助走线及公共电极，可以形成多个相同的公共电极信号回路；当辅助走线断线时，公共电极信号可通过多条路径进行信号维持，从而保证公共电极信号的稳定性，提升显示效果。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的阵列基板的结构的示意图；
图2为本申请实施例提供的阵列基板上的辅助走线及第一信号引线的第一种排布方式的示意图；
图3为本申请实施例提供的阵列基板上的第二信号引线排布方式的示意图；
图4为本申请实施例提供的阵列基板上的辅助走线及第一信号引线的第二种排布方式的示意图；
图5为本申请实施例提供的阵列基板上的辅助走线及第一信号引线的第三种排布方式的示意图；
图6为本申请实施例提供的液晶显示面板的结构的示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。本申请的权利要求书及说明书中的术语“第一”、“第二”、“第三”、“第四”、“第五”、“第六”等是用于区别不同对象，而不是用于描述特定顺序。
请参阅图1，图1为本申请实施例提供的阵列基板的结构的示意图。如图1所示，本申请实施例的阵列基板100包括基板101、第一金属层102、第一绝缘层103、第二金属层104、第二绝缘层105、平坦层106、公共电极层107、辅助走线层108、第三绝缘层109及像素电极层110。其中，基板101、第一金属层102、第一绝缘层103、第二金属层104、第二绝缘层105、平坦层106、公共电极层107、辅助走线层108、第三绝缘层109及像素电极层110依次层叠设置。
其中，第一金属层102包括栅极、扫描线、第一信号引线1021及第二信号引线1022。在工艺过程中，可通过沉积工艺先在基板101上沉积第一金属层102，再经过图案化工艺形成栅极、扫描线、第一信号引线1021及第二信号引线1022。需要说明的是，本申请实施例中的第一信号引线1021及第二信号引线1022均用于接入公共电极信号。
其中，第二金属层104包括源极、漏极、数据线、第一连接金属1041及第二连接金属1042。在工艺过程中，可通过沉积工艺先在第一绝缘层103上沉积第二金属层104，再经过图案化工艺形成源极、漏极、数据线、第一连接金属1041及第二连接金属1042。
其中，公共电极层107包括公共电极1071。在工艺过程中，可通过沉积工艺在平坦层106上沉积公共电极层107。公共电极1071为整面设置的面状电极。在液晶显示面板中，公共电极与像素电极共同形成水平电场，从而实现显示。需要说明的是，在像素电极设置成条纹状、公共电极1071设置成开口区整面性覆盖的情况，为降低公共电极1071的电阻、减小扫描线、数据线的信号扰动造成的耦合作用，在公共电极1071上设置辅助走线1081，从而可以提升显示效果。
其中，辅助走线层108包括辅助走线1081。在工艺过程中，可通过沉积工艺先在公共电极层107沉积辅助走线层108，再经过图案化工艺形成辅助走线1081。可以理解的，辅助走线层108与公共电极层107之间并未设置绝缘层，辅助走线层108与公共电极层107接触；也即，辅助走线1081设置在公共电极1071上，并与公共电极1071接触。
其中，像素电极层110包括像素电极、第一连接电极1101及第二连接电极1102。在工艺过程中，可通过沉积工艺在第三绝缘层109上沉积像素电极层110，再经过图案化工艺形成像素电极、第一连接电极1101及第二连接电极1102。
具体的，请继续参阅图1，阵列基板设置有第一过孔111、第二过孔112、第三过孔113、第四过孔114、第五过孔115及第六过孔116。第一过孔111贯穿第一绝缘层103，且第一过孔111对应设置在第一信号引线1021的正上方。第二过孔112贯穿第三绝缘层109，且第二过孔112对应设置在辅助走线1081的正上方。第三过孔113贯穿第三绝缘层109、辅助走线层108、公共电极层107、平坦层106及第二绝缘层105，且第三过孔113对应设置在第一连接金属1041的正上方。第四过孔114贯穿第一绝缘层103，且第四过孔114对应设置在第二信号引线1022的正上方。第五过孔115贯穿第三绝缘层109及辅助走线层108，且第五过孔115对应设置在公共电极1071的正上方。第六过孔116贯穿第三绝缘层109、辅助走线层108、公共电极层107、平坦层106及第二绝缘层105，且第六过孔116对应设置在第二连接金属1042的正上方。
其中，第一连接金属1041延伸至第一过孔111内。第一连接电极1101延伸至第二过孔112及第三过孔113内。辅助走线1081通过第一连接电极1101及第一连接金属1041与第一信号引线1021连接。第二连接金属1042延伸至第四过孔114内。第二连接电极1102延伸至第五过孔115及第六过孔116内。公共电极1071通过第二连接电极1102及第二连接金属1042与第二信号引线1022连接。
可以理解的，现有的阵列基板仅仅通过一条信号引线将公共电极信号传至公共电极，再通过公共电极将公共电极信号传至辅助走线；也即，现有的阵列基板将公共电极信号传至公共电极及辅助走线上仅设置一条路径。而本申请实施例提供的阵列基板100通过第一信号引线1021将公共电极信号传至辅助走线1081上，通过第二信号引线1022将公共电极信号传至公共电极1071上；也即，本申请实施例的阵列基板100将公共电极信号传至公共电极1071及辅助走线1081上设置有两条路径。
其中，本申请实施例的阵列基板100将公共电极信号传至公共电极1071及辅助走线1081上的路径包括第一路径和第二路径。第一路径：公共电极信号依次经第一信号引线1021、第一连接金属1041及第一连接电极1101传至辅助走线1081上；第二路径：公共电极信号依次经第二信号引线1022、第二连接金属1042及第二连接电极1102传至公共电极1071上。也即，本申请实施例将公共电极信号通过不同的信号引线分别传至辅助走线1081及公共电极1071上，可以形成多个相同的公共电极信号回路；当辅助走线1081断线时，公共电极信号可通过多条路径进行信号维持，从而保证公共电极信号的稳定性，提升显示效果。
进一步的，请参阅2，图2为本申请实施例提供的阵列基板上的辅助走线及第一信号引线的第一种排布方式的示意图。结合图1、图2所示，辅助走线1081包括多条第一辅助走线10811、一条第二辅助走线10812、多条第三辅助走线10813及多条第四辅助走线10814。多条第一辅助走线10811沿着第一方向间隔设置，每条第一辅助走线10811沿着第二方向延伸。每条第一辅助走线10811均与第二辅助走线10812连接，且第二辅助走线10812与第一信号引线1021连接。多条第三辅助走线10813沿着第二方向间隔设置。多条第四辅助走线10814沿着第二方向间隔设置。第一信号引线1021与辅助走线1081连接。
其中，第二辅助走线10812包括第一走线段10812A、第二走线段10812B、第三走线段10812C及第四走线段10812D。第一走线段10812A与第二走线段10812B相对设置。第三走线段10812C与第四走线段10812D相对设置。第一走线段10812A、第三走线段10812B、第二走线段10812C及第四走线段10812D首尾依次连接。每条第一辅助走线10811均包括相对设置的第一端部A和第二端部B。第一端部A与第一走线段10812A连接，第二端部B与第二走线段连接10812B。第三走线段10812C通过多条第三辅助走线10813与靠近第三走线段10812C的第一辅助走线10811连接。第四走线段10812D通过多条第四辅助走线10814与靠近第四走线段10812D的第一辅助走线10811连接。
需要说明的是，在申请实施例中，由于辅助走线1081与第一信号引线1021位于不同层，故在阵列基板100上需设置过孔，从而可以通过过孔连接辅助走线1081及第一信号引线1021。本领域技术人员可以根据需要在阵列基板上合理设置过孔，以连接辅助走线1081及第一信号引线1021。
进一步的，请参阅3，图3为本申请实施例提供的阵列基板上的第二信号引线排布方式的示意图。结合图1、图3所示，第二信号引线1022包括多条第一子信号引线10221及一第二子信号引线10222。多条第一子信号引线10221沿着第二方向间隔设置，每条第一子信号引线10221沿着第一方向延伸；每条第一子信号引线10221均与第二子信号引线10222连接。第二子信号引线10222与公共电极1071连接。
其中，第二子信号引线10222包括第一部分10222A、第二部分10222B、第三部分10222C及第四部分10222D。第一部分10222A、第三部分10222B、第二部分10222C及第四部分10222D首尾依次连接，且围绕多条第一子信号引线10221设置。
需要说明的是，在本申请实施例中，由于公共电极1071与第二信号引线1022位于不同层，故在阵列基板100上需设置过孔，从而可以通过过孔连接公共电极1071及第二信号引线1022。本领域技术人员可以根据需要在阵列基板100上合理设置过孔，以连接公共电极1071及第二信号引线1022。
请参阅图4，图4为本申请实施例提供的阵列基板上的辅助走线及第一信号引线的第二种排布方式的示意图。其中，图4所示的阵列基板100与图2所示的阵列基板100的区别在于：图2所示的阵列基板100上的第二辅助走线10812包括第一走线段10812A、第二走线段10812B、第三走线段10812C及第四走线段10812D；图4所示的阵列基板100上的第二辅助走线10812包括第一走线段10812A及第二走线段10812B。
相较于图2所示的阵列基板，图4所示的阵列基板100在保证多条第一辅助走线10811均与第二辅助走线10812连接的前提，并不需要设置第三走线段10812C及第四走线段10812D，从而可以提升阵列基板100的布线空间。
请参阅图5，图5为本申请实施例提供的阵列基板上的辅助走线及第一信号引线的第三种排布方式的示意图。其中，图5所示的阵列基板100与图2所示的阵列基板100的区别在于：图2所示的阵列基板100上的辅助走线1081包括多条第一辅助走线10811、一条第二辅助走线10812、多条第三辅助走线10813及多条第四辅助走线10814；图5所示的阵列基板100上的辅助走线1081包括多条第一辅助走线10811、一条第二辅助走线10812及多条第三辅助走线10813。相较于图2所示的阵列基板100，图5所示的阵列基板100可以提升阵列基板100的布线空间。
本申请实施例提供的阵列基板，通过设置第一信号引线及第二信号引线，将公共电极信号通过第一信号引线传至辅助走线及通过第二信号引线传至公共电极；也即，将公共电极信号通过不用的信号引线分别传至辅助走线及公共电极，可以形成多个相同的公共电极信号回路；当辅助走线断线时，公共电极信号可通过多条路径进行信号维持，从而保证公共电极信号的稳定性，提升显示效果。
请阅图6，图6为本申请实施例提供的液晶显示面板的结构的示意图。本申请实施例提供的液晶显示面板1000包括阵列基板1001，阵列基板1001包括以上所述的阵列基板、彩膜基板1002以及液晶层1003。液晶层1003设置在阵列基板1001和彩膜基板1002之间。阵列基板1001具体可参照以上所述。
本申请实施例提供的液晶显示面板，通过设置第一信号引线及第二信号引线，将公共电极信号通过第一信号引线传至辅助走线及通过第二信号引线传至公共电极；也即，将公共电极信号通过不用的信号引线分别传至辅助走线及公共电极，可以形成多个相同的公共电极信号回路；当辅助走线断线时，公共电极信号可通过多条路径进行信号维持，从而保证公共电极信号的稳定性，提升显示效果。
以上对本申请实施例所提供的阵列基板及液晶显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其包括：
    公共电极，所述公共电极为面状电极；
    辅助走线，所述辅助走线设置在所述公共电极上，并与所述公共电极接触；
    信号引线，所述信号引线包括第一信号引线及第二信号引线，所述第一信号引线与所述辅助走线连接，所述第二信号引线与所述公共电极连接。
  2. 根据权利要求1所述的阵列基板，其中，所述辅助走线包括多条第一辅助走线及一第二辅助走线；多条所述第一辅助走线沿着第一方向间隔设置，每条所述第一辅助走线沿着第二方向延伸；每条所述第一辅助走线均与所述第二辅助走线连接，且所述第二辅助走线与所述第一信号引线连接。
  3. 根据权利要求2所述的阵列基板，其中，所述第二辅助走线包括第一走线段及第二走线段；
    所述第一辅助走线包括第一端部和第二端部，所述第一端部与所述第一走线段连接，所述第二端部与所述第二走线段连接。
  4. 根据权利要求3所述的阵列基板，其中，所述第二辅助走线还包括第三走线段及第四走线，且所述第一走线段、所述第三走线段、所述第二走线段及所述第四走线段首尾依次连接。
  5. 根据权利要求4所述的阵列基板，其中，所述辅助走线还包括多条第三辅助走线，多条所述第三辅助走线沿着所述第二方向间隔设置；
    所述第三走线段通过多条所述第三辅助走线与靠近所述第三走线段的所述第一辅助走线连接。
  6. 根据权利要求5所述的阵列基板，其中，所述辅助走线还包括多条第四辅助走线，多条所述第四辅助走线沿着所述第二方向间隔设置；
    所述第四走线段通过多条所述第四辅助走线与靠近所述第四走线段的所述第一辅助走线连接。
  7. 根据权利要求1所述的阵列基板，其中，所述第二信号引线包括多条第一子信号引线及一第二子信号引线；
    多条所述第一子信号引线沿着所述第二方向间隔设置，每条所述第一子信号引线沿着所述第一方向延伸；每条所述第一子信号引线均与所述第二子信号引线连接。
  8. 根据权利要求7所述的阵列基板，其中，所述第二子信号引线包括第一部分、第二部分、第三部分及第四部分，所述第一部分、所述第三部分、所述第二部分及所述第四部分首尾依次连接，且围绕多条所述第一子信号引线。
  9. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括依次层叠设置的基板、包括所述第一信号引线和所述第二信号引线的第一金属层、第一绝缘层、第二金属层、第二绝缘层、平坦层、包括所述公共电极的公共电极层、包括所述辅助走线的辅助走线层、第三绝缘层及像素电极层。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板设置有第一过孔、第二过孔及第三过孔，所述第一过孔贯穿所述第一绝缘层，所述第二过孔贯穿所述第三绝缘层，所述第三过孔贯穿所述第三绝缘层、所述辅助走线层、所述公共电极层、所述平坦层及所述第二绝缘层；
    所述第二金属层包括第一连接金属，所述第一连接金属延伸至所述第一过孔内；所述像素电极层包括第一连接电极，所述第一连接电极延伸至所述第二过孔及所述第三过孔内；所述辅助走线通过所述第一连接电极及所述第一连接金属与所述第一信号引线连接。
  11. 根据权利要求9所述的阵列基板，其中，所述阵列基板设置有第四过孔、第五过孔及第六过孔，所述第四过孔贯穿所述第一绝缘层，所述第五过孔贯穿所述第三绝缘层及所述辅助走线层，所述第六过孔贯穿所述第三绝缘层、所述辅助走线层、所述公共电极层、所述平坦层及所述第二绝缘层；
    所述第二金属层包括第二连接金属，所述第二连接金属延伸至所述第四过孔内；所述像素电极层包括第二连接电极，所述第二连接电极延伸至所述第五过孔及所述第六过孔内；所述公共电极通过所述第二连接电极及所述第二连接金属与所述第二信号引线连接。
  12. 一种液晶显示面板，其包括：
    阵列基板；
    彩膜基板，所述彩膜基板与所述阵列基板相对设置；及
    液晶层，所述液晶层设置在所述阵列基板与所述彩膜基板之间；
    所述阵列基板包括：
    公共电极，所述公共电极为面状电极；
    辅助走线，所述辅助走线设置在所述公共电极上，并与所述公共电极接触；
    信号引线，所述信号引线包括第一信号引线及第二信号引线，所述第一信号引线与所述辅助走线连接，所述第二信号引线与所述公共电极连接。
  13. 根据权利要求12所述的液晶显示面板，其中，所述辅助走线包括多条第一辅助走线及一第二辅助走线；多条所述第一辅助走线沿着第一方向间隔设置，每条所述第一辅助走线沿着第二方向延伸；每条所述第一辅助走线均与所述第二辅助走线连接，且所述第二辅助走线与所述第一信号引线连接。
  14. 根据权利要求13所述的液晶显示面板，其中，所述第二辅助走线包括第一走线段及第二走线段；
    所述第一辅助走线包括第一端部和第二端部，所述第一端部与所述第一走线段连接，所述第二端部与所述第二走线段连接。
  15. 根据权利要求14所述的液晶显示面板，其中，所述第二辅助走线还包括第三走线段及第四走线，且所述第一走线段、所述第三走线段、所述第二走线段及所述第四走线段首尾依次连接。
  16. 根据权利要求15所述的液晶显示面板，其中，所述辅助走线还包括多条第三辅助走线，多条所述第三辅助走线沿着所述第二方向间隔设置；
    所述第三走线段通过多条所述第三辅助走线与靠近所述第三走线段的所述第一辅助走线连接。
  17. 根据权利要求16所述的液晶显示面板，其中，所述辅助走线还包括多条第四辅助走线，多条所述第四辅助走线沿着所述第二方向间隔设置；
    所述第四走线段通过多条所述第四辅助走线与靠近所述第四走线段的所述第一辅助走线连接。
  18. 根据权利要求12所述的液晶显示面板，其中，所述第二信号引线包括多条第一子信号引线及一第二子信号引线；
    多条所述第一子信号引线沿着所述第二方向间隔设置，每条所述第一子信号引线沿着所述第一方向延伸；每条所述第一子信号引线均与所述第二子信号引线连接。
  19. 根据权利要求18所述的液晶显示面板，其中，所述第二子信号引线包括第一部分、第二部分、第三部分及第四部分，所述第一部分、所述第三部分、所述第二部分及所述第四部分首尾依次连接，且围绕多条所述第一子信号引线。
  20. 根据权利要求12所述的液晶显示面板，其中，所述阵列基板包括依次层叠设置的基板、包括所述第一信号引线和所述第二信号引线的第一金属层、第一绝缘层、第二金属层、第二绝缘层、平坦层、包括所述公共电极的公共电极层、包括所述辅助走线的辅助走线层、第三绝缘层及像素电极层。
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