WO2023071007A1 - 脉宽时钟拓扑结构电路 - Google Patents

脉宽时钟拓扑结构电路 Download PDF

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WO2023071007A1
WO2023071007A1 PCT/CN2022/078669 CN2022078669W WO2023071007A1 WO 2023071007 A1 WO2023071007 A1 WO 2023071007A1 CN 2022078669 W CN2022078669 W CN 2022078669W WO 2023071007 A1 WO2023071007 A1 WO 2023071007A1
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clock
delay
pulse width
module
topology
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PCT/CN2022/078669
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English (en)
French (fr)
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姜晓伟
包兴刚
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上海亿家芯集成电路设计有限公司
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Priority to US18/278,515 priority Critical patent/US20240137011A1/en
Priority to EP22884924.6A priority patent/EP4283874A1/en
Publication of WO2023071007A1 publication Critical patent/WO2023071007A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay

Definitions

  • the invention relates to a pulse width clock topological structure circuit, which is suitable for chips of CPU, GPU, asynchronous operation core unit module and DSP operation module.
  • Edge-triggered register units are widely used.
  • Edge-triggered registers are mainly composed of 2-stage latches (DFF).
  • DFF 2-stage latches
  • the edge trigger has the advantages of anti-noise effect, anti-glitch, not easy to lose stored data, simple timing design and perfect test verification method.
  • the disadvantages are low integration, area, power consumption and performance that cannot meet the requirements of high-performance circuits.
  • the latch By controlling the clock to achieve a "micro" width high or low level (that is, pulse clock), the latch (Latch) works in an “edge-triggered” manner, thereby solving the power consumption and performance of the flip-flop And area (PPA) issues to meet the chip design with high design requirements.
  • PPA flip-flop And area
  • the object of the present invention is to provide a pulse width clock topology circuit to solve the problems raised in the above background technology.
  • the present invention provides the following technical solutions:
  • a pulse width clock topology circuit comprising: a clock pulse width generation module and a clock topology delay module;
  • the clock pulse width generation module connects n-level delay sub-modules serially to the input clock, and the output end of each delay sub-module is connected to the input end of the selector, and the required m+1 control signals are selected by the selector.
  • the delay sub-module delays for a certain time, and the certain delay time of each delay sub-module may be equal or unequal.
  • the delay sub-module includes an odd number of inverters and several buffers, wherein the inverters and buffers are connected to each other or alternately connected.
  • the total delay of the n-stage delay sub-modules is less than the pulse width of the input clock.
  • the input terminal of the first stage of the n-level delay sub-module is connected to the original input clock, and the input terminal of the second level to the n-level of the n-level delay sub-module is connected to the previous stage delay sub-module output of the module.
  • the output terminal of the selector performs "AND" operation with the original input clock to generate clocks with different pulse widths as required.
  • the clock topology delay module consists of clock signals with different delays to form a topology structure.
  • the delay time of each latch of the clock topology delay module is consistent, so as to achieve the clock balance function.
  • the beneficial effect of the present invention is that the pulse width clock topology circuit has higher performance.
  • the pulse width clock topology circuit can effectively control the delay rate of the clock, so that each input clock has a certain delay to meet the stringent requirements of the pulse width for signal integrity.
  • Fig. 1 is a schematic diagram of a pulse width clock topology circuit as a first embodiment of the present invention
  • FIG. 2 is a schematic diagram of a pulse width clock topology circuit as a second embodiment of the present invention.
  • Fig. 3 is a schematic diagram of a clock pulse width generation module and a clock topology delay module of the pulse width clock topology circuit of the present invention.
  • a pulse width clock topology circuit includes: a clock pulse width generation module and a clock topology delay module.
  • the clock pulse width generation module performs serial connection of n-level delay sub-modules (Delay) to the input clock, and the output end of each delay sub-module is connected to the input end of the selector (MUX), and the m +1 control signal to select a certain delay clock required, and perform "AND" operation with the original input clock (CI) to generate different pulse width clock outputs, and as the input of the clock topology delay module,
  • the clock topology delay module can generate multiple different delayed clocks for use by different latches, where n>1, and 2 (m+1) ⁇ n.
  • the delay sub-module (Delay) delays for a certain time, and the certain time delayed by each delay sub-module (Delay) may be equal or unequal.
  • the delay sub-module includes an odd number of inverters (N) and several buffers (Buffer), wherein the inverters and buffers are connected to each other or alternately connected.
  • the total delay of the n-level delay sub-module (Delay) is less than the pulse width of the input clock.
  • the input terminal of the first stage of the n-level delay sub-module is connected to the original input clock (CI), from the second level to the n-level of the n-level delay sub-module (Delay)
  • the input terminal of is connected to the output terminal of the delay sub-module (Delay) of the previous stage.
  • the output terminal of the selector performs "AND” (AND) operation with the original input clock to generate required clocks with different pulse widths.
  • the clock topology delay module consists of clock signals (Cnt0, Cnt1...Cntx) with different delays to form a topology.
  • the delay time of each latch of the clock topology delay module is the same, so as to achieve the clock balance function.
  • the clock pulse width generation module performs n-level delay sub-module (Delay) serial connection to the original input clock (CI), wherein the delay sub-module has a specific delay function, and is composed of an odd number of inverters (N) and several Buffers are connected to each other or alternately connected.
  • the output end of each delay sub-module is output to the input end of the selector (MUX), and a certain delay clock is selected through the m+1 control signals of the selector (MUX), and is compared with the original input clock (CI) performs "AND" operation to generate different pulse width clock outputs, and as the input of the clock topology delay module, the clock topology delay module can generate x different delayed clocks.
  • the pulse width clock topology circuit can effectively control the delay rate of the clock, so that each input clock has a certain delay, so as to meet the stringent requirements of the pulse width for signal integrity.
  • Figure 1 shows a relatively simple first embodiment.
  • the output terminals (Cnt0, Cnt1...Cntx) of the topology clock connect the required y (C11, C21..Cy1) clock signals to the x output terminals of the topology clock (and x ⁇ y), among which y ( C11, C21..Cy1) clock signals are respectively provided to the latches (LAT#) that require different delay clocks.
  • Figure 2 shows a second, relatively complex embodiment.
  • One or more of the output terminals (Cnt0, Cnt1...Cntx) of the topology clock (PG module) are connected to the required y (C11, C21..Cy1) clock signals, of which y (C11, C21.. Cy1) clock signals are respectively provided to the latches (LAT#) that require different delay clocks.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

一种脉宽时钟拓扑结构电路，包括：时钟脉宽生成模块和时钟拓扑延时模块。时钟脉宽生成模块将输入时钟与n级延时子模块串行连接，每级延时子模块的输出端连接到选择器的输入端，通过选择器的m+1个控制信号选择所需的某一延时时钟，并且与原输入时钟进行"与"操作来生成不同的脉宽时钟输出，并且作为时钟拓扑延时模块的输入，时钟拓扑延时模块可产生多个不同的延时时钟以供不同的锁存器使用。

Description

脉宽时钟拓扑结构电路 技术领域
本发明涉及一种脉宽时钟拓扑结构电路，适用于CPU、GPU、异步运算核心单元模块及DSP运算模块的芯片。
背景技术
凡数字电路设计，广泛应用沿触发的寄存器单元。沿触发的寄存器主要是2级锁存器构成(DFF)。沿触发器具有抗噪效、抗毛刺、存储数据不易丢失、时序设计简单和测试验证方法完善等优点。然而，缺点方面表现在集成度低、面积、功耗和性能无法满足高性能电路的要求。
通过控制时钟来实现“微”宽度的高电平或低电平(即，脉冲时钟)，使得锁存器(Latch)以“沿触发”的方式工作，进而解决了触发器的功耗、性能和面积(PPA)问题，以满足高设计要求的芯片设计。
传统方式的性能需要进一步提升以满足用户的需求。
发明内容
本发明的目的在于提供一种脉宽时钟拓扑结构电路，以解决上述背景技术中提出的问题。
为实现上述目的，本发明提供如下技术方案：
一种脉宽时钟拓扑结构电路，包括：时钟脉宽生成模块和时钟拓扑延时模块；
时钟脉宽生成模块对输入时钟进行n级延时子模块串行连接，每级延时子模块的输出端连接到选择器的输入端，通过选择器的m+1个控制信号选择所需的某一延时时钟，并且与原输入时钟进行“与”操作来生成不同的脉宽时钟输出，并且作为时钟拓扑延时模块的输入，时钟拓扑延时模块可产生多 个不同的延时时钟以供不同锁存器使用，其中n＞1，且2 (m+1)≥n。
作为本发明进一步的方案：延时子模块延时一定时间，且每个延时子模块所延时的一定时间可相等或不相等。
作为本发明进一步的方案：延时子模块，包括奇数个反相器和若干个缓冲器，其中反相器和缓冲器相互连接或交替连接。
作为本发明进一步的方案：n级延时子模块所延时的总延时小于输入时钟脉宽。
作为本发明进一步的方案：n级延时子模块的第1级的输入端连接原输入时钟，从n级延时子模块的第2级到第n级的输入端连接前一级延时子模块的输出端。
作为本发明进一步的方案：选择器的输出端与原输入时钟进行“与”操作来产生所需不同脉宽的时钟。
作为本发明进一步的方案：时钟拓扑延时模块由不同延时的时钟信号组成拓扑结构。
作为本发明进一步的方案：时钟拓扑延时模块的每个锁存器的延迟时间一致，以达到时钟平衡功能。
与现有技术相比，本发明的有益效果是：使得脉宽时钟拓扑结构电路具有更高的性能。
脉宽时钟拓扑结构电路可以有效控制时钟的延迟率，使得每个输入时钟具有一定延迟，以满足脉冲宽度对于信号完整性的严苛要求。
附图说明
图1是作为本发明的第一实施例的一种脉宽时钟拓扑结构电路的示意图；
图2是作为本发明的第二实施例的一种脉宽时钟拓扑结构电路的示意图；以及
图3是本发明的脉宽时钟拓扑结构电路的时钟脉宽生成模块和时钟拓扑延时模块的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1至图3所示，一种脉宽时钟拓扑结构电路，包括：时钟脉宽生成模块和时钟拓扑延时模块。
时钟脉宽生成模块对输入时钟进行n级延时子模块(Delay)串行连接，每级延时子模块的输出端连接到选择器(MUX)的输入端，通过选择器(MUX)的m+1个控制信号选择所需的某一延时时钟，并且与原输入时钟(CI)进行“与”(AND)操作来生成不同的脉宽时钟输出，并且作为时钟拓扑延时模块的输入，时钟拓扑延时模块可产生多个不同的延时时钟以供不同的锁存器使用，其中n＞1，且2 (m+1)≥n。
作为一种具体的实施方式，延时子模块(Delay)延时一定时间，且每个延时子模块(Delay)所延时的一定时间可相等或不相等。
作为一种具体的实施方式，延时子模块(Delay)包括奇数个反相器(N)和若干个缓冲器(Buffer)，其中反相器和缓冲器相互连接或交替连接。
作为一种具体的实施方式，n级延时子模块(Delay)所延时的总延时小于输入时钟脉宽。
作为一种具体的实施方式，n级延时子模块(Delay)的第1级的输入端连接原输入时钟(CI)，从n级延时子模块(Delay)的第2级到第n级的输入端连接前一级延时子模块(Delay)的输出端。
作为一种具体的实施方式，选择器(MUX)的输出端与原输入时钟进行“与”(AND)操作来产生所需不同脉宽的时钟。
作为一种具体的实施方式，时钟拓扑延时模块由不同延时的时钟信号(Cnt0,Cnt1...Cntx)组成拓扑结构。
作为一种具体的实施方式，时钟拓扑延时模块的每个锁存器的延迟时间一致，以达到时钟平衡功能。
时钟脉宽生成模块对原输入时钟(CI)进行n级延时子模块(Delay)串行连接，其中延时子模块具体一定的延时功能，并且由奇数个反相器(N)和若干个缓冲器(Buffer)相互连接或交替连接组成。此外，每级延时子模块的输出端输出到选择器(MUX)的输入端，通过选择器(MUX)的m+1个控制信号选择所需的某一延时时钟，并且与原输入时钟(CI)进行“与”(AND)操作来生成不同的脉宽时钟输出，并且作为时钟拓扑延时模块的输入，时钟拓扑延时模块可产生x个不同的延时时钟。脉宽时钟拓扑结构电路可以有效地控制时钟的延迟率，使得每个输入时钟具有一定延迟，以满足脉冲宽度对于信号完整性的严苛要求。
图1示出了一种相对简单的第一实施例。拓扑时钟的输出端(Cnt0,Cnt1...Cntx)把所需的y个(C11，C21..Cy1)时钟信号连接到拓扑时钟的x个输出端(且x≥y)，其中y个(C11，C21..Cy1)时钟信号分别提供给需要不同延时时钟的锁存器(LAT#)。
图2示出了一种相对复杂的第二实施例。拓扑时钟(PG模块)的输出端(Cnt0,Cnt1...Cntx)中一个或多个连接到所需的y个(C11，C21..Cy1)时钟信号，其中y个(C11，C21..Cy1)时钟信号分别提供给需要不同延时时钟的锁存器(LAT#)。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实 现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (8)

  1. 一种脉宽时钟拓扑结构电路，包括：时钟脉宽生成模块和时钟拓扑延时模块，其特征在于，
    所述时钟脉宽生成模块对输入时钟进行n级延时子模块串行连接，每级所述延时子模块的输出端连接到选择器的输入端，通过所述选择器的m+1个控制信号选择所需的某一延时时钟，并且与原输入时钟进行“与”操作来生成不同的脉宽时钟输出，并且作为所述时钟拓扑延时模块的输入，所述时钟拓扑延时模块能够产生多个不同的所述延时时钟以供不同的锁存器使用，其中n＞1，且2 (m+1)≥n。
  2. 根据权利要求1所述的脉宽时钟拓扑结构电路，其特征在于，
    所述延时子模块延时一定时间，且每个所述延时子模块所延时的所述一定时间是相等的或者是不相等的。
  3. 根据权利要求2所述的脉宽时钟拓扑结构电路，其特征在于，
    所述延时子模块包括奇数个反相器和若干个缓冲器，其中所述反相器和所述缓冲器相互连接或交替连接。
  4. 根据权利要求1所述的脉宽时钟拓扑结构电路，其特征在于，
    所述n级延时子模块所延时的总延时小于输入时钟脉宽。
  5. 根据权利要求1所述的脉宽时钟拓扑结构电路，其特征在于，
    所述n级延时子模块的第1级的输入端连接所述原输入时钟，从所述n级延时子模块的第2级到第n级的输入端连接前一级所述延时子模块的输出端。
  6. 根据权利要求1所述的脉宽时钟拓扑结构电路，其特征在于，
    所述选择器的输出端与所述原输入时钟进行所述“与”操作来产生所需不同脉宽的时钟。
  7. 根据权利要求1所述的脉宽时钟拓扑结构电路，其特征在于，
    所述时钟拓扑延时模块由不同延时的时钟信号组成拓扑结构。
  8. 根据权利要求1所述的脉宽时钟拓扑结构电路，其特征在于，
    所述时钟拓扑延时模块的每个所述锁存器的延迟时间一致，以达到时钟平衡功能。
PCT/CN2022/078669 2021-10-28 2022-03-01 脉宽时钟拓扑结构电路 WO2023071007A1 (zh)

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