WO2023035375A1 - 高可靠性功率半导体器件及其制作方法 - Google Patents

高可靠性功率半导体器件及其制作方法 Download PDF

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Publication number
WO2023035375A1
WO2023035375A1 PCT/CN2021/126348 CN2021126348W WO2023035375A1 WO 2023035375 A1 WO2023035375 A1 WO 2023035375A1 CN 2021126348 W CN2021126348 W CN 2021126348W WO 2023035375 A1 WO2023035375 A1 WO 2023035375A1
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Prior art keywords
type
trench
conductivity
conductivity type
conductive polysilicon
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PCT/CN2021/126348
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English (en)
French (fr)
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朱袁正
叶鹏
周锦程
杨卓
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无锡新洁能股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention relates to a power semiconductor device, in particular to a highly reliable shielded gate trench power semiconductor structure.
  • the gate electrode and the drain electrode are usually connected to a high potential, so that the power MOS device is in a conduction state.
  • the gate voltage disappears, the drain voltage is sharply affected by the inductance in the circuit.
  • the device undergoes avalanche breakdown.
  • the avalanche current can only flow into the source electrode contact hole through the P-type body region below the N-type source region. There is a parasitic resistance in the current path, and a voltage drop will be generated at this time.
  • the parasitic NPN transistor composed of the N-type source region, the P-type body region and the N-type epitaxial layer It will be turned on, where the N-type source region is the emitter region, the P-type body region is the base region, and the N-type epitaxial layer is the collector region; the turn-on of the NPN parasitic triode makes the current increase rapidly, and the sharp rise in junction temperature breaks the device. thermal equilibrium, resulting in irreversible damage.
  • the current will be transferred to other locations with lower breakdown voltage, which is the heat transfer phenomenon, which makes it difficult for the current to be fixed and concentrated in one place, and the device is not easy to fail; when the inductance is small, the entire avalanche process takes a shorter time , the avalanche current corresponding to the avalanche failure of the device is relatively large.
  • the large size causes the device to burn locally at the breakdown weak point, and the general burn location is at the corner of the device.
  • the purpose of the present invention is to provide a high-reliability power semiconductor device and a manufacturing method thereof, so as to solve the problem in the prior art that the device fails at a corner position under instantaneous high current, resulting in a decrease in reliability.
  • the technical solution adopted in the embodiment of the present invention is:
  • an embodiment of the present invention provides a high-reliability power semiconductor device, including a substrate of a first conductivity type, an epitaxial layer of a first conductivity type is disposed on the substrate of the first conductivity type, and an epitaxial layer of the first conductivity type is arranged on the substrate of the first conductivity type.
  • the surface of a conductive type epitaxial layer is provided with strip-shaped first-type trenches parallel to each other and uniformly distributed, and the periphery of the first-type trenches is surrounded by second-type trenches;
  • the first type of trench is filled with the first type of conductive polysilicon, and the first type of conductive polysilicon in the first type of trench passes through the field oxygen layer and the epitaxy Layer insulation, the epitaxial layer between the adjacent first-type trenches and the first-type trenches are provided with a second-type insulating dielectric layer, and a source metal is provided above the second-type insulating dielectric layer, The source metal is in ohmic contact with the first-type conductive polysilicon in the first-type trench through the first-type through hole in the second-type insulating dielectric layer; the second-type trench is filled with the first-type conductive polysilicon, The first type of conductive polysilicon in the second type of trench is insulated from the epitaxial layer by the field oxygen layer, and at the top view angle of the device, a second type of conductive polysilicon is arranged above the second type of trench parallel to the first type of trench.
  • the lower half of the first type of trench is provided with the first type of conductive polysilicon
  • the upper half is provided with the second type of conductive polysilicon
  • the first type of conductive polysilicon is provided.
  • the polysilicon and the second type of conductive polysilicon are insulated by the first type of insulating medium, the first type of conductive polysilicon is insulated from the epitaxial layer by the field oxide layer, the second type of conductive polysilicon is insulated from the epitaxial layer by the gate oxide layer, and the adjacent first type of trench
  • the surface of the epitaxial layer of the first conductivity type between the grooves is provided with a body region of the second conductivity type, and a source region of the first conductivity type is arranged on the surface of the body region of the second conductivity type.
  • a second type of insulating medium is provided above the source region of the second type, and a source metal is provided above the second type of insulating medium, and the source metal is connected to the second type of through hole in the second type of insulating medium layer.
  • the source region of a conductivity type and the body region of the second conductivity type are in ohmic contact; the surface of the epitaxial layer between the trench segment of the second type of trench parallel to the first type of trench and the adjacent first type of trench is provided with a second
  • the body region of the second conductivity type is provided with a second type of insulating dielectric layer above the second type of conductive type body region, and a source metal is provided above the second type of insulating dielectric layer, and the source metal passes through the second The via-like hole is in ohmic contact with the body region of the second conductivity type;
  • a second type of insulating dielectric layer is provided above the first type of trench, and a gate is provided above the second type of insulating dielectric layer
  • the gate metal is in ohmic contact with the second type of conductive polysilicon through a third type of through hole in the second type of insulating dielectric layer;
  • a well region of the first conductivity type is provided at the bottom of the epitaxial layer of the first conductivity type below the through hole of the second type.
  • the concentration of impurities of the first conductivity type in the well region of the first conductivity type is higher than the concentration of impurities of the first conductivity type in the epitaxial layer of the first conductivity type.
  • the direction perpendicular to the first-type trench is the Y-axis direction, and in the view of the device, in the Y-axis direction, the edge of the well region of the first conductivity type does not cross the first-type trench and the Y-axis direction.
  • the direction parallel to the trenches of the first type is the direction of the X-axis, and in the view of the device, in the direction of the X-axis, the edge of the well region of the first conductivity type does not cross the end of the through-hole of the second type.
  • the field oxide layer, the gate oxide layer, the first type of insulating medium, and the second type of insulating medium are composed of silicon dioxide or silicon nitride.
  • the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type
  • an embodiment of the present invention provides a method for manufacturing a high-reliability power semiconductor device, including the following steps:
  • Step 1 providing a substrate of the first conductivity type, and growing a first epitaxial layer of the first conductivity type on the substrate of the first conductivity type;
  • Step 2 selectively implanting impurities of the first conductivity type on the surface of the epitaxial layer of the first conductivity type in the first layer to form a well region of the first conductivity type;
  • Step 3 forming a second epitaxial layer of the first conductivity type
  • Step 4 Selectively etching the first type of groove and the second type of groove on the surface of the first conductivity type epitaxial layer;
  • Step 5 forming a field oxide layer on the bottom and sidewalls of the first type trench and the second type trench;
  • Step 6 Deposit conductive polysilicon to fill the first-type trench and the second-type trench, and then etch the conductive polysilicon to form the first-type conductive polysilicon in the first-type trench and the second-type trench;
  • Step 7 selectively etching the upper half of the conductive polysilicon in the first type of trench
  • Step 8 Depositing an insulating dielectric layer to fill the upper half of the first type of trench;
  • Step 9 removing the insulating dielectric layer above the epitaxial layer of the first conductivity type
  • Step 10 selectively etching part of the insulating dielectric layer in the first-type trench to form the first-type insulating dielectric;
  • Step eleven forming a gate oxide layer in the first type of trench
  • Step 12 Deposit conductive polysilicon to fill the upper half of the first type of trench, and then etch the conductive polysilicon to form the second type of conductive polysilicon in the upper half of the first type of trench;
  • Step 13 Implanting impurities of the second conductivity type on the surface of the device and annealing to form a body region of the second conductivity type, then selectively implanting impurities of the first conductivity type, and forming a source region of the first conductivity type after activation;
  • Step 14 depositing an insulating medium to form a second type of insulating medium on the surface of the device
  • Step 15 Selectively etch the second type of insulating medium and the epitaxial layer to form the first type of through hole, the second type of through hole, and the third type of through hole;
  • Step sixteen After depositing metal on the surface of the device, selectively etch the metal to form source metal and gate metal.
  • an embodiment of the present invention provides another method for manufacturing a high-reliability power semiconductor device, including the following steps:
  • Step 1 providing a first conductivity type substrate
  • Step 2 selectively etching the substrate of the first conductivity type, and forming a well region of the first conductivity type in the unetched part;
  • Step 3 forming a first conductivity type epitaxial layer
  • Step 4 Selectively etching the first type of groove and the second type of groove on the surface of the first conductivity type epitaxial layer;
  • Step 5 forming a field oxide layer on the bottom and sidewalls of the first type trench and the second type trench;
  • Step 6 Deposit conductive polysilicon to fill the first-type trench and the second-type trench, and then etch the conductive polysilicon to form the first-type conductive polysilicon in the first-type trench and the second-type trench;
  • Step 7 selectively etching the upper half of the conductive polysilicon in the first type of trench
  • Step 8 Depositing an insulating dielectric layer to fill the upper half of the first type of trench;
  • Step 9 removing the insulating dielectric layer above the epitaxial layer of the first conductivity type
  • Step 10 selectively etching part of the insulating dielectric layer in the first-type trench to form the first-type insulating dielectric;
  • Step eleven forming a gate oxide layer in the first type of trench
  • Step 12 Deposit conductive polysilicon to fill the upper half of the first type of trench, and then etch the conductive polysilicon to form the second type of conductive polysilicon in the upper half of the first type of trench;
  • Step 13 Implanting impurities of the second conductivity type on the surface of the device and annealing to form a body region of the second conductivity type, then selectively implanting impurities of the first conductivity type, and forming a source region of the first conductivity type after activation;
  • Step 14 depositing an insulating medium to form a second type of insulating medium on the surface of the device
  • Step 15 Selectively etch the second type of insulating medium and the epitaxial layer to form the first type of through hole, the second type of through hole, and the third type of through hole;
  • Step sixteen After depositing metal on the surface of the device, selectively etch the metal to form source metal and gate metal.
  • the beneficial effect brought by the technical solution provided by the embodiment of the present invention is: the high-reliability power semiconductor device proposed by this application avoids the accumulation of large current at the corner position of the device, so that the corner position is not damaged, which improves the device reliability. At the same time, due to the existence of the well region of the first conductivity type, the on-resistance of the device is also significantly reduced.
  • FIG. 1 is a schematic top view of the distribution of the metal and the first conductivity type well region of the device provided by the embodiment of the present invention
  • Fig. 2 is a schematic cross-sectional structure cut along the dotted line AA' in Fig. 1;
  • Fig. 3 is a schematic cross-sectional structure cut along the dotted line BB' in Fig. 1;
  • Fig. 4 is a schematic cross-sectional structure cut along dotted line CC ' among Fig. 1;
  • Fig. 5 is a schematic cross-sectional structure cut along the dotted line DD' in Fig. 1;
  • FIG. 6 is a schematic diagram of a cross-sectional structure of a cell without a well region of the first conductivity type
  • FIG. 7 is a schematic cross-sectional structure diagram of a cell provided with a well region of the first conductivity type
  • Fig. 8 is an electric field distribution diagram cut along the dotted line EE' and the dotted line FF' when the cell structures in Fig. 6 and Fig. 7 are respectively broken down by a small current;
  • Fig. 9 is an electric field distribution diagram cut along the dotted line EE' and the dotted line FF' when the cellular structures in Fig. 6 and Fig. 7 are broken down respectively;
  • FIG. 10 is a schematic cross-sectional structure diagram of forming a first epitaxial layer of a first conductivity type on a substrate of a first conductivity type according to an embodiment of the present invention
  • FIG. 11 is a schematic cross-sectional structure diagram of forming a well region of the first conductivity type according to an embodiment of the present invention.
  • FIG. 12 is a schematic cross-sectional structure diagram of forming a second layer of the first conductivity type epitaxial layer according to an embodiment of the present invention.
  • FIG. 13 is a schematic cross-sectional structure diagram of forming the first type of groove and the second type of groove according to the embodiment of the present invention.
  • FIG. 14 is a schematic cross-sectional structure diagram of forming a field oxygen layer according to an embodiment of the present invention.
  • 15 is a schematic cross-sectional structure diagram of forming the first type of conductive polysilicon according to an embodiment of the present invention.
  • Fig. 16 is a schematic cross-sectional structure diagram of etching the upper half of the conductive polysilicon in the first type of trench according to the embodiment of the present invention.
  • Fig. 17 is a schematic cross-sectional structure diagram of depositing an insulating dielectric layer and filling the upper half of the first type of trench according to an embodiment of the present invention
  • FIG. 18 is a schematic cross-sectional structure diagram of removing the insulating dielectric layer above the epitaxial layer of the first conductivity type according to an embodiment of the present invention
  • 19 is a schematic cross-sectional structure diagram of forming a first type of insulating medium according to an embodiment of the present invention.
  • FIG. 20 is a schematic cross-sectional structure diagram of forming a gate oxide layer according to an embodiment of the present invention.
  • 21 is a schematic cross-sectional structure diagram of forming the second type of conductive polysilicon according to an embodiment of the present invention.
  • 22 is a schematic cross-sectional structure diagram of forming a body region of the second conductivity type and a source region of the first conductivity type according to an embodiment of the present invention
  • FIG. 23 is a schematic cross-sectional structure diagram of forming a second type of insulating medium according to an embodiment of the present invention.
  • 24 is a schematic cross-sectional structure diagram of forming the first type of through hole, the second type of through hole, and the third type of through hole according to the embodiment of the present invention.
  • Fig. 25 is a schematic cross-sectional structure diagram of a first conductivity type substrate provided by an embodiment of the present invention.
  • 26 is a schematic cross-sectional structure diagram of selectively etching a substrate of the first conductivity type and forming a well region of the first conductivity type in the unetched part according to an embodiment of the present invention
  • the present invention includes the following two embodiments, which are described by taking an N-type power semiconductor device as an example;
  • a high-reliability power semiconductor device proposed in this embodiment includes an N-type substrate 1, an N-type epitaxial layer 2 is arranged above the N-type substrate 1, and strips are arranged on the surface of the N-type epitaxial layer 2.
  • Parallel to each other and evenly distributed first-type grooves 3, surrounded by second-type grooves 16 on the periphery of the first-type grooves 3; as shown in Figure 1, outside the left end of the first-type grooves 3 , and the outside of the right end are also distributed with second-type grooves 16, which are not shown in Figure 1; the second-type grooves 16 are arranged around all the first-type grooves 3;
  • FIG. 3 it is a schematic cross-sectional structure cut along the dotted line BB' in Figure 1, the dotted line BB' is located in the middle of the first type of groove 3, and the first type of groove 3 is filled with One type of conductive polysilicon 5, the first type of conductive polysilicon 5 in the first type of trench 3 is insulated from the epitaxial layer 2 by the field oxygen layer 6, and the epitaxial layer 2 between the adjacent first type of trenches 3 is insulated from the first type of A second-type insulating dielectric layer 12 is arranged above the trench 3, and a source metal 13 is arranged above the second-type insulating dielectric layer 12, and the source metal 13 passes through the second-type insulating dielectric layer 12.
  • the first type of through hole 15 is in ohmic contact with the first type of conductive polysilicon 5 in the first type of trench 3; the second type of trench 16 is filled with the first type of conductive polysilicon 5, and the second type of trench 16 is filled
  • One type of conductive polysilicon 5 is insulated from the epitaxial layer 2 through the field oxygen layer 6, and a second type of insulating dielectric layer 12 is arranged above the second type of trench 16 parallel to the first type of trench 3.
  • a source metal 13 is provided above the insulating-like dielectric layer 12, and the source metal 13 is in ohmic contact with the first-type conductive polysilicon 5 in the second-type trench 16 through the first-type through hole 15;
  • FIG. 2 it is a schematic cross-sectional structure cut along the dotted line AA' in FIG. position, the lower half of the first type trench 3 is provided with the first type of conductive polysilicon 5, and the upper half is provided with the second type of conductive polysilicon 8, the first type of conductive polysilicon 5 and the second type of conductive polysilicon 8 pass through the first type
  • the insulating medium 7 is insulated, the first type conductive polysilicon 5 is insulated from the epitaxial layer 2 through the field oxide layer 6, the second type conductive polysilicon 8 is insulated from the epitaxial layer 2 through the gate oxide layer 9, and the adjacent first type trenches 3
  • the surface of the N-type epitaxial layer 2 is provided with a P-type body region 10, an N-type source region 11 is arranged on the surface of the P-type body region 10, and an N-type source region 11 is arranged on the surface of the first-type trench 3 and the N-type source region 11.
  • the second type of insulating medium 12 is provided with a source metal 13 above the second type of insulating medium 12, and the source metal 13 communicates with the N-type via hole 14 in the second type of insulating medium layer 12.
  • the source region 11 and the P-type body region 10 are in ohmic contact;
  • the surface of the epitaxial layer 2 between the groove segment of the second type of trench 16 parallel to the first type of trench 3 and the adjacent first type of trench 3 is provided with P-type body region 10
  • a second-type insulating dielectric layer 12 is arranged above the P-type body region 10
  • a source metal 13 is arranged above the second-type insulating dielectric layer 12, and the source metal 13 make ohmic contact with the P-type body region 10 through the second type of through hole 14;
  • FIG. 5 it is a schematic cross-sectional structure cut along the dotted line DD' in Figure 1.
  • a second type of trench is provided above the first type of trench 3.
  • An insulating dielectric layer 12, a gate metal 17 is arranged above the second type insulating dielectric layer 12, and the gate metal 17 passes through the third type through hole 18 in the second type insulating dielectric layer 12 and the second type Conductive polysilicon 8 ohm contacts;
  • an N-type well region 4 is provided at the bottom of the N-type epitaxial layer 2 corresponding to the second type of through hole 14, and the concentration of N-type impurities in the N-type well region 4 is higher than that of the N-type impurity.
  • the concentration of the N-type impurity in the type epitaxial layer 2 As shown in Figure 2, the edge of the N-type well region 4 and the second type of communication between the first type trench 3 and the second type trench 16 The distance between the holes 14 is d1, and d1 is 5 ⁇ m; as shown in FIG. 4 , the distance between the edge of the N-type well region 4 and the end of the second type of through hole 14 is d2, and d2 is 1 ⁇ m;
  • the field oxide layer 6, the gate oxide layer 9, the first type insulating medium 7, and the second type insulating medium 12 are composed of silicon dioxide or silicon nitride;
  • Step 1 as shown in FIG. 10 , provides an N-type substrate 1, and grows a first layer of N-type epitaxial layer 2 on the N-type substrate 1;
  • N-type impurities are selectively implanted on the surface of the first N-type epitaxial layer 2 to form an N-type well region 4 ;
  • Step 3 as shown in FIG. 12 , forming a second N-type epitaxial layer 2;
  • Step 4 selectively etches the first-type trenches 3 and the second-type trenches 16 on the surface of the N-type epitaxial layer 2;
  • Step 5 As shown in FIG. 14 , a field oxide layer 6 is formed on the bottom and sidewalls of the first-type trench 3 and the second-type trench 16 ;
  • Step 6 As shown in FIG. 15 , deposit conductive polysilicon to fill the first-type trench 3 and the second-type trench 16 , and then etch the conductive polysilicon to form in the first-type trench 3 and the second-type trench 16 The first type of conductive polysilicon 5;
  • Step 7 as shown in Figure 16, selectively etching the upper half of the conductive polysilicon in the first type of trench 3;
  • Step 8 As shown in FIG. 17 , an insulating dielectric layer is deposited to fill the upper half of the first-type trench 3;
  • Step 9 as shown in FIG. 18 , remove the insulating dielectric layer above the N-type epitaxial layer 2;
  • Step ten as shown in Figure 19, selectively etches part of the insulating medium layer in the first type trench 3 to form the first type insulating medium 7;
  • Step eleven as shown in FIG. 20 , forming a gate oxide layer 9 in the first-type trench 3 ;
  • Step 12 As shown in FIG. 21 , deposit conductive polysilicon to fill the upper half of the first-type trench 3 , and then etch the conductive polysilicon to form a second-type conductive polysilicon 8 in the upper half of the first-type trench 3 ;
  • Step 13 implant P-type impurities on the surface of the device and then anneal to form a P-type body region 10 , then selectively implant N-type impurities, and form an N-type source region 11 after activation;
  • Step 14 as shown in FIG. 23 , deposit an insulating medium to form a second type of insulating medium 12 on the surface of the device;
  • Step fifteen selectively etch the second-type insulating medium 12 and the epitaxial layer to form the first-type through-hole 15 , the second-type through-hole 14 , and the third-type through-hole 18 ;
  • Step 16 As shown in FIGS. 2 and 4 , after depositing metal on the device surface, selectively etch the metal to form source metal 13 and gate metal 17 .
  • Step 1 as shown in FIG. 25 , provides an N-type substrate 1;
  • Step 2 as shown in FIG. 26, selectively etches on the N-type substrate 1, and the unetched N-type substrate 1 region is the N-type well region 4;
  • Step 3 as shown in FIG. 12 , forming a second N-type epitaxial layer 2;
  • Step four to step sixteen are exactly the same as step four to step sixteen of embodiment 1.
  • FIG. 6 it is a schematic diagram of the cross-sectional structure of a cell without an N-type well region 4, and as shown in Figure 7, it is a schematic diagram of a cross-sectional structure of a cell with an N-type well region 4, and the above two structures are small Breakdown voltage test under current conditions, leakage current in chip area 1mm 2 Under the condition of , the breakdown voltages of the two structures are exactly the same, as shown in Figure 8, the leakage current of the cell structures in Figure 6 and Figure 7 is respectively in the chip area of 1mm 2
  • the electric field distribution diagram cut along the dotted line EE' and the dotted line FF' under the condition of breakdown, the electric field distribution of the two structures is exactly the same, so the breakdown voltage is also exactly the same;
  • the breakdown voltage of the structure in Figure 7 is lower than that of the structure in Figure 6.

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Abstract

本发明提供一种高可靠性功率半导体器件，包括第一导电类型衬底，在所述第一导电类型衬底上方设有第一导电类型外延层，在所述第一导电类型外延层的表面设置条形的互相平行且均匀分布的第一类沟槽，在所述第一类沟槽的外围环绕着第二类沟槽；在对器件的俯视角度，在第一类沟槽的两端的尽头，在第一类沟槽的上方设有第二类绝缘介质层，在所述第二类绝缘介质层的上方设有栅极金属，所述栅极金属通过第二类绝缘介质层内的第三类通孔与第二类导电多晶硅欧姆接触；在对器件的俯视角度，在第二类通孔对应的下方的第一导电类型外延层的底部设有第一导电类型阱区。本发明避免了器件在边角位置有大电流的聚集，提升了器件的可靠性。

Description

高可靠性功率半导体器件及其制作方法 技术领域
本发明涉及一种功率半导体器件，尤其是一种高可靠性的屏蔽栅沟槽功率半导体结构。
背景技术
在非钳位感性的负载电路测试模式下，栅电极和漏电极通常接高电位，使功率MOS器件处于导通状态，当栅电压消失时，此时在电路中电感作用下，漏极电压急剧升高，器件发生雪崩击穿，以N型功率器件为例，此时雪崩电流只能通过N型源区下面的P型体区流到源电极接触孔内，由于在P型体区的雪崩电流路径中存在一个寄生电阻，此时会产生一个电压降，当该电压降大于PN结的导通压降时，由N型源区、P型体区和N型外延层构成的寄生NPN三极管将开启，其中N型源区为发射区，P型体区为基区，N型外延层为集电区；NPN寄生三极管的开启，使得电流迅速增大，结温的急剧上升打破了器件的热平衡，导致不可逆的损坏。
在电感较大的情况下，减小寄生电阻可以抑制寄生三极管的开启，从而提升器件的雪崩耐量，但是当电感很小的时候，器件的雪崩耐量就会明显减小；这是由于电感较大的时候，整个雪崩过程的时间较长，在器件内部一旦有电流集中，就会导致局部发热，局部发热会使得局部击穿电压升高，局部击穿电压升高导致该处电流下降，该处电流就会转移至其他击穿电压较低的位置，这就是热转移现象，这导致电流很难固定集中于一处，器件不容易失效；当电感很小的时候，整个雪崩过程的时间较短，器件雪崩失效所对应的雪崩电流较大，在器件内部一旦有电流集中，由于时间较短，很难产生热转移现象，导致器件往往在击穿薄弱点发生寄生三极管开启失效，或者直接电流过大导致器件在击穿薄弱点局部烧毁，而一般烧毁的位置就在器件的边角位置。
为了提升功率半导体器件在瞬间大电流下的可靠性，使得失效点从边角位置转移到器件内部，需要改进器件结构。
发明内容
本发明的目的是在于提供一种高可靠性功率半导体器件及其制作方法，解决现有技术中存在瞬间大电流下器件在边角位置失效导致可靠性下降的问题。为实现以上技术目的，本发明实施例采用的技术方案是：
第一方面，本发明实施例提供了一种高可靠性功率半导体器件，包括第一导电类型衬底，在所述第一导电类型衬底上方设有第一导电类型外延层，在所述第一导电类型外延层的表面设置条形的互相平行且均匀分布的第一类沟槽，在所述第一类沟槽的外围环绕着第二类沟槽；
在对器件的俯视角度，在第一类沟槽的中部位置，第一类沟槽内填充满了第一类导电多晶硅，第一类沟槽内的第一类导电多晶硅通过场氧层与外延层绝 缘，相邻的第一类沟槽之间的外延层与第一类沟槽的上方设有第二类绝缘介质层，在所述第二类绝缘介质层的上方设有源极金属，所述源极金属通过第二类绝缘介质层内的第一类通孔与第一类沟槽内的第一类导电多晶硅欧姆接触；第二类沟槽内填充满了第一类导电多晶硅，第二类沟槽内的第一类导电多晶硅通过场氧层与外延层绝缘，在对器件的俯视角度，与第一类沟槽平行的第二类沟槽槽段的上方设有第二类绝缘介质层，在所述第二类绝缘介质层的上方设有源极金属，所述源极金属通过第一类通孔与第二类沟槽内的第一类导电多晶硅欧姆接触；
在对器件的俯视角度，在第一类沟槽的两侧位置，第一类沟槽的下半段设有第一类导电多晶硅，上半段设有第二类导电多晶硅，第一类导电多晶硅与第二类导电多晶硅通过第一类绝缘介质绝缘，第一类导电多晶硅通过场氧层与外延层绝缘，第二类导电多晶硅通过栅氧层与外延层绝缘，相邻的第一类沟槽之间的第一导电类型外延层的表面设有第二导电类型体区，在该第二导电类型体区的表面设有第一导电类型源区，在第一类沟槽与第一导电类型源区的上方设有第二类绝缘介质，在所述第二类绝缘介质的上方设有源极金属，所述源极金属通过第二类绝缘介质层内的第二类通孔与第一导电类型源区、该第二导电类型体区欧姆接触；与第一类沟槽平行的第二类沟槽槽段与相邻的第一类沟槽之间的外延层的表面设有第二导电类型体区，在该第二导电类型体区的上方设有第二类绝缘介质层，在所述第二类绝缘介质层的上方设有源极金属，所述源极金属通过第二类通孔与该第二导电类型体区欧姆接触；
在对器件的俯视角度，在第一类沟槽的两端的尽头，在第一类沟槽的上方设有第二类绝缘介质层，在所述第二类绝缘介质层的上方设有栅极金属所述栅极金属通过第二类绝缘介质层内的第三类通孔与第二类导电多晶硅欧姆接触；
在对器件的俯视角度，在第二类通孔对应的下方的第一导电类型外延层的底部设有第一导电类型阱区。
进一步地，所述第一导电类型阱区内的第一导电类型杂质的浓度高于第一导电类型外延层内的第一导电类型杂质的浓度。
进一步地，与第一类沟槽垂直的方向为Y轴方向，在对器件的俯视角度，在Y轴方向上，所述第一导电类型阱区的边缘不越过所述第一类沟槽与第二类沟槽之间的第二类通孔。
进一步地，与第一类沟槽平行的方向为X轴方向，在对器件的俯视角度，在X轴方向上，所述第一导电类型阱区的边缘不越过第二类通孔的尽头。
进一步地，所述场氧层、栅氧层、第一类绝缘介质、第二类绝缘介质由二氧化硅或氮化硅构成。
进一步地，所述功率半导体器件包括N型功率半导体器件和P型功率半导体器件，当所述功率半导体器件为所述N型功率半导体器件时，第一导电类型为N型，第二导电类型为P型，当所述功率半导体器件为所述P型半导体器件时，第一导电类型为P型，第二导电类型为N型。
第二方面，本发明实施例提供了一种高可靠性功率半导体器件的制作方法， 包括以下步骤：
步骤一：提供第一导电类型衬底，在所述第一导电类型衬底上生长第一层第一导电类型外延层；
步骤二：在第一层第一导电类型外延层的表面选择性注入第一导电类型杂质，形成第一导电类型阱区；
步骤三：形成第二层第一导电类型外延层；
步骤四：在第一导电类型外延层的表面选择性刻蚀出第一类沟槽与第二类沟槽；
步骤五：在第一类沟槽与第二类沟槽的底部与侧壁形成场氧层；
步骤六：淀积导电多晶硅填满第一类沟槽与第二类沟槽，然后刻蚀导电多晶硅，在第一类沟槽与第二类沟槽内形成第一类导电多晶硅；
步骤七：选择性刻蚀第一类沟槽内的上半部分导电多晶硅；
步骤八：淀积绝缘介质层填充满第一类沟槽的上半部分；
步骤九：去除第一导电类型外延层上方的绝缘介质层；
步骤十：选择性刻蚀第一类沟槽内的部分绝缘介质层，形成第一类绝缘介质；
步骤十一：在第一类沟槽内形成栅氧层；
步骤十二：淀积导电多晶硅填充满第一类沟槽的上半部分，然后刻蚀导电多晶硅，在第一类沟槽的上半部分形成第二类导电多晶硅；
步骤十三：在器件表面注入第二导电类型杂质后退火形成第二导电类型体区，然后选择性注入第一导电类型杂质，激活后形成第一导电类型源区；
步骤十四：淀积绝缘介质，在器件表面形成第二类绝缘介质；
步骤十五：选择性刻蚀第二类绝缘介质与外延层，形成第一类通孔、第二类通孔、第三类通孔；
步骤十六：在器件表面淀积金属后，选择性刻蚀金属形成源极金属与栅极金属。
第三方面，本发明实施例提供了另一种高可靠性功率半导体器件的制作方法，包括以下步骤：
步骤一：提供第一导电类型衬底；
步骤二：选择性刻蚀第一导电类型衬底，未被刻蚀的部分形成第一导电类型阱区；
步骤三：形成第一导电类型外延层；
以下步骤同第一种制作方法；
步骤四：在第一导电类型外延层的表面选择性刻蚀出第一类沟槽与第二类沟槽；
步骤五：在第一类沟槽与第二类沟槽的底部与侧壁形成场氧层；
步骤六：淀积导电多晶硅填满第一类沟槽与第二类沟槽，然后刻蚀导电多晶硅，在第一类沟槽与第二类沟槽内形成第一类导电多晶硅；
步骤七：选择性刻蚀第一类沟槽内的上半部分导电多晶硅；
步骤八：淀积绝缘介质层填充满第一类沟槽的上半部分；
步骤九：去除第一导电类型外延层上方的绝缘介质层；
步骤十：选择性刻蚀第一类沟槽内的部分绝缘介质层，形成第一类绝缘介质；
步骤十一：在第一类沟槽内形成栅氧层；
步骤十二：淀积导电多晶硅填充满第一类沟槽的上半部分，然后刻蚀导电多晶硅，在第一类沟槽的上半部分形成第二类导电多晶硅；
步骤十三：在器件表面注入第二导电类型杂质后退火形成第二导电类型体区，然后选择性注入第一导电类型杂质，激活后形成第一导电类型源区；
步骤十四：淀积绝缘介质，在器件表面形成第二类绝缘介质；
步骤十五：选择性刻蚀第二类绝缘介质与外延层，形成第一类通孔、第二类通孔、第三类通孔；
步骤十六：在器件表面淀积金属后，选择性刻蚀金属形成源极金属与栅极金属。
本发明实施例提供的技术方案带来的有益效果是：本申请提出的高可靠性功率半导体器件，避免了器件在边角位置有大电流的聚集，使得边角位置不受伤害，这样提升了器件的可靠性。同时由于第一导电类型阱区的存在，器件的导通电阻也会明显降低。
附图说明
图1为本发明实施例提供的器件的金属与第一导电类型阱区分布的俯视示意图；
图2为沿着图1中的虚线AA’截得的的剖面结构示意图；
图3为沿着图1中的虚线BB’截得的的剖面结构示意图；
图4为沿着图1中的虚线CC’截得的的剖面结构示意图；
图5为沿着图1中的虚线DD’截得的的剖面结构示意图；
图6为不设有第一导电类型阱区的元胞的剖面结构示意图；
图7为设有第一导电类型阱区的元胞的剖面结构示意图；
图8为图6与图7中的元胞结构分别在小电流击穿时沿着虚线EE’与虚线FF’截得的电场分布图；
图9为图6与图7中的元胞结构分别在大电流击穿时沿着虚线EE’与虚线FF’截得的电场分布图；
图10为本发明实施例在第一导电类型衬底上形成第一层第一导电类型外延层的剖面结构示意图；
图11为本发明实施例形成第一导电类型阱区的剖面结构示意图；
图12为本发明实施例形成第二层第一导电类型外延层的剖面结构示意图；
图13为本发明实施例形成第一类沟槽与第二类沟槽的剖面结构示意图；
图14为本发明实施例形成场氧层的剖面结构示意图；
图15为本发明实施例形成第一类导电多晶硅的剖面结构示意图；
图16为本发明实施例刻蚀第一类沟槽内的上半部分导电多晶硅的剖面结构 示意图；
图17为本发明实施例淀积绝缘介质层填充满第一类沟槽的上半部分的剖面结构示意图；
图18为本发明实施例去除第一导电类型外延层上方的绝缘介质层的剖面结构示意图；
图19为本发明实施例形成第一类绝缘介质的剖面结构示意图；
图20为本发明实施例形成栅氧层的剖面结构示意图；
图21为本发明实施例形成第二类导电多晶硅的剖面结构示意图；
图22为本发明实施例形成第二导电类型体区与第一导电类型源区的剖面结构示意图；
图23为本发明实施例形成第二类绝缘介质的剖面结构示意图；
图24为本发明实施例形成第一类通孔、第二类通孔、第三类通孔的剖面结构示意图；
图25为本发明实施例提供的第一导电类型衬底的剖面结构示意图；
图26为本发明实施例选择性刻蚀第一导电类型衬底，未被刻蚀的部分形成第一导电类型阱区的剖面结构示意图；
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本发明，并不用于限定本发明。
本发明包括以下两种实施例，以N型功率半导体器件为例进行说明；
实施例1：
本实施例提出的一种高可靠性功率半导体器件，包括N型衬底1，在所述N型衬底1上方设有N型外延层2，在所述N型外延层2的表面设置条形的互相平行且均匀分布的第一类沟槽3，在所述第一类沟槽3的外围环绕着第二类沟槽16；如图1中，在第一类沟槽3的左端外侧、右端外侧均还分布有第二类沟槽16，只是图1中未示出；第二类沟槽16是环绕所有的第一类沟槽3设置的；
如图3所示，为沿着图1中的虚线BB’截得的的剖面结构示意图，虚线BB’位于在第一类沟槽3的中部位置，第一类沟槽3内填充满了第一类导电多晶硅5，第一类沟槽3内的第一类导电多晶硅5通过场氧层6与外延层2绝缘，相邻的第一类沟槽3之间的外延层2与第一类沟槽3的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有源极金属13，所述源极金属13通过第二类绝缘介质层12内的第一类通孔15与第一类沟槽3内的第一类导电多晶硅5欧姆接触；第二类沟槽16内填充满了第一类导电多晶硅5，第二类沟槽16内的第一类导电多晶硅5通过场氧层6与外延层2绝缘，与第一类沟槽3平行的第二类沟槽16槽段的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有源极金属13，所述源极金属13通过第一类通孔15与第二类沟槽16内的第一类导电多晶硅5欧姆接触；
如图2所示，为沿着图1中的虚线AA’截得的的剖面结构示意图，虚线AA’ 位于在第一类沟槽3的两侧位置，在第一类沟槽3的两侧位置，第一类沟槽3的下半段设有第一类导电多晶硅5，上半段设有第二类导电多晶硅8，第一类导电多晶硅5与第二类导电多晶硅8通过第一类绝缘介质7绝缘，第一类导电多晶硅5通过场氧层6与外延层2绝缘，第二类导电多晶硅8通过栅氧层9与外延层2绝缘，相邻的第一类沟槽3之间的N型外延层2的表面设有P型体区10，在该P型体区10的表面设有N型源区11，在第一类沟槽3与N型源区11的上方设有第二类绝缘介质12，在所述第二类绝缘介质12的上方设有源极金属13，所述源极金属13通过第二类绝缘介质层12内的第二类通孔14与N型源区11、该P型体区10欧姆接触；与第一类沟槽3平行的第二类沟槽16槽段与相邻的第一类沟槽3之间的外延层2的表面设有P型体区10，在该P型体区10的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有源极金属13，所述源极金属13通过第二类通孔14与该P型体区10欧姆接触；
如图5所示，为沿着图1中的虚线DD’截得的的剖面结构示意图，在第一类沟槽3的两端的尽头，在第一类沟槽3的上方设有第二类绝缘介质层12，在所述第二类绝缘介质层12的上方设有栅极金属17，所述栅极金属17通过第二类绝缘介质层12内的第三类通孔18与第二类导电多晶硅8欧姆接触；
在对器件的俯视角度，在第二类通孔14对应的下方的N型外延层2的底部设有N型阱区4，所述N型阱区4内的N型杂质的浓度高于N型外延层2内的N型杂质的浓度；如图2所示，所述N型阱区4的边缘与所述第一类沟槽3和第二类沟槽16之间的第二类通孔14之间的距离为d1，d1为5μm；如图4所示，所述N型阱区4的边缘与第二类通孔14的尽头之间的距离为d2，d2为1μm；
场氧层6、栅氧层9、第一类绝缘介质7、第二类绝缘介质12由二氧化硅或氮化硅构成；
本实施例中的一种高可靠性功率半导体器件的制作方法，包括以下步骤：
步骤一如图10所示，提供N型衬底1，在所述N型衬底1上生长第一层N型外延层2；
步骤二如图11所示，在第一层N型外延层2的表面选择性注入N型杂质，形成N型阱区4；
步骤三如图12所示，形成第二层N型外延层2；
步骤四如图13所示，在N型外延层2的表面选择性刻蚀出第一类沟槽3与第二类沟槽16；
步骤五如图14所示，在第一类沟槽3与第二类沟槽16的底部与侧壁形成场氧层6；
步骤六如图15所示，淀积导电多晶硅填满第一类沟槽3与第二类沟槽16，然后刻蚀导电多晶硅，在第一类沟槽3与第二类沟槽16内形成第一类导电多晶硅5；
步骤七如图16所示，选择性刻蚀第一类沟槽3内的上半部分导电多晶硅；
步骤八如图17所示，淀积绝缘介质层填充满第一类沟槽3的上半部分；
步骤九如图18所示，去除N型外延层2上方的绝缘介质层；
步骤十如图19所示，选择性刻蚀第一类沟槽3内的部分绝缘介质层，形成第 一类绝缘介质7；
步骤十一如图20所示，在第一类沟槽3内形成栅氧层9；
步骤十二如图21所示，淀积导电多晶硅填充满第一类沟槽3的上半部分，然后刻蚀导电多晶硅，在第一类沟槽3的上半部分形成第二类导电多晶硅8；
步骤十三如图22所示，在器件表面注入P型杂质后退火形成P型体区10，然后选择性注入N型杂质，激活后形成N型源区11；
步骤十四如图23所示，淀积绝缘介质，在器件表面形成第二类绝缘介质12；
步骤十五如图24所示，选择性刻蚀第二类绝缘介质12与外延层，形成第一类通孔15、第二类通孔14、第三类通孔18；
步骤十六如图2与图4所示，在器件表面淀积金属后，选择性刻蚀金属形成源极金属13与栅极金属17。
实施例2：
实施例2与实施例1的区别在于制造方法，本实施例的制作方法，包括以下步骤：
步骤一如图25所示，提供N型衬底1；
步骤二如图26所示，在N型衬底1上选择性刻蚀，未被刻蚀的N型衬底1区域就是N型阱区4；
步骤三如图12所示，形成第二层N型外延层2；
步骤四至步骤十六与实施例1的步骤四至步骤十六完全相同。
如图6所示为不设有N型阱区4的元胞的剖面结构示意图，如图7所示为设有N型阱区4的元胞的剖面结构示意图，对上述两个结构进行小电流条件下的击穿电压测试，在芯片面积1mm 2漏电流
Figure PCTCN2021126348-appb-000001
的条件下，两个结构的击穿电压完全相同，如图8所示为图6与图7中的元胞结构分别在芯片面积1mm 2漏电流
Figure PCTCN2021126348-appb-000002
条件下击穿时沿着虚线EE’与虚线FF’截得的电场分布图，两个结构的电场分布完全相同，所以击穿电压也完全相同；对上述两个结构进行大电流条件下的击穿电压测试，在芯片面积1mm 2漏电流20A的条件下，图7结构的击穿电压低于图6结构，如图9所示为图6与图7中的元胞结构分别在芯片面积1mm 2漏电流20A条件下击穿时沿着虚线EE’与虚线FF’截得的电场分布图，由于N型阱区4的存在，图7结构的电场线围成的面积小于图6结构的电场线围成的面积，这意味着在大电流击穿的条件下，图7结构的击穿电压低于图6结构，因此本申请器件在承受瞬间大电流击穿时，N型阱区4对应的区域会吸收绝大多数的电流，避免了器件在边角位置有大电流的聚集，使得边角位置不受伤害，这样提升了器件的可靠性；同时由于N型阱区4的存在，器件的导通电阻也会明显降低。
最后所应说明的是，以上具体实施方式仅用以说明本发明的技术方案而非限制，尽管参照实例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本发明技术方案的精神和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (8)

  1. 一种高可靠性功率半导体器件，包括第一导电类型衬底(1)，在所述第一导电类型衬底(1)上方设有第一导电类型外延层(2)，在所述第一导电类型外延层(2)的表面设置条形的互相平行且均匀分布的第一类沟槽(3)，在所述第一类沟槽(3)的外围环绕着第二类沟槽(16)；其特征在于，
    在对器件的俯视角度，在第一类沟槽(3)的中部位置，第一类沟槽(3)内填充满了第一类导电多晶硅(5)，第一类沟槽(3)内的第一类导电多晶硅(5)通过场氧层(6)与外延层(2)绝缘，相邻的第一类沟槽(3)之间的外延层(2)与第一类沟槽(3)的上方设有第二类绝缘介质层(12)，在所述第二类绝缘介质层(12)的上方设有源极金属(13)，所述源极金属(13)通过第二类绝缘介质层(12)内的第一类通孔(15)与第一类沟槽(3)内的第一类导电多晶硅(5)欧姆接触；第二类沟槽(16)内填充满了第一类导电多晶硅(5)，第二类沟槽(16)内的第一类导电多晶硅(5)通过场氧层(6)与外延层(2)绝缘，在对器件的俯视角度，与第一类沟槽(3)平行的第二类沟槽(16)槽段的上方设有第二类绝缘介质层(12)，在所述第二类绝缘介质层(12)的上方设有源极金属(13)，所述源极金属(13)通过第一类通孔(15)与第二类沟槽(16)内的第一类导电多晶硅(5)欧姆接触；
    在对器件的俯视角度，在第一类沟槽(3)的两侧位置，第一类沟槽(3)的下半段设有第一类导电多晶硅(5)，上半段设有第二类导电多晶硅(8)，第一类导电多晶硅(5)与第二类导电多晶硅(8)通过第一类绝缘介质(7)绝缘，第一类导电多晶硅(5)通过场氧层(6)与外延层(2)绝缘，第二类导电多晶硅(8)通过栅氧层(9)与外延层(2)绝缘，相邻的第一类沟槽(3)之间的第一导电类型外延层(2)的表面设有第二导电类型体区(10)，在该第二导电类型体区(10)的表面设有第一导电类型源区(11)，在第一类沟槽(3)与第一导电类型源区(11)的上方设有第二类绝缘介质(12)，在所述第二类绝缘介质(12)的上方设有源极金属(13)，所述源极金属(13)通过第二类绝缘介质层(12)内的第二类通孔(14)与第一导电类型源区(11)、该第二导电类型体区(10)欧姆接触；与第一类沟槽(3)平行的第二类沟槽(16)槽段与相邻的第一类沟槽(3)之间的外延层(2)的表面设有第二导电类型体区(10)，在该第二导电类型体区(10)的上方设有第二类绝缘介质层(12)，在所述第二类绝缘介质层(12)的上方设有源极金属(13)，所述源极金属(13)通过第二类通孔(14)与该第二导电类型体区(10)欧姆接触；
    在对器件的俯视角度，在第一类沟槽(3)的两端的尽头，在第一类沟槽(3)的上方设有第二类绝缘介质层(12)，在所述第二类绝缘介质层(12)的上方设有栅极金属(17)，所述栅极金属(17)通过第二类绝缘介质层(12)内的第三类通孔(18)与第二类导电多晶硅(8)欧姆接触；
    在对器件的俯视角度，在第二类通孔(14)对应的下方的第一导电类型外 延层(2)的底部设有第一导电类型阱区(4)。
  2. 如权利要求1所述的高可靠性功率半导体器件，其特征在于，
    所述第一导电类型阱区(4)内的第一导电类型杂质的浓度高于第一导电类型外延层(2)内的第一导电类型杂质的浓度。
  3. 如权利要求1所述的高可靠性功率半导体器件，其特征在于，
    与第一类沟槽(3)垂直的方向为Y轴方向，在对器件的俯视角度，在Y轴方向上，所述第一导电类型阱区(4)的边缘不越过所述第一类沟槽(3)与第二类沟槽(16)之间的第二类通孔(14)。
  4. 如权利要求1所述的高可靠性功率半导体器件，其特征在于，
    与第一类沟槽(3)平行的方向为X轴方向，在对器件的俯视角度，在X轴方向上，所述第一导电类型阱区(4)的边缘不越过第二类通孔(14)的尽头。
  5. 如权利要求1所述的高可靠性功率半导体器件，其特征在于，
    所述场氧层(6)、栅氧层(9)、第一类绝缘介质(7)、第二类绝缘介质(12)由二氧化硅或氮化硅构成。
  6. 如权利要求1所述的高可靠性功率半导体器件，其特征在于，
    所述功率半导体器件包括N型功率半导体器件和P型功率半导体器件，当所述功率半导体器件为所述N型功率半导体器件时，第一导电类型为N型，第二导电类型为P型，当所述功率半导体器件为所述P型半导体器件时，第一导电类型为P型，第二导电类型为N型。
  7. 一种高可靠性功率半导体器件的制作方法，其特征在于，包括以下步骤：
    步骤一：提供第一导电类型衬底(1)，在所述第一导电类型衬底(1)上生长第一层第一导电类型外延层(2)；
    步骤二：在第一层第一导电类型外延层(2)的表面选择性注入第一导电类型杂质，形成第一导电类型阱区(4)；
    步骤三：形成第二层第一导电类型外延层(2)；
    步骤四：在第一导电类型外延层(2)的表面选择性刻蚀出第一类沟槽(3)与第二类沟槽(16)；
    步骤五：在第一类沟槽(3)与第二类沟槽(16)的底部与侧壁形成场氧层(6)；
    步骤六：淀积导电多晶硅填满第一类沟槽(3)与第二类沟槽(16)，然后刻蚀导电多晶硅，在第一类沟槽(3)与第二类沟槽(16)内形成第一类导电多晶硅(5)；
    步骤七：选择性刻蚀第一类沟槽(3)内的上半部分导电多晶硅；
    步骤八：淀积绝缘介质层填充满第一类沟槽(3)的上半部分；
    步骤九：去除第一导电类型外延层(2)上方的绝缘介质层；
    步骤十：选择性刻蚀第一类沟槽(3)内的部分绝缘介质层，形成第一类绝缘介质(7)；
    步骤十一：在第一类沟槽(3)内形成栅氧层(9)；
    步骤十二：淀积导电多晶硅填充满第一类沟槽(3)的上半部分，然后刻蚀 导电多晶硅，在第一类沟槽(3)的上半部分形成第二类导电多晶硅(8)；
    步骤十三：在器件表面注入第二导电类型杂质后退火形成第二导电类型体区(10)，然后选择性注入第一导电类型杂质，激活后形成第一导电类型源区(11)；
    步骤十四：淀积绝缘介质，在器件表面形成第二类绝缘介质(12)；
    步骤十五：选择性刻蚀第二类绝缘介质(12)与外延层，形成第一类通孔(15)、第二类通孔(14)、第三类通孔(18)；
    步骤十六：在器件表面淀积金属后，选择性刻蚀金属形成源极金属(13)与栅极金属(17)。
  8. 一种高可靠性功率半导体器件的制作方法，其特征在于，包括以下步骤：
    步骤一：提供第一导电类型衬底(1)；
    步骤二：选择性刻蚀第一导电类型衬底(1)，未被刻蚀的部分形成第一导电类型阱区(4)；
    步骤三：形成第一导电类型外延层(2)；
    步骤四：在第一导电类型外延层(2)的表面选择性刻蚀出第一类沟槽(3)与第二类沟槽(16)；
    步骤五：在第一类沟槽(3)与第二类沟槽(16)的底部与侧壁形成场氧层(6)；
    步骤六：淀积导电多晶硅填满第一类沟槽(3)与第二类沟槽(16)，然后刻蚀导电多晶硅，在第一类沟槽(3)与第二类沟槽(16)内形成第一类导电多晶硅(5)；
    步骤七：选择性刻蚀第一类沟槽(3)内的上半部分导电多晶硅；
    步骤八：淀积绝缘介质层填充满第一类沟槽(3)的上半部分；
    步骤九：去除第一导电类型外延层(2)上方的绝缘介质层；
    步骤十：选择性刻蚀第一类沟槽(3)内的部分绝缘介质层，形成第一类绝缘介质(7)；
    步骤十一：在第一类沟槽(3)内形成栅氧层(9)；
    步骤十二：淀积导电多晶硅填充满第一类沟槽(3)的上半部分，然后刻蚀导电多晶硅，在第一类沟槽(3)的上半部分形成第二类导电多晶硅(8)；
    步骤十三：在器件表面注入第二导电类型杂质后退火形成第二导电类型体区(10)，然后选择性注入第一导电类型杂质，激活后形成第一导电类型源区(11)；
    步骤十四：淀积绝缘介质，在器件表面形成第二类绝缘介质(12)；
    步骤十五：选择性刻蚀第二类绝缘介质(12)与外延层，形成第一类通孔(15)、第二类通孔(14)、第三类通孔(18)；
    步骤十六：在器件表面淀积金属后，选择性刻蚀金属形成源极金属(13)与栅极金属(17)。
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