WO2023028893A1 - Structure semi-conductrice, son procédé de fabrication et mémoire flash non-et 3d - Google Patents

Structure semi-conductrice, son procédé de fabrication et mémoire flash non-et 3d Download PDF

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Publication number
WO2023028893A1
WO2023028893A1 PCT/CN2021/115836 CN2021115836W WO2023028893A1 WO 2023028893 A1 WO2023028893 A1 WO 2023028893A1 CN 2021115836 W CN2021115836 W CN 2021115836W WO 2023028893 A1 WO2023028893 A1 WO 2023028893A1
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groove
isolation
gate
dielectric layer
device region
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PCT/CN2021/115836
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English (en)
Chinese (zh)
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黄腾
华子群
石艳伟
姚兰
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长江存储科技有限责任公司
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Priority to PCT/CN2021/115836 priority Critical patent/WO2023028893A1/fr
Priority to CN202180003435.XA priority patent/CN113939906A/zh
Publication of WO2023028893A1 publication Critical patent/WO2023028893A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • the present application relates to the field of semiconductor technology, in particular to a semiconductor structure, a manufacturing method and a three-dimensional memory.
  • Three-dimensional memory (3D NAND Flash) is widely used in computers, solid-state hard drives and electronic devices due to its advantages of high storage density and fast programming speed.
  • the market requires that the storage capacity be continuously increased without increasing the storage area.
  • the storage density of the three-dimensional memory needs to be increased and the size reduced.
  • the peripheral circuit of the three-dimensional memory includes devices with various operating voltages, such as high-voltage devices (HV device) and low-voltage devices (LV device), etc., and there are PMOS devices, NMOS devices and shallow trench isolation (STI) devices in high-voltage devices and low-voltage devices. , shallow trench isolation), shallow trench isolation is used to isolate adjacent devices.
  • HV device high-voltage devices
  • LV device low-voltage devices
  • PMOS devices NMOS devices
  • STI shallow trench isolation
  • shallow trench isolation shallow trench isolation
  • the purpose of this application is to provide a semiconductor structure, a manufacturing method and a three-dimensional memory, which can reduce the process flow and save costs while achieving a good isolation effect.
  • the present application provides a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate including a first device region and a second device region; forming a plurality of first grooves on the first device region, A second groove is formed on the second device region, and the first groove and the second groove are formed at the same time; a first isolation trench is formed on the first device region, and the first isolation trench separates adjacent first grooves ; forming a second isolation trench at a position corresponding to the second groove in the second device region.
  • the first isolation trench and the second isolation trench are formed simultaneously.
  • the first groove also includes:
  • Ion doping is performed on the first device region and the second device region.
  • the second isolation trench is formed in the second device region corresponding to the position of the second groove, it further includes:
  • a first dielectric layer and a second dielectric layer are respectively formed on the first device region and the second device region, the first dielectric layer is at least partly located on the inner wall of the first groove, and the first dielectric layer
  • the thickness of the layer is smaller than the thickness of the second dielectric layer; the first gate and the second gate are respectively formed on the first dielectric layer and the second dielectric layer, and the first gate A source and a drain are respectively formed on both sides of the second gate.
  • a plurality of third grooves are formed in the second device region, and the second grooves are located between adjacent third grooves.
  • a first dielectric layer and a second dielectric layer are respectively formed on the first device region and the second device region, the first dielectric layer is at least partially located on the inner wall of the first groove, and the second dielectric layer is at least partially located on the third groove
  • the inner wall of the first dielectric layer is less than the thickness of the second dielectric layer; the first grid and the second grid are respectively formed on the first dielectric layer and the second dielectric layer, and the first grid and the second grid
  • a source and a drain are formed on both sides of the pole, respectively.
  • the second isolation trench is formed in the second device region corresponding to the position of the second groove, it further includes:
  • Dielectric materials are respectively filled in the first isolation trench and the second isolation trench to form the first isolation structure and the second isolation structure.
  • an embodiment of the present application also provides a semiconductor structure, including: a substrate, the substrate includes a first device region and a second device region; the first device region is provided with a plurality of first transistors and located adjacent The first isolation structure between the first transistors, the gate of the first transistor is at least partly located in the first groove; the second device area is provided with a plurality of second transistors and the first transistor located between adjacent second transistors Two isolation structures, the depth of the second isolation structure is greater than the depth of the first isolation structure.
  • the depth of the second isolation structure is the sum of the depth of the first isolation structure and the depth of the first groove.
  • the first transistor includes a first dielectric layer at least partially located in the first groove
  • the gate of the first transistor is located on the first dielectric layer
  • the second transistor includes a second dielectric layer at least partially located in the third groove
  • the second gate of the second transistor is at least partially located in the third groove
  • the thickness of the first dielectric layer is smaller than the thickness of the second dielectric layer.
  • an embodiment of the present application further provides a three-dimensional memory, including an array storage structure and a peripheral circuit, wherein any semiconductor structure described above is located in the peripheral circuit.
  • the present application provides a semiconductor structure, a manufacturing method, and a three-dimensional memory.
  • the manufacturing method of the semiconductor structure includes: providing a substrate, the substrate including a first device region and a second device region; forming a plurality of first device regions on the first device region A groove, a second groove is formed on the second device region, and the first groove and the second groove are formed simultaneously; a first isolation trench is formed in the first device region, and the first isolation trench separates adjacent The first groove; forming a second isolation trench at a position corresponding to the second groove in the second device region, by forming the second groove and the first groove simultaneously, and forming a second isolation based on the position of the second groove grooves, so that the depth of the second isolation trench corresponds to the sum of the depth of the first groove and the depth of the first isolation trench, without additional process, in the first device region and the second device region respectively
  • the first isolation trench and the second isolation trench with different depths are formed to meet the isolation requirements of different semiconductor devices.
  • FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present application
  • Figure 2 is a schematic structural view of the substrate provided in one embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of forming a first active region and a second active region in one embodiment of the present application
  • Fig. 4 is a schematic structural diagram of forming a first groove and a second groove in one embodiment of the present application
  • FIG. 5 is a schematic structural diagram of forming a first isolation trench and a second isolation trench in an embodiment of the present application
  • Figure 6 is a schematic structural view of forming a first isolation structure and a second isolation structure in one embodiment of the present application
  • FIG. 7 is a schematic structural diagram of forming a first dielectric layer in one embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of forming a first gate in an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a semiconductor structure formed in an embodiment of the present application.
  • FIG. 10 is a flowchart of a method for fabricating a semiconductor structure according to another embodiment of the present application.
  • Fig. 11 is a schematic structural diagram of forming the first groove, the second groove and the third groove in another embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of forming a first isolation trench and a second isolation trench in another embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of forming a first isolation structure and a second isolation structure in another embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of forming a first dielectric layer and a second dielectric layer in another embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of forming a first gate and a second gate in another embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of forming a semiconductor structure in another embodiment of the present application.
  • 17 is a schematic structural diagram of forming a semiconductor structure including multiple transistors in another embodiment of the present application.
  • Fig. 18 is a schematic block diagram of a storage system in some embodiments of the present application.
  • the present application provides a method for manufacturing a semiconductor structure.
  • the specific process may include the following with reference to the structural diagrams in FIG. 2 to FIG. 9:
  • Step S101 providing a substrate 210, and the substrate 210 includes a first device region and a second device region.
  • FIG. 2 shows the structure formed in step S101 , including: a substrate 210 located in the first device region and the second device region of the A1 region and the A2 region shown in FIG. 2 .
  • the substrate 210 serves as the basis for forming semiconductor devices.
  • the substrate 210 is a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), or other materials.
  • step S101 it also includes:
  • Step S105 performing ion doping on the first device region and the second device region.
  • FIG. 3 shows the structure formed in step S104 , including: a substrate 210 , a first active region 221 and a second active region 222 .
  • ion doping is performed on the first device region and the second device region, and the first active region 221 and the second active region 222 can be formed in the first device region and the second device region respectively, and the first groove 231 is located in the first active area 221 (ie, the first device area), and the second groove 232 is located in the second active area 222 (ie, the second device area).
  • the active area (Active Area, AA) refers to the area covered by the formation of the source electrode, the drain electrode and the conductive trench.
  • the substrate 210 is implanted with one or more ions to form a well region, and then the substrate 210 is divided into regions one after another through an etching process, and these regions may be the first active regions.
  • Region 221 or second active region 222 that is, the first active region 221 and the second active region 222 are formed on the substrate 210 .
  • a high voltage (HV) device region and a low voltage (LV) device region are formed in the peripheral circuit of the three-dimensional memory.
  • the first device region and the second device region may be a low voltage device region and a high voltage device region respectively.
  • Step S102 forming a plurality of first grooves 231 on the first device region, forming second grooves 232 on the second device region, and forming the first grooves 231 and the second grooves 232 at the same time.
  • step S102 shows the structure formed in step S102, including: a substrate 210, a first active region 221 and a first groove 231 located in the first active region 221, a second active region 222 and a groove located in the second active region
  • the second groove 232 in 222 can form the first groove 231 and the second groove 232 in the vertical direction of the substrate 210 in the first active region 221 and the second active region 222 respectively by an etching process. .
  • Step S103 forming a first isolation trench 241 in the first device region, and the first isolation trench 241 separates adjacent first grooves 231 .
  • Step S104 forming a second isolation trench 242 at a position corresponding to the second groove 232 in the second device region.
  • FIG. 5 shows the structure formed in steps S103 and S104, including: a substrate 210, a first active region 221, a first groove 231 and a first isolation trench 241 located in the first active region 221, a second active region 222 and the second isolation trench 242 located in the second active region 222, wherein the depth of the first groove 231 is L1, the depth of the first isolation trench 241 is L2, and the depth of the second isolation trench 242 is L3, the depth L3 of the second isolation trench 242 is greater than the depth L2 of the first isolation trench 241 .
  • the first groove 231 and the second groove 232 can be simultaneously formed on the substrate 210 through an etching process, so the depths of the first groove 231 and the second groove 232 are consistent, that is, the first groove 231 and the second groove 232 have the same depth.
  • the depths of the groove 231 and the second groove 232 are both L1, after forming the first groove 231 and the second groove 232, in the first active region 221 not corresponding to the first groove 231, by etching
  • the first isolation trench 241 is formed by the process, and the second isolation trench 242 is formed at the position corresponding to the second groove 232 in the second device region.
  • the corresponding here refers to continuing to etch downward at the bottom of the second groove 232 Forming the second isolation trench 242, by forming the second groove 232 and the first groove 231 simultaneously, and forming the second isolation trench 242 based on the position of the second groove 232, the depth of the second isolation trench 242 is L3 is greater than the depth L2 of the first isolation trench 241, without additional process, the first isolation trench 241 and the second isolation trench 242 with different depths are respectively formed in the first device region and the second device region, Meet the isolation requirements of different semiconductor devices.
  • first isolation trench 241 and the second isolation trench 242 are formed simultaneously.
  • steps S103 and S104 are performed at the same time, that is, when the first isolation trench 241 and the second isolation trench 242 are formed at the same time, the first active region 221 not corresponding to the first groove 231 is formed by the etching process.
  • the first isolation trench 241 is formed, and at the same time, the second isolation trench 242 is formed at the position corresponding to the second groove 232 in the second device region, that is, the bottom of the second groove 232 is etched downward to form the second isolation trench 242.
  • the depth L2 of the first isolation trench 241 is consistent with the depth of further etching in the second groove 232, therefore, the depth L3 of the second isolation trench 242 is the depth L1 of the first groove 231 and the sum of the depth L2 of the first isolation trench 241, by simultaneously forming the first isolation trench and the second isolation trench with different depths, while meeting the isolation requirements of different semiconductor devices, the process flow is reduced and the cost is saved.
  • the further development of technology is possible.
  • the depth L3 of the second isolation trench 242 is the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241, but in the actual process, due to The second isolation trench 242 is formed by etching on the basis of the second groove 232, and the second isolation trench 242 is formed by etching on a basis not corresponding to the first groove 231.
  • the first The etching depths of the isolation trench 241 and the second isolation trench 242 are basically different. Based on the difference in the initial depths of the first isolation trench 241 and the second isolation trench 242, in the process of continuing the etching, As the etching depth gradually increases, the depth of further etching will be affected by the existing etching depth.
  • the depth L3 of the second isolation trench 242 is the same as the depth L1 of the first groove 231. There may be a slight deviation from the sum of the depth L2 of the first isolation trench 241, but the depth L3 of the second isolation trench 242 is positively related to the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241 , that is, the depth L3 of the second isolation trench 242 always corresponds to the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241 .
  • step S104 it also includes:
  • a dielectric material is filled in the first isolation trench 241 and the second isolation trench 242 respectively to form a first isolation structure 243 and a second isolation structure 244 .
  • the dielectric material includes oxide
  • STI shallow trench isolation
  • the first isolation structure 243 and the second isolation structure 244 can be formed by filling the dielectric material in the first isolation trench 241 and the second isolation trench 242 respectively by thermal oxidation reaction (Thermal Oxidation), because the second isolation trench 242
  • the depth L3 always corresponds to the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241, and the depth of the second isolation structure 244 is greater than the depth of the first isolation structure 243 to meet the isolation requirements of different semiconductor devices .
  • the material of shallow trench isolation is oxide, such as silicon dioxide (SiO2).
  • the dielectric material filled in the first isolation trench 241 and the second isolation trench 242 is not limited as long as it can achieve lateral isolation.
  • step S104 it also includes:
  • Step S106 forming a first dielectric layer 251 on the first device region, the first dielectric layer 251 is at least partially located on the inner wall of the first groove 231 .
  • step S106 shows the structure formed in step S106, including: the substrate 210, the first active region 221, the first isolation structure 243 located in the first active region 221, the first groove 231, and the first groove 231 located in the first groove 231.
  • the height of layer 251 is lower than the top surface of substrate 210 .
  • a second dielectric layer 252 may also be formed on the second device region.
  • the first groove 231 is located in the substrate 210 for forming a gate corresponding to the first groove 231, and the first dielectric layer 251 is located in the first groove 231 as a gate oxide layer for holding the substrate 210 and the insulation between the gate.
  • the material of the substrate 210 is silicon, and the natural oxide of silicon is silicon dioxide.
  • a high-quality dielectric layer such as the first dielectric layer 251 serving as a gate oxide layer, can be formed through a thermal oxidation reaction. Also during the process, the thermally grown oxide can be used as a mask for implantation, diffusion and etching.
  • the method for forming the second dielectric layer 252 is basically the same as the method for forming the first dielectric layer 251, and corresponding adjustments can be made according to the position, thickness, and width of the second dielectric layer 252. Since the formation of the first dielectric layer 252 The method of the dielectric layer 251 has been described in detail, and will not be repeated here.
  • the thermal oxidation reaction means that the silicon wafer is placed in an atmosphere of a gaseous oxidant such as molecular oxygen (O2) and/or water vapor (H2O) at high temperature (typically 900-1200° C.).
  • a gaseous oxidant such as molecular oxygen (O2) and/or water vapor (H2O) at high temperature (typically 900-1200° C.).
  • the thermal oxidation reaction is a dry oxygen method
  • the thermal oxidation reaction is a wet oxygen method.
  • an initial oxide layer will be formed at the gas/solid interface. The oxidant needs to diffuse through the initial oxide layer to reach the surface of the wafer to form an oxide layer.
  • the first dielectric layer 251 with controllable thickness can be formed by controlling the temperature, rate constant (such as the type of oxidant, the characteristics of the wafer surface) and the reaction time of the thermal oxidation reaction, so that the thickness of the first dielectric layer 251 is smaller than that of the first dielectric layer 251.
  • a depth of the groove 231 that is, the first dielectric layer 251 is at least partially located on the inner wall of the first groove 231 , and the height of the first dielectric layer 251 is lower than the top surface of the substrate 210 .
  • Step S107 forming a first gate 261 on the first dielectric layer 251 , and forming a source and a drain on both sides of the first gate 261 .
  • FIG. 8 shows the structure formed by "forming the first gate 261 on the first dielectric layer 251" in step S107, including: the substrate 210; the first active region 221 and the first isolation structure located in the first active region 221 243, the first groove 231, the first dielectric layer 251 and the first gate 261 in the first groove 231; the second active region 222 and the second isolation structure 244 in the second active region 222, Wherein, a part of the first gate 261 is located in the first groove 231 , and another part is located above the top surface of the substrate 210 .
  • a second gate 262 may also be formed on the second dielectric layer 252 in the second device region.
  • the conductive material may be filled in the first groove 231 by physical vapor deposition (PVD), so as to form the first gate 261 corresponding to the first groove 231, the first gate A part of the electrode 261 is located in the first groove 231 , and another part is located above the top surface of the substrate 210 , that is, the top of the first gate 261 is higher than the top of the substrate 210 .
  • PVD physical vapor deposition
  • a recess gate structure Recess Gate
  • a first groove 231 is formed on the substrate 210, and then a first dielectric layer 251 and a first gate 261 are sequentially formed in the first groove 231, so as to form a part located in the substrate.
  • a part of the first gate 261 located above the substrate 210 increases the effective contact area between the first gate 261 and the first active region 221 through the concave gate structure, and increases the channel of the first gate 261.
  • the length improves the problem of slow reading and writing speed of semiconductor devices, so that the area of semiconductor devices can be made smaller.
  • the isolation requirements of different semiconductor devices are met by using the first isolation structure 243 and the second isolation structure 244 with different depths formed in different active regions (that is, the Dual STI process).
  • the dual STI process Integration, the area of peripheral circuits can be effectively reduced and the isolation requirements of different semiconductor devices can be met, which provides the possibility for the further development of semiconductor technology.
  • the method for forming the second gate 262 is basically the same as the method for forming the first gate 261, and can be made according to the position where the second dielectric layer 252 is formed and the thickness and width of the second gate 262. Since the method for forming the first gate 261 has been described in detail, details will not be repeated here.
  • the first gate 261 is used to control whether the semiconductor device is turned on, the first gate 261 is mostly made of conductive materials, such as polysilicon (Poly), tungsten (W) or aluminum (Al). Yes, without limitation.
  • FIG. 9 shows the structure formed in the step S107 "and forming the source and the drain on both sides of the first gate 261", including: the substrate 210; the first active region 221 and the first active region 221; The first isolation structure 243, the first groove 231, the first dielectric layer 251 located in the first groove 231 and the first transistor corresponding to the first gate 261; the second active region 222 and the second active region 222 The second isolation structure 244 in the region 222 , wherein a part of the first gate 261 is located in the substrate 210 and another part is located above the substrate 210 .
  • a source and a drain may be respectively formed on both sides of the second gate 262 in the second device region.
  • the thermally grown oxide can be used as a mask for ion implantation, diffusion and etching.
  • the first gate 261 is formed on the first dielectric layer 251.
  • the first gate 261 Since the first gate 261 is very thick and the top of the first gate 261 is higher than the substrate 210, the first gate 261 can be used as a mask layer for forming the source and drain to prevent ion implantation into the corresponding region below the first gate 261 (the thickness of the first gate 261 is thick enough so that the ions The implanted atoms cannot reach the first dielectric layer 251), only the source and the drain are formed on both sides of the first gate 261 (while the ion-implanted atoms can easily pass through the corresponding gate oxide layer above the source and the drain , to form the source and the drain), that is, according to the first gate 261, a self-alignment (Self Align) is formed between the source, the drain and the first gate 261.
  • Self Align Self Align
  • the method for forming the source and drain of the second gate 262 is basically the same as the method for forming the source and drain of the first gate 261, and the position and thickness of the second gate 262 can be And the width and the position, width and depth of the source and drain of the second gate 262 are adjusted accordingly. Since the method for forming the source and drain of the first gate 261 has been described in detail, it will not be described here. Let me repeat.
  • transistors can be divided into PMOS transistors and NMOS transistors, wherein PMOS transistors are also called P-Metal-Oxide-Semiconductor (P-Metal-Oxide-Semiconductor), and NMOS transistors are also called N-Type Metal-Oxide-Semiconductor. (N-Metal-Oxide-Semiconductor).
  • the first transistor includes a first gate 261 and a source and a drain located on both sides of the gate. By applying a driving voltage to the first gate 261, whether the source is connected to the drain is controlled, thereby realizing the control of the semiconductor device. Whether the circuit is conducting.
  • FIGS. 2 to 3 and FIGS. 11 to 16 It is a schematic flow chart of a method for manufacturing a semiconductor structure according to another embodiment of the present application. The specific process is compared with the structural diagrams of FIGS. 2 to 3 and FIGS. 11 to 16, and may include the following:
  • a plurality of third grooves 333 are formed in the second device region, and the second grooves 332 are located between adjacent third grooves 333 .
  • the substrate 210 different from the structure formed in step S102 shown in FIG. 4, it includes: a substrate 210 and a first groove 231 and a second groove 232 formed on the substrate 210, as shown in FIG.
  • the schematic diagram of the structure of forming the first groove 331, the second groove 332 and the third groove 333 in the embodiment includes: the substrate 310, the first active region 321 and the first groove located in the first active region 321 The groove 331 , the second active region 322 , and the second groove 332 and the third groove 333 located in the second active region 322 .
  • FIG. 12 shows the structure formed in the adjusted step S103 and step S104, including: the substrate 310; The first groove 331 and the first isolation trench 341 of an active region 321; the second active region 322 and the second isolation trench 342 and the third groove 333 in the second active region 322, wherein,
  • the depth of the first groove 331 is L4, the depth of the first isolation trench 341 is L5, the depth of the second isolation trench 342 is L6, and the depth L6 of the second isolation trench 342 is the depth L4 of the first groove 331 and the depth L5 of the first isolation trench 341 .
  • step S104 it also includes:
  • a dielectric material is filled in the first isolation trench 341 and the second isolation trench 342 respectively to form a first isolation structure 343 and a second isolation structure 344 .
  • multiple isolation structures may also exist in the first active region 321 and the second active region 322 and between the first active region 321 and the second active region 322, for example,
  • the first isolation structure 343 and the second isolation structure 344, the first isolation structure 343 and the second isolation structure 344 may be shallow trench isolation (STI, shallow trench isolation), which play a role of lateral isolation for NMOS devices and PMOS devices.
  • STI shallow trench isolation
  • the first isolation structure 343 and the second isolation structure 344 can be respectively formed in the first isolation trench 341 and the second isolation trench 342 by thermal oxidation reaction (Thermal Oxidation), since the depth L6 of the second isolation trench 342 always corresponds to Based on the sum of the depth L4 of the first groove 331 and the depth L5 of the first isolation trench 341, the depth of the second isolation structure 344 corresponds to the depth L4 of the first groove 331 and the depth of the first isolation structure 343, so as to satisfy Isolation requirements of different semiconductor devices.
  • the material of shallow trench isolation is oxide, such as silicon dioxide.
  • steps S106 to S107 need to be adjusted according to the third groove 333, for example, steps S108 to Step S109, as shown in Fig. 14 to Fig. 16 respectively correspond to the structural schematic diagrams formed in steps S108 to S109.
  • step S104 it also includes:
  • Step S108 Forming a first dielectric layer 351 and a second dielectric layer on the first device region and the second device region respectively, the first dielectric layer 351 is at least partially located on the inner wall of the first groove, and the second dielectric layer is at least partially located on the first groove In the inner wall of the three grooves, the thickness of the first dielectric layer is smaller than the thickness of the second dielectric layer.
  • FIG. 14 shows the structure formed in step S108, including: a substrate 310; a first active region 321, a first isolation structure 343 located in the first active region 321, a first groove 331, and a first groove 331 located in the first groove 331.
  • the first dielectric layer 351 is at least partially located on the inner wall of the first groove 331, the second dielectric layer 352 is at least partially located on the inner wall of the third groove 333, and the height of the first dielectric layer 351 and the second dielectric layer 352 is lower than the substrate 310 top surface.
  • Step S109 Forming a first gate 361 and a second gate on the first dielectric layer 351 and the second dielectric layer 352 respectively, and forming a source and a gate respectively on both sides of the first gate 361 and the second gate 362 drain.
  • FIG. 15 shows the structure formed by "forming the first gate 361 and the second gate 362 respectively on the first dielectric layer 351 and the second dielectric layer 352" in step S109, including: a substrate 310; a first active region 321 And the first isolation structure 343 in the first active region 321, the first groove 331, the first dielectric layer 351 in the first groove 331, and the first gate 361; the second active region 322 and the The second isolation structure 344 in the second active region 322, the third groove 333, the second dielectric layer 352 and the second gate 362 located in the third groove 333, wherein the first gate 361 and the second gate Parts of the poles 362 are respectively located in the substrates 310 , and the other parts are respectively located above the substrates 310 .
  • the gate is used to control whether the semiconductor device is turned on, and the first gate 361 and the second gate 362 are mostly made of conductive materials, such as polysilicon (Poly), tungsten (W) or aluminum (Al), as long as they are conductive Materials can be used, and there is no specific limitation.
  • conductive materials such as polysilicon (Poly), tungsten (W) or aluminum (Al), as long as they are conductive Materials can be used, and there is no specific limitation.
  • the first groove 331 and the third groove 333 can be filled with conductive material by physical vapor deposition (PVD) respectively, so as to form The first grid 361 and the second grid 362 of the first groove 331 and the third groove 333, a part of the first grid 361 and the second grid 362 are respectively located in the first groove 331, and the other part is respectively located in the substrate 310 , that is, the top of the first gate 361 is higher than the top of the substrate 310 .
  • PVD physical vapor deposition
  • the first groove 331 and the third groove 333 are formed on the substrate 310, and then the first dielectric layer 351 and the first grid 361 are formed in the first groove 331 and in sequence
  • the second dielectric layer 352 and the second gate 362 are sequentially formed in the third groove 333 and in the third groove 333 to form a part respectively located in the first groove 331 and the third groove 333, and another part located in the substrate
  • the first gate 361 and the second gate 362 above the top surface of 310 increase the effective contact area between the gate and the active region through the concave gate structure, and increase the contact area between the first gate 361 and the second gate 362.
  • the length of the channel improves the problem of slow reading and writing speed of the semiconductor device, so that the area of the semiconductor device can be further made smaller.
  • the process flow is reduced while meeting the isolation requirements of different semiconductor devices, and the cost is saved.
  • the area of peripheral circuits can be effectively reduced and the isolation requirements of different semiconductor devices can be met, which provides the possibility for the further development of semiconductor technology.
  • FIG. 16 shows the structure formed in the step S109 "and forming the source and the drain on both sides of the first gate 361 and the second gate 362", including: the substrate 310, the first active region 321 and the A first isolation structure 343 of an active region 321, a first groove 331, a first dielectric layer 351 located in the first groove 331, a first transistor corresponding to the first gate 361, and a second active region 322 And the second isolation structure 344 located in the second active region 322, the third groove 333, the second dielectric layer 352 located in the third groove 333, and the second transistor corresponding to the second gate 362, wherein, Parts of the first gate 361 and the second gate 362 are respectively located in the first groove 331 and the third groove 333 , and the other part is located above the top surface of the substrate 310 .
  • the transistor includes a gate and a source and a drain located on both sides of the gate.
  • a driving voltage By applying a driving voltage to the gate, the conduction from the source to the drain is controlled, so as to control whether the circuit in the semiconductor device is conducted.
  • FIG. 17 it is a schematic structural diagram of a semiconductor device in which a plurality of first transistors and a plurality of second transistors are respectively formed in the first device region and the second device region.
  • a first transistor there are multiple transistors formed in the first device region a first transistor, a first isolation structure 343 is formed between the plurality of first transistors, and the first isolation structure 343 is used to separate the plurality of first transistors; a plurality of second transistors are formed in the second device region, A second isolation structure 344 is respectively formed between the second transistors, and the second isolation structure 344 is used to isolate a plurality of first transistors.
  • the first device region and the second device region are low-voltage device regions and high-voltage device regions respectively.
  • the depth of the second isolation structure 344 is greater than that of the first isolation
  • the depth of the structure 343 is to meet the isolation requirements of different semiconductor devices.
  • step S106 has been described in detail above.
  • the process is basically the same, except that corresponding adjustments are made according to the third groove 333 , which has been described in detail above, and will not be described in detail here.
  • a third device region is formed in the peripheral circuit of the three-dimensional memory, wherein the first device region is far away from the second device region.
  • a third device region is also formed on the side.
  • the third device region (not shown in the figure), the first device region and the second device region may be an ultra-low voltage device region, a low voltage device region and a high voltage device region respectively.
  • one or more device areas different from the ultra-low voltage device area, low voltage device area, and high voltage device area may also be formed in the peripheral circuit, without limitation.
  • the third device region or more device regions can be passed similar to
  • step S101 to step S107 forms multiple recessed gate structures and shallow trench isolation structures with different depths in different device regions to meet the isolation requirements of different semiconductor devices. Since the principles are similar and have been described in detail above, No more details here.
  • the embodiment of the present application also provides a semiconductor structure, including:
  • the substrate includes a first device region and a second device region;
  • the first device region is provided with a plurality of first transistors and a first isolation structure 243 between adjacent first transistors, and the first gate 261 of the first transistor is at least partly located in the first groove 231;
  • the second device region is provided with a plurality of second transistors and a second isolation structure between adjacent second transistors, and the depth of the second isolation structure 244 is greater than that of the first isolation structure 243 .
  • the depth of the second isolation structure 244 is the sum of the depth of the first isolation structure 243 and the depth of the first groove 231 .
  • FIG. 9 it is a schematic structural diagram of a semiconductor structure formed in an embodiment of the present application, including: a substrate 210, a first active region 221, a first isolation structure 243 located in the first active region 221, a first The groove 231, the first dielectric layer 251 in the first groove 231 and the first transistor corresponding to the first gate 261, the first active region 222 and the second isolation structure in the first active region 222 244, wherein a part of the first gate 261 is located in the first groove 331, and the other part is located above the top surface of the substrate 210, and the depth of the second isolation structure 244 corresponds to the depth of the first groove 231 and the first isolation The sum of the depths of structures 243 .
  • the semiconductor structure further includes: the first transistor includes a first dielectric layer 251 at least partially located in the first groove 231 , and the first gate 261 of the first transistor is located on the first dielectric layer 251 .
  • FIG. 9 which is a schematic structural view of the semiconductor structure formed by performing steps S101 to S107, a first groove 231 is formed on the substrate 210 by using a concave gate structure, and then in the first groove 231
  • the first dielectric layer 251 and the first gate 261 are sequentially formed to form a part of the first gate 261 located in the first groove 231 and a part of the first gate 261 located above the top surface of the substrate 210, and the gate structure is enlarged by the concave gate structure.
  • the effective contact area with the active region increases the channel length of the first gate 261 and improves the problem of slow reading and writing speed of the semiconductor device, so that the area of the semiconductor device can be made smaller.
  • the process flow is reduced and the cost is saved.
  • the area of peripheral circuits can be effectively reduced and the isolation requirements of different semiconductor devices can be met, which provides the possibility for the further development of semiconductor technology.
  • the semiconductor structure further includes: the first transistor includes a first dielectric layer 351 at least partly located in the first groove 331, the first gate 361 of the first transistor is located on the first dielectric layer 351, and the second transistor includes at least The second dielectric layer 352 is partially located in the third groove 333 , the second gate 362 of the second transistor is at least partially located in the third groove 333 , and the thickness of the first dielectric layer 351 is smaller than that of the second dielectric layer 352 .
  • FIG. 16 it is a schematic structural diagram of a semiconductor structure formed in another embodiment of the present application, including: a substrate 310, a first active region 321, and a The first isolation structure 343 of the active region 321, the first groove 331, the first dielectric layer 351 located in the first groove 331 and the first transistor corresponding to the first gate 361, the second active region 322 and The second isolation structure 344 located in the second active region 322, the third groove 333, the second dielectric layer 352 located in the third groove 333, and the second transistor corresponding to the second gate 362, wherein the first Part of the first gate 361 and the second gate 362 are located in the substrate 310, and the other part is located above the substrate 310, and the depth of the second isolation structure 344 corresponds to the depth of the first groove 331 and the depth of the first isolation structure 343 Sum.
  • the subsequent steps S103 to S106 need to be based on the third groove 333
  • the subsequent steps S103 to S106 need to be based on the third groove 333
  • Corresponding adjustments are made to finally form a schematic structural diagram of the semiconductor structure as shown in FIG. 16 , which has been described in detail above and will not be repeated here.
  • the concave gate structure Recess Gate
  • the first groove 331, the second groove 332 and the third groove 333 are formed on the substrate 310, and then the first dielectric layer 351 and the first dielectric layer 351 are sequentially formed in the first groove 331.
  • the first grid 361, the second dielectric layer 352 and the second grid 362 are sequentially formed in the third groove 333 to form a part located in the first groove 331 and the third groove 333, and a part located in the substrate 310
  • the length of the channel improves the problem of slow reading and writing speed of the semiconductor device, so that the area of the semiconductor device can be further made smaller.
  • the process flow is reduced and the cost is saved.
  • the area of peripheral circuits can be effectively reduced and the isolation requirements of different semiconductor devices can be met, which provides the possibility for the further development of semiconductor technology.
  • the first device region and the first device region may be respectively a low-voltage device region and a high-voltage device region, which have been described in detail above and will not be repeated here.
  • a third device region is formed in the peripheral circuit of the three-dimensional memory, wherein the first device region is far away from the second device region.
  • a third device region is also formed on the side.
  • the third device region, the first device region and the second device region may be an ultra-low voltage device region, a low voltage device region and a high voltage device region respectively.
  • one or more device areas that are different from the high-voltage device area, low-voltage device area, and ultra-low-voltage device area may also be formed in the peripheral circuit, without limitation.
  • a plurality of recessed gate structures can be formed in the third device region or more device regions through a process similar to step S101 to step S107 and in different devices Shallow trench isolation structures with different depths are formed in the regions to meet the isolation requirements of different semiconductor devices. Since the principles are similar and have been described in detail above, details will not be repeated here.
  • the embodiment of the present application also provides a three-dimensional memory (not shown in the figure), the three-dimensional memory includes an array storage structure and peripheral circuits, wherein any one of the above-mentioned semiconductor structures is located in in the peripheral circuit.
  • a three-dimensional memory includes an array storage structure (Array) and a peripheral circuit (Periphery). Above or below the array storage structure may also be located around the array storage structure, and peripheral circuits are used to control the corresponding array storage structure.
  • the semiconductor structure can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), etc., which is not specifically limited.
  • an embodiment of the present application further provides a storage system, the controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data, and the three-dimensional memory includes any one of the semiconductor structures described above.
  • the storage system 400 includes a controller 410 and one or more three-dimensional memories 420 , wherein the three-dimensional memories 420 include one or more array storage structures 421 and peripheral circuits 422 .
  • the storage system 400 can communicate with the host 500 through the controller 410 , wherein the controller 410 can be connected to the one or more three-dimensional memories 420 via channels in the one or more three-dimensional memories 420 .
  • Each three-dimensional memory 420 may be managed by the controller 410 via channels in the three-dimensional memory 420 .
  • the manufacturing method of the semiconductor structure includes: providing a substrate, the substrate includes a first device region and a second device region; on the first device region Forming a plurality of first grooves, forming second grooves on the second device region, and forming the first grooves and the second grooves at the same time; forming first isolation trenches in the first device region, the first isolation trenches Opening adjacent first grooves; forming a second isolation trench at a position corresponding to the second groove in the second device region, by forming the second groove and the first groove simultaneously, and based on the position of the second groove forming a second isolation trench, so that the depth of the second isolation trench corresponds to the sum of the depth of the first groove and the depth of the first isolation trench; A first isolation trench and a second isolation trench with different depths are respectively formed in the two device regions to meet the isolation requirements of different semiconductor devices.

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

L'invention concerne une structure semi-conductrice, son procédé de fabrication et une mémoire flash NON-ET 3D. Le procédé de fabrication de la structure semi-conductrice consiste à : fournir un substrat qui comprend une première région de dispositif et une deuxième région de dispositif ; former une pluralité de premières rainures dans la première région de dispositif, et former une deuxième rainure dans la deuxième région de dispositif, les premières rainures et la deuxième rainure étant formées simultanément ; former des premières tranchées d'isolation dans la première région de dispositif ; et former une deuxième tranchée d'isolation dans la deuxième région de dispositif et à une position correspondant à la deuxième rainure.
PCT/CN2021/115836 2021-08-31 2021-08-31 Structure semi-conductrice, son procédé de fabrication et mémoire flash non-et 3d WO2023028893A1 (fr)

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CN202180003435.XA CN113939906A (zh) 2021-08-31 2021-08-31 半导体结构、制作方法及三维存储器

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW466685B (en) * 1999-12-09 2001-12-01 Nippon Electric Co Element isolating method in semiconductor integrated circuit device, semiconductor integrated circuit device and manufacturing method thereof
US20050090059A1 (en) * 2003-10-22 2005-04-28 Hynix Semiconductor Inc. Method for manufacturing a non-volatile memory device
CN101286480A (zh) * 2007-02-07 2008-10-15 旺宏电子股份有限公司 在存储器阵列与周边逻辑元件上形成硅化物的结构及方法
US20090159966A1 (en) * 2007-12-20 2009-06-25 Chih-Jen Huang High voltage semiconductor device, method of fabricating the same, and method of fabricating the same and a low voltage semiconductor device together on a substrate
US20100207204A1 (en) * 2009-02-13 2010-08-19 Kim Young-Mok Semiconductor device and method of fabricating the same
US20220085048A1 (en) * 2020-09-17 2022-03-17 Samsung Electronics Co., Ltd. Semiconductor device and electronic system including the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW466685B (en) * 1999-12-09 2001-12-01 Nippon Electric Co Element isolating method in semiconductor integrated circuit device, semiconductor integrated circuit device and manufacturing method thereof
US20050090059A1 (en) * 2003-10-22 2005-04-28 Hynix Semiconductor Inc. Method for manufacturing a non-volatile memory device
CN101286480A (zh) * 2007-02-07 2008-10-15 旺宏电子股份有限公司 在存储器阵列与周边逻辑元件上形成硅化物的结构及方法
US20090159966A1 (en) * 2007-12-20 2009-06-25 Chih-Jen Huang High voltage semiconductor device, method of fabricating the same, and method of fabricating the same and a low voltage semiconductor device together on a substrate
US20100207204A1 (en) * 2009-02-13 2010-08-19 Kim Young-Mok Semiconductor device and method of fabricating the same
US20220085048A1 (en) * 2020-09-17 2022-03-17 Samsung Electronics Co., Ltd. Semiconductor device and electronic system including the same

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