WO2023028893A1

WO2023028893A1 - Semiconductor structure, manufacturing method therefor, and 3d nand flash

Info

Publication number: WO2023028893A1
Application number: PCT/CN2021/115836
Authority: WO
Inventors: 黄腾; 华子群; 石艳伟; 姚兰
Original assignee: 长江存储科技有限责任公司
Priority date: 2021-08-31
Filing date: 2021-08-31
Publication date: 2023-03-09
Also published as: CN113939906A

Abstract

Disclosed are a semiconductor structure, a manufacturing method therefor and a 3D NAND Flash. The manufacturing method for the semiconductor structure comprises: providing a substrate that comprises a first device region and a second device region; forming a plurality of first grooves in the first device region, and forming a second groove in the second device region, the first grooves and the second groove being formed simultaneously; forming first isolation trenches in the first device region; and forming a second isolation trench in the second device region and at a position corresponding to the second groove.

Description

Semiconductor structure, manufacturing method and three-dimensional memory

technical field

The present application relates to the field of semiconductor technology, in particular to a semiconductor structure, a manufacturing method and a three-dimensional memory.

Background technique

Three-dimensional memory (3D NAND Flash) is widely used in computers, solid-state hard drives and electronic devices due to its advantages of high storage density and fast programming speed. The market requires that the storage capacity be continuously increased without increasing the storage area. In order to meet this requirement, the storage density of the three-dimensional memory needs to be increased and the size reduced.

The peripheral circuit of the three-dimensional memory includes devices with various operating voltages, such as high-voltage devices (HV device) and low-voltage devices (LV device), etc., and there are PMOS devices, NMOS devices and shallow trench isolation (STI) devices in high-voltage devices and low-voltage devices. , shallow trench isolation), shallow trench isolation is used to isolate adjacent devices. However, since the working voltage of the high-voltage device is higher than that of the low-voltage device, in order to achieve a good isolation effect, it is necessary to adopt an unnecessary process when forming shallow trench isolation in different regions, resulting in cumbersome process and increased cost. .

Therefore, there are defects in the prior art and need to be improved and developed.

technical problem

The purpose of this application is to provide a semiconductor structure, a manufacturing method and a three-dimensional memory, which can reduce the process flow and save costs while achieving a good isolation effect.

technical solution

In order to solve the above problems, the present application provides a method for manufacturing a semiconductor structure, including: providing a substrate, the substrate including a first device region and a second device region; forming a plurality of first grooves on the first device region, A second groove is formed on the second device region, and the first groove and the second groove are formed at the same time; a first isolation trench is formed on the first device region, and the first isolation trench separates adjacent first grooves ; forming a second isolation trench at a position corresponding to the second groove in the second device region.

Wherein, the first isolation trench and the second isolation trench are formed simultaneously.

Wherein, before forming the first groove, it also includes:

Ion doping is performed on the first device region and the second device region.

Wherein, after the second isolation trench is formed in the second device region corresponding to the position of the second groove, it further includes:

A first dielectric layer and a second dielectric layer are respectively formed on the first device region and the second device region, the first dielectric layer is at least partly located on the inner wall of the first groove, and the first dielectric layer The thickness of the layer is smaller than the thickness of the second dielectric layer; the first gate and the second gate are respectively formed on the first dielectric layer and the second dielectric layer, and the first gate A source and a drain are respectively formed on both sides of the second gate.

Wherein, while forming the second grooves, a plurality of third grooves are formed in the second device region, and the second grooves are located between adjacent third grooves.

Wherein, a first dielectric layer and a second dielectric layer are respectively formed on the first device region and the second device region, the first dielectric layer is at least partially located on the inner wall of the first groove, and the second dielectric layer is at least partially located on the third groove The inner wall of the first dielectric layer is less than the thickness of the second dielectric layer; the first grid and the second grid are respectively formed on the first dielectric layer and the second dielectric layer, and the first grid and the second grid A source and a drain are formed on both sides of the pole, respectively.

Dielectric materials are respectively filled in the first isolation trench and the second isolation trench to form the first isolation structure and the second isolation structure.

In order to solve the above problems, an embodiment of the present application also provides a semiconductor structure, including: a substrate, the substrate includes a first device region and a second device region; the first device region is provided with a plurality of first transistors and located adjacent The first isolation structure between the first transistors, the gate of the first transistor is at least partly located in the first groove; the second device area is provided with a plurality of second transistors and the first transistor located between adjacent second transistors Two isolation structures, the depth of the second isolation structure is greater than the depth of the first isolation structure.

Wherein, the depth of the second isolation structure is the sum of the depth of the first isolation structure and the depth of the first groove.

Wherein, the first transistor includes a first dielectric layer at least partially located in the first groove, the gate of the first transistor is located on the first dielectric layer, and the second transistor includes a second dielectric layer at least partially located in the third groove , the second gate of the second transistor is at least partially located in the third groove, and the thickness of the first dielectric layer is smaller than the thickness of the second dielectric layer.

In order to solve the above problems, an embodiment of the present application further provides a three-dimensional memory, including an array storage structure and a peripheral circuit, wherein any semiconductor structure described above is located in the peripheral circuit.

Beneficial effect

The present application provides a semiconductor structure, a manufacturing method, and a three-dimensional memory. The manufacturing method of the semiconductor structure includes: providing a substrate, the substrate including a first device region and a second device region; forming a plurality of first device regions on the first device region A groove, a second groove is formed on the second device region, and the first groove and the second groove are formed simultaneously; a first isolation trench is formed in the first device region, and the first isolation trench separates adjacent The first groove; forming a second isolation trench at a position corresponding to the second groove in the second device region, by forming the second groove and the first groove simultaneously, and forming a second isolation based on the position of the second groove grooves, so that the depth of the second isolation trench corresponds to the sum of the depth of the first groove and the depth of the first isolation trench, without additional process, in the first device region and the second device region respectively The first isolation trench and the second isolation trench with different depths are formed to meet the isolation requirements of different semiconductor devices.

Description of drawings

FIG. 1 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present application;

Figure 2 is a schematic structural view of the substrate provided in one embodiment of the present application;

FIG. 3 is a schematic structural diagram of forming a first active region and a second active region in one embodiment of the present application;

Fig. 4 is a schematic structural diagram of forming a first groove and a second groove in one embodiment of the present application;

5 is a schematic structural diagram of forming a first isolation trench and a second isolation trench in an embodiment of the present application;

Figure 6 is a schematic structural view of forming a first isolation structure and a second isolation structure in one embodiment of the present application;

FIG. 7 is a schematic structural diagram of forming a first dielectric layer in one embodiment of the present application;

FIG. 8 is a schematic structural diagram of forming a first gate in an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a semiconductor structure formed in an embodiment of the present application;

FIG. 10 is a flowchart of a method for fabricating a semiconductor structure according to another embodiment of the present application;

Fig. 11 is a schematic structural diagram of forming the first groove, the second groove and the third groove in another embodiment of the present application;

FIG. 12 is a schematic structural diagram of forming a first isolation trench and a second isolation trench in another embodiment of the present application;

FIG. 13 is a schematic structural diagram of forming a first isolation structure and a second isolation structure in another embodiment of the present application;

FIG. 14 is a schematic structural diagram of forming a first dielectric layer and a second dielectric layer in another embodiment of the present application;

FIG. 15 is a schematic structural diagram of forming a first gate and a second gate in another embodiment of the present application;

FIG. 16 is a schematic structural diagram of forming a semiconductor structure in another embodiment of the present application;

17 is a schematic structural diagram of forming a semiconductor structure including multiple transistors in another embodiment of the present application;

Fig. 18 is a schematic block diagram of a storage system in some embodiments of the present application.

Embodiment of this application

The application will be described in further detail below in conjunction with the accompanying drawings and embodiments. In particular, the following examples are only used to illustrate the present application, but not to limit the scope of the present application. Likewise, the following embodiments are only some of the embodiments of the present application but not all of them, and all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

In addition, the directional terms mentioned in this application, such as [top], [bottom], [front], [back], [left], [right], [inside], [outside], [side], etc., only is the direction with reference to the attached drawings. Therefore, the directional terms used are used to illustrate and understand the application, but not to limit the application. In the various figures, structurally similar elements are denoted by the same reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown in the drawings.

In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings.

As shown in FIG. 1, the present application provides a method for manufacturing a semiconductor structure. The specific process may include the following with reference to the structural diagrams in FIG. 2 to FIG. 9:

Step S101: providing a substrate 210, and the substrate 210 includes a first device region and a second device region.

Specifically, the fabrication method of the semiconductor structure according to the embodiment of the present application will be described in detail with reference to FIG. 2 to FIG. 9 .

FIG. 2 shows the structure formed in step S101 , including: a substrate 210 located in the first device region and the second device region of the A1 region and the A2 region shown in FIG. 2 . The substrate 210 serves as the basis for forming semiconductor devices. The substrate 210 is a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), or other materials.

Wherein, after step S101, it also includes:

Step S105: performing ion doping on the first device region and the second device region.

FIG. 3 shows the structure formed in step S104 , including: a substrate 210 , a first active region 221 and a second active region 222 .

Specifically, ion doping is performed on the first device region and the second device region, and the first active region 221 and the second active region 222 can be formed in the first device region and the second device region respectively, and the first groove 231 is located in the first active area 221 (ie, the first device area), and the second groove 232 is located in the second active area 222 (ie, the second device area). The active area (Active Area, AA) refers to the area covered by the formation of the source electrode, the drain electrode and the conductive trench. After step S101 is performed, the substrate 210 is implanted with one or more ions to form a well region, and then the substrate 210 is divided into regions one after another through an etching process, and these regions may be the first active regions. Region 221 or second active region 222 , that is, the first active region 221 and the second active region 222 are formed on the substrate 210 .

Different from logic chips, since three-dimensional memory needs to meet the operations of reading, writing and erasing, and different operations require different operating voltages, the peripheral circuits of three-dimensional memory require multiple devices that provide different maximum operating voltages. Correspondingly, A high voltage (HV) device region and a low voltage (LV) device region are formed in the peripheral circuit of the three-dimensional memory. Wherein, the first device region and the second device region may be a low voltage device region and a high voltage device region respectively.

Step S102: forming a plurality of first grooves 231 on the first device region, forming second grooves 232 on the second device region, and forming the first grooves 231 and the second grooves 232 at the same time.

4 shows the structure formed in step S102, including: a substrate 210, a first active region 221 and a first groove 231 located in the first active region 221, a second active region 222 and a groove located in the second active region The second groove 232 in 222 can form the first groove 231 and the second groove 232 in the vertical direction of the substrate 210 in the first active region 221 and the second active region 222 respectively by an etching process. .

Step S103 : forming a first isolation trench 241 in the first device region, and the first isolation trench 241 separates adjacent first grooves 231 .

Step S104 : forming a second isolation trench 242 at a position corresponding to the second groove 232 in the second device region.

5 shows the structure formed in steps S103 and S104, including: a substrate 210, a first active region 221, a first groove 231 and a first isolation trench 241 located in the first active region 221, a second active region 222 and the second isolation trench 242 located in the second active region 222, wherein the depth of the first groove 231 is L1, the depth of the first isolation trench 241 is L2, and the depth of the second isolation trench 242 is L3, the depth L3 of the second isolation trench 242 is greater than the depth L2 of the first isolation trench 241 .

Specifically, in general, the first groove 231 and the second groove 232 can be simultaneously formed on the substrate 210 through an etching process, so the depths of the first groove 231 and the second groove 232 are consistent, that is, the first groove 231 and the second groove 232 have the same depth. The depths of the groove 231 and the second groove 232 are both L1, after forming the first groove 231 and the second groove 232, in the first active region 221 not corresponding to the first groove 231, by etching The first isolation trench 241 is formed by the process, and the second isolation trench 242 is formed at the position corresponding to the second groove 232 in the second device region. The corresponding here refers to continuing to etch downward at the bottom of the second groove 232 Forming the second isolation trench 242, by forming the second groove 232 and the first groove 231 simultaneously, and forming the second isolation trench 242 based on the position of the second groove 232, the depth of the second isolation trench 242 is L3 is greater than the depth L2 of the first isolation trench 241, without additional process, the first isolation trench 241 and the second isolation trench 242 with different depths are respectively formed in the first device region and the second device region, Meet the isolation requirements of different semiconductor devices.

Wherein, the first isolation trench 241 and the second isolation trench 242 are formed simultaneously.

Specifically, when steps S103 and S104 are performed at the same time, that is, when the first isolation trench 241 and the second isolation trench 242 are formed at the same time, the first active region 221 not corresponding to the first groove 231 is formed by the etching process. The first isolation trench 241 is formed, and at the same time, the second isolation trench 242 is formed at the position corresponding to the second groove 232 in the second device region, that is, the bottom of the second groove 232 is etched downward to form the second isolation trench 242. Two isolation trenches 242, the depth L2 of the first isolation trench 241 is consistent with the depth of further etching in the second groove 232, therefore, the depth L3 of the second isolation trench 242 is the depth L1 of the first groove 231 and the sum of the depth L2 of the first isolation trench 241, by simultaneously forming the first isolation trench and the second isolation trench with different depths, while meeting the isolation requirements of different semiconductor devices, the process flow is reduced and the cost is saved. The further development of technology is possible.

In addition, it should be noted that, in general, the depth L3 of the second isolation trench 242 is the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241, but in the actual process, due to The second isolation trench 242 is formed by etching on the basis of the second groove 232, and the second isolation trench 242 is formed by etching on a basis not corresponding to the first groove 231. The first The etching depths of the isolation trench 241 and the second isolation trench 242 are basically different. Based on the difference in the initial depths of the first isolation trench 241 and the second isolation trench 242, in the process of continuing the etching, As the etching depth gradually increases, the depth of further etching will be affected by the existing etching depth. Therefore, in the actual process, the depth L3 of the second isolation trench 242 is the same as the depth L1 of the first groove 231. There may be a slight deviation from the sum of the depth L2 of the first isolation trench 241, but the depth L3 of the second isolation trench 242 is positively related to the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241 , that is, the depth L3 of the second isolation trench 242 always corresponds to the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241 .

Wherein, after step S104, it also includes:

A dielectric material is filled in the first isolation trench 241 and the second isolation trench 242 respectively to form a first isolation structure 243 and a second isolation structure 244 .

Wherein, the dielectric material includes oxide.

Specifically, as shown in FIG. 6, there are multiple isolation structures in and between the first active region 221 and the second active region 222, for example, located The first isolation structure 243 in the first active region 221 and the second isolation structure 244 located in the second active region 222, the first isolation structure 243 and the second isolation structure 244 can be shallow trench isolation (STI, shallow trench isolation ), which acts as lateral isolation for NMOS devices and PMOS devices. The first isolation structure 243 and the second isolation structure 244 can be formed by filling the dielectric material in the first isolation trench 241 and the second isolation trench 242 respectively by thermal oxidation reaction (Thermal Oxidation), because the second isolation trench 242 The depth L3 always corresponds to the sum of the depth L1 of the first groove 231 and the depth L2 of the first isolation trench 241, and the depth of the second isolation structure 244 is greater than the depth of the first isolation structure 243 to meet the isolation requirements of different semiconductor devices . Generally, the material of shallow trench isolation is oxide, such as silicon dioxide (SiO2). In addition, it should be noted that the dielectric material filled in the first isolation trench 241 and the second isolation trench 242 is not limited as long as it can achieve lateral isolation.

Wherein, after step S104, it also includes:

Step S106 : forming a first dielectric layer 251 on the first device region, the first dielectric layer 251 is at least partially located on the inner wall of the first groove 231 .

7 shows the structure formed in step S106, including: the substrate 210, the first active region 221, the first isolation structure 243 located in the first active region 221, the first groove 231, and the first groove 231 located in the first groove 231. The first dielectric layer 251, the second active region 222, and the second isolation structure 244 located in the second active region 222, wherein the first dielectric layer 251 is at least partially located on the inner wall of the first groove 231, and the first dielectric layer The height of layer 251 is lower than the top surface of substrate 210 . In addition, as shown in FIG. 7 , a second dielectric layer 252 may also be formed on the second device region.

Specifically, the first groove 231 is located in the substrate 210 for forming a gate corresponding to the first groove 231, and the first dielectric layer 251 is located in the first groove 231 as a gate oxide layer for holding the substrate 210 and the insulation between the gate. In general, the material of the substrate 210 is silicon, and the natural oxide of silicon is silicon dioxide. When exposed to an environment containing an oxidizing agent at a relatively high temperature, a layer will gradually form on all silicon surfaces that are in contact with the oxidizing agent thin oxide layer. A high-quality dielectric layer, such as the first dielectric layer 251 serving as a gate oxide layer, can be formed through a thermal oxidation reaction. Also during the process, the thermally grown oxide can be used as a mask for implantation, diffusion and etching.

In addition, it should be noted that the method for forming the second dielectric layer 252 is basically the same as the method for forming the first dielectric layer 251, and corresponding adjustments can be made according to the position, thickness, and width of the second dielectric layer 252. Since the formation of the first dielectric layer 252 The method of the dielectric layer 251 has been described in detail, and will not be repeated here.

Specifically, the thermal oxidation reaction means that the silicon wafer is placed in an atmosphere of a gaseous oxidant such as molecular oxygen (O2) and/or water vapor (H2O) at high temperature (typically 900-1200° C.). When the gaseous oxidant is molecular oxygen, the thermal oxidation reaction is a dry oxygen method, and when the gaseous oxidant is water vapor, the thermal oxidation reaction is a wet oxygen method. Through the thermal oxidation reaction, an initial oxide layer will be formed at the gas/solid interface. The oxidant needs to diffuse through the initial oxide layer to reach the surface of the wafer to form an oxide layer. Once it reaches the surface of the wafer, the oxidant needs to pass through again The formed oxide layers are cycled sequentially to finally form the first dielectric layer 251 . The first dielectric layer 251 with controllable thickness can be formed by controlling the temperature, rate constant (such as the type of oxidant, the characteristics of the wafer surface) and the reaction time of the thermal oxidation reaction, so that the thickness of the first dielectric layer 251 is smaller than that of the first dielectric layer 251. A depth of the groove 231 , that is, the first dielectric layer 251 is at least partially located on the inner wall of the first groove 231 , and the height of the first dielectric layer 251 is lower than the top surface of the substrate 210 .

Step S107 : forming a first gate 261 on the first dielectric layer 251 , and forming a source and a drain on both sides of the first gate 261 .

FIG. 8 shows the structure formed by "forming the first gate 261 on the first dielectric layer 251" in step S107, including: the substrate 210; the first active region 221 and the first isolation structure located in the first active region 221 243, the first groove 231, the first dielectric layer 251 and the first gate 261 in the first groove 231; the second active region 222 and the second isolation structure 244 in the second active region 222, Wherein, a part of the first gate 261 is located in the first groove 231 , and another part is located above the top surface of the substrate 210 . In addition, as shown in FIG. 8 , a second gate 262 may also be formed on the second dielectric layer 252 in the second device region.

Specifically, after forming the first dielectric layer 251, the conductive material may be filled in the first groove 231 by physical vapor deposition (PVD), so as to form the first gate 261 corresponding to the first groove 231, the first gate A part of the electrode 261 is located in the first groove 231 , and another part is located above the top surface of the substrate 210 , that is, the top of the first gate 261 is higher than the top of the substrate 210 . By adopting a recess gate structure (Recess Gate), a first groove 231 is formed on the substrate 210, and then a first dielectric layer 251 and a first gate 261 are sequentially formed in the first groove 231, so as to form a part located in the substrate. In 210, a part of the first gate 261 located above the substrate 210 increases the effective contact area between the first gate 261 and the first active region 221 through the concave gate structure, and increases the channel of the first gate 261. The length improves the problem of slow reading and writing speed of semiconductor devices, so that the area of semiconductor devices can be made smaller. At the same time, the isolation requirements of different semiconductor devices are met by using the first isolation structure 243 and the second isolation structure 244 with different depths formed in different active regions (that is, the Dual STI process). Through the combination of concave gate structure process and Dual STI process (Integration), the area of peripheral circuits can be effectively reduced and the isolation requirements of different semiconductor devices can be met, which provides the possibility for the further development of semiconductor technology.

In addition, it should be noted that the method for forming the second gate 262 is basically the same as the method for forming the first gate 261, and can be made according to the position where the second dielectric layer 252 is formed and the thickness and width of the second gate 262. Since the method for forming the first gate 261 has been described in detail, details will not be repeated here.

Specifically, since the first gate 261 is used to control whether the semiconductor device is turned on, the first gate 261 is mostly made of conductive materials, such as polysilicon (Poly), tungsten (W) or aluminum (Al). Yes, without limitation.

9 shows the structure formed in the step S107 "and forming the source and the drain on both sides of the first gate 261", including: the substrate 210; the first active region 221 and the first active region 221; The first isolation structure 243, the first groove 231, the first dielectric layer 251 located in the first groove 231 and the first transistor corresponding to the first gate 261; the second active region 222 and the second active region 222 The second isolation structure 244 in the region 222 , wherein a part of the first gate 261 is located in the substrate 210 and another part is located above the substrate 210 . In addition, as shown in FIG. 9 , a source and a drain may be respectively formed on both sides of the second gate 262 in the second device region.

As can be seen from the above, during the process, the thermally grown oxide can be used as a mask for ion implantation, diffusion and etching. For example, after forming the first dielectric layer 251 as a gate oxide layer, the first gate 261 is formed on the first dielectric layer 251. Since the first gate 261 is very thick and the top of the first gate 261 is higher than the substrate 210, the first gate 261 can be used as a mask layer for forming the source and drain to prevent ion implantation into the corresponding region below the first gate 261 (the thickness of the first gate 261 is thick enough so that the ions The implanted atoms cannot reach the first dielectric layer 251), only the source and the drain are formed on both sides of the first gate 261 (while the ion-implanted atoms can easily pass through the corresponding gate oxide layer above the source and the drain , to form the source and the drain), that is, according to the first gate 261, a self-alignment (Self Align) is formed between the source, the drain and the first gate 261.

In addition, it should be noted that the method for forming the source and drain of the second gate 262 is basically the same as the method for forming the source and drain of the first gate 261, and the position and thickness of the second gate 262 can be And the width and the position, width and depth of the source and drain of the second gate 262 are adjusted accordingly. Since the method for forming the source and drain of the first gate 261 has been described in detail, it will not be described here. Let me repeat.

Specifically, transistors can be divided into PMOS transistors and NMOS transistors, wherein PMOS transistors are also called P-Metal-Oxide-Semiconductor (P-Metal-Oxide-Semiconductor), and NMOS transistors are also called N-Type Metal-Oxide-Semiconductor. (N-Metal-Oxide-Semiconductor). The first transistor includes a first gate 261 and a source and a drain located on both sides of the gate. By applying a driving voltage to the first gate 261, whether the source is connected to the drain is controlled, thereby realizing the control of the semiconductor device. Whether the circuit is conducting.

The above steps are the first embodiment of the present application, which can form the first isolation trench and the second isolation trench with different depths at the same time, reduce the process flow and save costs while meeting the isolation requirements of different semiconductor devices, as shown in Figure 10 It is a schematic flow chart of a method for manufacturing a semiconductor structure according to another embodiment of the present application. The specific process is compared with the structural diagrams of FIGS. 2 to 3 and FIGS. 11 to 16, and may include the following:

Wherein, while forming the second groove 332 , a plurality of third grooves 333 are formed in the second device region, and the second grooves 332 are located between adjacent third grooves 333 .

Specifically, different from the structure formed in step S102 shown in FIG. 4, it includes: a substrate 210 and a first groove 231 and a second groove 232 formed on the substrate 210, as shown in FIG. The schematic diagram of the structure of forming the first groove 331, the second groove 332 and the third groove 333 in the embodiment includes: the substrate 310, the first active region 321 and the first groove located in the first active region 321 The groove 331 , the second active region 322 , and the second groove 332 and the third groove 333 located in the second active region 322 .

When the first groove 331 , the second groove 332 and the third groove 333 are formed on the substrate 310 , subsequent steps S103 and S104 need to be adjusted according to the third groove 333 . Subsequently, the above-mentioned step S103 and step S104 are adjusted according to the third groove 333. FIG. 12 shows the structure formed in the adjusted step S103 and step S104, including: the substrate 310; The first groove 331 and the first isolation trench 341 of an active region 321; the second active region 322 and the second isolation trench 342 and the third groove 333 in the second active region 322, wherein, The depth of the first groove 331 is L4, the depth of the first isolation trench 341 is L5, the depth of the second isolation trench 342 is L6, and the depth L6 of the second isolation trench 342 is the depth L4 of the first groove 331 and the depth L5 of the first isolation trench 341 .

Wherein, after step S104, it also includes:

A dielectric material is filled in the first isolation trench 341 and the second isolation trench 342 respectively to form a first isolation structure 343 and a second isolation structure 344 .

Specifically, as shown in FIG. 13, multiple isolation structures may also exist in the first active region 321 and the second active region 322 and between the first active region 321 and the second active region 322, for example, The first isolation structure 343 and the second isolation structure 344, the first isolation structure 343 and the second isolation structure 344 may be shallow trench isolation (STI, shallow trench isolation), which play a role of lateral isolation for NMOS devices and PMOS devices. The first isolation structure 343 and the second isolation structure 344 can be respectively formed in the first isolation trench 341 and the second isolation trench 342 by thermal oxidation reaction (Thermal Oxidation), since the depth L6 of the second isolation trench 342 always corresponds to Based on the sum of the depth L4 of the first groove 331 and the depth L5 of the first isolation trench 341, the depth of the second isolation structure 344 corresponds to the depth L4 of the first groove 331 and the depth of the first isolation structure 343, so as to satisfy Isolation requirements of different semiconductor devices. Generally, the material of shallow trench isolation is oxide, such as silicon dioxide.

When the first groove 331, the second groove 332, and the third groove 333 are formed on the substrate 310, subsequent steps S106 to S107 need to be adjusted according to the third groove 333, for example, steps S108 to Step S109, as shown in Fig. 14 to Fig. 16 respectively correspond to the structural schematic diagrams formed in steps S108 to S109.

Wherein, after step S104, it also includes:

Step S108: Forming a first dielectric layer 351 and a second dielectric layer on the first device region and the second device region respectively, the first dielectric layer 351 is at least partially located on the inner wall of the first groove, and the second dielectric layer is at least partially located on the first groove In the inner wall of the three grooves, the thickness of the first dielectric layer is smaller than the thickness of the second dielectric layer.

FIG. 14 shows the structure formed in step S108, including: a substrate 310; a first active region 321, a first isolation structure 343 located in the first active region 321, a first groove 331, and a first groove 331 located in the first groove 331. The first dielectric layer 351; the second active region 322 and the second isolation structure 344 located in the second active region 322, the third groove 333 and the second dielectric layer 352 located in the third groove 333, wherein, The first dielectric layer 351 is at least partially located on the inner wall of the first groove 331, the second dielectric layer 352 is at least partially located on the inner wall of the third groove 333, and the height of the first dielectric layer 351 and the second dielectric layer 352 is lower than the substrate 310 top surface.

Step S109: Forming a first gate 361 and a second gate on the first dielectric layer 351 and the second dielectric layer 352 respectively, and forming a source and a gate respectively on both sides of the first gate 361 and the second gate 362 drain.

FIG. 15 shows the structure formed by "forming the first gate 361 and the second gate 362 respectively on the first dielectric layer 351 and the second dielectric layer 352" in step S109, including: a substrate 310; a first active region 321 And the first isolation structure 343 in the first active region 321, the first groove 331, the first dielectric layer 351 in the first groove 331, and the first gate 361; the second active region 322 and the The second isolation structure 344 in the second active region 322, the third groove 333, the second dielectric layer 352 and the second gate 362 located in the third groove 333, wherein the first gate 361 and the second gate Parts of the poles 362 are respectively located in the substrates 310 , and the other parts are respectively located above the substrates 310 .

Specifically, the gate is used to control whether the semiconductor device is turned on, and the first gate 361 and the second gate 362 are mostly made of conductive materials, such as polysilicon (Poly), tungsten (W) or aluminum (Al), as long as they are conductive Materials can be used, and there is no specific limitation.

Specifically, after forming the first dielectric layer 351 and the second substance layer 352, the first groove 331 and the third groove 333 can be filled with conductive material by physical vapor deposition (PVD) respectively, so as to form The first grid 361 and the second grid 362 of the first groove 331 and the third groove 333, a part of the first grid 361 and the second grid 362 are respectively located in the first groove 331, and the other part is respectively located in the substrate 310 , that is, the top of the first gate 361 is higher than the top of the substrate 310 . By adopting the concave grid structure (Recess Gate), the first groove 331 and the third groove 333 are formed on the substrate 310, and then the first dielectric layer 351 and the first grid 361 are formed in the first groove 331 and in sequence At the same time, the second dielectric layer 352 and the second gate 362 are sequentially formed in the third groove 333 and in the third groove 333 to form a part respectively located in the first groove 331 and the third groove 333, and another part located in the substrate The first gate 361 and the second gate 362 above the top surface of 310 increase the effective contact area between the gate and the active region through the concave gate structure, and increase the contact area between the first gate 361 and the second gate 362. The length of the channel improves the problem of slow reading and writing speed of the semiconductor device, so that the area of the semiconductor device can be further made smaller. At the same time, by simultaneously forming the first isolation structure 343 and the second isolation structure 344 with different depths (that is, the Dual STI process), the process flow is reduced while meeting the isolation requirements of different semiconductor devices, and the cost is saved. Through the combination of concave gate structure process and Dual STI process, the area of peripheral circuits can be effectively reduced and the isolation requirements of different semiconductor devices can be met, which provides the possibility for the further development of semiconductor technology.

16 shows the structure formed in the step S109 "and forming the source and the drain on both sides of the first gate 361 and the second gate 362", including: the substrate 310, the first active region 321 and the A first isolation structure 343 of an active region 321, a first groove 331, a first dielectric layer 351 located in the first groove 331, a first transistor corresponding to the first gate 361, and a second active region 322 And the second isolation structure 344 located in the second active region 322, the third groove 333, the second dielectric layer 352 located in the third groove 333, and the second transistor corresponding to the second gate 362, wherein, Parts of the first gate 361 and the second gate 362 are respectively located in the first groove 331 and the third groove 333 , and the other part is located above the top surface of the substrate 310 .

Specifically, the transistor includes a gate and a source and a drain located on both sides of the gate. By applying a driving voltage to the gate, the conduction from the source to the drain is controlled, so as to control whether the circuit in the semiconductor device is conducted.

As shown in FIG. 17, it is a schematic structural diagram of a semiconductor device in which a plurality of first transistors and a plurality of second transistors are respectively formed in the first device region and the second device region. As can be seen from FIG. 17, there are multiple transistors formed in the first device region a first transistor, a first isolation structure 343 is formed between the plurality of first transistors, and the first isolation structure 343 is used to separate the plurality of first transistors; a plurality of second transistors are formed in the second device region, A second isolation structure 344 is respectively formed between the second transistors, and the second isolation structure 344 is used to isolate a plurality of first transistors. Generally, the first device region and the second device region are low-voltage device regions and high-voltage device regions respectively. By forming shallow trench isolation structures with different depths in different device regions, the depth of the second isolation structure 344 is greater than that of the first isolation The depth of the structure 343 is to meet the isolation requirements of different semiconductor devices.

In addition, it should be noted that the specific process flow from step S106 to step S107 has been described in detail above. The process is basically the same, except that corresponding adjustments are made according to the third groove 333 , which has been described in detail above, and will not be described in detail here.

With the development of semiconductor devices, it is necessary to provide more devices with different maximum operating voltages. Correspondingly, a third device region is formed in the peripheral circuit of the three-dimensional memory, wherein the first device region is far away from the second device region. A third device region is also formed on the side. Wherein, the third device region (not shown in the figure), the first device region and the second device region may be an ultra-low voltage device region, a low voltage device region and a high voltage device region respectively.

In addition, in addition to the ultra-low voltage device area, low voltage device area, and high voltage device area, one or more device areas different from the ultra-low voltage device area, low voltage device area, and high voltage device area may also be formed in the peripheral circuit, without limitation. . When there is a third device region or more device regions in the semiconductor structure, the third device region or more device regions can be passed similar to

The process flow from step S101 to step S107 forms multiple recessed gate structures and shallow trench isolation structures with different depths in different device regions to meet the isolation requirements of different semiconductor devices. Since the principles are similar and have been described in detail above, No more details here.

Based on the manufacturing method of the semiconductor structure described in the above embodiments, the embodiment of the present application also provides a semiconductor structure, including:

a substrate 210, the substrate includes a first device region and a second device region;

The first device region is provided with a plurality of first transistors and a first isolation structure 243 between adjacent first transistors, and the first gate 261 of the first transistor is at least partly located in the first groove 231;

The second device region is provided with a plurality of second transistors and a second isolation structure between adjacent second transistors, and the depth of the second isolation structure 244 is greater than that of the first isolation structure 243 .

Wherein, the depth of the second isolation structure 244 is the sum of the depth of the first isolation structure 243 and the depth of the first groove 231 .

As shown in FIG. 9 , it is a schematic structural diagram of a semiconductor structure formed in an embodiment of the present application, including: a substrate 210, a first active region 221, a first isolation structure 243 located in the first active region 221, a first The groove 231, the first dielectric layer 251 in the first groove 231 and the first transistor corresponding to the first gate 261, the first active region 222 and the second isolation structure in the first active region 222 244, wherein a part of the first gate 261 is located in the first groove 331, and the other part is located above the top surface of the substrate 210, and the depth of the second isolation structure 244 corresponds to the depth of the first groove 231 and the first isolation The sum of the depths of structures 243 .

Wherein, the semiconductor structure further includes: the first transistor includes a first dielectric layer 251 at least partially located in the first groove 231 , and the first gate 261 of the first transistor is located on the first dielectric layer 251 .

Specifically, as shown in FIG. 9 , which is a schematic structural view of the semiconductor structure formed by performing steps S101 to S107, a first groove 231 is formed on the substrate 210 by using a concave gate structure, and then in the first groove 231 The first dielectric layer 251 and the first gate 261 are sequentially formed to form a part of the first gate 261 located in the first groove 231 and a part of the first gate 261 located above the top surface of the substrate 210, and the gate structure is enlarged by the concave gate structure. The effective contact area with the active region increases the channel length of the first gate 261 and improves the problem of slow reading and writing speed of the semiconductor device, so that the area of the semiconductor device can be made smaller. At the same time, by simultaneously forming the first isolation trench and the second isolation trench with different depths, while meeting the isolation requirements of different semiconductor devices, the process flow is reduced and the cost is saved. Through the combination of concave gate structure process and Dual STI process, the area of peripheral circuits can be effectively reduced and the isolation requirements of different semiconductor devices can be met, which provides the possibility for the further development of semiconductor technology.

Wherein, the semiconductor structure further includes: the first transistor includes a first dielectric layer 351 at least partly located in the first groove 331, the first gate 361 of the first transistor is located on the first dielectric layer 351, and the second transistor includes at least The second dielectric layer 352 is partially located in the third groove 333 , the second gate 362 of the second transistor is at least partially located in the third groove 333 , and the thickness of the first dielectric layer 351 is smaller than that of the second dielectric layer 352 .

Specifically, different from the solution shown in FIG. 9, as shown in FIG. 16, it is a schematic structural diagram of a semiconductor structure formed in another embodiment of the present application, including: a substrate 310, a first active region 321, and a The first isolation structure 343 of the active region 321, the first groove 331, the first dielectric layer 351 located in the first groove 331 and the first transistor corresponding to the first gate 361, the second active region 322 and The second isolation structure 344 located in the second active region 322, the third groove 333, the second dielectric layer 352 located in the third groove 333, and the second transistor corresponding to the second gate 362, wherein the first Part of the first gate 361 and the second gate 362 are located in the substrate 310, and the other part is located above the substrate 310, and the depth of the second isolation structure 344 corresponds to the depth of the first groove 331 and the depth of the first isolation structure 343 Sum.

Specifically, as shown in FIG. 11 , when the first groove 331 , the second groove 332 and the third groove 333 are formed on the substrate 310 , the subsequent steps S103 to S106 need to be based on the third groove 333 Corresponding adjustments are made to finally form a schematic structural diagram of the semiconductor structure as shown in FIG. 16 , which has been described in detail above and will not be repeated here. By adopting the concave gate structure (Recess Gate), the first groove 331, the second groove 332 and the third groove 333 are formed on the substrate 310, and then the first dielectric layer 351 and the first dielectric layer 351 are sequentially formed in the first groove 331. The first grid 361, the second dielectric layer 352 and the second grid 362 are sequentially formed in the third groove 333 to form a part located in the first groove 331 and the third groove 333, and a part located in the substrate 310 The first gate 361 and the second gate 362 above the top surface of the top surface, the effective contact area between the gate and the active region is increased by the concave gate structure, and the contact area between the first gate 361 and the second gate 362 is increased. The length of the channel improves the problem of slow reading and writing speed of the semiconductor device, so that the area of the semiconductor device can be further made smaller. By forming the first isolation structure 343 and the second isolation structure 344 with different depths at the same time, while meeting the isolation requirements of different semiconductor devices, the process flow is reduced and the cost is saved. Through the combination of concave gate structure process and Dual STI process, the area of peripheral circuits can be effectively reduced and the isolation requirements of different semiconductor devices can be met, which provides the possibility for the further development of semiconductor technology.

Wherein, the first device region and the first device region may be respectively a low-voltage device region and a high-voltage device region, which have been described in detail above and will not be repeated here.

With the development of semiconductor devices, it is necessary to provide more devices with different maximum operating voltages. Correspondingly, a third device region is formed in the peripheral circuit of the three-dimensional memory, wherein the first device region is far away from the second device region. A third device region is also formed on the side. Wherein, the third device region, the first device region and the second device region may be an ultra-low voltage device region, a low voltage device region and a high voltage device region respectively.

In addition, in addition to the high-voltage device area, low-voltage device area, and ultra-low-voltage device area, one or more device areas that are different from the high-voltage device area, low-voltage device area, and ultra-low-voltage device area may also be formed in the peripheral circuit, without limitation. . When there is a third device region or more device regions in the semiconductor structure, a plurality of recessed gate structures can be formed in the third device region or more device regions through a process similar to step S101 to step S107 and in different devices Shallow trench isolation structures with different depths are formed in the regions to meet the isolation requirements of different semiconductor devices. Since the principles are similar and have been described in detail above, details will not be repeated here.

Based on the manufacturing method of the semiconductor structure described in the above-mentioned embodiments, the embodiment of the present application also provides a three-dimensional memory (not shown in the figure), the three-dimensional memory includes an array storage structure and peripheral circuits, wherein any one of the above-mentioned semiconductor structures is located in in the peripheral circuit.

Specifically, a three-dimensional memory (3D NAND Flash) includes an array storage structure (Array) and a peripheral circuit (Periphery). Above or below the array storage structure may also be located around the array storage structure, and peripheral circuits are used to control the corresponding array storage structure. In addition, the semiconductor structure can also be applied to other microelectronic devices, such as non-volatile flash memory (Nor Flash), etc., which is not specifically limited.

Based on the semiconductor structure described in the foregoing embodiments, an embodiment of the present application further provides a storage system, the controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data, and the three-dimensional memory includes any one of the semiconductor structures described above.

Specifically, as shown in FIG. 18 , the storage system 400 includes a controller 410 and one or more three-dimensional memories 420 , wherein the three-dimensional memories 420 include one or more array storage structures 421 and peripheral circuits 422 . The storage system 400 can communicate with the host 500 through the controller 410 , wherein the controller 410 can be connected to the one or more three-dimensional memories 420 via channels in the one or more three-dimensional memories 420 . Each three-dimensional memory 420 may be managed by the controller 410 via channels in the three-dimensional memory 420 .

Different from the prior art, the semiconductor structure, manufacturing method and three-dimensional memory in this embodiment, the manufacturing method of the semiconductor structure includes: providing a substrate, the substrate includes a first device region and a second device region; on the first device region Forming a plurality of first grooves, forming second grooves on the second device region, and forming the first grooves and the second grooves at the same time; forming first isolation trenches in the first device region, the first isolation trenches Opening adjacent first grooves; forming a second isolation trench at a position corresponding to the second groove in the second device region, by forming the second groove and the first groove simultaneously, and based on the position of the second groove forming a second isolation trench, so that the depth of the second isolation trench corresponds to the sum of the depth of the first groove and the depth of the first isolation trench; A first isolation trench and a second isolation trench with different depths are respectively formed in the two device regions to meet the isolation requirements of different semiconductor devices.

The above descriptions are only preferred embodiments of the application, and are not intended to limit the application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the application should be included in the protection of the application. within range.

Claims

A manufacturing method of a semiconductor structure, the manufacturing method of the semiconductor structure comprising:

providing a substrate comprising a first device region and a second device region;

forming a plurality of first grooves on the first device region, forming second grooves on the second device region, and forming the first grooves and the second grooves simultaneously;

forming a first isolation trench in the first device region, the first isolation trench separates adjacent first grooves;

A second isolation trench is formed in the second device region corresponding to the second groove.
The method for fabricating a semiconductor structure according to claim 1, wherein the first isolation trench and the second isolation trench are formed simultaneously.
The method for manufacturing a semiconductor structure according to claim 2, wherein, before forming the first groove, further comprising:

Ion doping is performed on the first device region and the second device region.
The method for fabricating a semiconductor structure according to claim 3, wherein after forming a second isolation trench in the second device region corresponding to the position of the second groove, further comprising:

forming a first dielectric layer on the first device region, the first dielectric layer is at least partially located on the inner wall of the first groove;

A first gate is formed on the first dielectric layer, and a source and a drain are respectively formed on two sides of the first gate.
The method for manufacturing a semiconductor structure according to claim 3, wherein a plurality of third grooves are formed in the second device region while forming the second grooves, and the second grooves are located in adjacent between the third grooves.
The method for manufacturing a semiconductor structure according to claim 5, wherein a first dielectric layer and a second dielectric layer are respectively formed on the first device region and the second device region, and the first dielectric layer is at least partially Located on the inner wall of the first groove, the second dielectric layer is at least partially located on the inner wall of the third groove, and the thickness of the first dielectric layer is smaller than the thickness of the second dielectric layer;

A first gate and a second gate are respectively formed on the first dielectric layer and the second dielectric layer, and a source and a gate are respectively formed on both sides of the first gate and the second gate. drain.
The method for fabricating a semiconductor structure according to claim 1, wherein after forming a second isolation trench in the second device region corresponding to the position of the second groove, further comprising:

Dielectric materials are respectively filled in the first isolation trench and the second isolation trench to form a first isolation structure and a second isolation structure.
A semiconductor structure comprising:

a substrate comprising a first device region and a second device region;

The first device region is provided with a plurality of first transistors and a first isolation structure between adjacent first transistors, and the first gates of the first transistors are at least partially located in the first groove;

The second device region is provided with a plurality of second transistors and a second isolation structure between adjacent second transistors, and the depth of the second isolation structure is greater than the depth of the first isolation structure.
The semiconductor structure according to claim 8, wherein the depth of the second isolation structure is the sum of the depth of the first isolation structure and the depth of the first groove.
The semiconductor structure as claimed in claim 8, wherein the first transistor comprises a first dielectric layer at least partially located in the first groove, and the gate of the first transistor is located on the first dielectric layer , the second transistor includes a second dielectric layer at least partially located in the third groove, the second gate of the second transistor is at least partially located in the third groove, the thickness of the first dielectric layer is less than the The thickness of the second dielectric layer.
A three-dimensional memory, wherein the three-dimensional memory comprises a memory cell array and a peripheral circuit, wherein the peripheral circuit comprises the semiconductor structure as claimed in claim 8 .