WO2023024146A1 - 薄膜晶体管阵列基板及其制作方法 - Google Patents

薄膜晶体管阵列基板及其制作方法 Download PDF

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Publication number
WO2023024146A1
WO2023024146A1 PCT/CN2021/116346 CN2021116346W WO2023024146A1 WO 2023024146 A1 WO2023024146 A1 WO 2023024146A1 CN 2021116346 W CN2021116346 W CN 2021116346W WO 2023024146 A1 WO2023024146 A1 WO 2023024146A1
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Prior art keywords
layer
substrate
platform
insulating layer
film transistor
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PCT/CN2021/116346
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English (en)
French (fr)
Inventor
卓毅
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/599,582 priority Critical patent/US20240030349A1/en
Priority to JP2021555339A priority patent/JP7480167B2/ja
Priority to KR1020217035233A priority patent/KR20230031114A/ko
Publication of WO2023024146A1 publication Critical patent/WO2023024146A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present application relates to the field of display technology, in particular to a thin film transistor array substrate and a manufacturing method thereof.
  • flat panel displays have become the current mainstream displays.
  • Commonly used flat panel displays include liquid crystal displays (Liquid Crystal Display, LCD) and active matrix driven organic electroluminescent displays (Active Matrix OLED, AMOLED).
  • thin-film transistors (Thin-Film Transistor, TFT) array substrate is the main driving element, and is a necessary structure of high-performance flat panel display device.
  • the thin film transistor array substrate includes a plurality of thin film transistors arranged in an array, including different types of bottom gate thin film transistors or top gate thin film transistors.
  • the top-gate thin film transistor has lower parasitic capacitance and better ductility because there is no overlap between the source-drain electrodes and the gate, and can reduce the delay during signal transmission.
  • a self-aligned (self-aligned) etching process is often used, that is, the gate pattern is defined and the etching process is performed simultaneously through a photolithography process.
  • the conductorization of the gate insulating layer and the non-channel region can effectively avoid the formation of high-resistance regions on both sides of the channel caused by alignment deviation.
  • the diffusion of the conductorization effect on both sides of the channel will cause low resistance regions at both ends of the channel, that is, the effective channel length will be shortened, which is not conducive to the reduction of the size of the TFT device.
  • This application provides a thin film transistor and its manufacturing method to solve the problem of low resistance regions at both ends of the channel due to the diffusion of the conductive effect on both sides of the channel of traditional film transistors, resulting in shortening of the effective channel length, which is not conducive to thin film transistors.
  • An embodiment of the present application provides a thin film transistor array substrate, including a substrate; a platform layer disposed on the substrate, an oxide active layer disposed on the substrate and located above the platform layer,
  • the oxide active layer includes a channel portion and conductor portions on opposite sides of the channel portion, wherein the top surface of the channel portion is at a level higher than the top surface of any conductor portion level at which the gate insulating layer is disposed on the oxide active layer a gate, disposed on the gate insulating layer, and an orthographic projection of the gate on the substrate covers an orthographic projection of the platform layer and the channel portion on the substrate; and a source and a drain electrode, and the source electrode and the drain electrode are electrically connected to the conductor portion.
  • the TFT array substrate further includes a buffer layer disposed on the substrate and covering the platform layer, wherein the material of the platform layer is an insulating material or a metal oxide.
  • the buffer layer includes a boss, and the channel portion is disposed on the boss and covers the whole boss.
  • the channel portion includes two slopes, one end of the slope is connected to the corresponding conductor portion, and the slope is inclined in a direction away from the channel portion and toward the corresponding conductor portion .
  • the platform layer includes a first end surface and a second end surface inclined outward, and the orthographic projection of the channel portion on the substrate covers the orthographic projection of the platform layer on the substrate .
  • the gate insulating layer includes two offset parts arranged oppositely, and the offset parts are defined on the end edge of the gate insulating layer corresponding to the gate and the corresponding end of the gate insulating layer.
  • the portion between the edges, wherein the orthographic projections of the two offset portions on the substrate respectively cover the first end surface and the second end surface of the platform layer and the slope edge of the channel portion on the substrate Orthographic projection on the bottom.
  • the thin film transistor array substrate further includes an interlayer insulating layer, the interlayer insulating layer covers the oxide active layer, the gate insulating layer and the gate, and the interlayer insulating layer A plurality of via holes are included, wherein the source electrode and the drain electrode are provided on the interlayer insulating layer, and are electrically connected to the conductor part through the plurality of via holes.
  • the embodiment of the present application also provides a method for manufacturing a thin film transistor array substrate, including depositing a platform layer on the substrate, the material of the platform layer is insulating material or metal oxide; forming a layer of oxide on the substrate source layer, and use a photolithography process to form a channel portion and conductor regions on opposite sides of the channel portion; deposit a gate insulating layer on the oxide active layer; and deposit a gate insulating layer on the gate insulating layer Depositing a gate metal layer; patterning the gate metal layer by a photolithography process to form a gate, and self-aligning etching the gate insulating layer to expose the oxide active layer Conductor region, wherein the orthographic projection of the gate on the substrate covers the orthographic projection of the platform layer and the channel part on the substrate; performing plasma treatment on the entire surface, so that the oxide has conducting the conductor region of the source layer and forming a conductor part, wherein the level of the top surface of the channel part is higher than the level of the top surface of any of the conduct
  • the step of forming an oxide active layer on the substrate also includes: depositing a buffer layer on the substrate to cover the platform layer, and the buffer layer is formed by a photolithography process The boss located directly above the platform layer, wherein the channel part is arranged on the boss and covers the whole boss.
  • the channel portion includes two slopes, one end of the slope is connected to the corresponding conductor portion, and the slope is inclined in a direction away from the channel portion and toward the corresponding conductor portion , wherein the gate insulating layer includes two offset portions oppositely arranged, and each of the offset portions is formed on an end edge of the gate insulating layer corresponding to the gate and a corresponding edge of the gate insulating layer.
  • the part between the end edges, and the orthographic projection of the two offset parts on the substrate respectively cover the opposite end faces of the platform layer and the slope of the channel part on the substrate orthographic projection.
  • the embodiment of the present application also provides a thin film transistor array substrate, including a substrate; a platform layer arranged on the substrate, and the material of the platform layer is an insulating material or a metal oxide; an oxide active layer arranged on the On the substrate and above the platform layer, the oxide active layer includes a channel portion and conductor portions on opposite sides of the channel portion, wherein the channel portion includes two slopes One end of the slope is connected to the corresponding conductor part, and the other end is connected to the channel part, and the level of the top surface of the channel part is higher than that of the top surface of any conductor part.
  • the embodiment of the present application provides a thin film transistor and a manufacturing method thereof.
  • the upper film layer structure forms a gentle slope-shaped offset portion
  • the orthographic projections of the two offset portions on the substrate cover the orthographic projections of the slope of the channel portion on the substrate, and fall on the first end surface and the second end surface of the platform layer respectively.
  • the conductive diffusion path of the oxide active layer is extended, and the length of the low-resistance region formed by the diffusion of the two ends of the channel part into the channel part after self-alignment etching is reduced, thereby effectively controlling Or suppress the shortening of the effective channel length to ensure the effective channel length, which is conducive to the reduction of the size of the thin film transistor device, and effectively solves the problem of low resistance at both ends of the channel due to the diffusion of the conductive effect on both sides of the channel of the traditional thin film transistor. region, leading to a shortened effective channel length, which is not conducive to the technical problem of shortening the size of thin film transistor devices.
  • FIG. 1 is a schematic cross-sectional structure diagram of a thin film transistor array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional structure diagram of a thin film transistor array substrate according to another embodiment of the present application.
  • FIG. 3 is a flowchart of a manufacturing method of a thin film transistor array substrate according to an embodiment of the present application.
  • FIG. 4 to FIG. 11 are schematic diagrams of film layer structures of thin film transistors manufactured in various steps in the method for manufacturing a thin film transistor array substrate according to an embodiment of the present application.
  • An embodiment of the present application provides a thin film transistor, which can be arranged in an array and prepared as a thin film transistor array substrate.
  • the thin film transistor array substrate is provided with several gate scanning lines and several data lines, and the several gate scanning lines and several data lines define a plurality of pixel units, and each pixel unit is provided with the thin film transistors and pixel electrodes.
  • the thin film transistor array substrate can be used as a driving substrate of a liquid crystal display or an organic light emitting diode display.
  • FIG. 1 is a schematic cross-sectional structure diagram of a thin film transistor array substrate 1 according to an embodiment of the present application.
  • the thin film transistor array substrate 1 provided by the embodiment of the present application includes a substrate 10, a platform layer 11, an oxide active layer 13, a gate insulating layer 14, a gate 15, and an interlayer insulating layer arranged in sequence. 16.
  • the material of the substrate 10 may be glass or transparent plastic, preferably glass.
  • the surface of the substrate 10 is provided with a platform layer 11 . Specifically, an insulating material is used to deposit a platform layer thin film, and the platform layer 11 is formed by patterning through a photolithography process.
  • the platform layer 11 includes a top surface and a first end surface 111 and a second end surface 112 . It should be noted that the first end surface 111 and the second end surface 112 are respectively arranged at opposite ends of the platform layer 11, and the first end surface 111 and the second end surface 112 are respectively directed from the top surface of the platform layer 11 to the direction of the substrate 10. Lean out. Preferably, an angle of 40°-80° is formed between the first end face 111 and the substrate 10 , and an angle of 40°-80° is formed between the second end face 112 and the substrate 10 . In one embodiment, the angle between the first end surface 111 and the substrate 10 is the same as the angle between the second end surface 112 and the substrate 10 . It should be noted that the above-mentioned angle range is set according to the process capability range of the etching process, and can promote the formation of the corresponding oblique configuration of the upper film layer.
  • an oxide active layer 13 is disposed on a substrate 10, and the material of the oxide active layer 13 may be indium gallium zinc oxide (IGZO), indium zinc tin oxide (indium zinc tin oxide, IZTO) or indium gallium zinc tin oxide (indium gallium zinc tin oxide, IGZTO) metal oxide semiconductor.
  • the oxide active layer 13 includes a channel portion 131 and conductor portions 132 on opposite sides of the channel portion 131 , wherein the channel portion 131 is located directly above the platform layer 11 .
  • the channel portion 131 since the platform layer 11 is disposed on the surface of the substrate 10 , the height of the channel portion 131 is thus increased, so that the channel portion 131 and the conductor portion 132 are located at different horizontal positions. That is, the height of the horizontal plane where the top surface of the channel portion 131 is higher than the height of the horizontal plane where the top surface of any conductor portion 132 is located.
  • the channel portion 131 includes two slopes 133, one end of each slope 133 is connected to the corresponding conductor portion 132, and the other end extends from the channel portion 131, wherein the slope 133 is away from the channel portion 131 and toward the corresponding The direction of the conductor portion 132 is inclined.
  • the gate insulating layer 14 is disposed on the oxide active layer 13 .
  • the gate electrode 15 is provided on the gate insulating layer 14 .
  • the gate 15 is formed by patterning the metal layer through a photolithography process, and self-aligned etching of the gate insulating layer 14 to expose the conductor region 130 of the oxide active layer 13 (As shown in FIG. 6 later), the whole surface is then treated with plasma to make the conductive region 130 of the oxide active layer 13 conductive to form the conductive portion 132 .
  • two offset portions 141 are formed on the gate insulating layer 14 after the aforementioned photolithography process and self-aligned etching.
  • the two offset portions 141 are disposed on opposite ends of the gate insulating layer 14 , and each offset portion 141 is disposed along the slope 133 of the channel portion 131 and covers the slope 133 . Specifically, each offset portion 141 is defined between an end edge of the gate insulating layer 14 corresponding to the gate 15 and a corresponding end edge of the gate insulating layer 14 .
  • the length of the platform layer 11 is smaller than the length of the channel portion 131 and substantially the same as the length of the gate 15 . That is, the orthographic projection of the gate 15 on the substrate 10 covers the orthographic projection of the platform layer 11 and the channel portion 131 on the substrate 10 . In this embodiment, the length difference between the platform layer 11 and the gate 15 is less than 2 microns.
  • the first end surface 111 and the second end surface 112 of the platform layer 11 respectively extend beyond the length range of the gate 15 in the vertical section. That is to say, the orthographic projection of each offset portion 141 on the substrate 10 covers the orthographic projection of the first end surface 111 or the second end surface 112 of the platform layer 11 on the substrate 10 .
  • an interlayer insulating layer 16 is deposited on the substrate 10 to cover the oxide active layer 13, the gate insulating layer 14, and the gate 15, and the interlayer insulating layer 16 is patterned to form a plurality of overlayers. hole 160.
  • the source and drain electrodes 17 are disposed on the interlayer insulating layer 16 and are electrically connected to the conductor portion 132 of the oxide active layer 13 through corresponding via holes 160 .
  • a passivation layer 18 is further formed on the interlayer insulating layer 16, and its material can be nitride (silicon nitride, etc.), oxide (silicon oxide, silicon dioxide) or a multi-layer structure film.
  • a planarization layer (not shown) is further provided on the passivation layer 18, and the planarization layer can provide further protection to the underlying film layer and play a better planarization effect.
  • the pixel electrode 19 is formed on the passivation layer 18 or on the planarization layer.
  • the pixel electrode 19 is formed through a patterned metal layer, and is electrically connected to the source electrode and the drain electrode 17 through the through hole 180 .
  • the embodiment of the present application provides a top-gate thin film transistor array substrate 1, which can be used as a driving substrate for a subsequent liquid crystal display or organic light emitting diode display.
  • FIG. 2 is a schematic cross-sectional structure diagram of a thin film transistor array substrate 1 according to another embodiment of the present application.
  • the TFT array substrate 1 in FIG. 2 is also provided with a buffer layer 12 (described in detail later), and other identical components will not be described in detail here.
  • the thin film transistor array substrate 1 provided in the embodiment of the present application includes a substrate 10, a platform layer 11, a buffer layer 12, an oxide active layer 13, a gate insulating layer 14, a gate 15, interlayer insulating layer 16 , source and drain electrodes 17 , passivation layer 18 and pixel electrode 19 .
  • an insulating material or a metal oxide material is used to deposit a thin film of the platform layer, and patterned by a photolithography process to form the platform layer 11 .
  • a buffer layer 12 is deposited on the substrate 10 to cover the platform layer 11 .
  • the material of the buffer layer 12 can be a nitride (silicon nitride, etc.), an oxide (silicon oxide, silicon dioxide), or a multilayer film.
  • the buffer layer 12 formed through deposition has a protrusion 121 at the corresponding lower platform.
  • the platform layer 11 is made of insulating material, so the buffer layer 12 may not be provided, but in order to increase the adhesion between the glass substrate and the various active layers on its surface, And it can provide the function of preventing impurities inside the glass substrate from diffusing into each active layer during the process.
  • the thin film transistor array substrate 1 of the embodiment of the present application is provided with a buffer layer 12 on the substrate 10 .
  • an oxide active layer 13 is deposited on the buffer layer 12 .
  • the oxide active layer 13 includes a channel portion 131 and conductor portions 132 located on opposite sides of the channel portion 131 . It should be noted that the channel portion 131 and the conductor portion 132 are located at different horizontal positions, that is, the top surface of the channel portion 131 is at a higher level than the top surface of any conductor portion 132 . Specifically, the channel portion 131 is disposed on the boss 121 of the buffer layer 12 and covers the entire boss 121 .
  • the channel portion 131 includes two slopes 133, one end of each slope 133 is connected to the corresponding conductor portion 132, and the other end extends from the channel portion 131, wherein the slope 133 is away from the channel portion 131 and It is inclined in the direction of the corresponding conductor part 132 .
  • the buffer layer 12 is disposed between the oxide active layer 13 and the substrate 10 and the platform layer 11 .
  • the gate insulating layer 14 is disposed on the oxide active layer 13 .
  • the gate electrode 15 is provided on the gate insulating layer 14 .
  • two offset portions 141 are formed on the gate insulating layer 14 after photolithography and self-alignment etching.
  • the two offset portions 141 are disposed on opposite ends of the gate insulating layer 14 , and each offset portion 141 is disposed along the slope 133 of the channel portion 131 and covers the slope 133 .
  • each offset portion 141 is defined between an end edge of the gate insulating layer 14 corresponding to the gate 15 and a corresponding end edge of the gate insulating layer 14 .
  • the length of the platform layer 11 is shorter than the length of the channel portion 131 and approximately the same as the length of the gate 15, that is, the orthographic projection of the channel portion 131 on the substrate 10 covers the surface of the platform layer 11 on the substrate. Orthographic projection on 10.
  • the orthographic projection of the gate 15 on the substrate 10 covers the orthographic projection of the platform layer 11 and the channel portion 131 on the substrate 10 .
  • the length difference between the platform layer 11 and the gate 15 is less than 2 microns. It can be seen from the schematic cross-sectional structure of the thin film transistor array substrate 1 in FIG. The vertical section respectively extends out the length range of the grid 15 . That is to say, the orthographic projection of each offset portion 141 on the substrate 10 is located on the first end surface 111 or the second end surface 112 of the platform layer 11 .
  • an interlayer insulating layer 16 is deposited on the buffer layer 12 to cover the oxide active layer 13, the gate insulating layer 14, and the gate 15, and the interlayer insulating layer 16 is patterned to form a plurality of overlayers. hole 160.
  • the source and drain electrodes 17 are disposed on the interlayer insulating layer 16 and are electrically connected to the conductor portion 132 of the oxide active layer 13 through corresponding via holes 160 .
  • a passivation layer 18 is further formed on the interlayer insulating layer 16 .
  • a planarization layer (not shown) is further disposed on the passivation layer 18 .
  • the pixel electrode 19 is formed on the passivation layer 18 or on the planarization layer.
  • the pixel electrode 19 is electrically connected to the source electrode and the drain electrode 17 through the through hole 180 .
  • the embodiment of the present application provides a top-gate thin film transistor array substrate 1 . Accordingly, the thin film transistor array substrate 1 of the embodiment of the present application can be used as a driving substrate for a subsequent liquid crystal display or organic light emitting diode display.
  • the arrangement of the platform layer 11 and the angle adjustment of the first end surface 111 and the second end surface 112 of the platform layer 11 are used to form the upper film structure.
  • Gentle slope-shaped offset portion 141 wherein the orthographic projection of the two offset portions 141 on the substrate 10 covers the orthographic projection of the slope edge 133 of the channel portion 131 on the substrate 10, and respectively fall on the bottom of the platform layer 11 On the first end surface 111 and the second end surface 112 .
  • the offset part 141 By setting the offset part 141, the conductive diffusion path of the oxide active layer 13 is extended, and the low-resistance region formed by diffusing the two ends of the channel part 131 into the channel part 131 after the self-aligned etching is reduced. length, so as to effectively regulate or suppress the shortening of the effective channel length, ensure the effective channel length, and facilitate the reduction of the size of the thin film transistor device.
  • the embodiment of the present application further provides a method for manufacturing a thin film transistor array substrate, that is, a method for manufacturing the thin film transistor array substrate 1 of the above embodiment.
  • FIG. 3 is a flowchart of a manufacturing method of the thin film transistor array substrate 1 according to the embodiment of the present application.
  • 4 to 11 are schematic diagrams of the film layer structure of the thin film transistor array substrate 1 produced in each step of the manufacturing method of the thin film transistor array substrate 1 according to the embodiment of the present application.
  • the manufacturing method of the thin film transistor array substrate 1 includes steps S10 to S80:
  • Step S10 depositing a platform layer on the substrate.
  • the platform layer 11 on the substrate 10 has a thickness of 100 angstroms ( ⁇ )-10000 ⁇ , and includes a first end surface 111 and a second end surface 112 that are inclined outwards respectively, and the platform layer
  • the material of layer 11 is an insulating material or a metal oxide.
  • the thin film transistor array substrate as shown in FIG. 1 may not be provided with a buffer layer.
  • the substrate in order to increase the adhesion between the glass substrate and the active layers on its surface, and to provide the function of blocking impurities inside the glass substrate from diffusing into each active layer during the process, the substrate can be further 10 Deposit a buffer layer.
  • the manufacturing method further includes step S101: depositing a buffer layer on the substrate to cover the platform layer.
  • the buffer layer 12 is silicon oxide, silicon nitride or a multi-layer film with a thickness of 1000 ⁇ -5000 ⁇ , wherein the buffer layer 12 forms a boss 121 directly above the platform layer 11 through a photolithography process.
  • Step S20 providing an oxide active layer on the substrate, and forming a channel portion and conductor regions on two opposite sides of the channel portion by photolithography.
  • the oxide active layer 13 is IGZO, IZTO, or IGZTO is made of metal oxide semiconductors and has a thickness of 50 ⁇ -1000 ⁇ .
  • the channel portion 131 includes two slopes 133 , one end of each slope 133 is connected to the corresponding conductor region 130 , and each slope 133 is inclined away from the channel portion 131 and toward the corresponding conductor region 130 .
  • the channel portion 131 is disposed on the boss 121 and covers the whole boss 121 .
  • Step S30 depositing a gate insulating layer on the oxide active layer.
  • the gate insulating layer 14 can be made of silicon oxide, silicon nitride or a multi-layer film, and has a thickness of 1000 ⁇ -3000 ⁇ .
  • Step S40 depositing a gate metal layer on the gate insulating layer.
  • the gate metal layer 150 may be made of molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), manganese (Mn), etc., or an alloy thereof, and There are 2000 ⁇ -10000 ⁇ thickness.
  • Step S50 patterning the gate metal layer by a photolithography process to form a gate, and self-aligning etching the gate insulating layer to expose the conductor region of the oxide active layer, wherein the gate
  • the orthographic projection of the pole on the substrate covers the orthographic projection of the mesa layer and the channel portion on the substrate.
  • FIG. 8 use a photomask 110 to perform a photolithography process to pattern the gate metal layer 150 to form the gate 15, and self-align and etch the gate insulating layer 14 to expose the oxide active layer. 13 conductor regions 130 .
  • FIG. 8 use a photomask 110 to perform a photolithography process to pattern the gate metal layer 150 to form the gate 15, and self-align and etch the gate insulating layer 14 to expose the oxide active
  • the gate insulating layer 14 forms two offset portions 141 after the above-mentioned photolithography process and self-aligned etching, and the two offset portions 141 respectively cover the slope 133 of the channel portion 131, and
  • the orthographic projection of each offset portion 141 on the substrate 10 is located on the first end surface 111 or the second end surface 112 of the platform layer 11 .
  • the orthographic projections of the offset portion 141 on the substrate 10 respectively cover the orthographic projections of the first end surface 111 and the second end surface 112 of the platform layer 11 on the substrate 10, and the slope edge 133 of the channel portion 131 is on the substrate 10. Orthographic projection on base 10.
  • Step S60 Perform plasma treatment on the entire surface to conduct the conductor region of the oxide active layer and form a conductor part, wherein the level of the top surface of the channel part is higher than any of the conductors The height of the horizontal plane where the top surface of the section is located.
  • the resistance is significantly reduced after treatment, and an N+ type conductor portion 132 is formed, corresponding to the platform layer 11.
  • the conductive diffusion path of the offset portion 141 on the first end surface 111 and the second end surface 112 of the first end surface 111 and the second end surface 112 is extended.
  • Step S70 depositing an interlayer insulating layer to cover the oxide active layer, the gate insulating layer and the gate, and patterning the interlayer insulating layer to form a plurality of via holes.
  • the interlayer insulating layer 16 can be made of silicon oxide, silicon nitride or a multi-layer film, and has a thickness of 1000 ⁇ -8000 ⁇ . After patterning, the interlayer insulating layer 16 exposes the source/drain contact region of the oxide active layer 13 and forms a plurality of via holes 160 .
  • Step S80 Depositing a layer of source/drain metal layer, and patterning the source and drain, the source and drain are electrically connected to the conductor part of the oxide active layer through the plurality of via holes .
  • a source/drain metal layer is deposited on the interlayer insulating layer 16, wherein the source/drain metal layer can be molybdenum (Mo), aluminum (Al), copper (Cu), Titanium (Ti), manganese (Mn), etc., or their alloys, and have a thickness of 2000 ⁇ -10000 ⁇ .
  • the source and drain 17 are formed through the patterned source/drain metal layer, which are electrically connected to the conductor portion 132 of the oxide active layer 13 through the via hole 160 .
  • a passivation layer 18 is further formed on the interlayer insulating layer 16, which can be made of silicon oxide, silicon nitride or a multi-layer structure film, and has a thickness of 1000 ⁇ -5000 ⁇ , and the passivation layer 18 forms a through hole 180 through a photolithography process.
  • a planarization layer (not shown) may also be disposed on the passivation layer 18 .
  • a pixel electrode layer is fabricated under the above-mentioned basic film structure, and the pixel electrode layer is patterned to form a pixel electrode 19 , and the pixel electrode 19 is electrically connected to the source electrode and the drain electrode 17 through the through hole 180 . Accordingly, the thin film transistor array substrate 1 of the present application can be used as a driving substrate for a subsequent liquid crystal display or organic light emitting diode display.
  • the setting of the platform layer and the adjustment of the angle of the first end surface and the second end surface of the platform layer are used to form the upper film layer structure Gentle slope-shaped offset portion, wherein the orthographic projection of the two offset portions on the substrate covers the orthographic projection of the slope edge of the channel portion on the substrate, and fall on the first end surface and the second end surface of the platform layer respectively superior.
  • the conductive diffusion path of the oxide active layer is extended, and the length of the low-resistance region formed by the diffusion of the two ends of the channel part into the channel part after self-alignment etching is reduced, thereby effectively controlling Or suppress the shortening of the effective channel length to ensure the effective channel length, which is conducive to the reduction of the size of the thin film transistor device, and effectively solves the problem of low resistance at both ends of the channel due to the diffusion of the conductive effect on both sides of the channel of the traditional thin film transistor. region, leading to a shortened effective channel length, which is not conducive to the technical problem of shortening the size of thin film transistor devices.

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Abstract

本申请公开一种薄膜晶体管阵列基板及其制作方法。薄膜晶体管阵列基板包括衬底、设置在衬底上的平台层。氧化物有源层包括沟道部及两导体部。源极和漏极与导体部电连接。沟道部的顶面所在的水平面高度高于任一导体部的顶面所在的水平面高度。栅极在衬底上的正投影覆盖平台层及沟道部在衬底上的正投影。

Description

薄膜晶体管阵列基板及其制作方法 技术领域
本申请涉及显示技术领域，尤其涉及一种薄膜晶体管阵列基板及其制作方法。
 背景技术
随着显示技术的发展，平面显示器已经成为目前的主流显示器。常用的平面显示器包括液晶显示器(Liquid Crystal Display，LCD)和有源矩阵驱动式有机电致发光显示器(Active Matrix OLED，AMOLED)。
在平面显示器中，薄膜晶体管(Thin-Film Transistor，TFT)阵列基板是主要的驱动元件，且是高性能平板显示装置的必要结构。薄膜晶体管阵列基板包括多个以阵列排布的薄膜晶体管，其包括底栅型(bottom gate)薄膜晶体管或顶栅型(Top gate)薄膜晶体管等不同类型。顶栅型薄膜晶体管，由于源漏电极与栅极之间没有重叠，因此具有更低的寄生电容和更好的延展性，能够降低信号传输过程中的延迟。在顶栅结构的金属氧化物薄膜晶体管技术中，为了降低沟道以外区域的电阻，往往采用自对准（self-aligned）刻蚀工艺，即通过一道光刻制程同时定义栅极图案以及刻蚀栅极绝缘层以及非沟道区域的导体化，这样可以有效避免对位偏差导致的沟道两侧高阻区域的形成。然而，沟道两侧导体化效果的扩散会使得沟道两端存在低阻区域，也就是有效沟道长度变短，这并不利于TFT器件尺寸的缩短。
 技术问题
本申请提供一种薄膜晶体管及其制作方法，以解决传统膜晶体管器的沟道两侧导体化效果的扩散造成沟道两端存在低阻区域，导致有效沟道长度变短，不利于薄膜晶体管器件尺寸的缩短的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种薄膜晶体管阵列基板，包括衬底；平台层，设置在所述衬底上，氧化物有源层，设置在所述衬底上，并位在所述平台层上方，所述氧化物有源层包括沟道部及位在所述沟道部相对两侧的导体部，其中所述沟道部的顶面所在的水平面高度高于任一所述导体部的顶面所在的水平面高度，栅极绝缘层，设置在所述氧化物有源层上 栅极，设置在所述栅极绝缘层上，且所述栅极在所述衬底上的正投影覆盖所述平台层及所述沟道部在所述衬底上的正投影；以及源极和漏极，所述源极和所述漏极与所述导体部电连接。
进一步地，所述薄膜晶体管阵列基板还包括缓冲层，所述缓冲层设置在所述衬底上，并且覆盖所述平台层，其中所述平台层的材料是绝缘材料或金属氧化物。
进一步地，所述缓冲层包括凸台，所述沟道部设置在所述凸台上，并包覆整个所述凸台。
进一步地，所述沟道部包括两坡边，所述坡边的一端连接相应的所述导体部，且所述坡边以远离所述沟道部并朝相应的所述导体部的方向倾斜。
进一步地，所述平台层包括分别朝外倾斜的第一端面及第二端面，且所述沟道部在所述衬底上的正投影覆盖所述平台层在所述衬底上的正投影。
进一步地，所述栅极绝缘层包括相对设置的两个偏移部，所述偏移部定义在所述栅极绝缘层对应所述栅极的端缘及所述栅极绝缘层的相应端缘之间的部分，其中所述两个偏移部在所述衬底上的正投影分别覆盖所述平台层的第一端面及第二端面及所述沟道部的坡边在所述衬底上的正投影。
进一步地，所述薄膜晶体管阵列基板还包括层间绝缘层，所述层间绝缘层覆盖所述氧化物有源层、所述栅极绝缘层及所述栅极，且所述层间绝缘层包括多个过孔，其中所述源极和漏极设在所述层间绝缘层上，并通过所述多个过孔电连接所述导体部。
本申请实施例还提供一种薄膜晶体管阵列基板的制作方法，包括在衬底上沉积一层平台层，所述平台层的材料是绝缘材料或金属氧化；在衬底上形成一层氧化物有源层，并利用光刻工艺形成沟道部及位在所述沟道部相对二侧的导体区域；在所述氧化物有源层沉积一层栅极绝缘层；在所述栅极绝缘层沉积一层栅极金属层；利用一道光刻工艺图形化所述层栅极金属层，以形成栅极，并自对准蚀刻所述栅极绝缘层，以暴露所述氧化物有源层的导体区域，其中所述栅极在所述衬底上的正投影覆盖所述平台层及所述沟道部在所述衬底上的正投影；进行整面等离子处理，使所述氧化物有源层的导体区域导体化并形成导体部，其中所述沟道部的顶面所在的水平面高度高于任一所述导体部的顶面所在的水平面高度；沉积层间绝缘层，以覆盖所述氧化物有源层、所述栅极绝缘层及所述栅极，并图形化所述层间绝缘层以形成多个过孔；以及沉积一层源极/漏极金属层，并图形化形成源极及漏极，所述源极及漏极通过所述多个过孔电连接所述氧化物有源层的导体部。
进一步地，在衬底上形成一层氧化物有源层的步骤之前还包括：在所述衬底上沉积一层缓冲层，以覆盖所述平台层，且所述缓冲层通过光刻工艺形成位在所述平台层正上方的凸台，其中所述沟道部设置在所述凸台上，并包覆整个所述凸台。
进一步地，所述沟道部包括两坡边，所述坡边的一端连接相应的所述导体部，且所述坡边以远离所述沟道部并朝相应的所述导体部的方向倾斜，其中所述栅极绝缘层包括相对设置的两个偏移部，每一所述偏移部形成在所述栅极绝缘层对应所述栅极的端缘及所述栅极绝缘层的相应端缘之间的部分，且所述两个偏移部在所述衬底上的正投影分别覆盖所述平台层的相对两端面及所述沟道部的坡边在所述衬底上的正投影。
本申请实施例还提供一种薄膜晶体管阵列基板，包括衬底；平台层，设置在所述衬底上，所述平台层的材料是绝缘材料或金属氧化物；氧化物有源层，设置在所述衬底上，并位在所述平台层上方，所述氧化物有源层包括沟道部及位在所述沟道部相对两侧的导体部，其中所述沟道部包括两坡边，所述坡边的一端连接相应的所述导体部，另一端连接所述沟道部，且所述沟道部的顶面所在的水平面高度高于任一所述导体部的顶面所在的水平面高度；栅极绝缘层，设置在所述氧化物有源层上；栅极，设置在所述栅极绝缘层上，且所述栅极在所述衬底上的正投影覆盖所述平台层及所述沟道部在所述衬底上的正投影；以及源极和漏极，所述源极和所述漏极与所述导体部电连接。
 有益效果
本申请实施例提供一种薄膜晶体管及其制作方法，利用平台层的设置，及对平台层的第一端面及第二端面的角度调控，使上方的膜层结构形成缓坡状的偏移部，其中两个偏移部在衬底上的正投影覆盖了沟道部的坡边在衬底上的正投影，并且分别落在平台层的第一端面及第二端面上。借由偏移部的设置，延长了氧化物有源层的导体化扩散路径，降低自对准刻蚀后沟道部的两端向沟道部内扩散形成的低阻区域的长度，从而有效调控或抑制有效沟道长度的变短，保证有效沟道长度，利于实现薄膜晶体管器件尺寸的缩小，有效解决了传统膜晶体管器的沟道两侧导体化效果的扩散造成沟道两端存在低阻区域，导致有效沟道长度变短，不利于薄膜晶体管器件尺寸的缩短的技术问题。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例的薄膜晶体管阵列基板的剖面结构示意图。
图2为本申请另一实施例的薄膜晶体管阵列基板的剖面结构示意图。
图3为本申请实施例的薄膜晶体管阵列基板的制作方法的流程图。
图4至图11为本申请实施例的薄膜晶体管阵列基板的制作方法中各步骤制得的薄膜晶体管的膜层结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
本申请实施例提供一种薄膜晶体管，其可以阵列排列，并制备成薄膜晶体管阵列基板。所述薄膜晶体管阵列基板上设置有数条栅极扫描线和数条数据线，所述数条栅极扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有所述薄膜晶体管和像素电极。所述薄膜晶体管阵列基板可以作为液晶显示器或有机发光二极管显示器的驱动基板。
请参阅图1，图1为本申请实施例的薄膜晶体管阵列基板1的剖面结构示意图。如图1所示，本申请实施例提供的薄膜晶体管阵列基板1包括依次设置的衬底10、平台层11、氧化物有源层13、栅极绝缘层14、栅极15、层间绝缘层16、源极和漏极17、钝化层18及像素电极19。衬底10的材料可为玻璃或透明塑料等材料，优选为玻璃。衬底10的表面设置有平台层11。具体的，使用绝缘材料沉积平台层薄膜，并通过光刻工艺图形化形成平台层11。平台层11包括顶面和第一端面111及第二端面112。需要说明的是，第一端面111及第二端面112分别设置在平台层11的相对二端，且第一端面111及第二端面112分别是由平台层11的顶面朝向衬底10的方向往外倾斜。较佳地，第一端面111与衬底10之间构成40°-80°的角度，第二端面112与衬底10之间构成40°-80°的角度。在一实施例中，第一端面111与衬底10的角度相同于第二端面112与衬底10之间的角度。特别注意的是，上述角度范围是依据刻蚀制程的制程能力范围来设置，并可促使上方膜层形成相应斜状构型。
如图1所示，氧化物有源层13设置在衬底10上，氧化物有源层13的材料可以是铟镓锌氧化物(indium gallium zinc oxide, IGZO)、铟锌锡氧化物(indium zinc tin oxide, IZTO)或铟镓锌锡氧化物(indium gallium zinc tin oxide, IGZTO)的金属氧化物半导体。氧化物有源层13包括沟道部131及位在沟道部131相对两侧的导体部132，其中沟道部131位在平台层11的正上方。特别注意的是，由于平台层11设置在衬底10的表面上，沟道部131的高度因此被提升，使沟道部131与导体部132分别位在不同的水平位置。亦即，沟道部131的顶面所在的水平面高度高于任一导体部132的顶面所在的水平面高度。具体地，沟道部131包括二坡边133，每一坡边133的一端连接相应的导体部132，另一端延伸自沟道部131，其中坡边133是以远离沟道部131并朝相应的导体部132的方向倾斜。
续请参阅图1，栅极绝缘层14设置在氧化物有源层13上。栅极15设置在栅极绝缘层14上。需要说明的是，栅极15是通过一道光刻工艺图形化金属层形成，并自对准蚀刻栅极绝缘层14，以暴露氧化物有源层13的导体区域130 (如后图6所示)，之后进行整面等离子(plasma)处理，使氧化物有源层13的导体区域130导体化而形成导体部132。进一步说，栅极绝缘层14在经过上述光刻工艺及自对准蚀刻之后形成两个偏移部141。所述两个偏移部141设置在栅极绝缘层14的相对二端，且每一偏移部141顺应着沟道部131的坡边133设置，并覆盖坡边133。具体的，每一偏移部141定义在栅极绝缘层14对应栅极15的端缘及栅极绝缘层14的相应端缘之间的部分。需要说明的是，平台层11的长度小于沟道部131的长度，并大致相同于栅极15的长度。亦即，栅极15在衬底10上的正投影覆盖平台层11及沟道部131在衬底10上的正投影。在此实施例中，平台层11的与栅极15之间的长度差小于2微米。由图1的薄膜晶体管阵列基板1的剖面结构示意图可看出，平台层11的第一端面111及第二端面112在垂直断面上分别延伸出栅极15的长度范围。也就是说，每一偏移部141在衬底10上的正投影覆盖平台层11的第一端面111或第二端面112在1在衬底10上的正投影。
如图1所示，在衬底10上沉积层间绝缘层16，以覆盖氧化物有源层13、栅极绝缘层14及栅极15，并图形化层间绝缘层16以形成多个过孔160。源极和漏极17设置在层间绝缘层16上，并通过相应的过孔160电连接氧化物有源层13的导体部132。此外，在层间绝缘层16上进一步形成钝化层18，其材料可为氮化物(氮化硅等)、氧化物(氧化硅、二氧化硅)或是多层结构薄膜。在另一实施例中，钝化层18上还设置有平坦化层(未图示)，所述平坦化层可对下方的膜层提供进一步的保护作用，并起到更佳的平坦化作用。在钝化层18或是在所述平坦化层上形成像素电极19。像素电极19是经由图形化金属层形成，并通过穿孔180电连接源极和漏极17。依据上述所有构件，本申请实施例提供了一种顶栅型薄膜晶体管阵列基板1，其可作为后续液晶显示器或有机发光二极管显示器的驱动基板。
请参阅图2，其为本申请另一实施例的薄膜晶体管阵列基板1的剖面结构示意图。图2所示实施例与图1的区别在于图2的薄膜晶体管阵列基板1还设置有缓冲层12(详如后述)，其他相同的构件于此不再详细说明。如图2所示，本申请实施例提供的薄膜晶体管阵列基板1包括依次设置的衬底10、平台层11、缓冲层12、氧化物有源层13、栅极绝缘层14、栅极15、层间绝缘层16、源极和漏极17、钝化层18及像素电极19。具体的，使用绝缘材料或金属氧化物材料沉积平台层薄膜，并通过光刻工艺图形化形成平台层11。
续请参阅图2，在衬底10上沉积缓冲层12，以覆盖平台层11。具体的，缓冲层12的材料可为氮化物(氮化硅等)、氧化物(氧化硅、二氧化硅)或是多层结构薄膜。经过沉积所形成的缓冲层12在对应下方的平台处具有凸台121。需要说明的是，在图1所示的实施例中，平台层11为绝缘材料所制，因此可以不设置缓冲层12，但为了增加玻璃衬底与其表面的各作用层之间的附着性，并且可提供阻挡玻璃衬底内部的杂质在工艺中扩散进入各作用层的功用，本申请实施例的薄膜晶体管阵列基板1在衬底10上设置有缓冲层12。
如图2所述，在缓冲层12上沉积一层氧化物有源层13。氧化物有源层13包括沟道部131及位在沟道部131相对两侧的导体部132。特别注意的是，沟道部131与导体部132分别位在不同的水平位置，亦即，沟道部131的顶面所在的水平面高度高于任一导体部132的顶面所在的水平面高度。具体的，沟道部131是设置在缓冲层12的凸台121上，并包覆整个凸台121。需要说明的是，沟道部131包括二坡边133，每一坡边133的一端连接相应的导体部132，另一端延伸自沟道部131，其中坡边133是以远离沟道部131并朝相应的导体部132的方向倾斜。如图2所示，缓冲层12设置在氧化物有源层13及衬底10及平台层11之间。
续请参阅图2，栅极绝缘层14设置在氧化物有源层13上。栅极15设置在栅极绝缘层14上。进一步说，栅极绝缘层14在经过光刻工艺及自对准蚀刻之后形成两个偏移部141。所述两个偏移部141设置在栅极绝缘层14的相对二端，且每一偏移部141顺应着沟道部131的坡边133设置，并覆盖坡边133。具体的，每一偏移部141定义在栅极绝缘层14对应栅极15的端缘及栅极绝缘层14的相应端缘之间的部分。需要说明的是，平台层11的长度小于沟道部131的长度，并大致相同于栅极15的长度，亦即，沟道部131在衬底10上的正投影覆盖平台层11在衬底10上的正投影。此外，栅极15在衬底10上的正投影覆盖平台层11及沟道部131在衬底10上的正投影。在此实施例中，平台层11的与栅极15之间的长度差小于2微米。由图1的薄膜晶体管阵列基板1的剖面结构示意图可看出，平台层11的第一端面111及第二端面112呈40°-80°的倾斜，使得第一端面111及第二端面112在垂直断面上分别延伸出栅极15的长度范围。也就是说，每一偏移部141在衬底10上的正投影位在平台层11的第一端面111或第二端面112上。
如图2所示，在缓冲层12上沉积层间绝缘层16，以覆盖氧化物有源层13、栅极绝缘层14及栅极15，并图形化层间绝缘层16以形成多个过孔160。源极和漏极17设置在层间绝缘层16上，并通过相应的过孔160电连接氧化物有源层13的导体部132。此外，在层间绝缘层16上进一步形成钝化层18。在另一实施例中，钝化层18上还设置有平坦化层(未图示)。在钝化层18或是在所述平坦化层上形成像素电极19。像素电极19通过穿孔180电连接源极和漏极17。依据上述所有构件，本申请实施例提供了一种顶栅型薄膜晶体管阵列基板1。据此，本申请实施例的薄膜晶体管阵列基板1可作为后续液晶显示器或有机发光二极管显示器的驱动基板。
如上所述，在本申请实施例的薄膜晶体管阵列基板1中，利用平台层11的设置，及对平台层11的第一端面111及第二端面112的角度调控，使上方的膜层结构形成缓坡状的偏移部141，其中两个偏移部141在衬底10上的正投影覆盖了沟道部131的坡边133在衬底10上的正投影，并且分别落在平台层11的第一端面111及第二端面112上。借由偏移部141的设置，延长了氧化物有源层13的导体化扩散路径，降低自对准刻蚀后沟道部131的两端向沟道部131内扩散形成的低阻区域的长度，从而有效调控或抑制有效沟道长度的变短，保证有效沟道长度，利于实现薄膜晶体管器件尺寸的缩小。
本申请实施例另外提供一种薄膜晶体管阵列基板的制作方法，亦即，一种用于制作上述实施例的薄膜晶体管阵列基板1的方法。
请参阅图3及图4至图11。图3为本申请实施例的薄膜晶体管阵列基板1的制作方法的流程图。图4至图11为本申请实施例的薄膜晶体管阵列基板1的制作方法中各步骤制得的薄膜晶体管阵列基板1的膜层结构示意图。
如图3所示，本申请实施例的薄膜晶体管阵列基板1的制作方法包括步骤S10~步骤S80：
步骤S10：在衬底上沉积一层平台层。具体的，如图4所示，在衬底10上的平台层11的厚度为100埃(angstroms, Å)-10000Å，并包括分别朝外倾斜的第一端面111及第二端面112，且平台层11的材料是绝缘材料或金属氧化物。
需要说明的是，若平台层11是绝缘材料所制，则可以如图1所示的薄膜晶体管阵列基板不设置缓冲层。
在另一实施例中，为了增加玻璃衬底与其表面的各作用层之间的附着性，并且可提供阻挡玻璃衬底内部的杂质在工艺中扩散进入各作用层的功用，可进一步在衬底10沉积一层缓冲层。具体的，如图5所示，所述制作方法还包括步骤S101：沉积一层缓冲层在所述衬底上，以覆盖所述平台层。缓冲层12为氧化硅、氮化硅或是多层结构薄膜，且具有1000Å-5000Å的厚度，其中缓冲层12通过光刻工艺形成位在平台层11正上方的凸台121。
步骤S20：在衬底上提供一层氧化物有源层，并利用光刻工艺形成沟道部及位在所述沟道部相对二侧的导体区域。具体的，如图6所示，氧化物有源层13为IGZO, IZTO, 或IGZTO的金属氧化物半导体所制，并具有50Å-1000Å的厚度。沟道部131包括二坡边133，每一坡边133的一端连接相应的导体区域130，且每一坡边133以远离沟道部131并朝相应的导体区域130的方向倾斜。其中，沟道部131设置在凸台121上，并包覆整个凸台121。
步骤S30：在氧化物有源层沉积一层栅极绝缘层。具体的，如图7所示，栅极绝缘层14可为氧化硅、氮化硅或是多层结构薄膜所制，并具有1000Å-3000Å的厚度。
步骤S40：在所述栅极绝缘层沉积一层栅极金属层。具体的，如图8所示，栅极金属层150可以是钼(Mo)，铝(Al)，铜(Cu)，钛(Ti)，锰(Mn)等，或者是其合金所制，并有2000Å-10000Å的厚度。
步骤S50：利用一道光刻工艺图形化所述层栅极金属层，以形成栅极，并自对准蚀刻所述栅极绝缘层，以暴露所述氧化物有源层的导体区域，其中栅极在所述衬底上的正投影覆盖所述平台层及所述沟道部在所述衬底上的正投影。。具体的，如图8所示，利用一道光罩110进行光刻工艺图形化层栅极金属层150以形成栅极15，并自对准蚀刻栅极绝缘层14，以暴露氧化物有源层13的导体区域130。如图9所示，栅极绝缘层14在经过上述光刻工艺及自对准蚀刻之后形成两个偏移部141，两个偏移部141分别覆盖沟道部131的坡边133，且两个偏移部141在衬底10上的正投影位在平台层11的第一端面111或第二端面112上。同时，偏移部141在衬底10上的正投影分别覆盖了平台层11的第一端面111及第二端面112在衬底10上的正投影，及沟道部131的坡边133在衬底10上的正投影。
步骤S60：进行整面等离子(plasma)处理，使所述氧化物有源层的导体区域导体化并形成导体部，其中所述沟道部的顶面所在的水平面高度高于任一所述导体部的顶面所在的水平面高度。具体的，如图9所示，对于上方没有光阻/栅极绝缘层14/金属保护的氧化物有源层13，其处理以后电阻明显降低，形成N+型导体部132，且对应平台层11的第一端面111及第二端面112上的偏移部141 的导体化扩散路径被延长。
步骤S70：沉积层间绝缘层，以覆盖所述氧化物有源层、所述栅极绝缘层及所述栅极，并图形化所述层间绝缘层以形成多个过孔。具体的，如图10所示，层间绝缘层16可为氧化硅、氮化硅或是多层结构薄膜所制，并具有1000Å-8000Å的厚度。层间绝缘层16经图形化后暴露出氧化物有源层13的源极/漏极接触区域及形成多个过孔160。
步骤S80：沉积一层源极/漏极金属层，并图形化形成源极及漏极，所述源极及漏极通过所述多个过孔电连接所述氧化物有源层的导体部。具体的，如图11所示，在层间绝缘层16上沉积源极/漏极金属层，其中源极/漏极金属层可以是钼(Mo)，铝(Al)，铜(Cu)，钛(Ti)，锰(Mn)等，或者是其合金所制，并有2000Å-10000Å的厚度。通过图形化后的源极/漏极金属层形成源极及漏极17，其借由过孔160电连接氧化物有源层13的导体部132。
此外，如图1及图2所示，在层间绝缘层16上进一步形成钝化层18，其可为氧化硅、氮化硅或是多层结构薄膜所制，并具有1000Å-5000Å的厚度，且钝化层18通过光刻工艺形成穿孔180。在另一实施例中，钝化层18上还可设置有平坦化层(未图示)。最后，在上述基础的膜层结构下制作像素电极层，并图形化所述像素电极层形成像素电极19，且像素电极19借由穿孔180电连接源极及漏极17。据此，本申请的薄膜晶体管阵列基板1可作为后续液晶显示器或有机发光二极管显示器的驱动基板。
综上所述，在本申请实施例的薄膜晶体管阵列基板及其制作方法中，利用平台层的设置，及对平台层的第一端面及第二端面的角度调控，使上方的膜层结构形成缓坡状的偏移部，其中两个偏移部在衬底上的正投影覆盖了沟道部的坡边在衬底上的正投影，并且分别落在平台层的第一端面及第二端面上。借由偏移部的设置，延长了氧化物有源层的导体化扩散路径，降低自对准刻蚀后沟道部的两端向沟道部内扩散形成的低阻区域的长度，从而有效调控或抑制有效沟道长度的变短，保证有效沟道长度，利于实现薄膜晶体管器件尺寸的缩小，有效解决了传统膜晶体管器的沟道两侧导体化效果的扩散造成沟道两端存在低阻区域，导致有效沟道长度变短，不利于薄膜晶体管器件尺寸的缩短的技术问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (17)

  1. 一种薄膜晶体管阵列基板，包括：
    衬底；
    平台层，设置在所述衬底上；
    氧化物有源层，设置在所述衬底上，并位在所述平台层上方，所述氧化物有源层包括沟道部及位在所述沟道部相对两侧的导体部，其中所述沟道部的顶面所在的水平面高度高于任一所述导体部的顶面所在的水平面高度；
    栅极绝缘层，设置在所述氧化物有源层上；
    栅极，设置在所述栅极绝缘层上，且所述栅极在所述衬底上的正投影覆盖所述平台层及所述沟道部在所述衬底上的正投影；以及
    源极和漏极，所述源极和所述漏极与所述导体部电连接。
  2. 如权利要求1所述的薄膜晶体管阵列基板，其中所述薄膜晶体管阵列基板还包括缓冲层，所述缓冲层设置在所述衬底上，并且覆盖所述平台层，其中所述平台层的材料是绝缘材料或金属氧化物。
  3. 如权利要求2所述的薄膜晶体管阵列基板，其中所述缓冲层包括凸台，所述沟道部设置在所述凸台上，并包覆整个所述凸台。
  4. 如权利要求1所述的薄膜晶体管阵列基板，其中所述沟道部包括两坡边，所述坡边的一端连接相应的所述导体部，且所述坡边以远离所述沟道部并朝相应的所述导体部的方向倾斜。
  5. 如权利要求4所述的薄膜晶体管阵列基板，其中所述平台层包括分别朝外倾斜的第一端面及第二端面，且所述沟道部在所述衬底上的正投影覆盖所述平台层在所述衬底上的正投影。
  6. 如权利要求5所述的薄膜晶体管阵列基板，其中所述栅极绝缘层包括相对设置的两个偏移部，所述偏移部定义在所述栅极绝缘层对应所述栅极的端缘及所述栅极绝缘层的相应端缘之间的部分，其中所述两个偏移部在所述衬底上的正投影分别覆盖所述平台层的第一端面及第二端面及所述沟道部的坡边在所述衬底上的正投影。
  7. 如权利要求1所述的薄膜晶体管阵列基板，其中所述薄膜晶体管阵列基板还包括层间绝缘层，所述层间绝缘层覆盖所述氧化物有源层、所述栅极绝缘层及所述栅极，且所述层间绝缘层包括多个过孔，其中所述源极和漏极设在所述层间绝缘层上，并通过所述多个过孔电连接所述导体部。
  8. 一种薄膜晶体管阵列基板的制作方法，包括：
    在衬底上沉积一层平台层，所述平台层的材料是绝缘材料或金属氧化物；
    在衬底上形成一层氧化物有源层，并利用光刻工艺形成沟道部及位在所述沟道部相对二侧的导体区域；
    在所述氧化物有源层沉积一层栅极绝缘层；
    在所述栅极绝缘层沉积一层栅极金属层；
    利用一道光刻工艺图形化所述层栅极金属层，以形成栅极，并自对准蚀刻所述栅极绝缘层，以暴露所述氧化物有源层的导体区域，其中所述栅极在所述衬底上的正投影覆盖所述平台层及所述沟道部在所述衬底上的正投影；
    进行整面等离子处理，使所述氧化物有源层的导体区域导体化并形成导体部，其中所述沟道部的顶面所在的水平面高度高于任一所述导体部的顶面所在的水平面高度；
    沉积层间绝缘层，以覆盖所述氧化物有源层、所述栅极绝缘层及所述栅极，并图形化所述层间绝缘层以形成多个过孔；以及
    沉积一层源极/漏极金属层，并图形化形成源极及漏极，所述源极及漏极通过所述多个过孔电连接所述氧化物有源层的导体部。
  9. 如权利要求8所述的薄膜晶体管阵列基板的制作方法，其中在衬底上形成一层氧化物有源层的步骤之前还包括：在所述衬底上沉积一层缓冲层，以覆盖所述平台层，且所述缓冲层通过光刻工艺形成位在所述平台层正上方的凸台，其中所述沟道部设置在所述凸台上，并包覆整个所述凸台。
  10. 如权利要求9所述的薄膜晶体管阵列基板的制作方法，其中所述沟道部包括两坡边，所述坡边的一端连接相应的所述导体部，且所述坡边以远离所述沟道部并朝相应的所述导体部的方向倾斜，其中所述栅极绝缘层包括相对设置的两个偏移部，所述偏移部形成在所述栅极绝缘层对应所述栅极的端缘及所述栅极绝缘层的相应端缘之间的部分，其中所述两个偏移部在所述衬底上的正投影分别覆盖所述平台层的相对两端面及所述沟道部的坡边在所述衬底上的正投影。
  11. 一种薄膜晶体管阵列基板，包括：
    衬底；
    平台层，设置在所述衬底上，所述平台层的材料是绝缘材料或金属氧化物；
    氧化物有源层，设置在所述衬底上，并位在所述平台层上方，所述氧化物有源层包括沟道部及位在所述沟道部相对两侧的导体部，其中所述沟道部包括两坡边，所述坡边的一端连接相应的所述导体部，另一端连接所述沟道部，且所述沟道部的顶面所在的水平面高度高于任一所述导体部的顶面所在的水平面高度；
    栅极绝缘层，设置在所述氧化物有源层上；
    栅极，设置在所述栅极绝缘层上，且所述栅极在所述衬底上的正投影覆盖所述平台层及所述沟道部在所述衬底上的正投影；以及
    源极和漏极，所述源极和所述漏极与所述导体部电连接。
  12. 如权利要求11所述的薄膜晶体管阵列基板，其中所述薄膜晶体管阵列基板还包括缓冲层，所述缓冲层设置在所述衬底上，并且覆盖所述平台层。
  13. 如权利要求12所述的薄膜晶体管阵列基板，其中所述缓冲层包括凸台，所述沟道部设置在所述凸台上，并包覆整个所述凸台。
  14. 如权利要求11所述的薄膜晶体管阵列基板，其中所述坡边以远离所述沟道部并朝相应的所述导体部的方向倾斜。
  15. 如权利要求14所述的薄膜晶体管阵列基板，其中所述平台层包括分别朝外倾斜的第一端面及第二端面，且所述沟道部在所述衬底上的正投影覆盖所述平台层在所述衬底上的正投影。
  16. 如权利要求15所述的薄膜晶体管阵列基板，其中所述栅极绝缘层包括相对设置的两个偏移部，所述偏移部定义在所述栅极绝缘层对应所述栅极的端缘及所述栅极绝缘层的相应端缘之间的部分，其中所述两个偏移部在所述衬底上的正投影分别覆盖所述平台层的第一端面及第二端面及所述沟道部的坡边在所述衬底上的正投影。
  17. 如权利要求11所述的薄膜晶体管阵列基板，其中所述薄膜晶体管阵列基板还包括层间绝缘层，所述层间绝缘层覆盖所述氧化物有源层、所述栅极绝缘层及所述栅极，且所述层间绝缘层包括多个过孔，其中所述源极和漏极设在所述层间绝缘层上，并通过所述多个过孔电连接所述导体部。
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