WO2023019545A1 - 芯片和装置 - Google Patents

芯片和装置 Download PDF

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Publication number
WO2023019545A1
WO2023019545A1 PCT/CN2021/113728 CN2021113728W WO2023019545A1 WO 2023019545 A1 WO2023019545 A1 WO 2023019545A1 CN 2021113728 W CN2021113728 W CN 2021113728W WO 2023019545 A1 WO2023019545 A1 WO 2023019545A1
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WIPO (PCT)
Prior art keywords
signal
test
chip
transmission path
signal transmission
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PCT/CN2021/113728
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English (en)
French (fr)
Inventor
崔昌明
黄俊林
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180097043.4A priority Critical patent/CN117280417A/zh
Priority to PCT/CN2021/113728 priority patent/WO2023019545A1/zh
Publication of WO2023019545A1 publication Critical patent/WO2023019545A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices

Definitions

  • the embodiments of the present application relate to the technical field of circuits, and in particular, to a chip and a device.
  • BIST built-in self-test
  • the chip and device provided by the present application can improve the accuracy of inter-chip connectivity test.
  • the embodiment of the present application provides a chip, the chip includes: including a test circuit, a plurality of signal transmission paths, a test signal input pin and a plurality of interconnection pins, the chip is a first chip, and the plurality of A plurality of interconnection pins are used to connect with the second chip; the test circuit is used for: passing through the first signal transmission path in the plurality of signal transmission paths, to the first interconnection pin in the plurality of interconnection pins transmitting a first test signal, so that the second chip detects the first signal transmission path based on the first test signal; through the second signal transmission path in the plurality of signal transmission paths, from the A second interconnection pin among the plurality of interconnection pins receives a second test signal, and generates a first test result based on the second test signal and the test signal generated by the test circuit, and the first test result is used for Indicating whether the second signal transmission path fails; receiving a third test signal from the test signal input pin, and transmitting the third test signal to the The third test signal from the
  • the test circuit shown in the embodiment of the present application can test the signal transmission path without combinatorial logic in the chip by using the built-in self-test signal, and test the signal transmission path with combinatorial logic in the chip by scanning the test signal , thereby improving the test efficiency and test accuracy of the test circuit.
  • test circuit provided in the embodiment of the present application can also test the signal transmission path for signal transmission inside the chip and between unit modules.
  • the test circuit is further configured to: transmit a fourth test signal through a fourth signal transmission path among the plurality of signal transmission paths; Four test signals, generating a second test result, the second test result is used to indicate whether a fault occurs in the fourth signal transmission path; no combinatorial logic is set in the fourth signal transmission path, and the fourth test signal is BIST signal.
  • the fourth signal transmission path is a path for transmitting signals between logic units in the chip.
  • the detection of the fourth signal transmission path can occur before the detection of the first signal transmission path to the third signal transmission path, so as to ensure that the signal transmission paths inside the chip are free of faults.
  • the accuracy of chip testing can be improved by using the BIST signal to test the signal transmission paths inside the chip without combinational logic.
  • the chip further includes a test signal output pin; the test circuit is further configured to: receive a fifth test signal from the test signal input pin, pass the fifth test signal through A fifth signal transmission path among the plurality of signal transmission paths is transmitted to the test signal output pin, and a combinational logic is arranged in the fifth signal transmission path.
  • the fifth test signal can be a scan test signal, and the test signal input pin and the test signal output pin can be connected to the test equipment, and the test equipment provides the third test signal to the fifth signal transmission path through the test signal input pin.
  • the fifth signal transmission path transmits the third test signal to the test equipment through the test signal output pin, so that the test equipment can test the fifth signal transmission path provided with combinational logic inside the chip, which can improve the accuracy of chip testing.
  • the test circuits described in the embodiments of the present application may include various types of circuit structures.
  • the test circuit includes a built-in self-test circuit and a scan test circuit;
  • the built-in self-test circuit includes a signal transmitting end and a signal receiving end; the signal transmitting end is used to generate The first test signal; the signal receiving end is used to generate the first test result based on the second test signal and the generated test signal;
  • the scan test circuit is used to obtain the test signal from the test signal
  • the input pin receives the third test signal, and transmits the third test signal to the third interconnection pin through the third signal transmission path.
  • test circuit tests the signal transmission path for signal transmission inside the chip and between unit modules:
  • the signal transmitting end is further configured to: generate the fourth test signal, and transmit the fourth test signal to the signal receiving end through the fourth signal transmission path.
  • the signal receiving end is further configured to: generate the second test result based on the fourth test signal and the test signal generated by the signal receiving end.
  • the scan test circuit is further configured to: receive the fifth test signal from the test signal input pin, and transmit the fifth test signal to the test signal output pin through the fifth signal transmission path.
  • the signal transmitting end is connected to the first interconnection pin through the first signal transmission path; the signal receiving end is connected to the first interconnection pin through the The second signal transmission path is connected to the second interconnection pin.
  • the chip further includes: a multiplexer, the multiplexer is arranged between the built-in self-test circuit and the plurality of interconnection pins; the multiplexer The selector is used to connect the signal transmitting end to the first interconnection pin through the first signal transmission path when a failure occurs in the first signal transmission path, and switch to the signal transmitting end through the multiple The sixth signal transmission path among the signal transmission paths is connected to the fourth interconnection pin among the plurality of interconnection pins.
  • the fourth interconnection pin is a redundant pin.
  • the multiplexer is further configured to: when a fault occurs in the second signal transmission path, connect the signal receiving end to the second signal transmission path through the second signal transmission path.
  • the interconnection pins are connected, and the signal receiving end is switched to be connected to the fifth interconnection pin of the plurality of interconnection pins through the seventh signal transmission path of the plurality of signal transmission paths.
  • the signal transmitting end includes a first linear feedback shift register
  • the signal receiving end includes a second linear feedback shift register
  • the first linear feedback shift register and the second linear feedback shift register The bilinear feedback shift register is obtained by multiplexing the function registers in the chip.
  • the scan test circuit includes a plurality of cascaded chip package registers, and the multiple cascaded chip package registers are obtained by multiplexing the first linear feedback shift register and the obtained by at least one of the second linear feedback registers.
  • the number of registers set in the chip can be reduced, thereby reducing
  • the layout area of the chip occupied by the small register simplifies the circuit in the chip, which is conducive to the realization of a small volume and highly integrated chip.
  • the chip further includes: a control circuit, configured to transmit a control signal to the signal transmitting end, so as to control the signal transmitting end to transmit the first test signal, the One of the third test signal and the function signal is output.
  • control circuit is further configured to: output a control signal to the signal receiving end, so as to control the signal receiving end to generate a test signal.
  • control circuit is further configured to: obtain the first test result from the signal receiving end, and control the input end of the multiplexer and the Switching of the connection relationship between the output terminals.
  • the embodiment of the present application provides a device, the device includes a first chip and a second chip, the first chip and the second chip are connected through interconnection pins; the first chip, through the first The signal transmission path transmits a first test signal to the second chip; the second chip generates a first test result based on the first test signal and the test signal generated by the second chip, and the first The test result is used to indicate whether the first signal transmission path fails; the second chip transmits a second test signal to the first chip through the second signal transmission path; the first chip, based on the first Two test signals and the test signal generated by the first chip generate a second test result, and the second test result is used to indicate whether a fault occurs in the second signal transmission path; the first chip, from the The test signal input pin of the first chip receives the third test signal, and transmits the third test signal to the second chip through the third signal transmission path; the second chip transmits the third test signal through the The test signal output pin output in the second chip; wherein, the first test signal and the second test
  • the first chip includes a first built-in self-test circuit and a first scan test circuit;
  • the first built-in self-test circuit includes a first signal transmitting terminal and a first signal receiving end; the first signal transmitting end is used to generate the first test signal; the second signal receiving end is used to generate based on the second test signal and the generated test signal The second test result;
  • the first scan test circuit configured to receive a third test signal from the test signal input pin, and transmit the third test signal to the second chip.
  • the second chip includes a second built-in self-test circuit and a second scan test circuit;
  • the second built-in self-test circuit includes a second signal transmitting terminal and a second signal receiving end; the second signal transmitting end is used to generate the second test signal; the second signal receiving end is used to generate based on the first test signal and the generated test signal The first test result;
  • the second scan test circuit configured to receive a third test signal from the first chip, and output the third test signal through a test signal output pin of the second chip.
  • Fig. 1 is a schematic structural diagram of the test circuit provided in the chip A provided by the embodiment of the present application;
  • Fig. 2 is another structural schematic diagram of the test circuit provided in the chip A provided by the embodiment of the present application;
  • FIG. 3 is a schematic structural diagram of the connection between chip A and chip B provided by the embodiment of the present application;
  • Fig. 4 is another structural schematic diagram of the test circuit provided in the chip A provided by the embodiment of the present application.
  • Fig. 5 is another structural schematic diagram of the test circuit provided in the chip A provided by the embodiment of the present application.
  • Fig. 6 is another structural schematic diagram of the test circuit provided in the chip A provided by the embodiment of the present application.
  • FIG. 7 is another schematic structural diagram of the test circuit provided in the chip A provided by the embodiment of the present application.
  • words such as “exemplary” or “for example” are used as examples, illustrations or illustrations. Any embodiment or design scheme described as “exemplary” or “for example” in the embodiments of the present application shall not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Rather, the use of words such as “exemplary” or “such as” is intended to present related concepts in a concrete manner.
  • “plurality” means two or more. For example, a plurality of outputs refers to two or more outputs.
  • the type of chip described in the embodiment of the present application may include but not limited to one of the following: system on chip (system on chip), memory (Memory), discrete device, application processor (application processor, AP), micro-electromechanical system ( micro-electro-mechanical system, MEMS), microwave radio frequency chip, application specific integrated circuit (application specific integrated circuit, ASIC) and other chips.
  • the above-mentioned application processing chip or application-specific integrated circuit may be a central processing unit (central processing unit, CPU), an image processing unit (graphics processing unit, GPU), an artificial intelligence processor, for example, a neural network processor (network processing unit) in a specific application. unit, NPU), etc.
  • the memory may be cache memory (cache), random access memory (random access memory, RAM), read only memory (read only memory, ROM), or other memory.
  • Discrete devices may include, but are not limited to, eg, field effect transistors, bipolar transistors, integrated operational amplifiers, and the like, for example.
  • the chips described in the embodiments of the present application are all equipped with a test circuit, which is used to test the signal transmission path inside the chip or test the interconnection performance between the chip and the chip to detect whether the signal transmission path is smooth , Whether the signal transmission is delayed and whether the chip pin is broken or not.
  • the test circuit provided in the chip will be described in detail below through the embodiments shown in FIGS. 1 to 7 .
  • FIG. 1 is a schematic structural diagram of a chip A provided in an embodiment of the present application.
  • chip A includes a test circuit.
  • a self-test needs to be performed to detect whether the various signal transmission paths inside the chip A are smooth and whether the signal transmission is delayed.
  • the test circuit described in the embodiment of the present application is used to test the signal transmission path inside the chip A.
  • the test circuit includes a built-in self-test circuit 1 and a scan test circuit 2 .
  • the built-in self-test circuit 1 includes a signal transmitting terminal 10 and a signal receiving terminal 11 .
  • the signal transmitting end 10 is used for transmitting signals, and the signal transmitting end 11 is used for receiving signals.
  • the signal transmitting end 10 includes a plurality of output ends, as shown schematically in FIG. 1 , the signal transmitting end 10 includes four output ends ao1 to ao4;
  • the signal receiving end 11 includes four input ends ai1-ai4. Multiple output terminals of the signal transmitting terminal 10 are correspondingly connected to multiple input terminals of the signal receiving terminal 11 through multiple signal transmission paths S1 - S4 in the chip A.
  • the signal transmitting end 10 may include a linear feedback shift register (LFSR, linear feedback shift register), and the signal receiving end 11 may also include an LFSR.
  • LFSR linear feedback shift register
  • both the signal transmitting end 10 and the signal receiving end 11 may include four-bit LFRS.
  • the signal receiving end 11 also includes a comparison circuit.
  • both the signal transmitting end 10 and the signal receiving end 11 can generate the same pseudo random binary sequence (PRBS, pseudo random binary sequence).
  • PRBS pseudo random binary sequence
  • the signal receiving end 11 compares the four-bit pseudo-random binary sequence received from the signal transmitting end 10 with the four-bit pseudo-random binary sequence generated by itself, and outputs the comparison result, which is used to indicate the signal transmission path S1 ⁇ Whether there is a fault in S4.
  • the failure may include, but not limited to, the following items, for example: short circuit, open circuit, delay and the like.
  • the four-bit pseudo-random binary sequence is 1100
  • the signal transmission path S1 is used to transmit the signal "1”
  • the signal transmission path S2 is used to transmit the signal "1”
  • the signal transmission path S3 is used to transmit the signal "0”.
  • Path S4 is used to transmit the signal "0".
  • the signal output by the signal transmission path S2 is "0", and the signal received by the signal receiving end 11 is "1000".
  • the signal receiving end 11 compares "1000” with "1100", determines that the received four-digit pseudo-random binary sequence is different from the pre-generated four-digit pseudo-random binary sequence, and the second digit is different, thereby outputting the comparison result,
  • the comparison result may be "0100", wherein "0” indicates that the corresponding signal transmission path is unblocked, and "1" indicates that the corresponding signal transmission path is abnormal. It should be noted that the number of output terminals included in the signal transmitting end 10 shown in FIG.
  • the signal transmitting end 10 may include a greater number of output ends (for example, including 15 output ends, 32 output ends, etc.), and likewise, the signal receiving end 11 may include a greater number of input ends (for example, including 15 input terminals, 32 input terminals, etc.), which is determined based on the number of signal transmission paths to be tested in chip A.
  • the multiple signal transmission paths S1-S4 connected to the output end of the signal transmitting end 10 and the input end of the signal receiving end 11 may be direct-connection paths, and no combinatorial logic is set on the transmission paths S1-S4 .
  • the scan test circuit 2 is used to test the signal transmission path provided with combinational logic.
  • the scan test circuit 2 includes at least one test chain, and each test chain in the at least one test chain is formed by a plurality of die wrapper registers (DWR, die wrapper register) connected in series.
  • FIG. 1 schematically shows that the scan test circuit 2 includes a test chain.
  • the plurality of DWRs are connected in series between the test signal input terminal ti and the test signal output terminal to of the chip A.
  • Combination logic 3 is provided, and the combination logic 3 is used to realize various logic functions of the chip A, and the logic functions may include but not limited to: operation and storage.
  • the combinatorial logic 3 may include but not limited to at least one of the following: arithmetic units (such as adders, multipliers, etc.), registers, and logic gates (such as AND gates, OR gates, NOT gates, XOR gates, etc.).
  • the combinatorial logic 3 includes multiple input terminals and multiple output terminals.
  • each input and each output of the combinatorial logic 3 is provided with a DWR.
  • Each DWR includes an input terminal ci1 and an output terminal co1, wherein the input terminal ci1 of DWR121 is connected to the test signal input terminal ti of chip A, and among DWR121 to DWR124, the output terminal co1 of the previous DWR is connected to the input of the subsequent DWR The terminal ci1 is connected, and the output terminal co1 of DWR124 is connected with the test signal output terminal to.
  • DWR121 and DWR122 also include an output terminal co2, the output terminal co2 of DWR121 and DWR122 is respectively connected to the two input terminals of the combinational logic; The two output terminals are connected.
  • each DWR also includes a clock signal input terminal and an enable signal input terminal, which are not shown in the figure. When the scanning test circuit 2 is working, the test signal input terminal ti and the test signal output terminal to are respectively connected to the test equipment.
  • each DWR forms a path from the input terminal ci1 to the output terminal co1, and the test equipment inputs the test signal T1 to the test signal input terminal ti, and the test signal T1 is stored in DWR121 and DWR122 through shift scanning; then, The test signal T1 stored in DWR121 and DWR122 is provided to the combinational logic 1 through the output terminal co2, and the combinational logic 1 processes the test signal T1 to generate a test signal T2, which is respectively stored in DWR123 and DWR124 through the input terminal ci2 of DWR123 and DWR124 ; Then, each DWR forms a path from the input terminal ci1 to the output terminal co1, and the test signal T2 stored in DWR123 and DWR124 is shifted and output to the test equipment through the test signal output terminal to.
  • the test equipment determines whether the signal transmission path provided with the combinational logic in the chip A is faulty or not based on the test signal T2 and the expected output signal.
  • the abnormality may include, but is not limited to, an open circuit, a short circuit, or a time delay, for example.
  • the test circuit of the chip in order to improve the test efficiency of the chip, the test circuit of the chip usually only adopts a circuit structure of a built-in self-test circuit to test the signal transmission paths inside the chip or between chips.
  • the signal output from the signal transmitting end of the built-in self-test circuit will be changed through the combinatorial logic, thereby disturbing the test result.
  • the combinational logic in the signal transmission path is an inverter
  • the "1100" output by the signal transmitter becomes "0011” through the inverter
  • the signal received by the signal receiver becomes "0011"
  • the test circuit shown in the embodiment of the present application adopts the built-in self-test circuit for testing the signal transmission path without combinational logic in the chip by setting the built-in self-test circuit and the scanning test circuit.
  • the signal transmission path is tested by using a scanning test circuit, thereby improving the test efficiency and test accuracy of the test circuit.
  • the chip A further includes a plurality of pins, which may also be referred to as interconnection pins or pads (PAD).
  • the pins of chip A are used to interconnect with other chips for signal interaction. It can be understood that the number of pins included in the chip A in the figure is only schematic, more pins may be included in an actual product, and the number of pins of the chip A is set based on the needs of the scene.
  • the test circuit 100 can also be connected to each pin of the chip A. After chip A is interconnected with other chips through each pin, the test circuit 100 can also test the signal transmission path between chip A and other chips, that is, through each pin of chip A, test the signal transmission path between chip A and other chips.
  • FIG. 2 is another schematic structural diagram of chip A provided by the embodiment of the present application.
  • FIG. 2 schematically shows that chip A includes eight pins of pins a1 , a2 , a3 , a4 , a5 , a6 , a7 and a8 .
  • Some pins in chip A can be signal output pins, which are used to output signals to other chips; some pins can be signal input pins, which are used to input signals from other chips; some pins can be bidirectional signal transmission Pins can either output signals to other chips or input signals from other chips.
  • the pins a1 to a3 and a8 are signal output pins
  • the pins a5 to a7 are signal input pins
  • the pin a4 is a bidirectional pin.
  • multiple output terminals of the signal transmitting terminal 10 are also connected to pins a1-pin a4 through signal transmission paths
  • multiple input terminals of signal receiving terminal 11 are also respectively connected to pins a4-pins through signal transmission paths.
  • Pin A7 is connected.
  • the signal transmission path for self-testing chip A is at least partly the same as the signal transmission path for interconnection testing between chip A and other chips, for example, the signal transmission path for self-testing chip A is the same as for chip A.
  • the signal transmission path for interconnection testing between chip A and other chips adopts the signal transmission path S4. Since the output terminal ao4 of the signal transmitting terminal 10 is connected to the input terminal ai4 of the signal receiving terminal 11, and the output terminal ao4 of the signal transmitting terminal 10 and the input terminal ai4 of the signal receiving terminal 11 are both connected to the pin a4, in order to prevent signal backflow,
  • a follower F is provided between the output terminal ao4 of the signal transmitting terminal 10 and the pin a4, and between the pin a4 and the input terminal ai4 of the signal receiving terminal 11, as shown in FIG. 2 .
  • the signal backflow mentioned here refers to that the signal input from the pin a4 flows into the signal transmitting terminal 10 through the input terminal ao4, and interferes with the circuit of the signal transmitting terminal 10 .
  • combinatorial logic 1 is provided on the signal transmission path connected to pin a8 in chip A. Therefore, the signal output end of the scan test circuit 2 (that is, the output end co1 of the DWR124) is connected to the pin a8.
  • the chips interconnected with chip A may include a test circuit with the same structure as chip A.
  • chip B includes built-in self-test circuit 4, scan test circuit 5, pin b1, b2, b3, b4, b5, b6, b7 and b8 eight pins (these eight pins can also be called for interconnection pins).
  • the pins b1 to b3 and b8 are signal input pins
  • the pins b5 to b7 are signal output pins
  • the pin b4 is a bidirectional pin.
  • the built-in self-test circuit 4 includes a signal transmitting end 20 and a signal receiving end 21.
  • the signal transmitting end 20 is connected to pins b4-pin b7 for outputting test signals to pins b4-pin b7.
  • the signal receiving end 21 is connected to pins b4-pin b7.
  • the pins b1-b4 are connected to receive test signals from the pins b1-b4.
  • the working principle of the built-in self-test circuit 4 is the same as that of the built-in self-test circuit 1 , for details, please refer to related descriptions, and will not repeat them here.
  • the scan test circuit 5 is arranged between the pin b8 and the test signal output terminal to2.
  • the scan test circuit 5 includes DWR125-DWR128.
  • the structure and working principle of the scan test circuit 5 are the same as those of the scan test circuit 2. For details, refer to the relevant description of the scan test circuit 2.
  • pins a1 to a8 of chip A are respectively connected to pins b1 to b8 of chip B correspondingly.
  • the signal transmitting end 10 and the signal receiving end 21 When testing the interconnection performance between chip A and chip B, the signal transmitting end 10 and the signal receiving end 21 generate the same pseudo-random binary sequence; the signal transmitting end 10 passes the generated pseudo-random binary sequence through pins a1-a4 And the pins b1-b4 are provided to the signal receiving end 21, and the signal receiving end 21 compares the pseudo-random binary sequence generated by itself with the pseudo-random code received through the pins b1-b4, and determines the pins based on the comparison result Whether the signal transmission path between a1 ⁇ a4 and pins b1 ⁇ b4 is faulty.
  • the signal transmitting end 20 and the signal receiving end 11 generate the same pseudo-random binary sequence; the signal transmitting end 20 provides the generated pseudo-random binary sequence to the signal receiving end 11 through pins b4-b7 and pins a4-a7, The signal receiving end 11 compares the pseudo-random binary sequence generated by itself with the pseudo-random code received through the pins a4-a7, and based on the comparison result, determines the signal between the pins a4-a7 and the pins b4-b7 Whether the transmission path is faulty.
  • the principle of determining the interconnection performance between chip A and chip B based on the pseudo-random binary sequence is the same as the work of determining whether each signal transmission path is abnormal based on the pseudo-random binary sequence when testing the signal transmission path inside chip A
  • the principle is the same, for details, refer to the relevant description of determining whether each signal transmission path is abnormal based on a pseudo-random binary sequence when testing the signal transmission path inside the chip A, and will not repeat it here.
  • the test equipment when testing the interconnection performance between chip A and chip B, the test equipment is connected to the test signal input terminal ti1 of chip A and the test signal output terminal to2 of chip B.
  • the test device is used to input a test signal T3 to the scan test circuit 2 through the test signal input terminal ti1.
  • the scan test circuit 2 processes the test signal T3 to generate a test signal T4 (refer to the description of the working principle of the test circuit 2 in FIG. 1 for the specific processing method), and outputs it to the scan test circuit 2 through the interface a8 and b8.
  • the scan test circuit 2 can further process the test signal T4 (for the specific processing method, refer to the description of the working principle of the test circuit 2 in FIG.
  • test signal T5 When the test signal T5 is the same as the expected signal, it means that there is no fault in the signal transmission path through the pin a8 and pin b8; when the test signal T5 is different from the expected signal, It means that there is a fault in the signal transmission path passing through the pin a8 and the pin b8.
  • the test circuit in chip A the working principle of the internal transmission path test of chip A, and the working principle of testing after interconnection with other chips are introduced.
  • the signal transmitting end 10 , the signal receiving end 11 in the chip A shown, and the DWR in the scan test circuit 2 are all independent registers.
  • the signal transmitting end 10, the signal receiving end 11 in the built-in self-test circuit 1, and the DWR in the scan test circuit 2 can all multiplex the function registers in the chip A (that is, A register used for signal storage and transmission after chip A is tested).
  • the LSFR in the signal transmitting end 10 and the DWR in the scan test circuit 2 can share the same register, and the LSFR in the signal receiving end 11 and the DWR in the scan test circuit 2 can also share the same register.
  • the function register in the multiplex chip A of the signal transmitting end 10, the signal receiving end 11 and the DWR below, and the signal transmitting end 10 and the DWR share the same register as an example, in conjunction with the structure of the test circuit 100 shown in Figure 4, this The test circuit 100 provided in the embodiment of the application is described in more detail.
  • the signal transmitting end 10 in the test circuit includes multi-stage cascaded registers SF01 , register SF02 , register SF03 and register SF04 .
  • Each of the plurality of registers includes an input terminal D, an input terminal SI, an enable terminal SE and an output terminal Q.
  • register SF01, register SF02, register SF03 and register SF04 are used to output function signals; in addition, register SF01, register SF02, register SF03 and register SF04 are also used to output pseudo-random binary sequence; further, register SF01, register SF02, Register SF03 and register SF04 are also used to output test signals.
  • a multiplexer is set between every two registers and between the first-level register and the signal input terminal, and the multiplexer is used to selectively combine the functional signal, random signal and test signal One of is supplied to the register and output from the output Q of the register.
  • the random signal is used to form a pseudo-random binary sequence
  • the test signal is used to perform a scan test.
  • FIG. 4 schematically shows the situation that two data selectors, a data selector D1 and a data selector D2, are arranged between every two registers and between the first-level register and the signal input terminal.
  • the two data selectors are both alternative data selectors.
  • each data selector D1 is respectively connected to the initial signal input ends s1-s4 of the signal transmitting end 10 for inputting the initial signal; except for the first-stage data selector D1, other
  • the second input end of the data selector D1 is respectively connected with the output end Q of the previous stage register; the output end of each data selector D1 is respectively connected with the first input end of the data selector D2; the output end of each data selector D1
  • the control terminals are all connected to the control signal input terminal c2 of the signal transmitting terminal 10; the second input terminal of each data selector D2 is used to input the function signal Func; the output terminal of each data selector D2 is connected to the input of the subsequent stage register
  • the terminal D is connected; the control terminal of each data selector D2 is connected with the control signal input terminal c0.
  • the test circuit 100 further includes an exclusive OR gate X1, which is used to perform an exclusive OR operation on the signals output by two registers in the four cascaded registers, and then provide them to the input terminal D of the first-stage register.
  • an exclusive OR gate X1 which is used to perform an exclusive OR operation on the signals output by two registers in the four cascaded registers, and then provide them to the input terminal D of the first-stage register.
  • the two input ends of the XOR gate X1 are respectively connected to the output Q of the register SF03 and the output Q of the register SF04, and the input end of the XOR gate X1 is connected to the second input of the first-stage data selector D1 end connection.
  • the two input terminals of the exclusive OR gate X1 are respectively connected to the output terminals of the third-level and fourth-level registers.
  • the two input terminals of the exclusive OR gate X1 may also be connected to the output terminals of the second-level and third-level registers, which is not specifically limited in this embodiment of the present application.
  • the input terminal SI of the register SF01 is connected to the test signal input terminal ti of the chip A, and the input terminal SI of each register in the registers SF02 to SF04 is connected to the output terminal Q of the previous register;
  • the enable terminal SE of a register is connected to the control signal input terminal c1 of the signal transmitting terminal 10 .
  • the output terminals Q of the registers SF01 - SF04 are connected to the signal output terminals ao1 - ao4 of the signal transmitting terminal 10 respectively.
  • the output terminals Q of the register SF01 and the register SF02 are also respectively connected to the input terminals of the combinational logic 1 shown in Figure 1; the second input terminals of the third-level data selector D2 and the fourth-level data selector D2 are also respectively It is connected with the output end of the combinational logic 3 shown in FIG. 1 .
  • the combinatorial logic 3 and the connection between each register and the combinatorial logic 3 are not shown in FIG. 4 .
  • the number of bits of the pseudo-random binary sequence to be output by the signal transmitting end 10 is equal to the number of cascaded registers.
  • a four-bit register is provided for outputting a four-bit pseudo-random binary sequence.
  • the signal transmitting end 10 can output more pseudo-random binary sequences, such as fifteen bits or thirty bits, etc., and the signal transmitting end 10 can set a larger number of registers, such as fifteen cascaded registers or thirty cascaded registers, etc.
  • the two input terminals of the XOR gate X1 can be respectively connected to the output terminals of the 28th-level and 30th-level registers.
  • FIG. 4 schematically shows that the number of registers included in the LSFR is equal to the number of DWRs included in the scan test circuit, and that the LSFR and the DWR share the same registers.
  • the scan test circuit may include a larger number of DWRs, for example ten, and the ten DWRs are cascaded into a scan test chain, and four DWRs are duplicated by the LSFR in the built-in self-test circuit. use.
  • the test circuit also includes a signal receiving end 11 .
  • the signal receiving end 11 includes an LSFR circuit 110 and a comparison circuit 111 .
  • the LSFR circuit 110 includes multi-level cascaded registers SF05, SF06, SF07, and SF08.
  • the structures of registers SF05-register SF08 are the same as those of registers SF01-register SF04, and will not be repeated here. Similar to the circuit of the signal transmitting end 10, the registers SF05-SF08 are not only used for outputting the pseudo-random binary sequence, but also used for outputting the function signal Func.
  • registers SF05 to SF08 do not output test signals.
  • a selector D1 is provided between every two registers and between the first-level register and the signal input terminal.
  • the structure of the selector D1 and the signals input by each input end of the selector D1 are the same as those of the selector D1 included in the signal transmitting end 10 , for details, refer to related descriptions.
  • the circuit of the signal receiving end 11 does not set the register D2
  • the input terminal D in the register SF05 ⁇ register SF08 is used to input the function signal Func
  • the input terminal SI in the register SF05 ⁇ register SF08 are respectively coupled to the output terminals of each selector D1.
  • the control terminals of each selector D1 are connected to the control signal input terminal c3 of the signal receiving terminal 11 .
  • the LSFR circuit 110 also includes an exclusive OR gate x2, the two input terminals of the exclusive OR gate x2 are respectively connected to the output terminal Q of the register SF07 and the output terminal Q of the register SF08, and the input terminal of the exclusive OR gate x2 is connected to the first stage The second input terminal of the data selector D1 is connected.
  • the enable terminal SE of each register is connected to the control signal input terminal c4 of the signal receiving terminal 11 . Therefore, the registers SF05 to SF08 selectively provide the function signal Func input from the input terminal D or the random signal input from the input terminal SI to the output terminal Q based on the enable signal input from the enable terminal SE, so as to output from the output terminal Q .
  • the comparison circuit 111 of the signal receiving end 11 of the chip A includes a plurality of registers, a plurality of XOR gates X3 and a plurality of XOR gates X4, which are schematically shown in FIG. 4 Register SF09-register SF12, four XOR gates X3 and four XOR gates X4.
  • each of the registers SF09-SF12 includes an input terminal D, an output terminal Q and an enable terminal SE.
  • the first input terminals of the multiple XOR gates X3 are respectively connected to the signal input terminals ai1-ai4 of the signal receiving terminal 11, and the second input terminals of the XOR gate X3 are respectively connected to the output terminals Q of the registers SF05-register SF08.
  • the output terminals of each XOR gate X3 are respectively connected to the second input terminals of XOR gate X4; the first input terminals of multiple XOR gates X4 are respectively connected to the output terminals Q of register SF09-register SF12 correspondingly, and multiple XOR gates
  • the output terminals of the gate X4 are respectively connected to the input terminals D of the registers SF09 - SF012.
  • the output terminals Q of the registers SF09 - SF12 are respectively connected with the output terminals o1 - o4 of the signal receiving terminal 11 .
  • the output terminals Q of the registers SF01 to SF04 are respectively combined with a plurality of exclusive OR
  • the first input end of the gate X3 is correspondingly connected, so as to realize the test of the internal signal transmission path of the chip A.
  • the output terminals Q of the registers SF01-register SF04 can also be respectively connected to the pins a1-a4 of the chip A through the signal output terminals ao1-ao4 of the signal transmitting terminal 10, and the multiple XOR gates x3
  • the first input terminals are respectively connected to the pins a4-a7 of the chip A through the signal input terminals ai1-ai4 of the signal receiving terminal 11, as shown in Figure 5, so as to realize the test of the interconnection performance between the chip A and other chips .
  • the rest of the components in FIG. 5 and the connections between the components are the same as the components shown in FIG. 4 .
  • chip A can also A plurality of selectors D3 and a plurality of selectors D4 are provided, the signal output ends ao1-ao4 are connected to the input ends of the plurality of selectors D3, and the first output ends of each selector D3 are respectively connected to the first input ends of each selector D4 Correspondingly connected, the second output ends of each selector D3 are respectively connected to the interfaces a1-a4; the second input ends of each selector D4 are respectively connected to the interfaces a4-a7, and the output ends of each selector D4 are respectively connected to the signal input Terminals ai1-ai4 are connected.
  • the selector D3 When testing the internal signal transmission path of chip A, the selector D3 forms the path from the input terminal to the first output terminal, the selector D4 forms the path from the first input terminal to the output terminal, and the signals output by registers SF01 to SF04 are provided to different The first input terminal of the OR gate X3; when the signal between the chip A and other chips is tested, the selector D3 forms a path from the input terminal to the second output terminal, and the selector D4 forms a path from the second input terminal to the output terminal, The signals output by the registers SF01 - SF04 are provided to the interfaces a1 - a4 respectively, and the signals input by the interfaces a4 - a7 are respectively provided to the first input ends of the different OR gates X3.
  • the LSFR 110 multiplexes the function register in the chip A, and the function register is not multiplexed by the scan test circuit.
  • the function registers multiplexed by the LSFR110 in the signal receiving end 11 are also multiplexed by the DWR in the scan test circuit.
  • the LSFR110 is the same as the circuit of the signal transmitting end 10. Refer to A description of the circuitry in terminal 10.
  • the structure of the signal transmitting end 20 can be the same as that of the signal transmitting end 10 in the chip A; the signal receiving end 21 in the chip B can also include LSFR and comparison circuit , the circuit structure of LSFR can be identical with the structure of the signal transmitting end 10 in the chip A, also can be identical with the LSFR110 in the signal receiving end 11 in the chip A, the comparison circuit in the signal receiving end 21 in the chip B can be with the chip
  • the comparison circuit 111 in A is the same, and will not be repeated here.
  • the chip A described in the embodiment of the present application may include multiple working modes. Taking the circuit structure shown in FIG. 4 as an example, the various working modes of the chip A, the working principle of the test circuit in each working mode, and the signal transmission path are described in more detail below.
  • Chip A can work in the first working mode, that is, the built-in self-test mode of chip A.
  • the data selector D1 forms a path from the first input end to the output end based on the control signal input by the control signal input end c2
  • the data selector D2 forms a path from the first input terminal to the output terminal based on the control signal input from the control signal input terminal c0
  • the registers SF01 to SF04 form a channel from the input terminal D to the output terminal Q based on the enable signal input from the enable terminal SE
  • the initial signals input by the initial signal input terminals s1 - s4 are provided to the registers respectively through the data selector D1 , the data selector D2 and the input terminal D of each register.
  • the initial signals input to the registers SF01-SF04 can be different signals, which are determined based on the number of bits of the PRBS to be generated and the preset sequence code generation rules.
  • the initial signal input to each register is 1 bit.
  • the initial signal input to the registers SF01 to SF04 is "1001". That is to say, the binary pseudo-random code sequence output by the registers SF01-SF04 is "1001".
  • the data selector D1 forms a path from the second input end to the output end based on the control signal input by the control signal input end c2, and keeps the path states of the remaining data selectors D2 and registers unchanged, and the XOR gate will
  • the signals output by the output terminal Q of the register SF03 and the register SF04 are provided to the second input terminal of the first-stage data selector D1 after the XOR operation, and the signal after the XOR operation is provided by the data selector D1 and the data selector D2 to register SF01; at the same time, the signal stored in the previous state on register SF01 is supplied to register SF02, the signal stored in the previous state on register SF02 is supplied to register SF03, and the signal stored in the previous state on register SF03 is supplied to register SF04.
  • the binary pseudo-random code sequence output by the registers SF01-SF04 in the second clock cycle is "1100".
  • the registers SF01-SF04 output a four-bit binary pseudo-random code sequence in each clock cycle.
  • the data selector D1 forms a path from the first input end to the output end based on the control signal input by the control signal input end c4, and the register SF05-SF08 form a path from the input terminal SI to the output terminal Q based on the enable signal input from the enable terminal SE.
  • the initial signal is respectively provided to the output terminal Q of the registers SF05-SF08 through the data selector D1 and the input terminal SI of the registers SF05-SF08. It should be noted that the initial signals input to the registers SF05-SF08 are the same as the initial signals input to the registers SF01-SF04.
  • the initial signals input to the registers SF01-SF04 are respectively "1001"
  • the initial signals input to the registers SF05-SF08 are respectively "1001”.
  • the data selector D1 forms a path from the second input terminal to the output terminal based on the control signal input by the control signal input terminal c4, based on the same working principle as the signal transmitting terminal of chip A in the second clock period
  • the register SF05-SF08 output a four-digit binary pseudo-random code sequence, which is the same as the four-digit binary pseudo-random code sequence output by the registers SF01-SF04 in the second clock cycle.
  • registers SF05 ⁇ SF08 output four clock cycles in each clock cycle bit binary pseudorandom code sequence.
  • the signals output by the output terminals Q of the registers SF01-SF04 and the signals output by the output terminals Q of the registers SF05-SF08 are correspondingly provided to the different OR gates x3, through the different OR gates x3,
  • the OR gate x3 performs an XOR operation and supplies it to the XOR gate x4, and the XOR gate x4 performs a second XOR operation on the signal provided by the XOR gate x3 and the signal output by the output terminal Q of the registers SF09 ⁇ SF12, and then provides them to the
  • the input terminal D of the registers SF09-SF12 is output through the output terminal Q of the registers SF09-SF12. Therefore, based on the results output by the output terminals Q of the registers SF09 - SF12 , it can be determined whether the signal transmission path inside the chip A is faulty.
  • the above-mentioned first working mode of chip A is the case of testing the internal transmission path of chip A.
  • each component in the test circuit will The working state and working principle are the same as the working state and working principle of testing the internal transmission path of chip A.
  • the difference is that the initial signal input to the registers SF01 ⁇ SF04 in the first clock cycle is the same as the initial signal input by the receiving end of chip B.
  • the signals are the same; the initial signals input to the registers SF05-SF08 in the last first clock cycle are the same as the initial signals input by the transmitter of chip B.
  • Chip A can also work in the second working mode, that is, the scan test mode of chip A.
  • the signal transmitting terminal 10 of the chip A works, and the signal receiving terminal 11 stops working.
  • the data selector D1 and the data selector D2 are turned off.
  • the registers SF01-SF04 form a path from the input terminal SI to the output terminal Q based on the enable signal input from the enable terminal SE, and the test signal T1 input from the test signal input terminal ti is provided to the register SF01 through the input terminal SI of the register SF01.
  • the register SF01 provides the test signal T1 stored in the previous clock cycle to the register SF02 through the input terminal SI of the register SF02, and the test signal T2 is provided to the register SF01 through the input terminal SI of the register SF01.
  • the register SF02 provides the test signal T1 and the register SF01 provides the test signal T2 to the combinatorial logic 1 shown in Figure 1, and after the processing of the combinatorial logic 1, the test signal T3 and the test signal T4 are generated and provided to the register SF03 and the register SF04 respectively .
  • the test signal T3 and the test signal T4 are output through the output terminal Q of the register SF04.
  • the external test equipment is connected to the input terminal SI of the register SF01 and the output terminal Q of the register SF04, so as to input the test signal T1 and the test signal T2 to the scan test chain formed by the register SF01 ⁇ register SF04, and output the test signal from the scan test chain.
  • Chip A can also work in the third working mode, which is the functional signal transmission mode of chip A.
  • the third working mode at the signal transmitting end 10 of the chip A, the data selector D2 forms a path from the second input end to the output end Q based on the control signal input from the control signal input end c0, and the data selector D1 is turned off,
  • the registers SF01-SF04 form a signal transmission path from the input terminal D to the output terminal Q based on the enable signal input from the enable terminal SE.
  • the data selector D1 is turned off, and the registers SF05-SF08 form a signal transmission path from the input end D to the output end Q based on the enable signal input from the enable end SE. Therefore, each function signal Func is input through the input terminal D of each register and output through the output terminal Q.
  • the test circuit in the chip A provided by the embodiment of the present application and the working principle of the test circuit are introduced above through the embodiments shown in FIGS. 1-5 .
  • the signal A described in the embodiment of the present application also includes more pins, and the more pins are redundant pins, It is used to migrate the signal transmission path of the failed pin to the signal transmission path formed by the redundant pin when a pin among the above-mentioned pins a1 ⁇ pin a7 or the transmission path including the pin fails , so as to repair the faulty pin or signal transmission path.
  • the test circuit with repair function will be introduced in more detail below in combination with FIG. 6 . In Fig.
  • the test circuit in the chip A includes a multiplexer 13 and a pin a9 in addition to a signal transmitting terminal 10, a signal receiving terminal 11, pins a1-pin a8, and the multiplexer 13
  • the four output terminals of the multiplexer 13 are respectively connected to the four input terminals ai1-ai4 of the signal receiving terminal 11, and the five input terminals of the multiplexer 13 are respectively connected to the pin a4-pin a7 and the pin a9.
  • the multiplexer 13 connects the signal input ends ai1-ai4 to the interfaces a4-a7 correspondingly based on the control of the control signal.
  • the multiplexer 13 switches the connection between the signal input terminal ai1 and the pin a5 to the signal input terminal ai1 and the pin ai1.
  • the pin a9 is connected, so that the signal transmission path where the faulty pin a5 is located is discarded, and the signal transmission path between the signal input terminal ai1 and the pin a9 is used for signal transmission.
  • the number of data selectors 13 and the number of redundant pins shown in FIG. number so that more abnormal signal transmission paths in chip A can be switched.
  • the signal transmitting terminal 10 in the chip A may also be connected to redundant pins on the chip A through a multiplexer, so that when the signal transmission path between the signal transmitting terminal 10 and each pin of the chip A fails, It is also possible to switch a failed pin to a redundant pin.
  • a multiplexer so that when the signal transmission path between the signal transmitting terminal 10 and each pin of the chip A fails, It is also possible to switch a failed pin to a redundant pin.
  • by setting redundant pins when the signal transmission path fails, it can be directly switched to the signal transmission path where the redundant pins are located, without additional manual repair, and the protection against abnormal signal transmission paths can be improved. Repair efficiency.
  • the chip 100 further includes a control circuit 14 , as shown in FIG. 7 .
  • the control circuit 14 described in the embodiment of the present application can be an integrated controller.
  • the control circuit 14 can be various digital logic devices or circuits, including but not limited to: microcontrollers, microprocessors or digital signal Processor (DSP, digital signal processor), etc.
  • the control circuit 14 can output control signals to the signal transmitting end 10 and the signal receiving end 11 as shown in any embodiment of FIGS.
  • the control circuit 14 is also used to receive signals from the signal receiving end 11, and determine whether the signal transmission path inside chip A or the signal transmission path between chip A and other chips is abnormal based on the received signal.
  • control circuit 14 includes signal output terminals C1 - C14 and signal input terminals C15 - C18 .
  • the signal output terminals C1-C3 are connected to the control signal input terminals c0-c2 of the signal transmitting terminal 10
  • the signal output terminals C4-C8 are connected to the initial signal input terminals s1-s4 of the signal transmitting terminal 10
  • the signal output terminal C8 is connected to multiple
  • the control terminal of the channel selector 13 is connected
  • the signal output terminals C9-C10 are connected with the control signal input terminals c3-c4 of the signal receiving terminal 11
  • the signal output terminals C11-C14 are connected with the initial signal input terminals s5-s8 of the signal receiving terminal 11
  • the signal input terminals C15 - C18 of the control circuit 14 are connected to the output terminals o1 - o4 of the signal receiving terminal 11 .
  • control circuit 14 can control the test circuit to work in the built-in self-test mode.
  • the control circuit 14 inputs the control signal CL1 to the control signal input terminal c0, and the control signal CL1 is used to instruct the selector D2 shown in FIG.
  • the control signal input terminal c1 inputs the control signal CL2, and the control signal CL2 is used to instruct the registers SF01-SF04 as shown in Figure 5 to form a path from the input terminal D to the output terminal Q;
  • the control circuit 14 inputs the control signal to the control signal input terminal c2 CL3, the control signal CL3 is used to instruct the selector D1 in the signal transmitting terminal 10 to form a path from the first input terminal to the output terminal;
  • the control circuit 14 inputs the control signal CL4 to the control signal input terminal c3, and the control signal CL4 is used to indicate the register SF05-SF08 form the path from the input terminal SI to the output terminal Q;
  • the control circuit 14 inputs the control signal CL5 to the control signal input terminal c4, and the control signal CL5 is used to instruct the selector D1 in the signal receiving terminal 11 to form the first input terminal to the output terminal Q.
  • control circuit 14 inputs the initial signal to the initial signal input terminal s1 ⁇ s4 of the signal transmitting terminal 10, and inputs the initial signal to the initial signal input terminal s5 ⁇ s8 of the signal receiving terminal 11; the control circuit 14 inputs the initial signal to the multiplexer 13
  • the control terminal of the control terminal inputs a control signal CL6, and the control signal CL6 is used to instruct the multiplexer 13 to form a path from the pins a7-a9 to the signal input terminals ai1-ai4 in the signal receiving terminal 11.
  • the signal transmitting end 10 Based on the control of the above-mentioned control signal, the signal transmitting end 10 generates a binary pseudo-random sequence and outputs it through the pins a1-a4; the signal receiving end 11 generates a binary pseudo-random sequence based on the control of the above-mentioned control signal.
  • the signal receiving end 11 also It is used to compare the generated binary pseudo-random sequence with the binary pseudo-random sequence received from the pins a4-a7, and the generated comparison result is provided to the control circuit 14 through the output terminals o1-o4.
  • the control circuit 14 inputs the control signal CL7 to the control signal input terminal c2, and the control signal CL7 is used to instruct the selector D1 in the signal transmitting terminal 10 to form a path from the second input terminal to the output terminal;
  • the control signal input terminal c4 inputs a control signal CL8, and the control signal CL8 is used to instruct the selector D1 in the signal receiving terminal 11 to form a path from the second input terminal to the output terminal, and keep the signals input by other signal input terminals unchanged.
  • the signals input by each signal input end remain unchanged.
  • the signal transmitting end 10 and the signal receiving end 11 can continuously generate a binary pseudo-random sequence, and the signal transmitting end 10 outputs the binary pseudo-random sequence generated in each cycle through pins a1-a4; the signal receiving end 11 outputs the generated binary pseudo-random sequence
  • the random sequence is compared with the binary pseudo-random sequence received from the pins a4-a7, and the generated comparison result is provided to the control circuit 14 through the output terminals o1-o4. Further, the control circuit 14 detects whether each signal transmission path fails based on the signals received from the output terminals o1-o4. For example, "0" represents normal, and "1" represents abnormality.
  • the signals received by the control circuit 14 from the output terminals o1-o4 are all "0000", It means that the signal transmission path through the pins a4-a7 is normal; if there is at least one clock cycle in the above-mentioned first to Nth clock cycles, there is a bit in the signal received by the control circuit 14 from the output terminals o1-o4 is "1", for example, in a certain clock cycle, the signal received by the control circuit 14 is "1000", then the signal transmission path corresponding to the first bit fails, that is, the signal input terminal shown in Figure 7 The signal transmission path from ai1 to pin a5 is faulty.
  • control circuit 14 controls the multiplexer 13 to connect the signal input terminal ai1 to the pin a9, and then adopts the same control signal from the first to the Nth clock cycle as described above to continue to control the connections between chip A and the rest of the chips.
  • the signal transmission path is detected.
  • the control circuit 14 can control the test circuit to work in the scan test mode.
  • the control circuit 14 inputs a control signal CL9 to the control signal input terminal c0, the control signal input terminal c2, the control signal input terminal c3, and the control signal input terminal c4.
  • the control signal CL9 is used to indicate the selector D1, the selector D2 and the registers SF05- SF08 is disabled;
  • the control circuit 14 inputs a control signal CL10 to the control signal input terminal c1, and the control signal CL10 is used to instruct the registers SF01-SF04 shown in FIG. 5 to form a path from the input terminal SI to the output terminal Q. Therefore, the registers SF01-SF04 form a scan test chain based on the control of the above-mentioned control signal to perform a scan test on the signal transmission path provided with combinational logic.
  • the control circuit 14 can also control the chip A to work in the working signal transmission mode.
  • the control circuit 14 inputs the control signal CL11 to the control signal input terminal c0, and the control signal CL11 is used to instruct the selector D2 shown in FIG. 5 to form a path from the second input terminal to the output terminal; the control circuit 14 inputs to the control signal input terminal c1
  • the control signal CL2, the control signal CL2 is used to instruct the registers SF01-SF04 shown in Figure 5 to form a path from the input terminal D to the output terminal Q;
  • the control circuit 14 inputs the control signal CL12 to the control signal input terminal c3, and the control signal CL12 It is used to instruct registers SF05 ⁇ SF08 to form a path from input terminal D to output terminal Q. Therefore, each function signal Func is input through the input terminal D of each register and output through the output terminal Q.
  • the embodiment of the present application also provides a device, which may include but not limited to: a radio frequency device, a power management device, or a terminal device.
  • the terminal device specifically may include but not limited to: portable computers (such as mobile phones), notebook computers, wearable electronic devices (such as smart watches), tablet computers, augmented reality (augmented reality, AR) or virtual reality (virtual reality, VR) equipment etc.
  • the device described in the embodiment of the present application may include the chip A as described in any embodiment shown in FIG. 1 to FIG. 7 .
  • the device described in the embodiment of the present application may further include a chip B, and the chip B is connected to the chip A for signal exchange.

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Abstract

本申请实施例提供了一种芯片和装置，该芯片包括测试电路，测试电路用于：通过第一信号传输通路，向第一互联引脚传输第一测试信号；通过第二信号传输通路，从第二互联引脚接收第二测试信号，基于第二测试信号以及所生成的测试信号，生成用于指示第二信号传输通路是否发生故障的第一测试结果；从测试信号输入引脚接收第三测试信号，将第三测试信号通过第三信号传输通路传输至第三互联引脚，其中，第一测试信号和第二测试信号为内建自测试BIST信号，第一信号传输通路和第二信号传输通路中未设置组合逻辑，第三信号传输通路中设置有组合逻辑，本申请实施例提供的芯片，可以提高对芯片中各逻辑单元进行测试的测试效率。

Description

芯片和装置 技术领域
本申请实施例涉及电路技术领域，尤其涉及一种芯片和装置。
背景技术
随着电子技术的发展，集成电路的功能显著的提升，大规模逻辑电路等被广泛应用。当前大规模逻辑电路中，为了实现更多以及更复杂的逻辑功能，通常在一个封装体中封装多个芯片，该多个芯片之间通过导电线路连接，以进行信号交流。
为了检测多个芯片之间的连通性能，需要对各芯片之间的连通性能进行测试。伴随着芯片高集成度的发展，为了降低芯片连通性能测试的复杂度，业界提出采用内建自测试(BIST，built-in self-test)的测试方法对芯片之间的互连通路进行测试。然而，当芯片的连通通路上设置有组合逻辑电路时，BIST电路生成的逻辑电平经过组合逻辑后会被改变，影响测试结果。由此，如何提高芯片间连通性能测试的准确性成为需要解决的问题。
发明内容
本申请提供的芯片和装置，可以提高芯片间连通性能测试的准确性。
为达到上述目的，本申请采用如下技术方案：
第一方面，本申请实施例提供一种芯片，该芯片包括：包括测试电路、多条信号传输通路、测试信号输入引脚和多个互联引脚，所述芯片为第一芯片，所述多个互联引脚用于与第二芯片连接；所述测试电路用于：通过所述多条信号传输通路中的第一信号传输通路，向所述多个互联引脚中的第一互联引脚传输第一测试信号，以使所述第二芯片基于所述第一测试信号对所述第一信号传输通路进行检测；通过所述多条信号传输通路中的第二信号传输通路，从所述多个互联引脚中的第二互联引脚接收第二测试信号，基于所述第二测试信号以及所述测试电路所生成的测试信号，生成第一测试结果，所述第一测试结果用于指示所述第二信号传输通路是否发生故障；从所述测试信号输入引脚接收第三测试信号，将所述第三测试信号通过所述多条信号传输通路中的第三信号传输通路传输至所述多个互联引脚中的第三互联引脚；其中，所述第一测试信号和所述第二测试信号为内建自测试BIST信号，所述第一信号传输通路和所述第二信号传输通路中未设置组合逻辑，所述第三信号传输通路中设置有组合逻辑。
本申请实施例所示的测试电路，可以针对芯片中未设置组合逻辑的信号传输通路，通过内建自测试信号进行测试，针对芯片中设置有组合逻辑的信号传输通路，通过扫描测试信号进行测试，从而提高测试电路的测试效率以及测试准确率。
本申请实施例提供的测试电路，还可以对芯片内部、各单元模块之间进行信号传输的信号传输通路进行测试。
在一种可能的实现方式中，所述测试电路还用于：通过所述多条信号传输通路中的第 四信号传输通路传输第四测试信号；基于经所述第四传输通路传输后的第四测试信号，生成第二测试结果，所述第二测试结果用于指示所述第四信号传输通路是否发生故障；所述第四信号传输通路中未设置组合逻辑，所述第四测试信号为BIST信号。
本申请实施例中，所述第四信号传输通路是芯片内部各逻辑单元之间用于传输信号的通路。对第四信号传输通路的检测可以发生在对第一信号传输通路～第三信号传输通路的检测之前，从而可以保证芯片内部各信号传输通路无故障。此外，通过采用BIST信号对芯片内部中、未设置组合逻辑的信号传输通路进行测试，可以提高芯片测试的准确性。
在一种可能的实现方式中，所述芯片还包括测试信号输出引脚；所述测试电路还用于：从所述测试信号输入引脚接收第五测试信号，将所述第五测试信号通过所述多条信号传输通路中的第五信号传输通路传输至所述测试信号输出引脚，所述第五信号传输通路中设置有组合逻辑。
该第五测试信号可以为扫描测试信号，测试信号输入引脚和测试信号输出引脚可以与测试设备连接，测试设备将第三测试信号通过测试信号输入引脚提供至第五信号传输通路，第五信号传输通路将第三测试信号传通过测试信号输出引脚传输至测试设备，以使得测试设备对芯片内部、设置有组合逻辑的第五信号传输通路进行测试，可以提高芯片测试的准确。
本申请实施例中所述的测试电路，可以包括多种类型的电路结构。在一种可能的实现方式中，所述测试电路包括内建自测试电路和扫描测试电路；所述内建自测试电路，包括信号发射端和信号接收端；所述信号发射端，用于生成所述第一测试信号；所述信号接收端，用于基于所述第二测试信号以及所生成的测试信号，生成所述第一测试结果；所述扫描测试电路，用于从所述测试信号输入引脚接收所述第三测试信号，将所述第三测试信号通过所述第三信号传输通路传输至所述第三互联引脚。
基于如上所述的测试电路的电路结构，在一种可能的实现方式中，当测试电路对芯片内部、各单元模块之间进行信号传输的信号传输通路进行测试时：
所述信号发射端还用于：生成所述第四测试信号，通过所述第四信号传输通路，向所述信号接收端传输所述第四测试信号。所述信号接收端还用于：基于所述第四测试信号以及所述信号接收端所生成的测试信号，生成所述第二测试结果。
所述扫描测试电路还用于：从所述测试信号输入引脚接收所述第五测试信号，将所述第五测试信号通过所述第五信号传输通路传输至所述测试信号输出引脚。
基于如上所述的测试电路的电路结构，在一种可能的实现方式中，所述信号发射端通过所述第一信号传输通路与所述第一互联引脚连接；所述信号接收端通过所述第二信号传输通路与所述第二互联引脚连接。
在一种可能的实现方式中，所述芯片还包括：多路选择器，所述多路选择器设置于所述内建自测试电路与所述多个互联引脚之间；所述多路选择器用于当所述第一信号传输通路发生故障时，将所述信号发射端通过所述第一信号传输通路与所述第一互联引脚连接，切换至所述信号发射端通过所述多条信号传输通路中的第六信号传输通路与所述多个互联引脚中的第四互联引脚连接。
本申请实施例中，第四互联引脚为冗余引脚，通过设置多路选择器和冗余引脚，可以在某一信号传输通路发生故障时，将发生故障的信号传输通路直接切换至冗余引脚所在的 信号传输通路上，不需要再进行额外的人工修复，提高对异常信号传输通路的修复效率。
在一种可能的实现方式中，所述多路选择器还用于：当所述第二信号传输通路发生故障时，将所述信号接收端通过所述第二信号传输通路与所述第二互联引脚连接，切换至所述信号接收端通过所述多条信号传输通路中的第七信号传输通路与所述多个互联引脚中的第五互联引脚连接。
在一种可能的实现方式中，所述信号发射端包括第一线性反馈移位寄存器，所述信号接收端包括第二线性反馈移位寄存器，所述第一线性反馈移位寄存器和所述第二线性反馈移位寄存器是通过复用所述芯片中的功能寄存器得到的。
在一种可能的实现方式中，所述扫描测试电路包括多个级联的芯片封装寄存器，所述多个级联的芯片封装寄存器是通过复用所述第一线性反馈移位寄存器和所述第二线性反馈寄存器中的至少一个得到的。
本申请实施例通过将第一线性反馈移位寄存器、第二性反馈移位寄存器以及扫描测试电路中的寄存器均复用芯片中的功能寄存器，可以减少芯片中所设置的寄存器的数目，从而减小寄存器所占用的芯片的版图面积，从而简化芯片中的电路，有利于小体积、高集成度芯片的实现。
在一种可能的实现方式中，所述芯片还包括：控制电路，所述控制电路用于向所述信号发射端传输控制信号，以控制所述信号发射端将所述第一测试信号、所述第三测试信号和功能信号中的一项输出。
在一种可能的实现方式中，所述控制电路还用于：向所述信号接收端输出控制信号，以控制所述信号接收端生成测试信号。
在一种可能的实现方式中，所述控制电路还用于：从所述信号接收端获得所述第一测试结果，基于所述第一测试结果，控制所述多路选择器的输入端和输出端之间连接关系的切换。
第二方面，本申请实施例提供一种装置，该装置包括第一芯片和第二芯片，所述第一芯片和第二芯片之间通过互联引脚连接；所述第一芯片，通过第一信号传输通路向所述第二芯片传输第一测试信号；所述第二芯片，基于所述第一测试信号和所述第二芯片所生成的测试信号，生成第一测试结果，所述第一测试结果用于指示所述第一信号传输通路是否发生故障；所述第二芯片，通过第二信号传输通路向所述第一芯片传输第二测试信号；所述第一芯片，基于所述第二测试信号和所述第一芯片所生成的测试信号，生成第二测试结果，所述第二测试结果用于指示所述第二信号传输通路是否发生故障；所述第一芯片，从所述第一芯片的测试信号输入引脚接收第三测试信号，将所述第三测试信号通过第三信号传输通路传输至所述第二芯片；所述第二芯片，将所述第三测试信号通过所述第二芯片中的测试信号输出引脚输出；其中，所述第一测试信号和所述第二测试信号为内建自测试BIST信号，所述第一信号传输通路和所述第二信号传输通路中未设置组合逻辑，所述第三信号传输通路中设置有组合逻辑。
基于第二方面，在一种可能的实现方式中，所述第一芯片包括第一内建自测试电路和第一扫描测试电路；所述第一内建自测试电路，包括第一信号发射端和第一信号接收端；所述第一信号发射端，用于生成所述第一测试信号；所述第二信号接收端，用于基于所述第二测试信号以及所生成的测试信号，生成所述第二测试结果；所述第一扫描测试电路， 用于从所述测试信号输入引脚接收第三测试信号，将所述第三测试信号通过所述第三信号传输通路传输至所述第二芯片。
基于第二方面，在一种可能的实现方式中，所述第二芯片包括第二内建自测试电路和第二扫描测试电路；所述第二内建自测试电路，包括第二信号发射端和第二信号接收端；所述第二信号发射端，用于生成所述第二测试信号；所述第二信号接收端，用于基于所述第一测试信号以及所生成的测试信号，生成所述第一测试结果；所述第二扫描测试电路，用于从所述第一芯片接收第三测试信号，将所述第三测试信号通过所述第二芯片的测试信号输出引脚输出。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的芯片A中所设置的测试电路的一个结构示意图；
图2是本申请实施例提供的芯片A中所设置的测试电路的又一个结构示意图；
图3是本申请实施例提供的芯片A与芯片B相连接的一个结构示意图；
图4是本申请实施例提供的芯片A中所设置的测试电路的又一个结构示意图；
图5是本申请实施例提供的芯片A中所设置的测试电路的又一个结构示意图；
图6是本申请实施例提供的芯片A中所设置的测试电路的又一个结构示意图；
图7是本申请实施例提供的芯片A中所设置的测试电路的又一个结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文所提及的"第一"、"第二"以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，"一个"或者"一"等类似词语也不表示数量限制，而是表示存在至少一个。"连接"等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的，等同于广义上的联通。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个输出端是指两个或两个以上的输出端。
本申请实施例所述的芯片的类型，可以包括但不限于以下之一：片上系统(system on chip)、存储器(Memory)、分立器件、应用处理芯片(application processor，AP)、微机电系统(micro-electro-mechanical system，MEMS)、微波射频芯片、专用集成电路 (applicationspecific integrated circuit，ASIC)等芯片。上述应用处理芯片或专用集成电路在具体应用中可以是中央处理器(central processing unit，CPU)、图像处理器(graphics processing unit，GPU)、人工智能处理器，例如，神经网络处理器(network processing unit，NPU)等。存储器可以是高速缓冲存储器(cache)、随机存取存储器(random access memory，RAM)、只读存储器(read only memory，ROM)或其他存储器。分立器件例如可以包括但不限于例如场效应晶体管、双极性晶体管、集成运算放大器等。本申请实施例所述的芯片中，均设置有测试电路，该测试电路用于对芯片内部的信号传输通路进行测试或者对芯与芯片之间的互联性能进行测试，以检测信号传输通路是否畅通、信号传输是否延迟以及芯片管脚是否有无断裂等。下面通过图1～图7所示的实施例，对芯片中所设置的测试电路进行详细描述。
请参考图1，图1是本申请实施例提供的芯片A的一个结构示意图。在图1中，芯片A包括测试电路。通常，芯片A在与其他芯片互联之前或者芯片A出厂之前需要进行自测试，以检测芯片A内部的各条信号传输通路是否流通以及信号传输是否延迟等。本申请实施例所述的测试电路，用于对芯片A内部的信号传输通路进行测试。如图1所示，测试电路包括内建自测试电路1和扫描测试电路2。
内建自测试电路1包括信号发射端10和信号接收端11。信号发射端10用于发射信号，信号发射端11用于接收信号。信号发射端10包括多个输出端，图1中示意性的示出了信号发射端10包括四个输出端ao1～ao4；信号接收端11包括多个输入端，图1中示意性的示出了信号接收端11包括四个输入端ai1～ai4。信号发射端10的多个输出端，通过芯片A中的多条信号传输通路S1～S4，与信号接收端11的多个输入端对应连接。信号发射端10可以包括线性反馈移位寄存器(LFSR，linear feedback shift register)，信号接收端11同样也可以包括LFSR。当信号发射端11和信号接收端12分别包括四个端口时，信号发射端10和信号接收端11均可以包括四位LFRS。此外，信号接收端11还包括比较电路。具体工作中，信号发射端10和信号接收端11均可以生成相同的伪随机二进制序列(PRBS，pseudo random binary sequence)。信号发射端10将所生成的四位伪随机二进制序列分别通过四条信号传输通路S1～S4提供至信号接收端11。信号接收端11将从信号发射端10接收到的四位伪随机二进制序列与自身所生成的四位伪随机二进制序列进行比对，输出比对结果，该比对结果用于指示信号传输通路S1～S4中是否发生故障。该故障例如可以包括但不限于以下一项：短路、断路和延迟等。作为示例，四位伪随机二进制序列为1100，信号传输通路S1用于传输信号“1”，信号传输通路S2用于传输信号“1”，信号传输通路S3用于传输信号“0”，信号传输通路S4用于传输信号“0”。假设信号传输通路S2断路，则信号传输通路S2输出的信号为“0”，信号接收端11接收到的信号为“1000”。信号接收端11将“1000”与“1100”进行比对，确定出所接收到的四位伪随机二进制序列与预先生成的四位伪随机二进制序列中，第二位不同，从而输出比对结果，例如该比对结果可以为“0100”，其中“0”指示对应的信号传输通路畅通、“1”指示对应的信号传输通路异常。需要说明的是，图1所示的信号发射端10所包括的输出端的数目、信号接收端11所包括的输入端的数目、以及内建自测试电路1所生成的伪随机二进制序列的位数均为示意性的，信号发射端10可以包括更多数目的输出端(例如包括15个输出端、32个输出端等)，同样，信号接收端11可以包括更多数目的输入端(例如包括15个输入端、32个输入端等)，其基于芯 片A中所要测试的信号传输通路的数目确定。还需要说明的是，与信号发射端10的输出端以及信号接收端11的输入端连接的多条信号传输通路S1～S4可以为直连通路，在传输通路S1～S4上均未设置组合逻辑。
扫描测试电路2用于对设置有组合逻辑的信号传输通路进行测试。扫描测试电路2包括至少一条测试链，该至少一条测试链中的每一条测试链是由多个芯片封装寄存器(DWR，die wrapper register)串联形成的。图1中示意性的示出了扫描测试电路2包括一条测试链。该多个DWR串联连接在芯片A的测试信号输入端ti和测试信号输出端to之间。此外，在测试信号输入端ti(也可以称为芯片A的测试信号输入引脚)和测试信号输出端to(也可以称为芯片A的测试信号输出引脚)之间的信号传输通路上还设置有组合逻辑3，该组合逻辑3用于实现芯片A的多种逻辑功能，该逻辑功能可以包括但不限于：运算和存储等。组合逻辑3可以包括但不限于以下至少一项：运算器(例如加法器、乘法器等)、缓存器和逻辑门(例如与门、或门、非门、异或门等)。组合逻辑3包括多个输入端和多个输出端，图1中示意性的示出了组合逻辑3包括两个输入端和两个输出端。组合逻辑3的每一个输入端和每一个输出端均设置有一个DWR。每一个DWR均包括输入端ci1和输出端co1，其中DWR121的输入端ci1与芯片A的测试信号输入端ti连接，DWR121至DWR124中，前一级DWR的输出端co1与后一级DWR的输入端ci1连接，DWR124的输出端co1与测试信号输出端to连接。此外，DWR121和DWR122还包括输出端co2，DWR121和DWR122的输出端co2分别与组合逻辑的两输入端连接；DWR123和DWR124还包括输入端ci2，DWR123和DWR124的输入端ci2分别与组合逻辑3的两输出端连接。此外，各DWR还包括时钟信号输入端和使能信号输入端，图中未示出。扫描测试电路2工作时，测试信号输入端ti和测试信号输出端to分别与测试设备连接。具体工作中，首先，各DWR形成输入端ci1至输出端co1的通路，测试设备向测试信号输入端ti输入测试信号T1，测试信号T1通过移位扫描的方式存储至DWR121和DWR122中；接着，DWR121和DWR122中存储的测试信号T1通过输出端co2提供至组合逻辑1中，组合逻辑1对测试信号T1进行处理后生成测试信号T2，通过DWR123和DWR124的输入端ci2分别存储至DWR123和DWR124中；然后，各DWR形成输入端ci1至输出端co1的通路，DWR123和DWR124中存储的测试信号T2通过测试信号输出端to移位输出至测试设备。从而，测试设备基于测试信号T2和期望输出的信号，来确定芯片A中设置有组合逻辑的信号传输通路是否发生故障。该异常例如可以包括但不限于：断路、短路或时延等。
传统技术中，为了提高芯片的测试效率，芯片的测试电路中通常仅采用内建自测试电路该一种电路结构，对芯片内部或芯片间的信号传输通路进行测试。然而，针对信号传输通路中存在组合逻辑的情况，内建自测试电路的信号发射端输出的信号经过组合逻辑则会被改变，从而干扰测试结果。例如，假设信传输通路中的组合逻辑为反相器，信号发射端输出的“1100”经过反相器变成“0011”，信号接收端接收到的信号即变为“0011”，从而导致信号接收端误判为所有的信号传输通路均发生故障，进而导致测试效率低下。
本申请实施例所示的测试电路，通过设置内建自测试电路和扫描测试电路，针对芯片中未设置组合逻辑的信号传输通路采用内建自测试电路进行测试，针对芯片中设置有组合逻辑的信号传输通路采用扫描测试电路进行测试，从而提高测试电路的测试效率以及测试准确率。
本申请实施例中，芯片A还包括多个引脚，该多个引脚也可以称为互联引脚或者焊盘(PAD)。芯片A的引脚用于与其他芯片进行互连，以进行信号交互。可以理解的是，图中芯片A所包括的引脚的数目只是示意性的，实际产品中可以包括更多个引脚，芯片A引脚的数目基于场景的需要而设置。测试电路100还可以与芯片A的各引脚连接。当芯片A通过各引脚与其他芯片互连后，测试电路100还可以对芯片A和其他芯片之间的信号传输通路进行测试，也即通过芯片A的各引脚对芯片A和其他芯片之间的互联性能进行测试，以检测芯片A和其他芯片之间的信号是否流通、信号传输是否延迟以及芯片管脚是否有无断裂等。如图2所示，图2是本申请实施例提供的芯片A的又一个结构示意图。图2中示意性的示出了芯片A包括引脚a1、a2、a3、a4、a5、a6、a7和a8八个引脚。芯片A中的部分引脚可以为信号输出引脚，其用于向其他芯片输出信号；部分引脚可以为信号输入引脚，其用于从其他芯片输入信号；部分引脚可以为双向信号传输引脚，其既可以向其他芯片输出信号，也可以从其他芯片输入信号。图2中示意性的示出了引脚a1～引脚a3以及引脚a8为信号输出引脚、引脚a5～引脚a7为信号输入引脚、引脚a4为双向引脚的情况。在图2中，信号发射端10的多个输出端还分别通过信号传输通路与引脚a1～引脚a4连接，信号接收端11的多个输入端还分别通过信号传输通路与引脚a4～引脚a7连接。一种可能的实现方式中，对芯片A进行自测试的信号传输通路和对芯片A与其他芯片进行互联测试的信号传输通路至少部分相同，例如，对芯片A进行自测试的信号传输通路和对芯片A与其他芯片进行互联测试的信号传输通路均采用信号传通路S4。由于信号发射端10的输出端ao4与信号接收端11的输入端ai4连接，并且信号发射端10的输出端ao4和信号接收端11的输入端ai4均与引脚a4连接，为了防止信号倒灌，本申请实施例中，在信号发射端10的输出端ao4与引脚a4之间、以及引脚a4和信号接收端11的输入端ai4之间均设置有跟随器F，如图2所示。这里所述的信号倒灌，是指从引脚a4输入的信号通过输入端ao4流入信号发射端10，对信号发射端10的电路产生干扰。此外，在图2中，芯片A中与引脚a8连接的信号传输通路上设置有组合逻辑1。从而，扫描测试电路2的信号输出端(也即DWR124的输出端co1)与引脚a8连接。
本申请实施例中，与芯片A互联的芯片，可以包括与芯片A相同结构的测试电路。下面以芯片B与芯片A互联为例，结合图3，对本申请实施例中提供的测试电路对芯片之间的互联性能进行测试的工作原理进行详细描述。在图3中，芯片B包括内建自测试电路4、扫描测试电路5、引脚b1、b2、b3、b4、b5、b6、b7和b8八个引脚(该八个引脚也可以称为互联引脚)。示意性的，引脚b1～引脚b3以及引脚b8为信号输入引脚、引脚b5～引脚b7为信号输出引脚、引脚b4为双向引脚。内建自测试电路4包括信号发射端20和信号接收端21，信号发射端20与引脚b4～引脚b7连接，用于向引脚b4～引脚b7输出测试信号，信号接收端21与引脚b1～b4连接，用于从引脚b1～b4接收测试信号。内建自测试电路4的工作原理与内建自测试电路1的工作原理相同，具体参考相关描述，在此不再赘述。扫描测试电路5设置于引脚b8和测试信号输出端to2之间。扫描测试电路5包括DWR125～DWR128，扫描测试电路5的结构以及工作原理与扫描测试电路2结构以及工作原理相同，具体参考对扫描测试电路2的相关描述。此外，在图3中，芯片A的引脚a1～a8分别与芯片B的引脚b1～b8对应连接。
对芯片A和芯片B之间的互联性能进行测试时，信号发射端10和信号接收端21生 成相同的伪随机二进制序列；信号发射端10将所生成的伪随机二进制序列通过引脚a1～a4以及引脚b1～b4提供至信号接收端21，信号接收端21将自身所生成的伪随机二进制序列与通过引脚b1～b4接收到的伪随机码进行比较，基于比较结果，来确定引脚a1～a4与引脚b1～b4之间的信号传输通路是否发生故障。同样，信号发射端20和信号接收端11生成相同的伪随机二进制序列；信号发射端20将所生成的伪随机二进制序列通过引脚b4～b7以及引脚a4～a7提供至信号接收端11，信号接收端11将自身所生成的伪随机二进制序列与通过引脚a4～a7接收到的伪随机码进行比较，基于比较结果，来确定引脚a4～a7与引脚b4～b7之间的信号传输通路是否发生故障。其中，基于伪随机二进制序列来确定芯片A与芯片B之间的互联性能的原理，与对芯片A内部的信号传输通路进行测试时、基于伪随机二进制序列来确定各信号传输通路是否异常的工作原理相同，具体参考与对芯片A内部的信号传输通路进行测试时、基于伪随机二进制序列来确定各信号传输通路是否异常的相关描述，不再赘述。
进一步的，对芯片A和芯片B之间的互联性能进行测试时，测试设备与芯片A的测试信号输入端ti1以及芯片B的测试信号输出端to2连接。测试设备用于通过测试信号输入端ti1向扫描测试电路2输入测试信号T3。扫描测试电路2对测试信号T3进行处理后生成测试信号T4(具体处理方法参考图1中对测试电路2的工作原理的描述)，通过接口a8、接口b8输出至扫描测试电路2。扫描测试电路2可以对测试信号T4进行进一步处理(具体处理方法参考图1中对测试电路2的工作原理的描述)，生成测试信号T5通过测试信号输出端to2提供至测试设备。测试设备将测试信号T5与期望信号进行比较，当测试信号T5与期望信号相同时，则说明经过引脚a8和引脚b8的信号传输通路不存在故障；当测试信号T5与期望信号不同时，则说明经过引脚a8和引脚b8的信号传输通路存在故障。
以上通过图1～图3所示的实施例，介绍了芯片A中的测试电路、芯片A内部传输通路测试的工作原理以及与其他芯片互联后进行测试的工作原理。如图1～图3所示的实施例中，所示的芯片A中的信号发射端10、信号接收端11以及扫描测试电路2中的DWR均为相互独立的寄存器。本申请实施例一种可能的实现方式中，内建自测试电路1中的信号发射端10、信号接收端11以及扫描测试电路2中的DWR均可以复用芯片A中的功能寄存器(也即芯片A测试完毕后用于进行信号存储和传输的寄存器)。此外，信号发射端10中的LSFR和扫描测试电路2中的DWR可以共用相同的寄存器，信号接收端11中的LSFR和扫描测试电路2中的DWR也可以共同相同的寄存器。下面以信号发射端10、信号接收端11以及DWR均复用芯片A中的功能寄存器、且信号发射端10和DWR共用相同的寄存器为例，结合图4所示的测试电路100的结构，对本申请实施例提供的测试电路100进行更为详细的描述。
如图4所示，测试电路中的信号发射端10包括多级级联的寄存器SF01、寄存器SF02、寄存器SF03和寄存器SF04。该多个寄存器中的每一个寄存器均包括输入端D、输入端SI、使能端SE和输出端Q。其中，寄存器SF01、寄存器SF02、寄存器SF03和寄存器SF04用于输出功能信号；此外，寄存器SF01、寄存器SF02、寄存器SF03和寄存器SF04还用于输出伪随机二进制序列；进一步的，寄存器SF01、寄存器SF02、寄存器SF03和寄存器SF04还用于输出测试信号。对于寄存器SF01～寄存器SF04，每两个寄存器之间以及第 一级寄存器与信号输入端之间均设置有多路选择器，多路选择器用于选择性的将功能信号、随机信号和测试信号中的一个提供至寄存器以及从寄存器的输出端Q输出。其中，随机信号用于形成伪随机二进制序列，测试信号用于进行扫描测试。图4中示意性的示出每两个寄存器之间以及第一级寄存器与信号输入端之间设置有数据选择器D1和数据选择器D2两个数据选择器的情况。该两个数据选择器均为二选一数据选择器。具体的，每一个数据选择器D1的第一输入端分别与信号发射端10的初始信号输入端s1～s4连接，以用于输入初始信号；除第一级数据选择器D1之外，其余各数据选择器D1的第二输入端分别与前一级寄存器的输出端Q连接；每一个数据选择器D1的输出端分别与数据选择器D2的第一输入端连接；每一个数据选择器D1的控制端均与信号发射端10的控制信号输入端c2连接；每一个数据选择器D2的第二输入端用于输入功能信号Func；每一个数据选择器D2的输出端与后一级寄存器的输入端D连接；每一个数据选择器D2的控制端与控制信号输入端c0连接。此外，测试电路100还包括异或门X1，异或门X1用于将四个级联的寄存器中的两个寄存器输出的信号进行异或运算后，提供至第一级寄存器的输入端D。在图4中，异或门X1的两个输入端分别与寄存器SF03的输出端Q以及寄存器SF04的输出端Q连接，异或门X1的输入端与第一级数据选择器D1的第二输入端连接。需要说明的是，本申请实施例中，异或门X1的两输入端分别与第三级和第四级寄存器的输出端连接，在其他可能的实现方式中，异或门X1的两输入端还可以与第二级和第三级寄存器的输出端连接，本申请实施例对此不做具体限定。寄存器SF01～寄存器SF04中，寄存器SF01的输入端SI与芯片A的测试信号输入端ti连接，寄存器SF02～寄存器SF04中的每一个寄存器的输入端SI与其前一级寄存器的输出端Q连接；每一个寄存器的使能端SE与信号发射端10的控制信号输入端c1连接。寄存器SF01～寄存器SF04的输出端Q，分别与信号发射端10的信号输出端ao1～ao4对应连接。此外，寄存器SF01和寄存器SF02的输出端Q还分别与如图1所示的组合逻辑1的输入端连接；第三级数据选择器D2和第四级数据选择器D2的第二输入端还分别与图1所示的组合逻辑3的输出端连接。图4中未示出组合逻辑3、以及各寄存器与组合逻辑3之间的连接情况。
需要说明的是，本申请实施例中，信号发射端10所要输出的伪随机二进制序列的位数与所级联的寄存器的数目相等。如图4所示的信号发射端10中，设置有四位寄存器，其用于输出四位伪随机二进制序列。在其他可能的实现方式中，信号发射端10可以输出更多位伪随机二进制序列，例如十五位或者三十位等，信号发射端10可以设置更多数目的寄存器，例如十五级级联的寄存器或者三十级级联的寄存器等。以三十级级联的寄存器为例，上述异或门X1的两个输入端可以分别与第二十八级以及第三十级寄存器的输出端连接。进一步的，图4中示意性的示出了LSFR所包括的寄存器的数目与扫描测试电路所包括的DWR的数目相等，且LSFR和DWR共用相同的寄存器。在其他可能实现方式中，扫描测试电路可以包括更多数目的DWR，例如包括十个，此时该十个DWR级联成扫描测试链，其中四个DWR被内建自测试电路中的LSFR复用。
以上描述了测试电路中信号发射端10的电路结构。进一步的，测试电路还包括信号接收端11。请继续参考图4，信号接收端11包括LSFR电路110和比较电路111。其中，LSFR电路110包括多级级联的寄存器SF05、寄存器SF06、寄存器SF07和寄存器SF08，寄存器SF05～寄存器SF08的结构与寄存器SF01～寄存器SF04的结构相同，不再赘述。与 信号发射端10的电路相类似，寄存器SF05～寄存器SF08除了用于输出伪随机二进制序列之外，还用于输出功能信号Func。与寄存器SF01～寄存器SF04不同的是，寄存器SF05～寄存器SF08不输出测试信号。此外，对于寄存器SF05～寄存器SF08，每两个寄存器之间以及第一级寄存器与信号输入端之间均设置有选择器D1。选择器D1的结构以及选择器D1的各输入端输入的信号，与信号发射端10所包括的选择器D1相同，具体参考相关描述。与信号发射端10的电路不同的是，信号接收端11的电路中不设置寄存器D2，寄存器SF05～寄存器SF08中的输入端D用于输入功能信号Func，寄存器SF05～寄存器SF08中的输入端SI分别耦合至各选择器D1的输出端。各选择器D1的控制端均与信号接收端11的控制信号输入端c3连接。进一步的，LSFR电路110还包括异或门x2，异或门x2的两个输入端分别与寄存器SF07的输出端Q以及寄存器SF08的输出端Q连接，异或门x2的输入端与第一级数据选择器D1的第二输入端连接。寄存器SF05～寄存器SF08中，每一个寄存器的使能端SE与信号接收端11的控制信号输入端c4连接。从而，寄存器SF05～寄存器SF08基于使能端SE输入的使能信号，选择性的将输入端D输入的功能信号Func或者输入端SI输入的随机信号提供至输出端Q，以从输出端Q输出。
继续参考图4，本申请实施例中，芯片A的信号接收端11的比较电路111包括多个寄存器、多个异或门X3以及多个异或门X4，图4中示意性的示出了寄存器SF09～寄存器SF12、四个异或门X3和四个异或门X4。其中，寄存器SF09～寄存器SF12中的每一个寄存器均包括输入端D、输出端Q和使能端SE。多个异或门X3的第一输入端分别与信号接收端11的信号输入端ai1～ai4对应连接，异或门X3第二输入端分别与寄存器SF05～寄存器SF08的输出端Q对应连接，多个异或门X3的输出端分别与异或门X4的第二输入端连接；多个异或门X4的第一输入端分别与寄存器SF09～寄存器SF12的输出端Q对应连接，多个异或门X4的输出端分别与寄存器SF09～寄存器SF012的输入端D连接。寄存器SF09～寄存器SF12的输出端Q分别与信号接收端11的输出端o1～o4。
如图4所示的芯片A中，寄存器SF01～寄存器SF04的输出端Q，分别通过信号发射端10的信号输出端ao1～ao4、信号接收端11的信号输入端ai1～ai4与多个异或门X3的第一输入端对应连接，从而实现芯片A内部信号传输通路的测试。在其他可能的实现方式中，寄存器SF01～寄存器SF04的输出端Q还可以通过信号发射端10的信号输出端ao1～ao4分别与芯片A的引脚a1～a4连接，多个异或门x3的第一输入端分别通过信号接收端11的信号输入端ai1～ai4分别与芯片A的引脚a4～a7对应连接，如图5所示，从而实现芯片A与其他芯片之间的互联性能的测试。图5中其余各部件以及各部件之间的连接关系与图4所示的各部件相同，具体参考图4所示的实施例中的相关描述。
进一步的，当芯片A既可以实现芯片A内部信号传输通路的测试、又可以实现芯片A与其他芯片之间的芯片传输通路的测试时，一种可能的实现方式中，在芯片A中还可以设置多个选择器D3和多个选择器D4，信号输出端ao1～ao4与多个选择器D3的输入端连接，各选择器D3的第一输出端分别与各选择器D4的第一输入端对应连接，各选择器D3的第二输出端分别与接口a1～a4对应连接；各选择器D4的第二输入端分别与接口a4～a7对应连接，各选择器D4的输出端分别与信号输入端ai1～ai4连接。图中未示出该实现方式。在对芯片A内部信号传输通路测试时，选择器D3形成输入端至第一输出端的通路，选择器D4形成第一输入端至输出端的通路，寄存器SF01～寄存器SF04输出的信号分别提供至 各异或门X3的第一输入端；在对芯片A与其他芯片之间的信号进行测试时，选择器D3形成输入端至第二输出端的通路，选择器D4形成第二输入端至输出端的通路，寄存器SF01～寄存器SF04输出的信号分别提供至接口a1～a4，接口a4～接口a7输入的信号分别提供至各异或门X3的第一输入端。
需要说明的是，图4-图5所示的信号接收端11中，LSFR110复用芯片A中的功能寄存器，该功能寄存器未被扫描测试电路复用。在其他可能的实现方式中，信号接收端11中的LSFR110所复用的功能寄存器，同样被扫描测试电路中的DWR复用，此时，LSFR110与信号发射端10的电路相同，具体参考信号发射端10中的电路的相关描述。
本申请实施例中，图3所示的芯片B中，信号发射端20的结构可以与芯片A中的信号发射端10的结构相同；芯片B中的信号接收端21也可以包括LSFR和比较电路，LSFR的电路结构可以与芯片A中的信号发射端10的结构相同，也可以与芯片A中的信号接收端11中LSFR110相同，芯片B中的信号接收端21中的比较电路，可以与芯片A中比较电路111相同，在此不再赘述。
基于图4-图5所述的芯片A中的测试电路的结构，本申请实施例中所述的芯片A可以包括多种工作模式。下面以图4所示的电路结构为例，对芯片A的多种工作模式、每一种工作模式下测试电路的工作原理以及信号传输通路进行更为详细的描述。
芯片A可以工作在第一种工作模式，也即芯片A的内建自测试模式。
基于芯片A的第一种工作模式，在芯片A的信号发射端10，在第一时钟周期，数据选择器D1基于控制信号输入端c2输入的控制信号，形成第一输入端至输出端的通路，数据选择器D2基于控制信号输入端c0输入的控制信号，形成第一输入端至输出端的通路，寄存器SF01～SF04基于使能端SE输入的使能信号，形成输入端D至输出端Q的通路，初始信号输入端s1～s4输入的初始信号分别通过数据选择器D1、数据选择器D2以及各寄存器的输入端D分别提供至各寄存器。需要说明的是，向寄存器SF01～SF04输入的初始信号可以为不同的信号，其基于所要产生的PRBS的位数以及预先设置的序列码生成规则来确定的。其中，向每一个寄存器输入的初始信号为1位比特位。例如，向寄存器SF01～SF04输入的初始信号为“1001”。也即此时寄存器SF01～SF04输出的二进制伪随机码序列为“1001”。在第二时钟周期，数据选择器D1基于控制信号输入端c2输入的控制信号，形成第二输入端至输出端的通路，保持其余各数据选择器D2以及各寄存器的通路状态不变，异或门将寄存器SF03和寄存器SF04的输出端Q输出的信号进行异或运算后提供至第一级数据选择器D1的第二输入端，该异或运算后的信号通过数据选择器D1和数据选择器D2提供至寄存器SF01；与此同时，寄存器SF01上一状态存储的信号提供至寄存器SF02、寄存器SF02上一状态存储的信号提供至寄存器SF03、寄存器SF03上一状态存储的信号提供至寄存器SF04。仍以第一时钟周期输出的二进制伪随机码序列为“1001”为例，基于该二进制伪随机码序列，寄存器SF01～SF04在第二时钟周期输出的二进制伪随机码序列为“1100”。在第三时钟周期～第N时钟周期，保持各数据选择器D1、各数据选择器D2以及各寄存器的通路状态不变，基于与上述第二时钟周期同样的工作原理输出四位二进制伪随机码序列。由此，寄存器SF01～SF04在每一个时钟周期均输出四位二进制伪随机码序列。
基于芯片A的第一种工作模式，在芯片A的信号接收端，在第一时钟周期，数据选 择器D1基于控制信号输入端c4输入的控制信号，形成第一输入端至输出端的通路，寄存器SF05～SF08基于使能端SE输入的使能信号，形成输入端SI至输出端Q的通路。初始信号分别通过数据选择器D1以及寄存器SF05～SF08的输入端SI分别提供至寄存器SF05～SF08的输出端Q。需要说明的是，向寄存器SF05～SF08输入的初始信号、与向寄存器SF01～SF04输入的初始信号相同。例如，向寄存器SF01～SF04输入的初始信号分别为“1001”，则向寄存器SF05～SF08输入的初始信号分别为“1001”。在第二时钟周期，数据选择器D1基于控制信号输入端c4输入的控制信号，形成第二输入端至输出端的通路，基于与芯片A的信号发射端在第二时钟周期相同的工作原理，寄存器SF05～SF08输出四位二进制伪随机码序列，该四位二进制伪随机码序列与寄存器SF01～SF04在第二时钟周期输出的四位二进制伪随机码序列相同。在第三时钟周期～第N时钟周期，保持各数据选择器D1以及各寄存器的通路状态不变，采用与上述第二时钟周期同样的工作原理，寄存器SF05～SF08在每一个时钟周期均输出四位二进制伪随机码序列。进一步的，在上述第一工作模式的每一个时钟周期，寄存器SF01～SF04的输出端Q输出的信号和寄存器SF05～SF08的输出端Q输出的信号均对应提供至各异或门x3，经异或门x3进行异或运算后提供至异或门x4，异或门x4对异或门x3提供的信号以及寄存器SF09～SF12的输出端Q输出的信号进行二次异或运算后，分别提供至寄存器SF09～SF12的输入端D，并经过寄存器SF09～SF12的输出端Q输出。从而，基于寄存器SF09～SF12的输出端Q输出的结果，即可判断出芯片A内部的信号传输通路是否发生故障。
如上所述的芯片A的第一工作模式是对芯片A内部传输通路进行测试的情况，对芯片A与芯片B之间的信号传输通路进行测试时，测试电路中的各部件在各个时钟周期的工作状态以及工作原理，与对芯片A内部传输通路进行测试的工作状态和工作原理相同，不同的是，在第一时钟周期向寄存器SF01～SF04输入的初始信号与芯片B的接收端输入的初始信号相同；在上第一时钟周期向寄存器SF05～SF08输入的初始信号与芯片B的发射端输入的初始信号相同。
芯片A还可以工作在第二种工作模式，也即芯片A的扫描测试模式。在第二种工作模式下，芯片A的信号发射端10工作、信号接收端11停止工作。此时，在芯片A的信号发射端10，数据选择器D1和数据选择器D2被截止。首先，寄存器SF01～SF04基于使能端SE输入的使能信号，形成输入端SI至输出端Q的通路，测试信号输入端ti输入的测试信号T1通过寄存器SF01的输入端SI提供至寄存器SF01。接着，寄存器SF01将上一时钟周期存储的测试信号T1通过寄存器SF02的输入端SI提供至寄存器SF02，测试信号T2通过寄存器SF01的输入端SI提供至寄存器SF01。然后，寄存器SF02将测试信号T1、寄存器SF01将测试信号T2提供至如图1所示的组合逻辑1，经过组合逻辑1的处理，生成测试信号T3和测试信号T4分别提供至寄存器SF03和寄存器SF04。最后，测试信号T3和测试信号T4通过寄存器SF04的输出端Q输出。此时，外部测试设备与寄存器SF01的输入端SI以及寄存器SF04的输出端Q连接，以向寄存器SF01～寄存器SF04形成的扫描测试链输入测试信号T1和测试信号T2，以及从扫描测试链输出测试信号T3和测试信号T4。
芯片A还可以工作在第三种工作模式，也即芯片A的功能信号传输模式。在第三种工作模式下，在芯片A的信号发射端10，数据选择器D2基于控制信号输入端c0输入的 控制信号，形成第二输入端至输出端Q的通路，数据选择器D1截止，寄存器SF01～SF04基于使能端SE输入的使能信号，形成输入端D至输出端Q的信号传输通路。在芯片A的信号接收端11，数据选择器D1截止，寄存器SF05～SF08基于使能端SE输入的使能信号，形成输入端D至输出端Q的信号传输通路。从而，各功能信号Func分别通过各寄存器的输入端D输入的信号通过输出端Q输出。
以上通过图1-图5所示的实施例介绍了本申请实施例提供的芯片A中的测试电路以及测试电路的工作原理。在图1-图5任意实施例所示的芯片A的基础上，进一步的，本申请实施例所述的信号A还包括更多个引脚，该更多个引脚为冗余引脚，用于在上述引脚a1～引脚a7中的引脚或包括该引脚的传输通路发生故障时，将发生故障的引脚的信号传输通路迁移至该冗余引脚形成的信号传输通路上，从而对发生故障的引脚或信号传输通路进行修复。下面结合图6，对具有修复功能的测试电路进行更为详细的介绍。在图6中，芯片A中的测试电路除了包括信号发射端10、信号接收端11、引脚a1～引脚a8之外，还包括多路选择器13和引脚a9，多路选择器13的四个输出端分别与信号接收端11的四个输入端ai1～ai4连接，多路选择器13的五个输入端分别与引脚a4～引脚a7以及引脚a9连接。假设芯片A上的各条信号传输通路均处于正常导通状态，多路选择器13基于控制信号的控制，将信号输入端ai1～ai4与接口a4～a7对应连接。假设引脚a5或者引脚a5所在的信号传输通路出现异常(短路、断路或者延迟等)，则多路选择器13将信号输入端ai1与引脚a5之间连接切换至信号输入端ai1与引脚a9连接，从而对发生故障的引脚a5所在的信号传输通路舍弃，采用信号输入端ai1至引脚a9之间的信号传输通路进行信号传输。需要说明的是，图4中所示的数据选择器13的数目、冗余引脚的数目为示意性的，实际场景中可以包括更多或更少的数据选择器13以及冗余引脚的数目，从而可以对芯片A中更多异常的信号传输通路进行切换。此外，芯片A中的信号发射端10也可以通过多路选择器与芯片A上的冗余引脚连接，从而信号发射端10与芯片A的各引脚之间的信号传输通路发生故障时，也可以将发生故障的引脚切换至冗余引脚上。本申请实施例通过设置冗余引脚，可以在信号传输通路发生故障时，直接切换至冗余引脚所在的信号传输通路上，不需要再进行额外的人工修复，提高对异常信号传输通路的修复效率。
在图1-图6任意所示的芯片A的结构的基础上，本申请实施例中，芯片100还包括控制电路14，如图7所示。本申请实施例中所述的控制电路14可以是一个集成控制器，具体实现中，控制电路14可以为各种数字逻辑器件或电路，包括但不限于：微控制器、微处理器或者数字信号处理器(DSP，digital signal processor)等。控制电路14可以向如图1-图6任意实施例中所示的信号发射端10和信号接收端11输出控制信号，以控制信号发射端10输出的信号、以及信号接收端11输入端的信号。此外，控制电路14还用于从信号接收端11接收信号，基于所接收的信号，确定芯片A内部的信号传输通路、或者芯片A与其他芯片之间的信号传输通路是否异常。下面将图5所示的芯片A中信号发射端10和信号接收端11分别抽象成图7所示的形式，对控制电路14对信号发射端10、信号接收端11以及多路选择器13的控制进行详细描述。如图7所示，控制电路14包括信号输出端C1～C14以及信号输入端C15～C18。其中，信号输出端C1～C3与信号发射端10的控制信号输入端c0～c2连接，信号输出端C4～C8与信号发射端10的初始信号输入端s1～s4连接，信号输出端C8与多路选择器13的控制端连接，信号输出端C9～C10与信号接收端 11的控制信号输入端c3～c4连接，信号输出端C11～C14与信号接收端11的初始信号输入端s5～s8连接，控制电路14的信号输入端C15～C18与信号接收端11的输出端o1～o4连接。下面以对芯片A和其他芯片之间的信号传输通路进行测试为例，结合图5和图7，对控制电路14对信号发射端和信号接收端的控制进行更为详细的描述。
具体的，控制电路14可以控制测试电路工作在内建自测试模式。在第一时钟周期，控制电路14向控制信号输入端c0输入控制信号CL1，该控制信号CL1用于指示如图5所示的选择器D2形成第一输入端至输出端的通路；控制电路14向控制信号输入端c1输入控制信号CL2，该控制信号CL2用于指示如图5所示的寄存器SF01～SF04形成输入端D至输出端Q的通路；控制电路14向控制信号输入端c2输入控制信号CL3，该控制信号CL3用于指示信号发射端10中的选择器D1形成第一输入端至输出端的通路；控制电路14向控制信号输入端c3输入控制信号CL4，该控制信号CL4用于指示寄存器SF05～SF08形成输入端SI至输出端Q的通路；控制电路14向控制信号输入端c4输入控制信号CL5，该控制信号CL5用于指示信号接收端11中的选择器D1形成第一输入端至输出端的通路；控制电路14向信号发射端10的初始信号输入端s1～s4输入初始信号，向信号接收端11的初始信号输入端s5～s8输入初始信号；控制电路14向多路选择器13的控制端输入控制信号CL6，控制信号CL6用于指示多路选择器13形成引脚a7～a9至信号接收端11中的信号输入端ai1～ai4的通路。从而，信号发射端10基于上述控制信号的控制，生成二进制伪随机序列通过引脚a1～a4输出；信号接收端11基于上述控制信号的控制，生成二进制伪随机序列，此外，信号接收端11还用于将所生成的二进制伪随机序列与从引脚a4～a7接收到的二进制伪随机序列进行比较，生成比较结果通过输出端o1～o4提供至控制电路14。在第二时钟周期，控制电路14向控制信号输入端c2输入控制信号CL7，该控制信号CL7用于指示信号发射端10中的选择器D1形成第二输入端至输出端的通路；控制电路14向控制信号输入端c4输入控制信号CL8，该控制信号CL8用于指示信号接收端11中的选择器D1形成第二输入端至输出端的通路，保持其余各信号输入端输入的信号不变。在第三时钟周期～第N时钟周期，保持各信号输入端输入的信号不变。从而，信号发射端10和信号接收端11可以持续生成二进制伪随机序列，信号发射端10将各周期生成的二进制伪随机序列通过引脚a1～a4输出；信号接收端11将所生成的二进制伪随机序列与从引脚a4～a7接收到的二进制伪随机序列进行比较，生成比较结果通过输出端o1～o4提供至控制电路14。进一步的，控制电路14基于从输出端o1～o4所接收到的信号，检测各信号传输通路是否发生故障。例如，“0”代表正常，“1”代表异常，在上述第一至第N个时钟周期中每一个时钟周期，控制电路14从输出端o1～o4所接收到的信号均为“0000”，则代表通过引脚a4～a7的信号传输通路正常；如果在上述第一至第N个时钟周期中，存在至少一个时钟周期，控制电路14从输出端o1～o4所接收到的信号中有一位为“1”，例如，在某一时钟周期，控制电路14所接收到的信号为“1000”，则与第一位对应的信号传输通路发生故障，也即图7中所示的信号输入端ai1至引脚a5的信号传输通路发生故障。此时，控制电路14控制多路选择器13将信号输入端ai1与引脚a9连接，然后采用如上所述的第一至第N时钟周期相同的控制信号，继续对芯片A与其余芯片之间的信号传输通路进行检测。
控制电路14可以控制测试电路工作在扫描测试模式。控制电路14向控制信号输入端c0、控制信号输入端c2、控制信号输入端c3、控制信号输入端c4输入控制信号CL9，该 控制信号CL9用于指示选择器D1、选择器D2以及寄存器SF05～SF08停止使能；控制电路14向控制信号输入端c1输入控制信号CL10，该控制信号CL10用于指示如图5所示的寄存器SF01～SF04形成输入端SI至输出端Q的通路。从而，寄存器SF01～SF04基于上述控制信号的控制，形成扫描测试链对设置有组合逻辑的信号传输通路进行扫描测试。
控制电路14还可以控制芯片A工作在工作信号传输模式。控制电路14向控制信号输入端c0输入控制信号CL11，该控制信号CL11用于指示如图5所示的选择器D2形成第二输入端至输出端的通路；控制电路14向控制信号输入端c1输入控制信号CL2，该控制信号CL2用于指示如图5所示的寄存器SF01～SF04形成输入端D至输出端Q的通路；控制电路14向控制信号输入端c3输入控制信号CL12，该控制信号CL12用于指示寄存器SF05～SF08形成输入端D至输出端Q的通路。从而，各功能信号Func分别通过各寄存器的输入端D输入的信号通过输出端Q输出。
本申请实施例还提供一种装置，该装置可以包括但不限于：射频装置、电源管理装置或终端装置等。其中，终端装置具体可以包括但不限于：便携式计算机(如手机)、笔记本电脑、可穿戴电子设备(如智能手表)、平板电脑、增强现实(augmentedreality，AR)或虚拟现实(virtual reality，VR)设备等。具体的，本申请实施例所述的装置可以包括如图1-图7任意实施例所述的芯片A。此外，本申请实施例所述的装置还可以包括芯片B，芯片B与芯片A连接，以进行信号交流。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (15)

  1. 一种芯片，其特征在于，包括测试电路、多条信号传输通路、测试信号输入引脚和多个互联引脚，所述芯片为第一芯片，所述多个互联引脚用于与第二芯片连接；所述测试电路用于：
    通过所述多条信号传输通路中的第一信号传输通路，向所述多个互联引脚中的第一互联引脚传输第一测试信号，以使所述第二芯片基于所述第一测试信号对所述第一信号传输通路进行检测；
    通过所述多条信号传输通路中的第二信号传输通路，从所述多个互联引脚中的第二互联引脚接收第二测试信号，基于所述第二测试信号以及所述测试电路所生成的测试信号，生成第一测试结果，所述第一测试结果用于指示所述第二信号传输通路是否发生故障；
    从所述测试信号输入引脚接收第三测试信号，将所述第三测试信号通过所述多条信号传输通路中的第三信号传输通路传输至所述多个互联引脚中的第三互联引脚；
    其中，所述第一测试信号和所述第二测试信号为内建自测试BIST信号，所述第一信号传输通路和所述第二信号传输通路中未设置组合逻辑，所述第三信号传输通路中设置有组合逻辑。
  2. 根据权利要求1所述的芯片，其特征在于，所述测试电路还用于：
    通过所述多条信号传输通路中的第四信号传输通路传输第四测试信号；
    基于经所述第四传输通路传输后的第四测试信号，生成第二测试结果，所述第二测试结果用于指示所述第四信号传输通路是否发生故障；
    其中，所述第四信号传输通路中未设置组合逻辑，所述第四测试信号为BIST信号。
  3. 根据权利要求1或2所述的芯片，其特征在于，所述芯片还包括测试信号输出引脚；所述测试电路还用于：
    从所述测试信号输入引脚接收第五测试信号，将所述第五测试信号通过所述多条信号传输通路中的第五信号传输通路传输至所述测试信号输出引脚，所述第五信号传输通路中设置有组合逻辑。
  4. 根据权利要求1-3任一项所述的芯片，其特征在于，所述测试电路包括内建自测试电路和扫描测试电路；
    所述内建自测试电路，包括信号发射端和信号接收端；
    所述信号发射端，用于生成所述第一测试信号；
    所述信号接收端，用于基于所述第二测试信号以及所生成的测试信号，生成所述第一测试结果；
    所述扫描测试电路，用于从所述测试信号输入引脚接收所述第三测试信号，将所述第三测试信号通过所述第三信号传输通路传输至所述第三互联引脚。
  5. 根据权利要求4所述的芯片，其特征在于，所述信号发射端通过所述第一信号传输通路与所述第一互联引脚连接；
    所述信号接收端通过所述第二信号传输通路与所述第二互联引脚连接。
  6. 根据权利要求5所述的芯片，其特征在于，所述芯片还包括：
    多路选择器，所述多路选择器设置于所述内建自测试电路与所述多个互联引脚之间；
    所述多路选择器用于当所述第一信号传输通路发生故障时，将所述信号发射端通过所述第一信号传输通路与所述第一互联引脚连接，切换至所述信号发射端通过所述多条信号传输通路中的第六信号传输通路与所述多个互联引脚中的第四互联引脚连接。
  7. 根据权利要求6所述的芯片，其特征在于，所述多路选择器还用于：
    当所述第二信号传输通路发生故障时，将所述信号接收端通过所述第二信号传输通路与所述第二互联引脚连接，切换至所述信号接收端通过所述多条信号传输通路中的第七信号传输通路与所述多个互联引脚中的第五互联引脚连接。
  8. 根据权利要求4-7任一项所述的芯片，其特征在于，所述信号发射端包括第一线性反馈移位寄存器，所述信号接收端包括第二线性反馈移位寄存器，所述第一线性反馈移位寄存器和所述第二线性反馈移位寄存器是通过复用所述芯片中的功能寄存器得到的。
  9. 根据权利要求8所述的芯片，其特征在于，所述扫描测试电路包括多个级联的芯片封装寄存器，所述多个级联的芯片封装寄存器是通过复用所述第一线性反馈移位寄存器和所述第二线性反馈寄存器中的至少一个得到的。
  10. 根据权利要求6所述的芯片，其特征在于，所述芯片还包括：
    控制电路，所述控制电路用于向所述信号发射端传输控制信号，以控制所述信号发射端将所述第一测试信号、所述第三测试信号和功能信号中的一项输出。
  11. 根据权利要求10所述的芯片，其特征在于，所述控制电路还用于：
    向所述信号接收端输出控制信号，以控制所述信号接收端生成测试信号。
  12. 根据权利要求10或11所述的芯片，其特征在于，所述控制电路还用于：
    从所述信号接收端获得所述第一测试结果，基于所述第一测试结果，控制所述多路选择器的输入端和输出端之间连接关系的切换。
  13. 一种装置，其特征在于，包括第一芯片和第二芯片，所述第一芯片和第二芯片之间通过互联引脚连接；
    所述第一芯片，通过第一信号传输通路向所述第二芯片传输第一测试信号；
    所述第二芯片，基于所述第一测试信号和所述第二芯片所生成的测试信号，生成第一测试结果，所述第一测试结果用于指示所述第一信号传输通路是否发生故障；
    所述第二芯片，通过第二信号传输通路向所述第一芯片传输第二测试信号；
    所述第一芯片，基于所述第二测试信号和所述第一芯片所生成的测试信号，生成第二测试结果，所述第二测试结果用于指示所述第二信号传输通路是否发生故障；
    所述第一芯片，从所述第一芯片的测试信号输入引脚接收第三测试信号，将所述第三测试信号通过第三信号传输通路传输至所述第二芯片；
    所述第二芯片，将所述第三测试信号通过所述第二芯片中的测试信号输出引脚输出；
    其中，所述第一测试信号和所述第二测试信号为内建自测试BIST信号，所述第一信号传输通路和所述第二信号传输通路中未设置组合逻辑，所述第三信号传输通路中设置有组合逻辑。
  14. 根据权利要求13所示的装置，其特征在于，所述第一芯片包括第一内建自测试电路和第一扫描测试电路；
    所述第一内建自测试电路，包括第一信号发射端和第一信号接收端；
    所述第一信号发射端，用于生成所述第一测试信号；
    所述第二信号接收端，用于基于所述第二测试信号以及所生成的测试信号，生成所述第二测试结果；
    所述第一扫描测试电路，用于从所述测试信号输入引脚接收第三测试信号，将所述第三测试信号通过所述第三信号传输通路传输至所述第二芯片。
  15. 根据权利要求13或14所述的装置，其特征在于，所述第二芯片包括第二内建自测试电路和第二扫描测试电路；
    所述第二内建自测试电路，包括第二信号发射端和第二信号接收端；
    所述第二信号发射端，用于生成所述第二测试信号；
    所述第二信号接收端，用于基于所述第一测试信号以及所生成的测试信号，生成所述第一测试结果；
    所述第二扫描测试电路，用于从所述第一芯片接收第三测试信号，将所述第三测试信号通过所述第二芯片的测试信号输出引脚输出。
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