WO2023000388A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023000388A1
WO2023000388A1 PCT/CN2021/110550 CN2021110550W WO2023000388A1 WO 2023000388 A1 WO2023000388 A1 WO 2023000388A1 CN 2021110550 W CN2021110550 W CN 2021110550W WO 2023000388 A1 WO2023000388 A1 WO 2023000388A1
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WIPO (PCT)
Prior art keywords
layer
display panel
cathode
substrate
spacer
Prior art date
Application number
PCT/CN2021/110550
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English (en)
French (fr)
Inventor
金蒙
吕磊
袁涛
黄金昌
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/600,477 priority Critical patent/US20230209902A1/en
Publication of WO2023000388A1 publication Critical patent/WO2023000388A1/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/50—OLEDs integrated with light modulating elements, e.g. with electrochromic elements, photochromic elements or liquid crystal elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/82—Cathodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/842—Containers
    • H10K50/8428—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present invention relates to the field of display technology, in particular to a display panel and a display device.
  • Organic Light Emitting Diodes organic light emitting diode (OLED) display technology has attracted the attention of more and more scientific researchers, and has been widely used in display fields such as mobile phones, tablets, and TVs. With the rapid development of display devices, the screen ratio of users to display devices The increasingly high requirements make the comprehensive display device with large size and high resolution become the future development direction.
  • OLED organic light emitting diode
  • optical components such as the front camera and face recognition are usually arranged under the screen.
  • the entire surface of the cathode is usually evaporated for the display area. Due to the low transmittance of the cathode to visible light and near-infrared light, the camera, face recognition device, etc.
  • Optical components cannot receive sufficient optical signals, which affects the normal operation of optical components.
  • the existing display panel has the problem of insufficient light transmittance in the area of the display panel corresponding to the optical element arranged under the screen. Therefore, it is necessary to provide a display panel and a display device to improve this defect.
  • Embodiments of the present application provide a display panel and a display device, which are used to solve the problem of insufficient light transmittance in a region of the display panel corresponding to an optical element arranged under the screen existing in the existing display panel.
  • An embodiment of the present application provides a display panel, the display panel includes a first display area, and the display panel further includes:
  • the pixel definition layer is disposed on one side of the substrate;
  • the plurality of first spacers are distributed in the first display area at intervals, and are arranged on the side of the pixel definition layer away from the substrate;
  • a via hole is provided on the first spacer, and a first cathode suppression layer formed of a light-transmitting material is provided in the via hole.
  • the via hole in the thickness direction of the display panel, the via hole at least penetrates through the first spacer.
  • the via hole penetrates through the first spacer and the pixel definition layer.
  • a filling layer formed of a light-transmitting material is further disposed in the via hole, and the filling layer is disposed on a side of the first cathode suppression layer away from the substrate.
  • a surface of the filling layer facing away from the base is flush with a surface of the first spacer facing away from the base.
  • the via hole is further provided with a filling layer formed of a light-transmitting material, and the filling layer is disposed on a side of the first cathode suppression layer close to the substrate.
  • a surface of the first cathode suppression layer facing away from the substrate is flush with a surface of the first spacer facing away from the substrate.
  • the opening area of the via hole is the same as that of the end of the first spacer away from the base.
  • the ratio of the areas is greater than or equal to 0.5 and less than or equal to 0.9.
  • the display panel further includes a second display area and a plurality of second spacers distributed at intervals in the second display area, and the second spacers are connected to the first spacers. objects are disposed on the same side of the pixel definition layer;
  • the area of the end of the first spacer away from the base is greater than the area of the end of the second spacer away from the base.
  • a ratio of an area of an end of the second spacer facing away from the base to an area of an end of the first spacer facing away from the base is greater than or equal to 0.14 and less than or equal to 0.25.
  • the first display area is provided with a plurality of sub-pixel units arranged in an array, the first spacer is arranged between the plurality of sub-pixel units, and each of the sub-pixels
  • the unit includes an anode, and the anode is disposed on a side of the pixel definition layer close to the substrate;
  • the minimum distance between the orthographic projection of the via hole on the substrate and the orthographic projection of the adjacent anode on the substrate is greater than or equal to 2 microns and less than or equal to 5 microns.
  • the display panel further includes a plurality of second cathode suppression layers, and the plurality of second cathode suppression layers are disposed on the part of the pixel definition layer corresponding to the first display area, and located on between multiple sub-pixel units;
  • the orthographic projection of the first cathode suppression layer on the substrate is separated from the orthographic projection of the second cathode suppression layer on the substrate.
  • the orthographic projections of the first cathode suppression layer and the second cathode suppression layer on the substrate are both separated from the orthographic projections of the adjacent anodes on the substrate.
  • the display panel further includes a cathode layer, the cathode layer is disposed on the side of the pixel definition layer away from the substrate, the first cathode suppression layer and the second cathode suppression layer The thicknesses are all less than or equal to the thickness of the cathode layer.
  • the embodiment of the present application also provides a display device, the display device includes a display panel, the display panel includes a first display area, and the display panel further includes:
  • the pixel definition layer is disposed on one side of the substrate;
  • the plurality of first spacers are distributed in the first display area at intervals, and are arranged on the side of the pixel definition layer away from the substrate;
  • a via hole is provided on the first spacer, and a first cathode suppression layer formed of a light-transmitting material is provided in the via hole.
  • the via hole in the thickness direction of the display panel, the via hole at least penetrates through the first spacer.
  • the via hole penetrates through the first spacer and the pixel definition layer.
  • a filling layer formed of a light-transmitting material is further disposed in the via hole, and the filling layer is disposed on a side of the first cathode suppression layer away from the substrate.
  • a surface of the filling layer facing away from the base is flush with a surface of the first spacer facing away from the base.
  • the via hole is further provided with a filling layer formed of a light-transmitting material, and the filling layer is disposed on a side of the first cathode suppression layer close to the substrate.
  • the embodiments of the present application provide a display panel and a display device, the display panel includes a first display area and a second display area, and the display panel further includes a substrate, a pixel definition layer, and a plurality of A first spacer, the pixel definition layer is disposed on one side of the substrate, a plurality of the first spacers are distributed in the first display area at intervals, and disposed on the pixel definition layer away from the One side of the base, the first spacer is provided with a via hole, the opening of the via hole faces the side of the first spacer away from the base, and the via hole is provided with a light-transmitting
  • the first cathode suppression layer formed by the material when adopting the entire surface evaporation process to form the cathode layer, the first cathode suppression layer can make no cathode layer deposition in the via hole of the first spacer, thereby increasing the first The light transmittance of each first spacer in the display area, thereby increasing the
  • FIG. 1 is a schematic plan view of a display panel provided in an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of the first display panel provided by the embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a second display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a third display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a fourth display panel provided by an embodiment of the present application.
  • Fig. 6 is a schematic plan view of the first display area provided by the embodiment of the present application.
  • FIG. 7 is a schematic plan view of the second display area provided by the embodiment of the present application.
  • FIG. 8 is a schematic plan view of the second type of first display area provided by the embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a fifth display panel provided by an embodiment of the present application.
  • FIG. 10 is a flowchart of a method for manufacturing a display panel provided by an embodiment of the present application.
  • the embodiment of the present application provides a display panel 100, as shown in FIG. 1, which is a schematic plan view of the structure of the display panel provided in the embodiment of the present application.
  • the display panel 100 includes a first display area 101 and a second display area 102.
  • the shape of the first display area 101 on the plane where the display panel 100 is located is circular, and the second display area 102 is arranged around the first display area 101 .
  • the shape of the first display area 101 is not limited to the above-mentioned circular shape, and may also be oval, drop-shaped, or other irregular figures, etc., and the first display area 101 may be set on the display panel 100 any position.
  • the first display area 101 is an additional function area
  • the second display area 102 is a main display area for displaying screen images.
  • the first display area 101 can be used to display screen images, seamlessly connected with the display screen of the second display area 102, so that the display panel 100 can present the effect of a full-screen display, and can also be used as an image set on the display panel 100.
  • Optical elements such as a camera and a face recognition device below provide a channel for obtaining external light, so that the display panel 100 can realize functions such as off-screen camera and face recognition, and improve user experience.
  • the light transmittance of the first display area 101 is greater than the light transmittance of the second display area 102 . It can be understood that the light transmittance of the first display area 101 is related to the film layer structure of the part of the display panel 100 corresponding to the first display area 101, the greater the light transmittance of the first display area 101, the greater the external environment that the optical element can obtain The greater the amount of light, the better the optics will work. If the optical element is a camera, the higher the light transmittance of the first display area 101 is, the better the imaging effect of the camera will be.
  • FIG. 2 is a schematic structural diagram of a first display panel provided in an embodiment of the present application, and the display panel 100 includes a substrate 110, a pixel definition layer 120, and a plurality of first spacers Objects 130, the pixel definition layer 120 is disposed on one side of the substrate 110, a plurality of the first spacers 130 are distributed in the first display area 101 at intervals, and disposed on the side of the pixel definition layer 120 away from One side of the base 110.
  • Each of the first spacers 130 is provided with a via hole 131, the opening of the via hole 131 faces the side of the first spacer 130 away from the base 110, and the via hole 131 is set There is a first cathode suppression layer 140 formed of a light transmissive material.
  • the number of via holes 131 provided on each of the first spacers 130 is not limited to one in the above-mentioned embodiment, and two or more via holes 131 may also be provided, and the via holes 131 may be in The first spacers 130 are arranged continuously or at intervals.
  • FIG. 6 is a schematic plan view of the first display area provided by the embodiment of the present application.
  • a plurality of first sub-pixel units 150 are arranged in the first display area 101, so The first spacers 130 are disposed between the plurality of first sub-pixel units 150 .
  • Each of the first sub-pixel units 150 includes an anode 151, an organic light-emitting layer 152, and a cathode layer 153.
  • the anode 151 is disposed on the side of the pixel definition layer 120 close to the substrate 110, and a plurality of the pixel definition layers 120 are disposed on the
  • the first sub-pixel opening 121 exposes the anode 151
  • the organic light-emitting layer 152 is disposed in the first sub-pixel opening 121 and is located on the side of the anode 151 facing away from the substrate 110
  • the cathode layer 153 is formed by the entire surface evaporation process, covering the pixel Layer 120 and organic light emitting layer 152 are defined.
  • the adhesion between the first cathode suppression layer 140 and the cathode layer 153 is small or even mutually repulsive.
  • the adhesive force is greater than the adhesive force between the cathode layer 153 and the first cathode suppression layer 140, so that no cathode layer is deposited in the via hole 131 of the first spacer 130 or the thickness of the deposited cathode layer is relatively thin, so that The light transmittance of the first spacer 130 to the light in the visible light band and the near infrared light band is greatly improved, so that the overall light transmittance of the first display area 101 is improved without changing the process technology of the cathode layer 153 rate, so that the optical elements disposed under the display panel 100 corresponding to the first display area 101 can receive sufficient light signals.
  • the material of the first cathode suppression layer 140 can be BAlq (bis(2-methyl-8-hydroxyquinoline)-4-(p-phenylphenol) aluminum), TAZ (3- At least one of (biphenyl-4-yl)-5-(4-tert-butylphenyl)-4-phenyl-4H-1,2,4-triazole) and OTI (indium oxide), so
  • the material of the cathode layer 153 is metal magnesium. Metal magnesium has poor adhesion on BAlq, TAZ and OTI materials. When metal magnesium is evaporated to form the cathode layer 153 , the first cathode suppression layer 140 can inhibit metal magnesium from forming a film on the first cathode suppression layer 140 .
  • the plurality of first sub-pixel units 150 include a first red sub-pixel unit 156, a first green sub-pixel unit 157 and a first blue sub-pixel unit 158, the first red sub-pixel unit 156,
  • the first green sub-pixel unit 157 and the first blue sub-pixel unit 158 may be circular or elliptical, so that the distance between the plurality of first sub-pixel units 150 is sufficient to place the first spacer 130 .
  • a plurality of first red sub-pixel units 156, a plurality of first green sub-pixel units 157 and a plurality of first blue sub-pixel units 158 are distributed at intervals in the first display area 101 according to a certain rule, and the first spacers 130 It is arranged in the middle of a matrix formed by a first red sub-pixel unit 156 , a blue sub-pixel unit 158 and two first green sub-pixel units 157 oppositely arranged.
  • every eight first sub-pixel units 150 share one first spacer 130 .
  • not all first sub-pixel units 150 need to be provided with first spacers 130, and the number and positions of first spacers 130 can be set according to actual needs, and there is no limitation here. .
  • the via hole 131 at least penetrates through the first spacer 130 .
  • the via hole 131 penetrates through the first spacer 130 and exposes the pixel definition layer 120 at the bottom of the first spacer 130 .
  • the display panel 100 also includes a first auxiliary layer 154 and a second auxiliary layer 155. Both the first auxiliary layer 154 and the second auxiliary layer 155 are prepared by an entire surface evaporation process.
  • the first auxiliary layer 154 covers the anode 151, Simultaneously with the pixel definition layer 120 , it is also deposited and formed on the pixel definition layer 120 exposed by the via holes 131 .
  • the second auxiliary layer 155 is also deposited and formed on the first auxiliary layer 154 located in the via hole 131 .
  • the first auxiliary layer 154 , the second auxiliary layer 155 , and the first cathode suppression layer 140 are sequentially stacked in the via hole 131 along the direction away from the substrate 110 .
  • the first auxiliary layer 154 includes a hole injection layer and a hole transport layer sequentially stacked along a direction away from the substrate 110 , and the hole injection layer covers the anode 151 .
  • the second auxiliary layer 155 includes an electron transport layer and an electron injection layer stacked in sequence along a direction away from the substrate 110 , and the electron transport layer covers the organic light emitting layer 152 .
  • a filling layer 160 formed of a light-transmitting material is further disposed in the via hole 131 , and the filling layer 160 is disposed on a side of the first cathode suppression layer 140 away from the substrate 110 .
  • the first auxiliary layer 154 , the second auxiliary layer 155 and the first cathode suppression layer 140 are sequentially formed on the pixel definition layer 120 exposed by the via hole 131 , and the filling layer 160 is formed on the first cathode suppression layer 140 .
  • the first auxiliary layer 154, the second auxiliary layer 155 and the first cathode suppression layer 140 cannot completely fill the via hole 131, and the first spacer 130 will be away from the substrate. There is still a deep recess on one side of the surface of 110, which will affect the encapsulation performance of the encapsulation layer formed in the subsequent preparation, and may cause the encapsulation failure of the encapsulation layer.
  • Filling the via hole 131 with the filling layer 160 can reduce the degree of depression of the concave part of the surface of the first spacer 130 away from the base 110, and improve the flatness of the surface of the first spacer 130 away from the base 110. degree, thereby reducing the risk of encapsulation failure at the encapsulation layer.
  • the surface of the filling layer 160 facing away from the base 110 is flush with the surface of the first spacer 130 facing away from the base 110, so that the via hole 131 is filled with the filling layer 160, Making the surface of the first spacer 130 facing away from the substrate 110 have no recessed part is beneficial to the film formation of the orderly encapsulation layer, thereby reducing the risk of encapsulation failure of the encapsulation layer.
  • FIG. 3 is a schematic structural diagram of a second display panel provided in the embodiment of the present application.
  • the structure of the second display panel shown in FIG. 3 is the same as that of the first display panel shown in FIG.
  • the structures of the display panels of the two types are substantially the same, except that the filling layer 160 in the display panel of the second type shown in FIG. 3 is disposed on the side of the first cathode suppression layer 140 close to the substrate 110 .
  • the filling layer 160 is formed on the pixel definition layer 120 exposed by the via hole 131 , and the first auxiliary layer 154 , the second auxiliary layer 155 and the first cathode suppression layer 140 are sequentially formed on the filling layer 160 .
  • the preparation process by first forming the filling layer 160, and then sequentially forming the first auxiliary layer 154, the second auxiliary layer 155 and the first cathode suppression layer 140 on the filling layer 160, the second The same technical effects as the above display panels are not repeated here.
  • the surface of the first cathode suppression layer 140 facing away from the base 110 and the surface of the first spacer 130 facing away from the base 110 flush.
  • FIG. 4 is a schematic structural diagram of a third display panel provided in the embodiment of the present application.
  • the structure of the third display panel shown in FIG. 4 is the same as that of the first display panel shown in FIG.
  • the structures of the two types of display panels are roughly the same, the difference is that in the third type of display panel shown in FIG. and the pixel definition layer 120 .
  • the display panel 100 further includes a thin film transistor array layer 170 disposed between the pixel definition layer 120 and the substrate 110, the thin film transistor array layer 170 includes a flat layer on the side close to the pixel definition layer 120, the process
  • the hole 131 penetrates through the first spacer 130 and the pixel definition layer 120 and exposes the planar layer, and the first auxiliary layer 154, the second auxiliary layer 155 and the first cathode suppression layer 140 are sequentially formed on the
  • the filling layer 160 is formed on the first cathode suppression layer 140 .
  • the surface of the filling layer 160 facing away from the base 110 needs to be flush with the surface of the first spacer 130 facing away from the base 110 .
  • FIG. 5 is a schematic structural diagram of a fourth display panel provided in the embodiment of the present application.
  • the structure of the fourth display panel shown in FIG. 5 is the same as that of the third display panel shown in FIG.
  • the structures of the two display panels are substantially the same, the difference is that in the fourth display panel shown in FIG.
  • the filling layer 160 is formed on the flat layer exposed by the via hole 131, and the first auxiliary layer 154, the second auxiliary layer 155 and the first cathode suppression layer 140 are sequentially formed on the filling layer 160. superior. In order to ensure the encapsulation effect of the fourth type of display panel shown in FIG. 5 .
  • the opening area of the via hole 131 is the same as that of the first spacer 130 .
  • the area ratio of the end of the pad 130 facing away from the base 110 is 0.7.
  • the main function of the first spacer 130 is to support the mask, and to limit the ratio of the opening area of the via hole 131 to the area of the end of the first spacer 130 away from the substrate 110 is 0.7, while ensuring sufficient supporting performance of the first spacer 130, the opening area of the via hole 131 can be made large enough to reduce the area of the cathode layer 153 deposited on the first spacer 130, thereby improving the display The light transmittance of the panel 100 at the first spacer 130 .
  • the ratio of the opening area of the via hole 131 to the area of the end of the first spacer 130 facing away from the substrate 110 is not limited to 0.7, but can also be 0.5, 0.6, 0.8 or 0.9, etc., only It needs to be between 0.5 and 0.9.
  • the planar shape of the first spacer 130 is a square, and the lengths of the four sides are all 40 microns, so
  • the area of the first spacer 130 is 1600 square micrometers
  • the opening shape of the via hole 131 is circular
  • the area of the via hole 131 is 1120 square micrometers.
  • the length of the circumference of the first spacer 130 is not limited to 40 microns, but can also be 30 microns, 35 microns or 38 microns, and only needs to be between 30 microns and 40 microns.
  • the display panel 100 further includes a plurality of second spacers 180 , and a plurality of second spacers
  • the objects 180 are distributed between the sub-pixel units in the second display area 102 at intervals, and are disposed on the same side of the pixel definition layer 120 as the first spacers 130 .
  • the multiple second sub-pixel units 104 include a second green sub-pixel unit 105, a second red sub-pixel unit 106 and a second blue sub-pixel unit 107, and the second green sub-pixel unit 105
  • the plane shape is oval, and the plane shapes of the second red sub-pixel unit 106 and the second blue sub-pixel unit 107 are rectangle or rhombus.
  • the second spacer 180 is disposed in the middle of the matrix formed by two opposite second green sub-pixel units 105 , one second red sub-pixel unit 106 and one blue sub-pixel unit 107 .
  • the heights of the first spacer 130 and the second spacer 180 are equal, and the area of the end of the first spacer 130 facing away from the base 110 is larger than that of the second spacer 180 facing away from the base 110 .
  • the first spacer 130 has the functions of transmitting light and supporting the mask at the same time, and the second spacer 180 only needs to have the function of supporting the mask.
  • the area of the end of the second spacer 180 away from the base 110 is smaller than the area of the end of the first spacer 130 away from the base 110 , it is possible to reduce the occupation of the second spacer 180 in the second display area 102 .
  • the area of the second sub-pixel unit 104 ensures that the display effect of the second display area 102 is not affected.
  • the ratio of the area of the end of the second spacer 180 away from the base 110 to the area of the end of the first spacer 130 away from the base 110 is 0.14.
  • the planar shape of the second spacer 180 is also a square, and the length of the surrounding area of the second spacer 180 is 15 microns, and the area of the second spacer 180 is 225 square microns.
  • the ratio of the area of the second spacer 180 to the area of the first spacer 130 is not limited to 0.14, but can also be 0.16, 0.2 or 0.25, etc., and only needs to be between 0.14 and 0.25. time.
  • the minimum distance T1 between the orthographic projection of the via hole 131 on the substrate 110 and the orthographic projection of the adjacent anode 151 on the substrate is 3 micrometers. It can be understood that due to the limitation of the precision of the manufacturing process, the distance between the via hole 131 and the adjacent anode 151 is too small, which may expose the adjacent anode 151 during the process of etching the via hole 131, resulting in the formation of deposition.
  • the first cathode suppression layer 140 is in contact with the anode 151 and affects the electrical properties of the anode 151 .
  • the distance T1 between the orthographic projection of the via hole 131 on the substrate 110 and the orthographic projection of the adjacent anode 151 on the substrate to be 3 microns, the contact between the first cathode suppression layer 140 and the adjacent anode 151 can be avoided, thereby ensuring that the anode 151 electrical properties.
  • the distance between the orthographic projection of the via hole 131 on the substrate 110 and the orthographic projection of the adjacent anode 151 on the substrate is not limited to 3 microns, and may also be 2 microns, 4 microns or 5 microns, etc., only need to be between 2 microns and 5 microns.
  • Figure 8 is a schematic plan view of the second type of first display area provided by the embodiment of the present application
  • Figure 9 is a fifth type of display panel provided by the embodiment of the present application
  • the structural schematic diagram of the display panel 100 further includes a plurality of second cathode suppression layers 190, and the plurality of second cathode suppression layers 190 are arranged on the part of the pixel definition layer 120 corresponding to the first display area 101, And between the plurality of first sub-pixel units 150, the orthographic projection of the first cathode suppression layer 140 on the substrate 110 is separated from the orthographic projection of the second cathode suppression layer 190 on the substrate 110 .
  • the material of the second cathode suppression layer 190 is the same as that of the first cathode suppression layer 140, and the adhesive force between the plurality of first sub-pixel units 150 in the first display area 101 and the cathode layer
  • the second cathode suppression layer 190 that is smaller or even mutually repulsive, when adopting the entire surface vapor deposition process to form the cathode layer, can make the thickness of the cathode layer deposited on the second cathode suppression layer 190 thinner or have no cathode layer deposition, thereby
  • the light transmittance between the plurality of first sub-pixel units 150 in the first display area 101 is increased, thereby further improving the overall light transmittance of the first display area 101 .
  • the orthographic projections of the first cathode suppression layer 140 and the second cathode suppression layer 190 on the substrate 110 are far away from the orthographic projections of the anode 151 on the substrate 110 .
  • the orthographic projection of the anode 151 on the substrate 110 will cover the orthographic projection of the first sub-pixel opening 121 on the substrate 110, and in order to ensure the normal display of each sub-pixel unit in the first display area 101, it is necessary to ensure that the cathode
  • the orthographic projection of the layer on the substrate 110 covers the orthographic projection of the first sub-pixel opening 121 on the substrate, and by setting the first cathode suppression layer 140 and the second cathode suppression layer 190 to not overlap with the anode 151, it can be guaranteed
  • the first cathode suppression layer 140 and the second cathode suppression layer 190 keep a certain distance from the first sub-pixel opening 121, while ensuring that the positive projection of the cathode layer 153 on the substrate 110 can cover the first sub-pixel opening 121 on the substrate 110.
  • Orthographic projection prevents the arrangement of the first cathode suppression layer 140 and the second cathode suppression layer 190 from causing interference and adverse effects on the display of the first display area 101
  • the thicknesses of the first cathode suppression layer 140 and the second cathode suppression layer 190 are both smaller than or equal to the thickness of the cathode layer 153 .
  • the first cathode suppression layer 140 and the second cathode suppression layer 190 have the same thickness, and are prepared by using the same fine mask plate through the same evaporation process. It can be understood that the first cathode suppression layer 140 and the second cathode suppression layer 190 can prevent the deposition of the cathode layer 153 thereon, by limiting the thickness of the first cathode suppression layer 140 and the second cathode suppression layer 190 to Less than or equal to the thickness of the cathode layer 153, can avoid the cathode layer 153 and the first cathode suppression layer 140 and the second cathode suppression layer 190 to produce a larger film layer difference, thereby ensuring that the packaging performance of the packaging layer of the display panel 100 is not good. Affected.
  • the shape of the second cathode suppression layer 190 may be a rectangle as shown in FIG. 8 , or For other polygons or circles, ellipses and other shapes.
  • the shape of the second cathode suppression layer 190 can be set according to requirements, which is not limited here.
  • the embodiment of the present application also provides a display device, the display device includes a device main body and a display panel, the device main body includes a housing, a power supply module, a processor module, a camera module, etc. on the body of the device.
  • the display panel may be the display panel provided in the above embodiment, and the display panel in the display device provided in the embodiment of the present application may achieve the same technical effect as the display panel provided in the above embodiment, which will not be repeated here.
  • FIG. 10 is a flow chart of the method for manufacturing a display panel provided by the embodiment of the present application.
  • the display panel 100 includes a first display area 101 and a second display area 102, the display panel 100 includes a base 110, a pixel definition layer 120 disposed on one side of the base 110, and a plurality of first spacers 130, A plurality of the first spacers 130 are distributed in the first display area 101 at intervals, and are arranged on the side of the pixel definition layer 120 away from the base 110.
  • the pixel definition layer 120 is provided with a A plurality of first sub-pixel openings 121 of a display area 101 , the first sub-pixel openings 121 expose the anode 151 at the bottom of the pixel definition layer 120 .
  • the manufacturing method of the display panel includes:
  • Step S10 forming a via hole 131 on the first spacer 130, the via hole 131 is recessed from the side of the first spacer 130 away from the base 110 toward the base 110;
  • Step S20 forming a first auxiliary layer 154 on the pixel definition layer 120 and in the via hole 131, the first auxiliary layer 154 covering the anode 151;
  • Step S30 forming an organic light emitting layer 152 on the first auxiliary layer 154 in the first sub-pixel opening 121;
  • Step S40 forming a second auxiliary layer 155 on the first auxiliary layer 154, the second auxiliary layer 155 covering the organic light-emitting layer 152;
  • Step S50 forming a first cathode suppression layer 140 on the second auxiliary layer 155 located in the via hole 131 by using a light-transmitting material;
  • Step S60 forming a cathode layer on the second auxiliary layer 155;
  • Step S70 forming a filling layer 160 on the first cathode suppression layer 140 in the via hole 131 by using a light-transmitting material.
  • the distance between the orthographic projection of the via hole 131 on the substrate 110 and the orthographic projection of the adjacent anode 151 on the substrate 110 is greater than or equal to 2 microns and less than or equal to 5 microns. Micron.
  • a via hole 131 is formed on each of the first spacers 130 by using a photolithography process.
  • the steps S20 , S40 and S60 all use the same common mask to vapor-deposit the first auxiliary layer 154 , the second auxiliary layer 155 and the cathode layer respectively.
  • the organic light emitting layer 152 is formed in the first sub-pixel opening 121 and the second sub-pixel opening 122 by using a first fine metal mask.
  • the first cathode suppression layer 140 is formed on the second auxiliary layer 155 in the via hole 131 by using a second fine metal mask.
  • the first cathode suppression layer 140 is formed on the second auxiliary layer 155 in the via hole 131 by using a second fine metal mask, and at the same time A second cathode suppression layer 190 is formed between the plurality of first sub-pixel units 150 in the display area 101 .
  • the orthographic projections of the first cathode suppression layer 140 and the second cathode suppression layer 190 on the substrate 110 are far away from the orthographic projections of the adjacent anode 151 on the substrate 110 .
  • the display panel 100 further includes a cathode layer 153, the cathode layer 153 is disposed on the side of the pixel definition layer 120 away from the substrate 110, the first cathode suppression layer 140 and the The thickness of the second cathode suppression layer 190 is less than or equal to the thickness of the cathode layer 153 .
  • the second display area 102 is provided with a plurality of second spacers 180 distributed at intervals, and the heights of the second spacers 180 and the first spacers 130 are equal to each other.
  • the ratio of the area of the second spacer 180 to the area of the first spacer 130 is greater than or equal to 0.14 and less than Or equal to 0.25.
  • the ratio of the opening area of the via hole 131 to the area of the first spacer 130 is Greater than or equal to 0.5 and less than or equal to 0.9.
  • the via hole 131 passes through the first spacer 130 .
  • the via hole 131 penetrates through the first spacer 130 and the pixel definition layer 120 .
  • the step S70 can be performed before the step S20, that is, the filling layer 160 is first formed in the via hole 131 using a light-transmitting material, and then the steps S20 to S60 are performed to sequentially form the first auxiliary layer 160 on the filling layer 160.
  • layer 154 , second auxiliary layer 155 and first cathode suppression layer 140 can be performed before the step S20, that is, the filling layer 160 is first formed in the via hole 131 using a light-transmitting material, and then the steps S20 to S60 are performed to sequentially form the first auxiliary layer 160 on the filling layer 160.
  • layer 154 , second auxiliary layer 155 and first cathode suppression layer 140 can be performed before the step S20, that is, the filling layer 160 is first formed in the via hole 131 using a light-transmitting material, and then the steps S20 to S60 are performed to sequentially form the first auxiliary layer 160 on the filling layer 160.
  • the first auxiliary layer 154 includes a hole injection layer and a hole transport layer sequentially stacked along a direction away from the substrate 110 , and the hole injection layer covers the anode 151 .
  • the second auxiliary layer 155 includes an electron transport layer and an electron injection layer stacked in sequence along a direction away from the substrate 110 , and the electron transport layer covers the organic light emitting layer 152 .
  • the embodiments of the present application provide a display panel, a manufacturing method thereof, and a display device.
  • the display panel includes a first display area and a second display area, and the display panel further includes a substrate, a pixel definition layer, and a multilayer a first spacer, the pixel definition layer is disposed on one side of the substrate, a plurality of the first spacers are distributed in the first display area at intervals, and are disposed on the pixel definition layer away from the pixel definition layer
  • One side of the base, the first spacer is provided with a via hole, the via hole is formed by the side of the first spacer away from the base and is recessed toward the base, and the inside of the via hole
  • a first cathode suppression layer formed of a light-transmitting material is provided.
  • the first cathode suppression layer can make no cathode layer deposited in the via hole of the first spacer, so that This increases the light transmittance of each first spacer in the first display area, thereby increasing the light transmittance of the first display area.

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Abstract

一种显示面板(100)及显示装置，显示面板(100)包括第一显示区(101)，显示面板(100)还包括基底(110)、像素定义层(120)和第一隔垫物(130)，第一隔垫物(130)上设置有过孔(131)，过孔(131)内设置有第一阴极抑制层(140)，第一阴极抑制层(140)可以使第一隔垫物(130)的过孔(131)中无阴极层(153)沉积，以此增大第一显示区(101)中各个第一隔垫物(130)的透光率，从而提升第一显示区(101)的透光率。

Description

显示面板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板及显示装置。
 背景技术
有机发光二极管（organic light emitting diode, OLED）显示技术受到了越来越多科研工作者的关注，并被广泛应用于手机、平板和电视等显示领域，而随着显示设备的快速发展，用户对显示设备的屏占比的要求越来越高，使得大尺寸和高分辨率的全面显示设备成为未来的发展方向。
 技术问题
在现有技术当中，为了尽可能的提升屏占比，通常采用将前置摄像头和面部识别等光学元件设置在屏下。但是，在现有的OLED全面显示设备中，针对显示区域通常采用整面蒸镀阴极，由于阴极对可见光和近红外波段光的透过率低，导致设置在屏下的摄像头、面部识别装置等光学元件无法接收到充足的光信号，影响光学元件的正常工作。
综上所述，现有显示面板存在显示面板与设置在屏下的光学元件对应的区域的透光率不足的问题。故，有必要提供一种显示面板及显示装置来改善这一缺陷。
 技术解决方案
本申请实施例提供一种显示面板及显示装置，用于解决现有显示面板存在的显示面板与设置在屏下的光学元件对应的区域的透光率不足的问题。
本申请实施例提供一种显示面板，所述显示面板包括第一显示区，所述显示面板还包括：
基底；
像素定义层，所述像素定义层设置于所述基底的一侧；
多个第一隔垫物，多个所述第一隔垫物间隔分布于所述第一显示区，并且设置于所述像素定义层背离所述基底的一侧；
其中，所述第一隔垫物上设置有过孔，所述过孔内设置有由透光材料形成的第一阴极抑制层。
根据本申请一实施例，在所述显示面板的厚度方向上，所述过孔至少贯穿所述第一隔垫物。
根据本申请一实施例，在所述显示面板的厚度方向上，所述过孔贯穿所述第一隔垫物和所述像素定义层。
根据本申请一实施例，所述过孔内还设置有由透光材料形成的填充层，所述填充层设置于所述第一阴极抑制层背离所述基底的一侧。
根据本申请一实施例，所述填充层背离所述基底的一侧表面与所述第一隔垫物背离所述基底的一侧表面齐平。
根据本申请一实施例，所述过孔还设置有由透光材料形成的填充层，所述填充层设置于所述第一阴极抑制层靠近所述基底的一侧。
根据本申请一实施例，所述第一阴极抑制层背离所述基底的一侧表面与所述第一隔垫物背离所述基底的一侧表面齐平。
根据本申请一实施例，在所述第一隔垫物背离所述基底的一侧表面所在的平面上，所述过孔的开口面积与所述第一隔垫物背离所述基底的一端的面积的比例大于或等于0.5且小于或等于0.9。
根据本申请一实施例，所述显示面板还包括第二显示区和多个间隔分布于所述第二显示区的第二隔垫物，所述第二隔垫物与所述第一隔垫物设置于所述像素定义层的同一侧；
其中，所述第一隔垫物背离所述基底的一端的面积大于所述第二隔垫物背离所述基底的一端的面积。
根据本申请一实施例，所述第二隔垫物背离所述基底的一端的面积与所述第一隔垫物背离所述基底的一端的面积的比例大于或等于0.14且小于或等于0.25。
根据本申请一实施例，所述第一显示区内设置有呈阵列分布的多个子像素单元，所述第一隔垫物设置于多个所述子像素单元之间，每一个所述子像素单元包括阳极，所述阳极设置于所述像素定义层靠近所述基底的一侧；
其中，所述过孔在所述基底的正投影与相邻所述阳极在所述基底的正投影之间的最小距离大于或等于2微米且小于或等于5微米。
根据本申请一实施例，所述显示面板还包括多个第二阴极抑制层，多个所述第二阴极抑制层设置于所述像素定义层对应所述第一显示区的部分上，并且位于多个所述子像素单元之间；
其中，所述第一阴极抑制层在所述基底的正投影与所述第二阴极抑制层在所述基底的正投影相离。
根据本申请一实施例，所述第一阴极抑制层和所述第二阴极抑制层在所述基底的正投影均与相邻的所述阳极在所述基底的正投影相离。
根据本申请一实施例，所述显示面板还包括阴极层，所述阴极层设置于所述像素定义层背离所述基底的一侧，所述第一阴极抑制层和所述第二阴极抑制层的厚度均小于或等于所述阴极层的厚度。
本申请实施例还提供一种显示装置，所述显示装置包括显示面板，所述显示面板包括第一显示区，所述显示面板还包括：
基底；
像素定义层，所述像素定义层设置于所述基底的一侧；
多个第一隔垫物，多个所述第一隔垫物间隔分布于所述第一显示区，并且设置于所述像素定义层背离所述基底的一侧；
其中，所述第一隔垫物上设置有过孔，所述过孔内设置有由透光材料形成的第一阴极抑制层。
根据本申请一实施例，在所述显示面板的厚度方向上，所述过孔至少贯穿所述第一隔垫物。
根据本申请一实施例，在所述显示面板的厚度方向上，所述过孔贯穿所述第一隔垫物和所述像素定义层。
根据本申请一实施例，所述过孔内还设置有由透光材料形成的填充层，所述填充层设置于所述第一阴极抑制层背离所述基底的一侧。
根据本申请一实施例，所述填充层背离所述基底的一侧表面与所述第一隔垫物背离所述基底的一侧表面齐平。
根据本申请一实施例，所述过孔还设置有由透光材料形成的填充层，所述填充层设置于所述第一阴极抑制层靠近所述基底的一侧。
 有益效果
本揭示实施例的有益效果：本申请实施例提供一种显示面板及显示装置，所述显示面板包括第一显示区和第二显示区，所述显示面板还包括基底、像素定义层和多个第一隔垫物，所述像素定义层设置于所述基底的一侧，多个所述第一隔垫物间隔分布于所述第一显示区，并且设置于所述像素定义层背离所述基底的一侧，所述第一隔垫物上设置有过孔，所述过孔的开口朝向所述第一隔垫物背离所述基底的一侧，所述过孔内设置有由透光材料形成的第一阴极抑制层，在采用整面蒸镀工艺形成阴极层时，第一阴极抑制层可以使所述第一隔垫物的过孔中无阴极层沉积，以此增大第一显示区中各个第一隔垫物的透光率，从而提升第一显示区的透光率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的平面结构示意图；
图2为本申请实施例提供的第一种显示面板的结构示意图；
图3为本申请实施例提供的第二种显示面板的结构示意图；
图4为本申请实施例提供的第三种显示面板的结构示意图；
图5为本申请实施例提供的第四种显示面板的结构示意图；
图6为本申请实施例提供的第一种第一显示区的平面结构示意图；
图7为本申请实施例提供的第二显示区的平面结构示意图；
图8为本申请实施例提供的第二种第一显示区的平面结构示意图；
图9为本申请实施例提供的第五种显示面板的结构示意图；
图10为本申请实施例提供的显示面板的制作方法的流程图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本揭示可用以实施的特定实施例。本揭示所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做进一步的说明：
本申请实施例提供一种显示面板100，如图1所示，图1为本申请实施例提供的显示面板的平面结构示意图，所述显示面板100包括第一显示区101和第二显示区102，所述第一显示区101在所述显示面板100所在平面的形状为圆形，所述第二显示区102围绕所述第一显示区101设置。
在实际应用中，所述第一显示区101的形状不仅限于上述的圆形，也可以为椭圆形、水滴形、或者其他不规则图形等，第一显示区101可以设置于显示面板100上的任意位置。
需要说明的是，所述第一显示区101为功能附加区，所述第二显示区102为用于显示画面图像的主显示区。所述第一显示区101既可以用于显示画面图像，与第二显示区102的显示画面无缝衔接，从而使得显示面板100可以呈现全面屏显示的效果，同时还可以作为设置在显示面板100下方的摄像头、人脸识别装置等光学元件提供获取外界光线的通道，从而使得显示面板100可以实现屏下摄像、人脸识别等功能，提高用户的体验。
在一实施例中，所述第一显示区101的透光率大于所述第二显示区102的透光率。可以理解的是，第一显示区101的透光率与显示面板100对应第一显示区101部分的膜层结构相关，第一显示区101的透光率越大，光学元件可以获取的外界环境光线量越多，光学元件的工作效果更好。若光学元件为摄像头，第一显示区101的透光率越高，摄像头的成像效果越好。
在一实施例中，如图2所示，图2为本申请实施例提供的第一种显示面板的结构示意图，所述显示面板100包括基底110、像素定义层120和多个第一隔垫物130，所述像素定义层120设置于所述基底110的一侧，多个所述第一隔垫物130间隔分布于所述第一显示区101，并且设置于所述像素定义层120背离所述基底110的一侧。
每一个所述第一隔垫物130上设置有一个过孔131，所述过孔131的开口朝向所述第一隔垫物130背离所述基底110的一侧，所述过孔131内设置有由透光材料形成的第一阴极抑制层140。在实际应用中，每一个所述第一隔垫物130上设置的过孔131的数量不仅限于上述实施例中的1个，也可以设置2个及以上的过孔131，过孔131可以在第一隔垫物130上呈连续排布或间隔排布。
结合图2和图6所示，图6为本申请实施例提供的第一种第一显示区的平面结构示意图，所述第一显示区101内设置有多个第一子像素单元150，所述第一隔垫物130设置于多个第一子像素单元150之间。每一个所述第一子像素单元150包括阳极151、有机发光层152和阴极层153，所述阳极151设置于像素定义层120靠近基底110的一侧，像素定义层120上设置的多个所述第一子像素开口121暴露出阳极151，有机发光层152设置于第一子像素开口121中并位于阳极151背离基底110的一侧上，阴极层153采用整面蒸镀工艺形成，覆盖像素定义层120和有机发光层152。
需要说明的是，所述第一阴极抑制层140与阴极层153的粘合力较小甚至相斥，采用整面蒸镀工艺形成阴极层153时，由于阴极层153与其他膜层之间的粘合力大于阴极层153与第一阴极抑制层140之间的粘合力，使得第一隔垫物130的过孔131中无阴极层沉积或者沉积的阴极层的厚度较薄，以此使第一隔垫物130区域对可见光波段和近红外光波段的光线的透光率得到极大提升，从而在不改变阴极层153的制程工艺的前提下，提升第一显示区101整体的透光率，使得设置在显示面板100对应第一显示区101下方的光学元件可以接收到充足的光信号。
在一实施例中，所述第一阴极抑制层140的材料可以为BAlq(双(2-甲基-8-羟基喹啉)-4-(对苯基苯酚)合铝)、TAZ(3-(联苯-4-基)-5-(4-叔丁基苯基)-4-苯基-4H-1,2,4-三唑)及OTI（氧化铟）中的至少一种，所述阴极层153的材料为金属镁。金属镁在BAlq、TAZ和OTI材料上的附着力较差，在蒸镀金属镁形成阴极层153时，第一阴极抑制层140可以抑制金属镁在第一阴极抑制层140上成膜。
在一实施例中，所述多个第一子像素单元150包括第一红色子像素单元156、第一绿色子像素单元157和第一蓝色子像素单元158，第一红色子像素单元156、第一绿色子像素单元157和第一蓝色子像素单元158可以呈圆形或者椭圆形，以使多个第一子像素单元150之间的间距足够放置第一隔垫物130。
多个第一红色子像素单元156、多个第一绿色子像素单元157和多个第一蓝色子像素单元158按照一定的规律在第一显示区101内间隔分布，第一隔垫物130设置在由一个第一红色子像素单元156与一个蓝色子像素单元158以及相对设置的两个第一绿色子像素单元157围合形成的矩阵的中间。
需要说明的是，在本申请实施例中，每8个第一子像素单元150共用一个第一隔垫物130。在实际应用中，并不是所有的第一子像素单元150之间均需要设置有第一隔垫物130，第一隔垫物130设置的数量以及位置可以实际需求设定，此处不做限制。
在一实施例中，在所述显示面板100的厚度方向上，所述过孔131至少贯穿所述第一隔垫物130。
如图2所示，过孔131贯穿所述第一隔垫物130，并且暴露出位于第一隔垫物130底部的像素定义层120。显示面板100还包括第一辅助层154和第二辅助层155，第一辅助层154和第二辅助层155均采用整面蒸镀工艺制备而成，第一辅助层154覆盖所述阳极151、像素定义层120的同时，还沉积形成在过孔131所暴露出的像素定义层120上。第二辅助层155在覆盖有机发光层152、第一辅助层154的同时，还沉积形成在位于过孔131中的第一辅助层154上。如此，使得过孔131中形成有沿远离基底110的方向依次层叠设置的第一辅助层154、第二辅助层155和第一阴极抑制层140。
具体的，第一辅助层154包括沿远离基底110的方向依次层叠设置的空穴注入层和空穴传输层，空穴注入层覆盖阳极151。第二辅助层155包括沿远离基底110的方向依次层叠设置的电子传输层和电子注入层，电子传输层覆盖有机发光层152。
进一步的，如图2所示，过孔131中还设置有由透光材料形成的填充层160，填充层160设置于第一阴极抑制层140背离所述基底110的一侧。
具体的，第一辅助层154、第二辅助层155和第一阴极抑制层140依次形成于过孔131所暴露出的像素定义层120上，填充层160形成于第一阴极抑制层140上。可以理解的是，当过孔131的深度较大时，第一辅助层154、第二辅助层155以及第一阴极抑制层140无法完全填充过孔131，会使第一隔垫物130背离基底110的一侧表面仍存在较深的凹陷的部分，如此会影响后续制备形成的封装层的封装性能，可能会导致封装层封装失效的问题。利用填充层160对过孔131进行填充，可以减小第一隔垫物130背离基底110的一侧表面的凹陷部分的凹陷程度，提高第一隔垫物130背离基底110的一侧表面的平整度，从而降低封装层封装失效的风险。
优选的，所述填充层160背离所述基底110的一侧表面与所述第一隔垫物130背离所述基底110的一侧表面齐平，如此通过填充层160对过孔131进行填充，使得第一隔垫物130背离基底110的一侧表面无凹陷的部分，有利于有序封装层成膜的效果，从而降低封装层封装失效的风险。
在一实施例中，如图3所述，图3为本申请实施例提供的第二种显示面板的结构示意图，图3所示的第二种显示面板的结构与图2所示的第一种显示面板的结构大致相同，区别之处在于：图3所示的第二种显示面板中的填充层160设置于第一阴极抑制层140靠近所述基底110的一侧。
具体的，填充层160形成于过孔131暴露出的像素定义层120上，第一辅助层154、第二辅助层155和第一阴极抑制层140依次形成于填充层160上。在制备过程中，通过先形成填充层160，再在填充层160上依次形成第一辅助层154、第二辅助层155和第一阴极抑制层140，同样可以获得与图2所示的第二种显示面板相同的技术效果，此处不再赘述。
进一步的，为保证显示面板100中封装层的封装效果，所述第一阴极抑制层140背离所述基底110的一侧表面与所述第一隔垫物130背离所述基底110的一侧表面齐平。
在一实施例中，如图4所示，图4为本申请实施例提供的第三种显示面板的结构示意图，图4所示的第三种显示面板的结构与图2所示的第一种显示面板的结构大致相同，区别之处在于：图4所示的第三种显示面板中，在所述显示面板100的厚度方向上，所述过孔131贯穿所述第一隔垫物130和所述像素定义层120。
具体的，所述显示面板100还包括设置于像素定义层120与所述基底110之间的薄膜晶体管阵列层170，薄膜晶体管阵列层170包括靠近像素定义层120一侧的平坦层，所述过孔131贯穿所述第一隔垫物130和所述像素定义层120并暴露出所述平坦层，所述第一辅助层154、第二辅助层155和第一阴极抑制层140依次形成于过孔131所暴露出的平坦层上，填充层160形成于第一阴极抑制层140上。为保证图4所示的第三种显示面板的封装效果，填充层160背离基底110的一侧表面需要与第一隔垫物130背离基底110的一侧表面齐平。
在一实施例中，如图5所示，图5为本申请实施例提供的第四种显示面板的结构示意图，图5所示的第四种显示面板的结构与图4所示的第三种显示面板的结构大致相同，区别之处在于，图5所示的第四种显示面板中，填充层160设置于第一阴极抑制层140靠近所述基底110的一侧。
具体的，所述填充层160形成于所述过孔131暴露出的平坦层上，所述第一辅助层154、第二辅助层155和第一阴极抑制层140依次形成于所述填充层160上。为保证图5所示的第四种显示面板的封装效果。
在一实施例中，结合图2和图6，在所述第一隔垫物130背离所述基底110的一侧表面所在的平面上，所述过孔131的开口面积与所述第一隔垫物130背离所述基底110的一端的面积的比例为0.7。
可以理解的是，第一隔垫物130的主要作用在于支撑掩膜板，将所述过孔131的开口面积与所述第一隔垫物130背离所述基底110的一端的面积的比例限定为0.7，可以在保证第一隔垫物130足够的支撑性能的同时，使过孔131的开口面积足够大，以此减少第一隔垫物130上沉积的阴极层153的面积，从而提高显示面板100在第一隔垫物130处的透光率。在实际应用中，所述过孔131的开口面积与所述第一隔垫物130背离所述基底110的一端的面积的比例不仅限于0.7，还可以为0.5、0.6、0.8或者0.9等，仅需要介于0.5至0.9之间即可。
具体的，在所述第一隔垫物130背离所述基底110的一侧表面所在的平面上，所述第一隔垫物130的平面形状为正方形，四边的边长均为40微米，所述第一隔垫物130的面积为1600平方微米，所述过孔131的开口形状为圆形，所述过孔131的面积为1120平方微米。在实际应用中，所述第一隔垫物130的四周变长不仅限于40微米，还可以为30微米、35微米或者38微米等，仅需要介于30微米至40微米之间即可。
在一实施例中，如图7所示，图7为本申请实施例提供的第二显示区的平面结构示意图，显示面板100还包括多个第二隔垫物180，多个第二隔垫物180间隔分布于第二显示区102中的多个子像素单元之间，并且与第一隔垫物130设置于所述像素定义层120的同一侧。
在一实施例中，多个所述第二子像素单元104包括第二绿色子像素单元105、第二红色子像素单元106和第二蓝色子像素单元107，第二绿色子像素单元105的平面形状呈椭圆形，第二红色子像素单元106和第二蓝色子像素单元107的平面形状呈矩形或者菱形等。第二隔垫物180设置在由两个相对设置的第二绿色子像素单元105以及一个第二红色子像素单元106和一个蓝色子像素单元107围合形成的矩阵的中间。
所述第一隔垫物130与所述第二隔垫物180的高度相等，所述第一隔垫物130背离所述基底110的一端的面积大于所述第二隔垫物180背离所述基底110的一端的面积。
可以理解的是，所述第一隔垫物130同时兼具透光和支撑掩膜板的作用，第二隔垫物180仅需要具有支撑掩膜板的作用即可。通过限定第二隔垫物180背离所述基底110的一端的面积小于第一隔垫物130背离所述基底110的一端的面积，可以减少第二隔垫物180占据第二显示区102中各第二子像素单元104的面积，从而保证第二显示区102的显示效果不受影响。
进一步的，所述第二隔垫物180背离所述基底110的一端与所述第一隔垫物130背离所述基底110的一端的面积的比例为0.14。
具体的，所述第二隔垫物180的平面形状也为正方形，第二隔垫物180的四周变长均为15微米，所述第二隔垫物180的面积为225平方微米。在实际应用中，所述第二隔垫物180的面积与所述第一隔垫物130的面积的比例不仅限于0.14，还可以为0.16、0.2或者0.25等，仅需要介于0.14至0.25之间即可。
在一实施例中，如图2所示，所述过孔131在所述基底110的正投影与相邻所述阳极151在所述基底的正投影之间的最小距离T1为3微米。可以理解的是，由于制程工艺精度的限制，过孔131与相邻阳极151之间的距离过小，可能会在刻蚀形成过孔131的过程中，暴露出相邻阳极151，导致沉积形成的第一阴极抑制层140与阳极151发生接触，影响阳极151的电学性能。通过限定过孔131在基底110的正投影与相邻阳极151在基底的正投影之间的距离T1为3微米，可以避免第一阴极抑制层140与相邻阳极151发生接触，从而保证阳极151的电学性能。
在实际应用中，所述过孔131在所述基底110的正投影与相邻所述阳极151在所述基底的正投影之间的距离不仅限于3微米，也可以为2微米、4微米或者5微米等，仅需要介于2微米至5微米之间即可。
在一实施例中，如图8和图9所示，图8为本申请实施例提供的第二种第一显示区的平面结构示意图，图9为本申请实施例提供的第五种显示面板的结构示意图，所述显示面板100还包括多个第二阴极抑制层190，多个所述第二阴极抑制层190设置于所述像素定义层120对应所述第一显示区101的部分上，并且位于多个所述第一子像素单元150之间，所述第一阴极抑制层140在所述基底110的正投影与所述第二阴极抑制层190在所述基底110的正投影相离。
具体的，所述第二阴极抑制层190与所述第一阴极抑制层140的材料相同，通过在第一显示区101中的多个第一子像素单元150之间设置与阴极层粘合力较小甚至相斥的第二阴极抑制层190，在采用整面蒸镀工艺形成阴极层时，可以使第二阴极抑制层190上沉积的阴极层厚度较薄或者没有阴极层沉积，从而在不改变阴极层的制程工艺的前提下，增大第一显示区101中多个第一子像素单元150之间的透光率，从而进一步提升第一显示区101整体的透光率。
进一步的，所述第一阴极抑制层140和所述第二阴极抑制层190在所述基底110的正投影均与所述阳极151在所述基底110的正投影相离。
需要说明的是，阳极151在基底110上的正投影会覆盖第一子像素开口121在基底110上的正投影，而为了保证第一显示区101中各子像素单元的正常显示，需要保证阴极层在基底110上的正投影覆盖所述第一子像素开口121在所述基底上的正投影，通过将第一阴极抑制层140和第二阴极抑制层190与阳极151设置不重合，可以保证第一阴极抑制层140和第二阴极抑制层190与第一子像素开口121保持一定的间距，同时保证阴极层153在基底110上的正投影可以覆盖第一子像素开口121在基底110上的正投影，防止第一阴极抑制层140和第二阴极抑制层190的设置对第一显示区101的显示造成干扰和不良影响。
进一步的，所述第一阴极抑制层140和所述第二阴极抑制层190的厚度均小于或等于所述阴极层153的厚度。
具体的，所述第一阴极抑制层140和所述第二阴极抑制层190的厚度相同，并且通过采用同一精细掩膜版通过同一蒸镀工艺制备而成。可以理解的是，第一阴极抑制层140和第二阴极抑制层190可以防止阴极层153在其上方沉积，通过限定所述第一阴极抑制层140和所述第二阴极抑制层190的厚度均小于或等于所述阴极层153的厚度，可以避免阴极层153与第一阴极抑制层140和第二阴极抑制层190产生较大的膜层段差，从而保证显示面板100的封装层的封装性能不受影响。
在一实施例中，在所述第二阴极抑制层190背离所述基底110的一侧表面所在的平面上，所述第二阴极抑制层190的形状可以为图8所示的矩形，也可以为其他多边形或者圆形、椭圆形等形状。第二阴极抑制层190的形状可以根据需求进行设定，此处不做限制。
本申请实施例还提供一种显示装置，所述显示装置包括装置主体和显示面板，所述装置主体包括壳体、电源模组、处理器模组和摄像模组等，所述显示面板设置于所述装置主体上。所述显示面板可以为上述实施例提供的显示面板，并且本申请实施例中提供的显示装置中的显示面板可以实现与上述实施例提供的显示面板相同的技术效果，此处不再赘述。
本申请实施例还提供一种显示面板的制作方法，下面结合图1至图10进行详细说明，图10为本申请实施例提供的显示面板的制作方法的流程图。
所述显示面板100包括第一显示区101和第二显示区102，所述显示面板100包括基底110、设置于所述基底110一侧的像素定义层120以及多个第一隔垫物130，多个所述第一隔垫物130间隔分布于所述第一显示区101，并且设置于所述像素定义层120背离所述基底110的一侧，所述像素定义层120上设置有位于第一显示区101的多个第一子像素开口121，所述第一子像素开口121暴露出位于像素定义层120底部的阳极151。
所述显示面板的制作方法包括：
步骤S10：在第一隔垫物130上形成过孔131，所述过孔131由所述第一隔垫物130背离基底110的一侧朝向所述基底110凹陷；
步骤S20：在像素定义层120上以及过孔131内形成第一辅助层154，所述第一辅助层154覆盖所述阳极151；
步骤S30：在所述第一子像素开口121中的所述第一辅助层154上形成有机发光层152；
步骤S40：在所述第一辅助层154上形成第二辅助层155，所述第二辅助层155覆盖所述有机发光层152；
步骤S50：在位于所述过孔131内的所述第二辅助层155上采用透光材料形成第一阴极抑制层140；
步骤S60：在所述第二辅助层155上形成阴极层；
步骤S70：在所述过孔131内的第一阴极抑制层140上采用透光材料形成填充层160。
在一实施例中，所述过孔131在所述基底110上的正投影与相邻所述阳极151在所述基底110上的正投影之间的距离大于或等于2微米且小于或等于5微米。
在一实施例中，所述步骤S10中，采用光刻工艺在每一个所述第一隔垫物130上形成一个过孔131。
在一实施例中，所述步骤S20、S40和S60均采用同一共用掩膜版分别整面蒸镀形成所述第一辅助层154、所述第二辅助层155和所述阴极层。
在一实施例中，所述步骤S30中，采用第一精细金属掩膜版在所述第一子像素开口121和所述第二子像素开口122内形成所述有机发光层152。
在一实施例中，所述步骤S50中，采用第二精细金属掩膜板在所述过孔131内的所述第二辅助层155上形成所述第一阴极抑制层140。
在一实施例中，所述步骤S50中，采用第二精细金属掩膜板在所述过孔131内的所述第二辅助层155上形成所述第一阴极抑制层140，同时在第一显示区101中的多个第一子像素单元150之间形成第二阴极抑制层190。
在一实施例中，所述第一阴极抑制层140和所述第二阴极抑制层190在所述基底110的正投影均与相邻的所述阳极151在所述基底110的正投影相离。
在一实施例中，所述显示面板100还包括阴极层153，所述阴极层153设置于所述像素定义层120背离所述基底110的一侧，所述第一阴极抑制层140和所述第二阴极抑制层190的厚度均小于或等于所述阴极层153的厚度。
在一实施例中，所述第二显示区102设置有多个间隔分布的第二隔垫物180，所述第二隔垫物180与所述第一隔垫物130的高度相等，在所述第一隔垫物130背离所述基底110的一侧表面所在的平面上，所述第二隔垫物180的面积与所述第一隔垫物130的面积的比例大于或等于0.14且小于或等于0.25。
在一实施例中，在所述第一隔垫物130背离所述基底110的一侧表面所在的平面上，所述过孔131的开口面积与所述第一隔垫物130的面积的比例大于或等于0.5且小于或等于0.9。
在一实施例中，在所述显示面板100的厚度方向上，所述过孔131贯穿所述第一隔垫物130。
在一实施例中，在所述显示面板100的厚度方向上，所述过孔131贯穿所述第一隔垫物130和所述像素定义层120。
在一实施例中，所述步骤S70可以在步骤S20之前进行，即先在过孔131内采用透光材料形成填充层160，然后进行步骤S20至S60，在填充层160上依次形成第一辅助层154、第二辅助层155和第一阴极抑制层140。
具体的，第一辅助层154包括沿远离基底110的方向依次层叠设置的空穴注入层和空穴传输层，空穴注入层覆盖阳极151。第二辅助层155包括沿远离基底110的方向依次层叠设置的电子传输层和电子注入层，电子传输层覆盖有机发光层152。
综上所述，本申请实施例提供一种显示面板及其制作方法、显示装置，所述显示面板包括第一显示区和第二显示区，所述显示面板还包括基底、像素定义层和多个第一隔垫物，所述像素定义层设置于所述基底的一侧，多个所述第一隔垫物间隔分布于所述第一显示区，并且设置于所述像素定义层背离所述基底的一侧，所述第一隔垫物上设置有过孔，所述过孔由所述第一隔垫物背离所述基底的一侧朝向所述基底凹陷形成，所述过孔内设置有由透光材料形成的第一阴极抑制层，在采用整面蒸镀工艺形成阴极层时，第一阴极抑制层可以使所述第一隔垫物的过孔中无阴极层沉积，以此增大第一显示区中各个第一隔垫物的透光率，从而提升第一显示区的透光率。
综上所述，虽然本申请以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为基准。

Claims (20)

  1. 一种显示面板，所述显示面板包括第一显示区，所述显示面板还包括：
    基底；
    像素定义层，所述像素定义层设置于所述基底的一侧；
    多个第一隔垫物，多个所述第一隔垫物间隔分布于所述第一显示区，并且设置于所述像素定义层背离所述基底的一侧；
    其中，所述第一隔垫物上设置有过孔，所述过孔内设置有由透光材料形成的第一阴极抑制层。
  2. 如权利要求1所述的显示面板，其中，在所述显示面板的厚度方向上，所述过孔至少贯穿所述第一隔垫物。
  3. 如权利要求2所述的显示面板，其中，在所述显示面板的厚度方向上，所述过孔贯穿所述第一隔垫物和所述像素定义层。
  4. 如权利要求2所述的显示面板，其中，所述过孔内还设置有由透光材料形成的填充层，所述填充层设置于所述第一阴极抑制层背离所述基底的一侧。
  5. 如权利要求4所述的显示面板，其中，所述填充层背离所述基底的一侧表面与所述第一隔垫物背离所述基底的一侧表面齐平。
  6. 如权利要求2所述的显示面板，其中，所述过孔还设置有由透光材料形成的填充层，所述填充层设置于所述第一阴极抑制层靠近所述基底的一侧。
  7. 如权利要求6所述的显示面板，其中，所述第一阴极抑制层背离所述基底的一侧表面与所述第一隔垫物背离所述基底的一侧表面齐平。
  8. 如权利要求1所述的显示面板，其中，在所述第一隔垫物背离所述基底的一侧表面所在的平面上，所述过孔的开口面积与所述第一隔垫物背离所述基底的一端的面积的比例大于或等于0.5且小于或等于0.9。
  9. 如权利要求1所述的显示面板，其中，所述显示面板还包括第二显示区和多个间隔分布于所述第二显示区的第二隔垫物，所述第二隔垫物与所述第一隔垫物设置于所述像素定义层的同一侧；
    其中，所述第一隔垫物背离所述基底的一端的面积大于所述第二隔垫物背离所述基底的一端的面积。
  10. 如权利要求9所述的显示面板，其中，所述第二隔垫物背离所述基底的一端的面积与所述第一隔垫物背离所述基底的一端的面积的比例大于或等于0.14且小于或等于0.25。
  11. 如权利要求1所述的显示面板，其中，所述第一显示区内设置有呈阵列分布的多个子像素单元，所述第一隔垫物设置于多个所述子像素单元之间，每一个所述子像素单元包括阳极，所述阳极设置于所述像素定义层靠近所述基底的一侧；
    其中，所述过孔在所述基底的正投影与相邻所述阳极在所述基底的正投影之间的最小距离大于或等于2微米且小于或等于5微米。
  12. 如权利要求11所述的显示面板，其中，所述显示面板还包括多个第二阴极抑制层，多个所述第二阴极抑制层设置于所述像素定义层对应所述第一显示区的部分上，并且位于多个所述子像素单元之间；
    其中，所述第一阴极抑制层在所述基底的正投影与所述第二阴极抑制层在所述基底的正投影相离。
  13. 如权利要求12所述的显示面板，其中，所述第一阴极抑制层和所述第二阴极抑制层在所述基底的正投影均与相邻的所述阳极在所述基底的正投影相离。
  14. 如权利要求12所述的显示面板，其中，所述显示面板还包括阴极层，所述阴极层设置于所述像素定义层背离所述基底的一侧，所述第一阴极抑制层和所述第二阴极抑制层的厚度均小于或等于所述阴极层的厚度。
  15. 一种显示装置，所述显示装置包括显示面板，所述显示面板包括第一显示区，所述显示面板还包括：
    基底；
    像素定义层，所述像素定义层设置于所述基底的一侧；
    多个第一隔垫物，多个所述第一隔垫物间隔分布于所述第一显示区，并且设置于所述像素定义层背离所述基底的一侧；
    其中，所述第一隔垫物上设置有过孔，所述过孔内设置有由透光材料形成的第一阴极抑制层。
  16. 如权利要求15所述的显示装置，其中，在所述显示面板的厚度方向上，所述过孔至少贯穿所述第一隔垫物。
  17. 如权利要求16所述的显示装置，其中，在所述显示面板的厚度方向上，所述过孔贯穿所述第一隔垫物和所述像素定义层。
  18. 如权利要求16所述的显示装置，其中，所述过孔内还设置有由透光材料形成的填充层，所述填充层设置于所述第一阴极抑制层背离所述基底的一侧。
  19. 如权利要求18所述的显示装置，其中，所述填充层背离所述基底的一侧表面与所述第一隔垫物背离所述基底的一侧表面齐平。
  20. 如权利要求16所述的显示装置，其中，所述过孔还设置有由透光材料形成的填充层，所述填充层设置于所述第一阴极抑制层靠近所述基底的一侧。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230116914A (ko) 2020-12-07 2023-08-04 오티아이 루미오닉스 인크. 핵 생성 억제 코팅 및 하부 금속 코팅을 사용한 전도성 증착 층의 패턴화
CN114497415B (zh) * 2022-01-24 2024-03-19 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
CN117396037A (zh) * 2022-02-14 2024-01-12 武汉华星光电半导体显示技术有限公司 显示面板及移动终端

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150047697A (ko) * 2013-10-24 2015-05-06 삼성디스플레이 주식회사 유기발광 표시 장치
CN107331791A (zh) * 2017-07-20 2017-11-07 上海天马有机发光显示技术有限公司 有机发光显示面板及其制备方法、有机发光显示装置
CN110265447A (zh) * 2019-06-24 2019-09-20 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法、显示装置
CN110993661A (zh) * 2019-12-02 2020-04-10 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置
CN111883687A (zh) * 2020-09-07 2020-11-03 云谷（固安）科技有限公司 Oled显示面板及其制备方法、显示装置
CN113054133A (zh) * 2021-03-09 2021-06-29 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法
CN113113456A (zh) * 2021-03-31 2021-07-13 武汉华星光电半导体显示技术有限公司 一种oled显示面板及其制备方法、显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108962964B (zh) * 2018-08-01 2020-06-30 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置
CN109638051A (zh) * 2018-12-14 2019-04-16 武汉华星光电半导体显示技术有限公司 一种oled面板的制作方法及oled面板
CN110047898B (zh) * 2019-04-26 2021-04-02 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN110783483B (zh) * 2019-08-30 2022-06-28 昆山国显光电有限公司 显示面板及其制作方法和显示装置
CN110783381B (zh) * 2019-08-30 2023-07-11 昆山国显光电有限公司 显示面板及其制作方法和显示装置
CN111584591B (zh) * 2020-05-22 2023-03-28 京东方科技集团股份有限公司 显示面板、驱动方法及显示装置
CN112054048A (zh) * 2020-09-17 2020-12-08 合肥维信诺科技有限公司 透光显示模组、显示面板及其制备方法
CN112103318B (zh) * 2020-09-17 2021-11-12 合肥维信诺科技有限公司 显示面板、显示面板的制备方法及显示装置
CN113054134B (zh) * 2021-03-09 2022-06-10 武汉华星光电半导体显示技术有限公司 显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150047697A (ko) * 2013-10-24 2015-05-06 삼성디스플레이 주식회사 유기발광 표시 장치
CN107331791A (zh) * 2017-07-20 2017-11-07 上海天马有机发光显示技术有限公司 有机发光显示面板及其制备方法、有机发光显示装置
CN110265447A (zh) * 2019-06-24 2019-09-20 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法、显示装置
CN110993661A (zh) * 2019-12-02 2020-04-10 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置
CN111883687A (zh) * 2020-09-07 2020-11-03 云谷（固安）科技有限公司 Oled显示面板及其制备方法、显示装置
CN113054133A (zh) * 2021-03-09 2021-06-29 武汉华星光电半导体显示技术有限公司 显示面板及其制备方法
CN113113456A (zh) * 2021-03-31 2021-07-13 武汉华星光电半导体显示技术有限公司 一种oled显示面板及其制备方法、显示装置

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