WO2022270525A1 - 半導体素子および半導体素子の製造方法 - Google Patents
半導体素子および半導体素子の製造方法 Download PDFInfo
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- WO2022270525A1 WO2022270525A1 PCT/JP2022/024816 JP2022024816W WO2022270525A1 WO 2022270525 A1 WO2022270525 A1 WO 2022270525A1 JP 2022024816 W JP2022024816 W JP 2022024816W WO 2022270525 A1 WO2022270525 A1 WO 2022270525A1
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- gallium oxide
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 146
- 238000004519 manufacturing process Methods 0.000 title abstract description 43
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims abstract description 80
- 229910001195 gallium oxide Inorganic materials 0.000 claims abstract description 80
- 239000013078 crystal Substances 0.000 claims abstract description 30
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 254
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 247
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 7
- 238000009826 distribution Methods 0.000 claims description 6
- 238000002050 diffraction method Methods 0.000 claims description 4
- 238000010894 electron beam technology Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 251
- 230000017525 heat dissipation Effects 0.000 abstract description 22
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 description 169
- 238000000034 method Methods 0.000 description 73
- 239000012535 impurity Substances 0.000 description 17
- 230000004048 modification Effects 0.000 description 12
- 238000012986 modification Methods 0.000 description 12
- 229910004298 SiO 2 Inorganic materials 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000005498 polishing Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000002245 particle Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 229910002601 GaN Inorganic materials 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000004913 activation Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000010000 carbonizing Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
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- 238000005530 etching Methods 0.000 description 2
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- 238000002248 hydride vapour-phase epitaxy Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
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- 239000011777 magnesium Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 238000005092 sublimation method Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 238000004627 transmission electron microscopy Methods 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/10—Inorganic compounds or compositions
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/04—After-treatment of single crystals or homogeneous polycrystalline material with defined structure using electric or magnetic fields or particle radiation
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
- C30B33/06—Joining of crystals
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
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- H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Definitions
- the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. More particularly, the present invention relates to a semiconductor device with a Ga 2 O 3 (gallium oxide) layer and a method of manufacturing a semiconductor device.
- Ga 2 O 3 gallium oxide
- Ga 2 O 3 has a bandgap larger than that of SiC (silicon carbide) and GaN (gallium nitride), and has recently attracted attention as a new wide-gap semiconductor material.
- the Barriga figure of merit is known as an index that indicates the basic performance of a power device.
- the Variga figure of merit for Ga 2 O 3 is several times greater than each of the Variga figure of merit for SiC and GaN. Therefore, Ga 2 O 3 is expected to be applied to energy-saving power semiconductor devices.
- Ga 2 O 3 has a thermal conductivity of approximately 0.1 W/cm ⁇ K.
- the thermal conductivity of Ga 2 O 3 is significantly lower than that of SiC (approximately 4.9 W/cm ⁇ K) and GaN (approximately 2 W/cm ⁇ K). Therefore, when Ga 2 O 3 is applied to a power semiconductor device, there is concern that the power semiconductor device will deteriorate in heat dissipation. The deterioration of the heat dissipation of the power semiconductor element causes deterioration of element performance and reliability due to heat generation of Ga 2 O 3 itself during operation.
- Patent Document 1 listed below discloses a conventional power semiconductor device containing Ga 2 O 3 .
- Patent Literature 1 listed below discloses a semiconductor device including a Ga 2 O 3 -based substrate, a monocrystalline Ga 2 O 3 -based layer, an anode electrode, a polycrystalline SiC substrate, and a cathode electrode.
- a single-crystal Ga 2 O 3 -based layer is formed on the surface of the Ga 2 O 3 -based substrate.
- the anode electrode is in Schottky contact with the monocrystalline Ga 2 O 3 -based layer.
- a polycrystalline SiC substrate is bonded to the back surface of the Ga 2 O 3 -based substrate.
- the cathode electrode is in ohmic contact with the polycrystalline SiC substrate.
- the heat generated at the Schottky junction interface in the single-crystal Ga 2 O 3 -based layer moves the Ga 2 O 3 -based substrate and the polycrystalline SiC substrate in the thickness direction (Ga 2 O 3 direction perpendicular to the surface of the system substrate) and is emitted to the outside from the back side of the polycrystalline SiC substrate.
- the power semiconductor device of Patent Document 1 has a long path for heat to be released to the outside, so there is still a problem that heat dissipation is low.
- Ga 2 O 3 -based substrates and polycrystalline SiC substrates are hard, methods such as chemical polishing have a slow polishing rate and cannot be used.
- a method such as mechanical polishing with a high polishing rate is used, it is difficult to reduce the thickness of the Ga 2 O 3 -based substrate and the polycrystalline SiC substrate to a uniform thickness. For this reason, it has been difficult to improve the heat dissipation by thinning the Ga 2 O 3 -based substrate and the polycrystalline SiC substrate.
- the present invention is intended to solve the above problems, and its object is to provide a semiconductor element and a method for manufacturing a semiconductor element that can improve heat dissipation.
- a semiconductor device includes a gallium oxide layer, a monocrystalline silicon carbide layer formed on one main surface side of the gallium oxide layer, and a monocrystalline silicon carbide layer formed on one main surface side of the gallium oxide layer. and a first electrode for controlling current flow in the gallium layer.
- the silicon carbide layer has a 3C-type crystal structure, and the plane orientation of the main surface of the silicon carbide layer on the gallium oxide layer side is (111), (100), or (110),
- the gallium oxide layer-side main surface of the silicon carbide layer has an off-angle of 0° or more and 10° or less, and the half width of the X-ray rocking curve of the plane orientation of the gallium oxide layer-side main surface of the silicon carbide layer is greater than 0. 2000 arcsec or less, and the full width at half maximum of the misorientation distribution of the main surface of the gallium oxide layer side in the silicon carbide layer measured by the electron beam backscatter diffraction method is greater than 0 and 2000 arcsec or less.
- the silicon layer fills.
- the silicon carbide layer has a hexagonal crystal structure, the plane orientation of the main surface of the silicon carbide layer on the gallium oxide layer side is (0001), and the plane orientation of the gallium oxide layer side of the silicon carbide layer is (0001).
- the off angle of the main surface is 0° or more and 10° or less
- the X-ray rocking curve half width of the plane orientation of the main surface on the side of the gallium oxide layer in the silicon carbide layer is greater than 0 and 2000 arcsec or less
- electron beam backscattering The silicon carbide layer satisfies at least one of the conditions that the full width at half maximum of the misorientation distribution of the gallium oxide layer side main surface of the silicon carbide layer measured by a diffraction method is greater than 0 and 2000 arcsec or less.
- the above semiconductor device preferably further comprises a bonding layer formed at the interface between the gallium oxide layer and the silicon carbide layer.
- the bonding layer is formed between a first amorphous layer made of gallium oxide formed on one main surface of the gallium oxide layer, and between the first amorphous layer and the silicon carbide layer. and a second amorphous layer made of silicon carbide.
- the bonding layer preferably contains silicon oxide.
- the gallium oxide layer is formed on the first gallium oxide layer and on one main surface of the first gallium oxide layer, and the second gallium oxide layer has a lower electrical conductivity than the first gallium oxide layer. gallium oxide layer.
- the bonding layer is formed in the first region on one main surface of the second gallium oxide layer
- the first electrode is formed in the first region on one main surface of the second gallium oxide layer. 2 and formed in a second region different from the first region.
- the second gallium oxide layer is formed in a third region on one main surface of the first gallium oxide layer, and the bonding layer is formed on the one main surface of the first gallium oxide layer.
- the first electrode is formed on one main surface of the second gallium oxide layer, and is formed in a fourth region different from the third region in the fourth region.
- the side surface between the two main surfaces of the second gallium oxide layer is in contact with the silicon carbide layer.
- the first electrode preferably further comprises a second electrode in Schottky contact with the gallium oxide layer and in ohmic contact with the other main surface of the gallium oxide layer.
- a method of manufacturing a semiconductor device includes steps of bonding one main surface of a gallium oxide layer and a single-crystal silicon carbide layer; on one main surface side of the gallium oxide layer.
- the present invention it is possible to provide a semiconductor element and a method for manufacturing a semiconductor element capable of improving heat dissipation.
- FIG. 1 is a cross-sectional view showing a configuration of a semiconductor element SD1 according to a first embodiment of the invention
- FIG. FIG. 4 is a cross-sectional view showing the first step of the method for manufacturing the semiconductor device SD1 according to the first embodiment of the present invention
- FIG. 10 is a cross-sectional view showing a second step of the method of manufacturing the semiconductor device SD1 in the first embodiment of the invention
- FIG. 10 is a cross-sectional view showing the third step of the method of manufacturing the semiconductor device SD1 according to the first embodiment of the present invention, and is a cross-sectional view in the case of using the surface activated bonding method
- FIG. 10 is a cross-sectional view showing a fourth step of the method of manufacturing the semiconductor device SD1 according to the first embodiment of the present invention, and is a cross-sectional view in the case of using the surface activated bonding method;
- FIG. 6 is an enlarged view of a main portion of FIG. 5;
- FIG. 10 is a cross-sectional view showing the third step of the method for manufacturing the semiconductor element SD1 in the first embodiment of the present invention, and is a cross-sectional view in the case of using a hydrophilic bonding method;
- FIG. 10 is a cross-sectional view showing a fourth step of the method for manufacturing the semiconductor element SD1 in the first embodiment of the present invention, and is a cross-sectional view in the case of using a hydrophilic bonding method;
- FIG. 9 is an enlarged view of a main portion of FIG. 8;
- FIG. 10 is a cross-sectional view showing a fifth step of the method for manufacturing the semiconductor device SD1 in the first embodiment of the invention;
- FIG. 12 is a cross-sectional view showing a sixth step of the method for manufacturing the semiconductor element SD1 in the first embodiment of the invention;
- FIG. 14 is a cross-sectional view showing a seventh step of the method for manufacturing the semiconductor device SD1 according to the first embodiment of the present invention;
- FIG. 4 is a cross-sectional view showing a heat dissipation path of the semiconductor element SD1 according to the first embodiment of the present invention; It is sectional drawing which shows the 1st process of the modification of the manufacturing method of the 1st Embodiment of this invention.
- FIG. 4 is a cross-sectional view showing the configuration of a semiconductor element SD2 according to a second embodiment of the present invention
- FIG. 11 is a cross-sectional view showing a first step of a method for manufacturing a semiconductor device SD2 according to a second embodiment of the present invention
- FIG. 12 is a cross-sectional view showing a second step of the method for manufacturing the semiconductor device SD2 according to the second embodiment of the present invention
- FIG. 14 is a cross-sectional view showing a third step of the method of manufacturing the semiconductor device SD2 according to the second embodiment of the present invention
- FIG. 14 is a cross-sectional view showing a fourth step of the method for manufacturing the semiconductor device SD2 according to the second embodiment of the present invention
- FIG. 14 is a cross-sectional view showing a fifth step of the method of manufacturing the semiconductor device SD2 according to the second embodiment of the present invention
- FIG. 14 is a cross-sectional view showing a sixth step of the method for manufacturing the semiconductor device SD2 according to the second embodiment of the present invention
- FIG. 12 is a cross-sectional view showing a first step of a modification of the method for manufacturing the semiconductor device SD2 according to the second embodiment of the present invention
- FIG. 14 is a cross-sectional view showing a second step of a modification of the method for manufacturing the semiconductor device SD2 according to the second embodiment of the present invention
- FIG. 14 is a cross-sectional view showing a third step of a modification of the method for manufacturing the semiconductor device SD2 according to the second embodiment of the present invention
- It is a cross-sectional view showing a heat dissipation path of the semiconductor element SD2 in the second embodiment of the present invention.
- It is a sectional view showing the composition of semiconductor element SD3 in a 3rd embodiment of the present invention.
- FIG. 4 is a cross-sectional view showing the configuration of a semiconductor device SD101 serving as a sample 3 (comparative example) in the first example of the present invention
- FIG. 4 is a diagram showing the relationship between the thermal resistance value of each of samples 1 to 3 and the thickness of the drift layer in the first example of the present invention
- FIG. 10 is a diagram showing the relationship between the surface temperature of the sample 4 and the thickness of the SiC layer in the second example of the present invention
- FIG. 10 is a diagram showing the configuration of a sample 5 and each measured value of the sample 5 in the third example of the present invention
- the expression “formed on the main surface” means formed in contact with the main surface.
- the expression “formed on the main surface side” means formed in contact with the main surface and formed without contact with the main surface (at a distance from the main surface). means both
- FIG. 1 is a cross-sectional view showing the configuration of a semiconductor element SD1 according to the first embodiment of the present invention.
- the bonding layer 3 is drawn thicker than the actual thickness.
- a semiconductor element SD1 (an example of a semiconductor element) in the first embodiment is an SBD (Schottky Barrier Diode).
- the semiconductor element SD1 includes a Ga 2 O 3 substrate 1 (an example of a gallium oxide layer), a SiC layer 2 (an example of a single crystal silicon carbide layer), a bonding layer 3 (an example of a bonding layer), and a Schottky electrode 4 ( an example of a first electrode) and an ohmic electrode 5 (an example of a second electrode).
- Ga 2 O 3 substrate 1 includes two main surfaces 1a and 1b.
- the main surface 1a of the Ga 2 O 3 substrate 1 faces upward in FIG.
- the main surface 1b of the Ga 2 O 3 substrate 1 faces downward in FIG.
- the Ga 2 O 3 substrate 1 is preferably set to a thickness (length in the vertical direction in FIG. 1) corresponding to the breakdown voltage required for the semiconductor element SD1.
- the Ga 2 O 3 substrate 1 includes an underlying substrate 11 (an example of a first gallium oxide layer) and a drift layer 12 (an example of a second gallium oxide layer).
- Underlying substrate 11 includes two major surfaces 11a and 11b.
- the main surface 11a of the underlying substrate 11 faces upward in FIG.
- a main surface 11b of the underlying substrate 11 faces downward in FIG.
- the base substrate 11 preferably has an impurity concentration as high as possible, and preferably has an impurity concentration of 10 18 /cm 3 or more and 10 20 /cm 3 or less.
- Drift layer 12 is formed on main surface 11 a of underlying substrate 11 .
- Drift layer 12 includes two main surfaces 12a and 12b.
- a principal surface 12 a of the drift layer 12 faces upward in FIG. 1 and forms the principal surface 1 a of the Ga 2 O 3 substrate 1 .
- a principal surface 12 b of the drift layer 12 faces downward in FIG. 1 and is in contact with the principal surface 11 a of the underlying substrate 11 .
- the conductivity of the drift layer 12 is lower than that of the underlying substrate 11 .
- each of the base substrate 11 and the drift layer 12 may contain impurities such as Si (silicon), Sn (tin), or Ge (germanium) to provide n-type conductivity. may have.
- Drift layer 12 preferably has a thickness of 1 ⁇ m or more and 50 ⁇ m or less. Drift layer 12 preferably has an impurity concentration of 10 14 /cm 3 or more and 10 17 /cm 3 or less. The thickness and impurity concentration of the drift layer 12 are set according to the breakdown voltage required for the SBD.
- the Ga 2 O 3 substrate 1 includes the base substrate 11 and the drift layer 12, the high conductivity of the base substrate 11 can ensure the conductivity of the semiconductor element SD1.
- the high insulation properties of the drift layer 12 can ensure a high withstand voltage in the semiconductor element SD1.
- the SiC layer 2 is formed on the main surface 1a side of the Ga 2 O 3 substrate 1 .
- the SiC layer 2 is a single crystal and has a crystal structure such as 3C type or hexagonal crystal.
- SiC layer 2 includes two main surfaces 2a and 2b.
- the principal surface 2a of the SiC layer 2 faces upward in FIG. 1, and the principal surface 2b of the SiC layer 2 faces downward in FIG.
- SiC layer 2 has a thickness of, for example, 1 ⁇ m to 4 ⁇ m.
- main surface 1a of Ga 2 O 3 substrate 1 (main surface 12a of drift layer 12) and main surface 2b of SiC layer 2 are bonded to each other.
- the single crystal SiC layer 2 has a high thermal conductivity. Therefore, the SiC layer 2 plays a role of releasing heat generated in the semiconductor element SD1 to the outside.
- Bonding layer 3 is formed at the interface between Ga 2 O 3 substrate 1 and SiC layer 2 . Bonding layer 3 is formed in region RG ⁇ b>1 of main surface 12 a of drift layer 12 and is in contact with main surface 2 b of SiC layer 2 .
- Schottky electrode 4 is formed in region RG2 of main surface 12a of drift layer 12 .
- Region RG2 is a region different from region RG1.
- the region RG1 and the region RG2 are adjacent to each other, and the side surface 4a of the Schottky electrode 4 is in contact with the SiC layer 2.
- the Schottky electrode 4 is in Schottky contact with the principal surface 1a of the Ga 2 O 3 substrate 1 (the principal surface 12a of the drift layer 12).
- Schottky electrode 4 is made of, for example, a Pt (platinum)/Ti (titanium)/Au (gold) electrode.
- An ohmic electrode 5 is formed on the principal surface 1 b of the Ga 2 O 3 substrate 1 .
- the ohmic electrode 5 is in ohmic contact with the major surface 1b of the Ga 2 O 3 substrate 1 (the major surface 11b of the underlying substrate 11).
- Ohmic electrode 5 is made of, for example, a Ti/Au electrode.
- FIG. 1 a method for manufacturing the semiconductor element SD1 in the first embodiment will be described with reference to FIGS. 2 to 12.
- FIG. 2 is a diagrammatic representation of the semiconductor element SD1 in the first embodiment.
- base substrate 11 is prepared.
- the plane orientation of the main surface 11a of the underlying substrate 11 is arbitrary, and is preferably the (010) plane or the like.
- the base substrate 11 may contain impurities such as Mg (magnesium) or N (nitrogen) for adjusting conductivity.
- Underlying substrate 11 may be amorphous.
- the underlying substrate 11 must serve as a support. Therefore, it is preferable that the underlying substrate 11 has a thickness of 100 ⁇ m or more and 1000 ⁇ m or less at the stage of FIG.
- the drift layer 12 is formed on the main surface 11a of the base substrate 11 using, for example, the MBE (Molecular Beam Epitaxy) method, the MOCVD (Metal Organic Chemical Vapor Deposition) method, or the HVPE (Hydride Vapor Phase Epitaxy) method. do.
- Drift layer 12 is epitaxially grown on main surface 11 a of base substrate 11 .
- a Ga 2 O 3 substrate 1 is obtained.
- the crystal structure of Ga 2 O 3 forming each of the base substrate 11 and the drift layer 12 is arbitrary, and is preferably ⁇ -type. ⁇ -type Ga 2 O 3 is more stable than Ga 2 O 3 of other crystal structures such as ⁇ -type Ga 2 O 3 .
- Si substrate 91 is prepared separately from Ga 2 O 3 substrate 1 .
- Si substrate 91 is made of, for example, p-type Si.
- Si substrate 91 includes two main surfaces 91a and 91b.
- the principal surface 91a of the Si substrate 91 faces downward in FIG. 3, and the principal surface 91b of the Si substrate 91 faces upward in FIG.
- the plane orientation of main surface 91b of Si substrate 91 is, for example, the (111) plane.
- the Si substrate 91 may have n-type conductivity or may be semi-insulating.
- the plane orientation of the main surface 91b of the Si substrate 91 may be the (100) plane, the (110) plane, or the like.
- Si substrate 91 has, for example, a diameter of 6 inches and a thickness of 1000 ⁇ m.
- SiC layer 2 includes two main surfaces 2a and 2b.
- the principal surface 2a of the SiC layer 2 faces downward in FIG. 3, and the principal surface 2b of the SiC layer 2 faces upward in FIG.
- the SiC layer 2 is formed on a base layer made of SiC obtained by carbonizing the main surface 91b of the Si substrate 91, using an MBE method, a CVD (Chemical Vapor Deposition) method, an LPE (Liquid Phase Epitaxy) method, or the like. and may be formed by homoepitaxially growing SiC.
- SiC layer 2 may be formed only by carbonizing main surface 91 b of Si substrate 91 .
- SiC layer 2 may be formed by heteroepitaxial growth on main surface 91b of Si substrate 91 (or with a buffer layer interposed therebetween).
- SiC layer 2 may have n-type or p-type conductivity, or may be semi-insulating.
- the SiC layer 2 is not intentionally doped with impurities.
- SiC layer 2 When SiC layer 2 is formed on main surface 91b of Si substrate 91 by any one of carbonization, homoepitaxial growth, and heteroepitaxial growth, SiC layer 2 has a 3C-type crystal structure.
- the SiC layer 2 has a 3C-type crystal structure
- the plane orientation of the main surface 2b of the SiC layer 2 (the main surface on the side of the Ga 2 O 3 substrate 1) is (111), (100), or (110). is preferred.
- the off angle of main surface 2b of SiC layer 2 is preferably 0° or more and 10° or less.
- the half width of the X-ray rocking curve of the plane orientation of the main surface 2b of the SiC layer 2 is greater than 0 and 2000 arcsec or less
- the SiC layer 2 preferably satisfies at least one of the two conditions (a) and (b) that the full width at half maximum of the misorientation distribution is greater than 0 and equal to or less than 2000 arcsec.
- the main surface 2b of the SiC layer 2 becomes a surface suitable for bonding.
- Si substrate 91 and SiC layer 2 are then turned over so that principal surface 91b of Si substrate 91 and principal surface 2b of SiC layer 2 face downward in FIG.
- the Ga 2 O 3 substrate 1 obtained in the process shown in FIG. 2 is set so that the main surface 1a of the Ga 2 O 3 substrate 1 faces upward in FIG.
- main surface 1a of Ga 2 O 3 substrate 1 main surface 12a of drift layer 12
- main surface 2b of SiC layer 2 are bonded.
- the arithmetic mean roughness Ra of the principal surface 2b of the SiC layer 2 is preferably greater than 0 and equal to or less than 1 nm.
- the arithmetic mean roughness Ra of the main surface 2b of the SiC layer 2 is more preferably greater than 0 and 0.5 nm or less. Moreover, when the size of the Si substrate 91 is 4 inches or more, the warp of the main surface 2b of the SiC layer 2 is preferably more than 0 and 50 ⁇ m or less.
- any method can be used to bond the main surface 1a of the Ga 2 O 3 substrate 1 and the main surface 2b of the SiC layer 2, and the surface activation bonding method is preferably used.
- the surface activation bonding method is used, Ga 2 is bonded in an atmosphere of reduced pressure of 1 ⁇ 10 ⁇ 5 Pa or less, preferably 1 ⁇ 10 ⁇ 6 Pa or less and normal temperature (for example, temperature of 10° C. or more and 30° C. or less).
- Main surface 1a of O 3 substrate 1 and main surface 2b of SiC layer 2 are each irradiated with energetic particles as indicated by arrow AW1.
- the energetic particles consist of, for example, ions, neutral atoms such as Ar (argon), Kr (krypton), or Ne (neon), or cluster ions.
- the energetic particles preferably consist of Ar.
- each of the amorphous layers 31 and 32 appear, for example, with a thickness greater than 0 and less than or equal to 5 nm.
- the amorphous layer 31 is obtained by amorphizing Ga 2 O 3 present on the main surface 1a of the Ga 2 O 3 substrate 1 by collision with energetic particles.
- the amorphous layer 32 is obtained by amorphizing SiC present on the main surface 2a of the SiC layer 2 by collision with energetic particles.
- amorphous layer 31 and amorphous layer 32 are brought into contact with each other.
- the principal surface 1a of the Ga 2 O 3 substrate 1 and the principal surface 2b of the SiC layer 2 are bonded together, and the bonding layer 3 appears.
- bonding layer 3 is a trace of bonding between Ga 2 O 3 substrate 1 and SiC layer 2 . If the Ga 2 O 3 substrate 1 and the SiC layer 2 are not bonded, the bonding layer 3 does not appear.
- the composition of the bonding layer 3 depends on the bonding method.
- the bonding layer 3 includes an amorphous layer 31 and an amorphous layer 32 when the surface activated bonding method described above is used.
- Amorphous layer 31 is formed on main surface 1 a of Ga 2 O 3 substrate 1 .
- Amorphous layer 32 is formed between amorphous layer 31 and main surface 2 a of SiC layer 2 .
- the amorphous layers 31 and 32 can be observed by TEM (Transmission electron microscopy) or the like.
- hydrophilization bonding may be used instead of surface activation bonding.
- the hydrophilic bonding method is also called Fusion Bonding or Silicon Direct Bonding (SDB).
- SDB Silicon Direct Bonding
- the SiO 2 layer 33 is formed on the main surface 1a of the Ga 2 O 3 substrate 1 by using the CVD method or the like.
- a SiO 2 layer 34 is formed on the principal surface 2 b of the SiC layer 2 .
- the SiO 2 layer 34 is formed by a method of forming the SiO 2 layer 34 on the main surface 2b of the SiC layer 2 using a CVD method or the like, a method of forming a Si layer on the main surface 2b of the SiC layer 2, and a method of thermally oxidizing the Si layer. Alternatively, it may be formed by a method of thermally oxidizing main surface 2b of SiC layer 2, or the like. Next, each of the SiO 2 layer 33 and the SiO 2 layer 34 is hydrophilized.
- SiO 2 layer 33 and SiO 2 layer 34 are brought into contact with each other as indicated by arrow AW2.
- the principal surface 1a of the Ga 2 O 3 substrate 1 and the principal surface 2b of the SiC layer 2 are bonded together, and the bonding layer 3 appears.
- bonding layer 3 in which SiO 2 layers 33 and 34 are integrated is obtained after bonding.
- the bonding layer 3 contains SiO2 .
- the thermal conductivity of the SiO2 layer is relatively low.
- the bonding layer 3 in the case of using the surface activated bonding method does not contain the SiO 2 layer. From the viewpoint of ensuring high thermal conductivity, it is preferable to use the surface activated bonding method.
- the Si substrate 91 is then completely removed by mechanical polishing and wet etching, for example. Thereby, main surface 2a of SiC layer 2 is exposed. Any method can be used as a method for removing Si substrate 91, such as dry etching or chemical polishing.
- SiC layer 2 and bonding layer 3 present in region RG2 of main surface 12a of drift layer 12 are then removed by normal photolithography and dry etching techniques. Thereby, region RG2 of main surface 12a of drift layer 12 is exposed. SiC layer 2 and bonding layer 3 existing in region RG1 of main surface 12a of drift layer 12 remain.
- an ohmic electrode 5 is then formed on main surface 1b of Ga 2 O 3 substrate 1 using a method such as vapor deposition.
- Schottky electrode 4 is then formed in region RG2 of main surface 12a of drift layer 12 using a method such as vapor deposition. Through the above steps, the semiconductor element SD1 is obtained.
- the underlying substrate 11 in the semiconductor element SD1 is as thin as possible. Therefore, after bonding the Ga 2 O 3 substrate 1 and the SiC layer 2 and before forming the ohmic electrode 5 , the base substrate 11 is preferably thinned to a thickness of 5 ⁇ m or more and 100 ⁇ m or less by grinding or the like.
- FIG. 13 is a cross-sectional view showing heat dissipation paths of the semiconductor element SD1 according to the first embodiment of the present invention.
- semiconductor device SD1 operates as follows. When a positive potential is applied to the Schottky electrode 4 while the ohmic electrode 5 is grounded, current flows from the Schottky electrode 4 to the ohmic electrode 5 through the Ga 2 O 3 substrate 1 . Schottky electrode 4 controls the current flowing through Ga 2 O 3 substrate 1 . The current flowing through Ga 2 O 3 substrate 1 depends on the potential applied to Schottky electrode 4 .
- the semiconductor element SD1 heat is generated in the region HR which is the Schottky interface (the interface between the main surface 1a of the Ga 2 O 3 substrate 1 and the Schottky electrode 4).
- the semiconductor element SD1 most of the heat generated in the region HR travels in the drift layer 12 along the extending direction of the main surface 1a of the Ga 2 O 3 substrate 1, as indicated by the arrow PH, and reaches the SiC layer 2. , and passes through the interior of SiC layer 2 and is emitted to the outside from main surface 2 a of SiC layer 2 .
- the heat generated at the Schottky interface is released to the side of the Ga 2 O 3 substrate 1 where the Schottky electrode 4 exists (upper side in FIG. 13).
- the heat generated at the Schottky interface is released from the opposite side of the Ga 2 O 3 substrate 1 to the Schottky electrode 4 (lower side in FIG. 13). , the heat dissipation path can be shortened. As a result, heat dissipation can be improved.
- a sputtering method, a CVD method, or the like can be employed as a method for forming the SiC layer 2 on the main surface 1a of the Ga 2 O 3 substrate 1.
- bonding as a method of forming the SiC layer 2 on the main surface 1a of the Ga 2 O 3 substrate 1, the following effects can be obtained as compared with the sputtering method, the CVD method, and the like.
- the use of bonding eliminates the need to heat the Ga 2 O 3 substrate 1 when forming the SiC layer 2 on the main surface 1 a of the Ga 2 O 3 substrate 1 . As a result, damage to the Ga 2 O 3 substrate 1 and the like due to heating can be avoided. On the other hand, when using the sputtering method or the CVD method, the Ga 2 O 3 substrate 1 must be heated.
- a base layer (here, the Si substrate 91) suitable for forming the SiC layer 2 can be used.
- the quality of SiC layer 2 can be improved, and single crystal SiC layer 2 can be formed.
- the sputtering method or the CVD method it is necessary to use the Ga 2 O 3 substrate 1 as a base layer.
- the SiC layer becomes polycrystalline or amorphous, and a single crystal SiC layer cannot be obtained.
- the SiC layer 2 becomes a single crystal as described above.
- Single-crystal SiC layers have higher thermal conductivity and resistivity than polycrystalline or amorphous SiC layers. Therefore, the single-crystal SiC layer 2 can improve the heat dissipation of the semiconductor element SD1 and suppress the leak current at the interface between the Ga 2 O 3 substrate 1 and the SiC layer 2 .
- a bulk SiC substrate may be used as the SiC layer 2 instead of using the one formed on the main surface 91a of the Si substrate 91 as shown in FIG.
- a modification using a bulk SiC substrate as the SiC layer 2 in the first embodiment will be described with reference to FIGS. 14 and 15.
- FIG. 14 and 15 A modification using a bulk SiC substrate as the SiC layer 2 in the first embodiment will be described with reference to FIGS. 14 and 15.
- SiC layer 2 which is a bulk SiC substrate, is prepared.
- a bulk SiC substrate is manufactured using, for example, a sublimation method.
- SiC layer 2 includes two main surfaces 2a and 2b.
- the principal surface 2a of the SiC layer 2 faces downward in FIG. 14, and the principal surface 2b of the SiC layer 2 faces upward in FIG.
- SiC layer 2 has a thickness of, for example, 100 ⁇ m to 500 ⁇ m.
- SiC layer 2 may have n-type or p-type conductivity, or may be semi-insulating.
- the SiC layer 2 is not intentionally doped with impurities.
- the SiC layer 2 When the SiC layer 2 is made of a bulk SiC substrate manufactured using a sublimation method or the like, the SiC layer 2 has a hexagonal crystal structure.
- the plane orientation of main surface 2b of SiC layer 2 (main surface on the side of Ga 2 O 3 substrate 1) is preferably (0001).
- the off angle of main surface 2b of SiC layer 2 is preferably 0° or more and 10° or less.
- the half width of the X-ray rocking curve of the plane orientation of the main surface 2b of the SiC layer 2 is greater than 0 and 2000 arcsec or less
- the SiC layer 2 preferably satisfies at least one of the two conditions (a) and (b) that the full width at half maximum of the misorientation distribution is greater than 0 and equal to or less than 2000 arcsec.
- the main surface 2b of the SiC layer 2 becomes a surface suitable for bonding.
- SiC layer 2 is inverted so that main surface 2b of SiC layer 2 faces downward in FIG.
- the Ga 2 O 3 substrate 1 obtained in the process shown in FIG. 2 is brought into a state in which the main surface 1a faces upward in FIG.
- main surface 1a (main surface 12a of drift layer 12) of Ga 2 O 3 substrate 1 (main surface 12a of drift layer 12) and main surface 2b of SiC layer 2 are bonded by an arbitrary bonding method, as indicated by arrow AW2.
- bonding layer 3 appears between principal surface 1a of Ga 2 O 3 substrate 1 and principal surface 2b of SiC layer 2 after bonding.
- the SiC layer 2 is polished from the main surface (the main surface opposite to the side where the Ga 2 O 3 substrate 1 is present) 2a side of the SiC layer 2 to thin the SiC layer 2 to a thickness of 1 ⁇ m to 4 ⁇ m, for example. do.
- Any method can be used as a polishing method for SiC layer 2, and for example, mechanical polishing, chemical polishing, or the like can be used.
- the semiconductor device SD1 is obtained through the steps after FIG. 10 of the first embodiment.
- the manufacturing method of semiconductor element SD1 in the modified example other than that described above is the same as the manufacturing method of the first embodiment, and therefore description thereof will not be repeated.
- FIG. 17 is a cross-sectional view showing the configuration of the semiconductor element SD2 according to the second embodiment of the present invention.
- semiconductor element SD2 (an example of a semiconductor element) in the second embodiment is SBD. Similar to the semiconductor element SD1, the semiconductor element SD2 includes a Ga 2 O 3 substrate 1 ( an example of a gallium oxide layer) and a single crystal SiC layer 2 (a single and a Schottky electrode 4 formed on the main surface 1a of the Ga 2 O 3 substrate 1 and controlling the current flowing through the Ga 2 O 3 substrate 1 .
- the Ga 2 O 3 substrate 1 has a convex shape facing upward in FIG. 17 when viewed in cross section in FIG.
- Drift layer 12 (an example of a second gallium oxide layer) is formed in region RG3 of main surface 11a of base substrate 11 (an example of a first gallium oxide layer).
- Main surface 1a of Ga 2 O 3 substrate 1 (main surface facing upward in FIG. 17) is composed of region RG4 of main surface 11a of base substrate 11 and main surface 12a of drift layer 12 .
- Region RG4 is a region different from region RG3.
- the regions RG3 and RG4 are adjacent to each other.
- the SiC layer 2 is formed on the main surface 1a side of the Ga 2 O 3 substrate 1 .
- main surface 1a of Ga 2 O 3 substrate 1 and main surface 2b of SiC layer 2 are bonded to each other.
- a side surface 12 c (an example of a side surface of the second gallium oxide layer) of drift layer 12 is in contact with SiC layer 2 .
- Side surface 12c of drift layer 12 is a surface between main surface 12a and main surface 12b of drift layer 12 .
- a bonding layer 3 (an example of a bonding layer) is formed at the interface between the Ga 2 O 3 substrate 1 and the SiC layer 2 .
- Bonding layer 3 is formed in region RG ⁇ b>4 of main surface 11 a of base substrate 11 and is in contact with main surface 2 b of SiC layer 2 .
- the bonding layer 3 is a trace of bonding between the Ga 2 O 3 substrate 1 and the SiC layer 2 .
- a Schottky electrode 4 (an example of a first electrode) is formed on the main surface 12 a of the drift layer 12 .
- Side surface 4 a of Schottky electrode 4 is in contact with SiC layer 2 .
- the Schottky electrode 4 is in Schottky contact with the principal surface 1a of the Ga 2 O 3 substrate 1 (the principal surface 12a of the drift layer 12).
- the configuration of the semiconductor element SD2 other than the above is the same as the configuration of the semiconductor element SD1 in the first embodiment, so the same members are denoted by the same reference numerals, and the description thereof will not be repeated.
- FIG. 18 a method for manufacturing the semiconductor element SD2 according to the second embodiment will be described with reference to FIGS. 18 to 23.
- the underlying substrate 11 is prepared, and the main surface 11a of the underlying substrate 11 faces upward in FIG. Further, the SiC layer 2 and the Si substrate 91 obtained in the process shown in FIG. 3 are arranged such that the main surface 91b of the Si substrate 91 and the main surface 2b of the SiC layer 2 face downward in FIG. In this state, main surface 11a of base substrate 11 and main surface 2b of SiC layer 2 are bonded by an arbitrary bonding method, as indicated by arrow AW2.
- a bonding layer 3 appears between the main surface 11a of the base substrate layer 11 and the main surface 2b of the SiC layer 2 after bonding.
- the Si substrate 91 is removed. Thereby, main surface 2a of SiC layer 2 is exposed.
- SiC layer 2 and bonding layer 3 existing in region RG3 of main surface 11a of base substrate 11 are removed by normal photoengraving technology and etching technology. As a result, region RG3 of main surface 11a of base substrate 11 is exposed. SiC layer 2 and bonding layer 3 existing in region RG4 of main surface 11a of base substrate 11 remain.
- drift layer 12 is formed in region RG3 of main surface 11a of underlying substrate 11 .
- the excess Ga 2 O 3 layer existing on the main surface 2a of the SiC layer 2 is removed by etching.
- the remaining Ga 2 O 3 layer becomes the drift layer 12 .
- Drift layer 12 is epitaxially grown on main surface 11 a of base substrate 11 .
- Main surface 12 a of drift layer 12 becomes part of main surface 1 a of Ga 2 O 3 substrate 1 .
- ohmic electrodes 5 are formed on main surface 11b of underlying substrate 11 .
- Schottky electrode 4 is then formed on main surface 12 a of drift layer 12 .
- the semiconductor element SD2 is obtained by the above steps.
- FIG. 24 a modified example of the manufacturing method of the semiconductor device SD2 in the second embodiment will be described with reference to FIGS. 24 to 26.
- FIG. 24 a modified example of the manufacturing method of the semiconductor device SD2 in the second embodiment will be described with reference to FIGS. 24 to 26.
- a Si substrate 91 is prepared with reference to FIG. Next, a single crystal SiC layer 2 is formed on the main surface 91 b of the Si substrate 91 . Next, SiC layer 2 existing in region RG3 of main surface 91b of Si substrate 91 is removed by ordinary photomechanical technology and dry etching technology. Thereby, region RG3 of main surface 91b of Si substrate 91 is exposed. SiC layer 2 existing in region RG4 of main surface 91b of Si substrate 91 remains.
- the underlying substrate 11 is prepared so that the main surface 11a of the underlying substrate 11 faces upward in FIG. Further, the SiC layer 2 and the Si substrate 91 obtained in the process shown in FIG. 24 are arranged such that the principal surface 91b of the Si substrate 91 and the principal surface 2b of the SiC layer 2 face downward in FIG. In this state, main surface 11a of base substrate 11 and main surface 2b of SiC layer 2 are bonded by an arbitrary bonding method in region RG4, as indicated by arrow AW3.
- bonding layer 3 appears between main surface 11a of base substrate 11 and main surface 2b of SiC layer 2 in region RG4.
- the Si substrate 91 is removed. Thereby, main surface 2a of SiC layer 2 is exposed, and the structure shown in FIG. 21 is obtained.
- the drift layer 12 is formed on the main surface 2a of the SiC layer 2 through the steps shown in FIGS.
- An ohmic electrode 5 is formed on the main surface 11 b of the underlying substrate 11 .
- a Schottky electrode 4 is formed on the main surface 12 a of the drift layer 12 .
- the semiconductor element SD2 is obtained by the above steps.
- the SiC layer 2 is partially removed while the Si substrate 91 is the base layer of the SiC layer 2 .
- Main surface 91b of Si substrate 91 in RG3 is exposed (in other words, the mesa structure of SiC layer 2 is formed before bonding base substrate 11 and SiC layer 2).
- the method of manufacturing the semiconductor element SD2 (in particular, the manufacturing conditions, etc.) other than those described above in the second embodiment and its modification is the same as the manufacturing method of the first embodiment, and thus description thereof will not be repeated. .
- FIG. 27 is a cross-sectional view showing heat dissipation paths of the semiconductor element SD2 according to the second embodiment of the present invention.
- semiconductor device SD2 operates as follows. When a positive potential is applied to the Schottky electrode 4 while the ohmic electrode 5 is grounded, current flows from the Schottky electrode 4 to the ohmic electrode 5 through the Ga 2 O 3 substrate 1 . Schottky electrode 4 controls the current flowing through Ga 2 O 3 substrate 1 . The current flowing through Ga 2 O 3 substrate 1 depends on the potential applied to Schottky electrode 4 .
- semiconductor element SD2 most of the heat generated in region HR is transferred from drift layer 12 to SiC layer 2 along the direction in which main surface 1a of Ga 2 O 3 substrate 1 extends, as indicated by arrow PH. , pass through the interior of the SiC layer 2 and are emitted from the main surface 2a of the SiC layer 2 to the outside.
- the heat generated at the Schottky interface is released to the side of the Ga 2 O 3 substrate 1 where the Schottky electrode 4 exists (upper side in FIG. 27).
- the heat generated at the Schottky interface is released from the opposite side (lower side in FIG. 27) of the Ga 2 O 3 substrate 1 to the side where the Schottky electrode 4 exists. , the heat dissipation path can be shortened. As a result, heat dissipation can be improved.
- the bonding interface between base substrate 11 and SiC layer 2 can have heat resistance at 1000° C., which is higher than the temperature assumed in these heat treatment processes.
- FIG. 28 is a cross-sectional view showing the configuration of the semiconductor element SD3 according to the third embodiment of the present invention.
- a semiconductor element SD3 (an example of a semiconductor element) in the third embodiment is a lateral MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Similar to the semiconductor device SD1, the semiconductor device SD3 includes a Ga 2 O 3 substrate 1 ( an example of a gallium oxide layer) and a single crystal SiC layer 2 (a single and a gate electrode 21 (an example of a first electrode) that is formed on the main surface 1a side of the Ga 2 O 3 substrate 1 and controls the current flowing through the Ga 2 O 3 substrate 1 . ing.
- a Ga 2 O 3 substrate 1 an example of a gallium oxide layer
- the semiconductor element SD3 includes a Ga 2 O 3 substrate 1, a SiC layer 2, a junction layer 3, a gate electrode 21, a drain electrode 22, a source electrode 23, and a gate insulating film 24.
- Ga 2 O 3 substrate 1 includes two main surfaces 1a and 1b.
- the main surface 1a of the Ga 2 O 3 substrate 1 faces upward in FIG.
- the main surface 1b of the Ga 2 O 3 substrate 1 faces downward in FIG.
- the thickness of the Ga 2 O 3 substrate 1 is preferably adjusted according to the breakdown voltage required for the semiconductor element SD3.
- the Ga 2 O 3 substrate 1 includes an underlying substrate 11 (an example of a first gallium oxide layer) and a Ga 2 O 3 layer 12 (an example of a side surface of the second gallium oxide layer).
- the Ga 2 O 3 layer 12 in the semiconductor element SD3 does not function as a drift layer, so in this embodiment it is referred to as a "Ga 2 O 3 layer” rather than a “drift layer”.
- Underlying substrate 11 includes two major surfaces 11a and 11b.
- the main surface 11a of the underlying substrate 11 faces upward in FIG.
- the main surface 11b of the underlying substrate 11 faces downward in FIG .
- the underlying substrate 11 may have an impurity concentration corresponding to the design of the semiconductor element SD3, and may be semi-insulated or metallized by increasing the impurity concentration.
- the Ga 2 O 3 layer 12 is formed on the main surface 11 a of the underlying substrate 11 .
- Ga 2 O 3 layer 12 includes two major surfaces 12a and 12b.
- the main surface 12a of the Ga 2 O 3 layer 12 faces upward in FIG. 28 and forms the main surface 1a of the Ga 2 O 3 substrate 1 .
- the main surface 12b of the Ga 2 O 3 layer 12 faces downward in FIG.
- the conductivity of the Ga 2 O 3 layer 12 is higher than that of the underlying substrate 11 .
- the Ga 2 O 3 layer 12 contains an impurity such as N introduced by ion implantation, and has p-type conductivity or semi-insulating properties to adjust the conductivity.
- the Ga 2 O 3 layer 12 may have n-type conductivity, which is higher in resistance than the n-type region 12d.
- the semiconductor element SD3 becomes a normally-on MOSFET.
- the Ga 2 O 3 layer 12 preferably has a thickness of 1 ⁇ m or more and 50 ⁇ m or less. The thickness of the Ga 2 O 3 layer 12 is set according to the breakdown voltage required for the MOSFET.
- Ga 2 O 3 layer 12 includes two n-type regions 12d. Each of the two n-type regions 12d is formed so as to face main surface 12a of Ga 2 O 3 layer 12 . Each of the two n-type regions 12d contains an impurity such as Si, Sn, or Ge and has n-type conductivity.
- a region near the main surface 1a of the Ga 2 O 3 substrate 1 between the gate electrode 21 and the drain electrode 22 is defined as a region HR.
- the region HR in the Ga 2 O 3 layer 12 preferably has an impurity concentration of 10 14 /cm 3 or more and 10 17 /cm 3 or less regardless of the conductivity type.
- the impurity concentration of the region HR in the Ga 2 O 3 layer 12 is set according to the breakdown voltage required for the semiconductor element SD3.
- the impurity concentration of the regions other than the region HR in the Ga 2 O 3 layer 12 is , preferably have an impurity concentration as high as possible, and preferably have an impurity concentration of 10 18 /cm 3 or more and 10 20 /cm 3 or less.
- Drain electrode 22 and source electrode 23 are each formed on main surface 1a of Ga 2 O 3 substrate 1 . Each of drain electrode 22 and source electrode 23 is in contact with each of two n-type regions 12d.
- a gate electrode 21 is formed on the main surface 1a of the Ga 2 O 3 substrate 1 with a gate insulating film 24 interposed therebetween. Gate electrode 21 is provided between drain electrode 22 and source electrode 23 .
- the SiC layer 2 is formed on the main surface 1a side of the Ga 2 O 3 substrate 1 .
- the SiC layer 2 is a single crystal and has a crystal structure such as 3C type or hexagonal crystal.
- SiC layer 2 includes two main surfaces 2a and 2b. Principal surface 2a of SiC layer 2 faces upward in FIG. 28, and principal surface 2b of SiC layer 2 faces downward in FIG.
- SiC layer 2 has a thickness of, for example, 1 ⁇ m to 4 ⁇ m.
- main surface 1a of Ga 2 O 3 substrate 1 and main surface 2b of SiC layer 2 are bonded to each other.
- the single crystal SiC layer 2 has a high thermal conductivity. Therefore, the SiC layer 2 plays a role of releasing heat generated in the semiconductor element SD3 to the outside.
- Bonding layer 3 is formed at the interface between each of two n-type regions 12d of Ga 2 O 3 substrate 1 and SiC layer 2 .
- the bonding layer 3 is formed on the main surface 1 a of the Ga 2 O 3 substrate 1 .
- the junction layer 3 is formed between the gate electrode 21 and the drain electrode 22 and between the gate electrode 21 and the source electrode 23 .
- Bonding layer 3 is in contact with main surface 2 b of SiC layer 2 .
- the bonding layer 3 is a trace of bonding between the Ga 2 O 3 substrate 1 and the SiC layer 2 . If the Ga 2 O 3 substrate 1 and the SiC layer 2 are not bonded, the bonding layer 3 does not appear.
- the semiconductor device SD3 is manufactured by a method substantially similar to that of the semiconductor device SD1 in the first embodiment.
- the base substrate 11 When bonding the Ga 2 O 3 substrate 1 and the SiC layer 2, the base substrate 11 must serve as a support. Therefore, until the Ga 2 O 3 substrate 1 and the SiC layer 2 are bonded, the base substrate 11 preferably has a thickness of 100 ⁇ m or more and 1000 ⁇ m or less.
- the base substrate 11 after bonding the Ga 2 O 3 substrate 1 and the SiC layer 2 and before forming the ohmic electrode 5, the base substrate 11 is subjected to a grinding treatment or the like from the viewpoint of improving the heat dissipation from the lower part of the base substrate 11. It is preferable that the thickness is reduced to 5 ⁇ m or more and 100 ⁇ m or less.
- the configuration and manufacturing method of the semiconductor device SD3 other than those described above are substantially the same as the configuration of the semiconductor device SD1 in the first embodiment. No.
- the semiconductor device SD3 operates as follows.
- the source electrode 23 is always kept at ground potential.
- a positive voltage is applied to each of the gate electrode 21 and the drain electrode 22
- a channel is formed in the main surface 1a of the Ga 2 O 3 substrate 1 immediately below the gate electrode 21, and two n-type regions 121 are formed.
- a current flows from the drain electrode 22 to the source electrode 23 through the .
- the magnitude of this current is controlled by the voltage applied to gate electrode 21 .
- the gate electrode 21 controls the current flowing through the Ga 2 O 3 substrate 1 .
- the semiconductor element SD3 In the semiconductor element SD3 , most of the heat generated in the region HR passes from the Ga2O3 layer 12 to the SiC layer 2 along the normal direction of the main surface 1a of the Ga2O3 substrate 1 , as indicated by the arrow PH. , and passes through the SiC layer 2 to be emitted from the main surface 2a of the SiC layer 2 to the outside.
- the heat generated in the semiconductor element SD3 is released to the side of the Ga 2 O 3 substrate 1 where the gate electrode 21 exists (upper side in FIG. 28).
- the heat generated in the semiconductor element SD3 is released from the opposite side (lower side in FIG. 28) of the Ga 2 O 3 substrate 1 to the side where the gate electrode 21 exists.
- a heat radiation path can be shortened. As a result, heat dissipation can be improved.
- samples 1 to 3 having the configurations described below as samples.
- a thermal resistance value was calculated for each of Samples 1 to 3 obtained.
- Sample 1 (example of the present invention): Five samples having the same structure as the semiconductor device SD1 shown in FIG. 1 were manufactured. The thickness of the drift layer of each of the five samples to be sample 1 was set to 10 ⁇ m, 20 ⁇ m, 30 ⁇ m, 40 ⁇ m, and 50 ⁇ m, respectively.
- Sample 2 (example of the present invention): Five samples having the same structure as the semiconductor device SD2 shown in FIG. 17 were manufactured. The thickness of the drift layer of each of the five samples to be sample 2 was set to 10 ⁇ m, 20 ⁇ m, 30 ⁇ m, 40 ⁇ m, and 50 ⁇ m, respectively.
- Sample 3 (comparative example): Five samples having the same structure as the semiconductor device SD101 shown in FIG. 29 were manufactured. The thickness of the drift layer of each of the five samples to be Sample 3 was 10 ⁇ m, 20 ⁇ m, 30 ⁇ m, 40 ⁇ m, and 50 ⁇ m, respectively.
- semiconductor element SD101 includes a Ga 2 O 3 drift layer 112, a SiC substrate 102, a Schottky electrode 104 and an ohmic electrode 105.
- Ga 2 O 3 drift layer 112 includes major surfaces 112a and 112b.
- the principal surface 112a faces upward in FIG. 29, and the principal surface 112b faces downward in FIG.
- a Schottky electrode 104 is formed on part of the main surface 112a of the Ga 2 O 3 drift layer 112 .
- SiC substrate 102 is formed on main surface 112 b of Ga 2 O 3 drift layer 112 .
- the SiC substrate 102 is provided on the main surface 112b of the Ga 2 O 3 drift layer 112 opposite to the side on which the Schottky electrode 104 exists (lower side in FIG. 29).
- SiC substrates are polycrystalline.
- SiC substrate 102 includes main surfaces 102a and 102b. Principal surface 102a faces upward in FIG. 29, and principal surface 102b faces downward in FIG.
- Main surface 102 a of SiC substrate 102 is bonded to main surface 112 b of Ga 2 O 3 drift layer 112 .
- An ohmic electrode 105 is formed on main surface 102 b of SiC substrate 102 .
- FIG. 30 is a diagram showing the relationship between the thermal resistance value of each of samples 1 to 3 and the thickness of the drift layer in the first example of the present invention.
- each of samples 1 and 2 had a thermal resistance value reduced by about 25% compared to sample 3.
- the rate of decrease in the thermal resistance value of each of samples 1 and 2 relative to sample 3 increased with the thickness of the drift layer.
- the inventors of the present application manufactured a sample 4 having the configuration described below.
- the surface temperature (maximum temperature of the Schottky electrode) during operation of each of the samples 4 thus obtained was examined.
- Sample 4 Six samples having basically the same structure as the semiconductor device SD2 shown in FIG. 17 were manufactured. However, one of the six samples, which will be Sample 4, is a comparative example and the thickness of the SiC layer is set to 0 (that is, the SiC layer is not formed). The remaining 5 samples out of the 6 samples to be sample 4 were examples of the present invention, and the thicknesses of the SiC layers were set to 10 ⁇ m, 20 ⁇ m, 30 ⁇ m, 40 ⁇ m, and 50 ⁇ m, respectively. For all samples, the drift layer diameter was 30 ⁇ m, the drift layer thickness was 10 ⁇ m, and the SiC layer diameter was 100 ⁇ m.
- FIG. 31 is a diagram showing the relationship between the surface temperature of the sample 4 and the thickness of the SiC layer in the second example of the present invention.
- the formation of the SiC layer significantly lowered the surface temperature. Especially when the thickness of the SiC layer was 20 ⁇ m or more, the surface temperature was 100° C. or less. It can be seen that the increase in surface temperature can be effectively suppressed by setting the thickness of the SiC layer to 20 ⁇ m or more, which is twice the thickness of the drift layer.
- the inventors of the present application manufactured a sample 5 having a configuration described below. Using the thermoreflectance signal of sample 5, the thermal resistance at the interface between the SiC layer and the Ga 2 O 3 substrate was calculated.
- FIG. 32 is a diagram showing the configuration of the sample 5 and each measured value of the sample 5 in the third example of the present invention.
- a 3C-type SiC layer was bonded to the (201) plane of a ⁇ -type Ga 2 O 3 substrate using a surface activation bonding method.
- a Mo (molybdenum) layer was formed on the main surface of the SiC layer opposite to the main surface to which the Ga 2 O 3 substrate was bonded.
- the Ga 2 O 3 substrate had a thickness of 0.65 mm.
- the SiC layer had a thickness of 1 ⁇ m.
- the Mo layer had a thickness of 104.1 nm.
- thermoreflectance signal of sample 5 was measured by the time domain thermoreflectance method. Specifically, the main surface of the Mo layer opposite to the main surface to which the SiC layer is bonded was irradiated with heating light composed of periodically modulated laser light and detection light composed of continuous wave laser light. . Each of the heating light and the detection light was irradiated as indicated by the arrow LR, and was irradiated so as to be coaxial with each other. A reflected light of the detection light was received to obtain a thermoreflectance signal.
- the thermal effusivity of Sample 5 was measured based on the obtained thermoreflectance signal.
- the thermal effusivity of sample 5 was converted into the thermal conductivity of sample 5.
- the thermal resistance of the interface between the Mo layer and the SiC layer was calculated from the obtained thermal conductivity of Sample 5. .
- the thermal resistance of the interface between the SiC layer and the Ga 2 O 3 substrate was 7.0 ⁇ 10 ⁇ 9 (m 2 K/W), which is very low.
- the present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can improve heat dissipation.
- INDUSTRIAL APPLICABILITY According to the present invention, an energy-saving effect can be obtained by improving the power energy conversion efficiency of a semiconductor device, and it contributes to the achievement of sustainable development goals.
- the semiconductor device of the present invention may be other than SBD and lateral MOSFET.
- a bulk SiC substrate may be used as the SiC layer 2, or hydrophilized bonding may be used as the bonding method.
- a method of manufacturing the semiconductor element SD1 of the first embodiment a method similar to the modified example of the manufacturing method of the second embodiment may be used. That is, before joining the Ga 2 O 3 substrate 1 and the SiC layer 2, the Si substrate in the region RG2 is partially removed while the Si substrate 91 is the underlying layer of the SiC layer 2. A major surface 91b of 91 may be exposed.
- Ga 2 O 3 (gallium oxide) substrate (an example of gallium oxide layer) 1a, 1b Main surface of Ga 2 O 3 substrate 2 SiC (silicon carbide) layer (an example of single crystal silicon carbide layer) 2a, 2b main surface of SiC layer 3 bonding layer (an example of bonding layer) 4,104 Schottky electrode (an example of the first electrode) 4a Side surface of Schottky electrode 5,105 Ohmic electrode (an example of second electrode)
- Underlying substrate of 11 Ga 2 O 3 substrate (an example of the first gallium oxide layer) 11a, 11b primary surface of underlying substrate 12 drift layer or Ga2O3 layer of Ga2O3 substrate ( an example of second gallium oxide layer) 12a, 12b main surface of the drift layer 12c side surface of the drift layer (an example of the side surface of the second gallium oxide layer) 12d n-type region of drift layer
- gate electrode an example of a first electrode
- 22 drain electrode 23 source electrode 24 gate insulating film 31, 32 amorphous layer (an example of
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Abstract
Description
1a,1b Ga2O3基板の主面
2 SiC(炭化ケイ素)層(単結晶炭化ケイ素層の一例)
2a,2b SiC層の主面
3 接合層(接合層の一例)
4,104 ショットキー電極(第1の電極の一例)
4a ショットキー電極の側面
5,105 オーミック電極(第2の電極の一例)
11 Ga2O3基板の下地基板(第1の酸化ガリウム層の一例)
11a,11b 下地基板の主面
12 Ga2O3基板のドリフト層またはGa2O3層(第2の酸化ガリウム層の一例)
12a,12b ドリフト層の主面
12c ドリフト層の側面(第2の酸化ガリウム層の側面の一例)
12d ドリフト層のn型領域
21 ゲート電極(第1の電極の一例)
22 ドレイン電極
23 ソース電極
24 ゲート絶縁膜
31,32 アモルファス層(第1および第2のアモルファス層の一例)
33,34 SiO2(酸化ケイ素)層
91 Si(ケイ素)基板
91a,91b Si基板の主面
102 SiC基板
102a,102b SiC基板の主面
112 Ga2O3ドリフト層
112a,112b Ga2O3ドリフト層の主面
HR 熱が発生する領域
RG1,RG2 ドリフト層の主面の領域
RG3,RG4 下地基板の主面の領域
SD1、SD2,SD3,SD101 半導体素子(半導体素子の一例)
Claims (12)
- 酸化ガリウム層と、
前記酸化ガリウム層の一方の主面側に形成された単結晶炭化ケイ素層と、
前記酸化ガリウム層の一方の主面側に形成され、前記酸化ガリウム層内を流れる電流を制御する第1の電極とを備えた、半導体素子。 - 前記炭化ケイ素層は3C型の結晶構造を有し、
前記炭化ケイ素層における前記酸化ガリウム層側の主面の面方位は(111)、(100)、または(110)であり、
前記炭化ケイ素層における前記酸化ガリウム層側の主面のオフ角は0°以上10°以下であり、
前記炭化ケイ素層における前記酸化ガリウム層側の主面の面方位のX線ロッキングカーブの半値幅は0より大きく2000arcsec以下である、および電子線後方散乱回折法による前記炭化ケイ素層における前記酸化ガリウム層側の主面の方位差分布の半値全幅は0より大きく2000arcsec以下である、のうち少なくともいずれか一方の条件を前記炭化ケイ素層は満たす、請求項1に記載の半導体素子。 - 前記炭化ケイ素層は六方晶の結晶構造を有し、
前記炭化ケイ素層における前記酸化ガリウム層側の主面の面方位は(0001)であり、
前記炭化ケイ素層における前記酸化ガリウム層側の主面のオフ角は0°以上10°以下であり、
前記炭化ケイ素層における前記酸化ガリウム層側の主面の面方位のX線ロッキングカーブ半値幅は0より大きく2000arcsec以下である、および電子線後方散乱回折法による前記炭化ケイ素層における前記酸化ガリウム層側の主面の方位差分布の半値全幅は0より大きく2000arcsec以下である、のうち少なくともいずれか一方の条件を前記炭化ケイ素層は満たす、請求項1に記載の半導体素子。 - 前記酸化ガリウム層と前記炭化ケイ素層との界面に形成された接合層をさらに備えた、請求項1に記載の半導体素子。
- 前記接合層は、
前記酸化ガリウム層の一方の主面に形成された酸化ガリウムよりなる第1のアモルファス層と、
前記第1のアモルファス層と前記炭化ケイ素層との間に形成された炭化ケイ素よりなる第2のアモルファス層とを含む、請求項4に記載の半導体素子。 - 前記接合層は、酸化ケイ素を含む、請求項4に記載の半導体素子。
- 前記酸化ガリウム層は、
第1の酸化ガリウム層と、
前記第1の酸化ガリウム層の一方の主面に形成され、前記第1の酸化ガリウム層よりも低い導電率を有する第2の酸化ガリウム層とを含む、請求項4に記載の半導体素子。 - 前記接合層は、前記第2の酸化ガリウム層の一方の主面の第1の領域に形成され、
前記第1の電極は、前記第2の酸化ガリウム層の一方の主面の第2の領域であって前記第1の領域とは異なる第2の領域に形成される、請求項7に記載の半導体素子。 - 前記第2の酸化ガリウム層は、前記第1の酸化ガリウム層の一方の主面における第3の領域に形成され、
前記接合層は、前記第1の酸化ガリウム層の一方の主面における第4の領域であって前記第3の領域とは異なる第4の領域に形成され、
前記第1の電極は、前記第2の酸化ガリウム層の一方の主面に形成される、請求項7に記載の半導体素子。 - 前記第2の酸化ガリウム層における2つの主面の間の面である側面は、前記炭化ケイ素層と接触する、請求項9に記載の半導体素子。
- 前記第1の電極は、前記酸化ガリウム層とショットキー接触し、
前記酸化ガリウム層の他方の主面とオーミック接触する第2の電極をさらに備えた、請求項1に記載の半導体素子。 - 酸化ガリウム層の一方の主面と、単結晶炭化ケイ素層とを接合する工程と、
前記酸化ガリウム層内を流れる電流を制御する第1の電極を、前記酸化ガリウム層の一方の主面側に形成する工程とを備えた、半導体素子の製造方法。
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