WO2022262061A1 - 多晶硅电阻及其制造方法、逐次逼近型模数转换器 - Google Patents
多晶硅电阻及其制造方法、逐次逼近型模数转换器 Download PDFInfo
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- WO2022262061A1 WO2022262061A1 PCT/CN2021/107427 CN2021107427W WO2022262061A1 WO 2022262061 A1 WO2022262061 A1 WO 2022262061A1 CN 2021107427 W CN2021107427 W CN 2021107427W WO 2022262061 A1 WO2022262061 A1 WO 2022262061A1
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- polysilicon
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- silicon oxide
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 170
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 170
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 152
- 238000002955 isolation Methods 0.000 claims abstract description 112
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 64
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 64
- 239000010703 silicon Substances 0.000 claims abstract description 64
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 62
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 58
- 239000012212 insulator Substances 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 13
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 238000005070 sampling Methods 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000011810 insulating material Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 11
- 230000005684 electric field Effects 0.000 abstract description 9
- 238000012545 processing Methods 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000013461 design Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
- H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
- H03M1/0612—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic over the full range of the converter, e.g. for correcting differential non-linearity
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
- H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
Definitions
- the invention relates to the technical field of integrated circuits, in particular to a polysilicon resistor, a manufacturing method thereof, and a successive approximation analog-to-digital converter.
- SAR ADCs Industrial successive approximation analog-to-digital converters
- SAR ADCs Industrial successive approximation analog-to-digital converters
- the SAR ADC signal input range is limited to 0 ⁇ 2.5V.
- a resistor divider network is generally integrated in the front end of the SAR ADC, so that the signal processing range of the SAR ADC can reach ⁇ 10V.
- FIG. 1 it is a typical industrial integrated SAR ADC structure diagram, which includes a resistor divider unit composed of resistors R1 and R2, a bandgap reference unit that outputs a reference voltage, and a successive approximation analog-to-digital conversion unit (SAR ADC unit), the resistance divider unit is integrated and set at the analog front end of the SAR ADC unit, the resistance ratio of the resistance R1 and the resistance R2 is 3:1, the resistance value of the resistance R3 and the resistance value of the resistance R2 are in the same order of magnitude, After being divided by the resistor divider unit, the signal range of -10V to +10V is only 0 to 2.5V when it reaches the front end of the SAR ADC unit. At the same time, the bandgap reference unit outputs a reference voltage of 2.5V to the SAR ADC unit.
- the resistor divider unit composed of resistors R1 and R2
- a bandgap reference unit that outputs a reference voltage
- the linearity of the resistor divider unit is very important, which directly affects the linearity of the entire SAR ADC.
- large semiconductor manufacturers in the world use metal thin film resistors, but metal thin film resistors require additional special process flow.
- the standard integrated circuit production process of general commercial foundries does not provide this device, and for integrated circuit design manufacturers without production lines In other words, it is impossible to use metal film resistors to develop high-performance SAR ADCs with more than 16 bits for industrial use.
- FIG. 2 The structure of a general polysilicon resistor is shown in FIG. 2 .
- the polysilicon resistor layer is isolated from the p-type substrate by an insulating silicon dioxide (SiO 2 ) layer, and there is a non-negligible capacitance.
- SiO 2 insulating silicon dioxide
- a strong electric field E will be formed between the polysilicon resistance layer and the p-type substrate.
- the resistivity increases; at the low-voltage end (0-2.5V) of the polysilicon resistance layer, the electric field is weak, the edge-poly effect is not obvious, and the resistivity hardly increases.
- the inconsistency of the resistivity of the polysilicon resistive layer at the high-voltage end and the low-voltage end will cause very serious nonlinearity.
- the purpose of the present invention is to provide a technical solution for the linearization of the voltage divider network of polysilicon resistors, which is used to solve the above-mentioned technical problems.
- a polysilicon resistor including:
- the second silicon substrate is disposed on the first silicon oxide layer, wherein an insulating isolation structure penetrating through the second silicon substrate is provided, and the insulating isolation structure divides the second silicon substrate into a plurality of Separate substrate isolation regions;
- the polysilicon resistance layer is disposed on the second silicon oxide layer, and includes a plurality of polysilicon resistance blocks separated from each other, and the plurality of polysilicon resistance blocks are arranged in one-to-one correspondence with the plurality of substrate isolation regions, and the plurality of The polysilicon resistance blocks are connected in series.
- the thickness of the first silicon oxide layer is greater than the thickness of the second silicon oxide layer.
- a plurality of the polysilicon resistance blocks are distributed in rows, and two adjacent polysilicon resistance blocks are electrically connected.
- the specifications of the multiple polysilicon resistance blocks are equal.
- a plurality of polysilicon resistance blocks are connected in series through conductive metal to form a resistance string, and both ends of the resistance string are electrically drawn out through conductive metal.
- the present invention also provides a method for manufacturing a polysilicon resistor, comprising the steps of:
- a silicon-on-insulator substrate is provided, and the silicon-on-insulator substrate includes a first silicon substrate, a first silicon oxide layer, and a second silicon substrate sequentially stacked along a first direction;
- An insulating isolation structure is formed on the silicon-on-insulator substrate, and the insulating isolation structure penetrates the second silicon substrate along the first direction and divides the second silicon substrate into a plurality of mutually separated Substrate isolation region;
- a polysilicon resistance layer is formed on the second silicon oxide layer, the polysilicon resistance layer includes a plurality of polysilicon resistance blocks separated from each other, and the plurality of polysilicon resistance blocks are arranged in one-to-one correspondence with the plurality of substrate isolation regions, And a plurality of said polysilicon resistance blocks are connected in series.
- the step of forming the insulating isolation structure on the silicon-on-insulator substrate includes:
- An isolation trench penetrating through the second silicon substrate along the first direction is formed on the insulating silicon substrate, and the isolation trench divides the second silicon substrate into a plurality of independent parts. the substrate isolation region;
- the isolation trench is filled with an insulating material to obtain the insulating isolation structure.
- the thickness of the second silicon oxide layer is smaller than the thickness of the first silicon oxide layer.
- the step of forming the polysilicon resistance layer on the second silicon oxide layer includes:
- a plurality of polysilicon resistance blocks are connected in series in sequence to form a resistance string, and the two ends of the resistance string are electrically drawn out.
- the present invention also provides a successive approximation analog-to-digital converter, including:
- Resistive divider unit one end of which is connected to the input voltage and the other end is grounded, and it comprises two polysilicon resistors arranged in series as described in any one of claims 1-5, and the common end of the two polysilicon resistors outputs a sampling Voltage;
- the bandgap reference unit outputs a reference voltage
- a successive approximation analog-to-digital conversion unit is connected to the resistance voltage dividing unit and the bandgap reference unit respectively, and receives the sampling voltage and the reference voltage.
- the polysilicon resistor and its manufacturing method of the present invention have at least the following beneficial effects:
- the upper silicon substrate layer of the silicon-on-insulator substrate is divided into insulated and isolated substrate isolation regions, and a silicon oxide layer and a polysilicon resistance layer are sequentially formed on the upper silicon substrate layer, and the polysilicon
- the resistance layer is divided into several polysilicon resistance blocks, and several polysilicon resistance blocks are placed on several substrate isolation regions one by one, so that the potential of the substrate isolation region closely follows the potential of the polysilicon resistance block, thereby making the polysilicon
- the resistance block and the substrate isolation area below cannot form a strong electric field, which effectively eliminates the carrier fringe effect on the polysilicon resistor;
- the polysilicon resistor is applied to the front-end resistor divider network of the successive approximation analog-to-digital converter , can effectively improve the linearity of the resistor divider network, thereby reducing the integral nonlinearity of the successive approximation analog-to-digital converter, and improving the accuracy of the successive approximation analog-to-digital converter.
- FIG. 1 is a schematic structural diagram of a successive approximation analog-to-digital converter in the prior art.
- FIG. 2 is a schematic structural diagram of a polysilicon resistor in the prior art.
- FIG. 3 is a schematic diagram showing the steps of the manufacturing method of the polysilicon resistor in the present invention.
- 4-14 are process flow diagrams of the manufacturing method of the polysilicon resistor in the present invention.
- FIG. 15 shows an equivalent circuit diagram of the polysilicon resistors in FIGS. 13-4 .
- the present invention provides a linearization technical scheme of the high-voltage polysilicon resistor divider network at the front end of the successive approximation analog-to-digital converter: utilizing the characteristics of the silicon-on-insulator (SOI) process, the upper silicon substrate layer of the silicon-on-insulator substrate It is divided into insulating and isolated substrate isolation regions, and a silicon oxide layer and a polysilicon resistance layer are sequentially formed on the upper silicon substrate layer, and the polysilicon resistance layer is divided into several polysilicon resistance blocks, and several polysilicon resistance blocks are divided into one by one Correspondingly placed on several substrate isolation regions, so that the potential of the substrate isolation region closely follows the potential of the polysilicon resistance block, so that the polysilicon resistance block and the underlying substrate isolation region cannot form a strong electric field to eliminate the load.
- the edge-to-edge effect of the currents improves the linearity of the front-end resistor divider network of the successive approximation analog-to-digital converter.
- the present invention provides a kind of manufacturing method of polysilicon resistance, and it comprises steps:
- a silicon-on-insulator substrate is provided, and the silicon-on-insulator substrate includes a first silicon substrate 1, a first silicon oxide layer 2, and a second silicon substrate 3 that are sequentially stacked along a first direction ;
- an insulating isolation structure 4 is formed on the silicon-on-insulator substrate, and the insulating isolation structure 4 penetrates the second silicon substrate 3 along the first direction and divides the second silicon substrate 3 into A plurality of mutually separated substrate isolation regions 301, 302, 303, 304, 305;
- a second silicon oxide layer 5 is formed on the silicon-on-insulator substrate, and the second silicon oxide layer 5 covers the substrate isolation regions 301, 302, 303, 304, 305 and the insulating isolation structure 4;
- a polysilicon resistance layer is formed on the second silicon oxide layer 5, and the polysilicon resistance layer includes mutually separated polysilicon resistance blocks 601, 602, 603, 604, 605, polysilicon resistance blocks 601, 602 , 603, 604, 605 are set in one-to-one correspondence with the substrate isolation regions 301, 302, 303, 304, 305, and the polysilicon resistance blocks 601, 602, 603, 604, 605 are connected in series.
- the silicon-on-insulator substrate provided includes a first silicon substrate 1 and a first silicon oxide layer 2 stacked in sequence along the first direction (the positive direction of the Z-axis). and the second silicon substrate 3 .
- silicon-on-insulator is a new type of semiconductor material that uses SiO2 insulating layer to completely isolate device silicon and substrate silicon. It can be produced by various processes such as wafer bonding and oxygen ion implantation.
- the thickness of the buried oxide layer (BOX) in the silicon-on-insulator material obtained by bonding can range from several hundred nanometers to more than 40 ⁇ m according to the requirements of the device.
- High-voltage integrated circuits and MEME devices generally require the thickness of the buried oxide layer to be greater than 200 nm, and the buried oxide layer Density is required. Therefore, in the present invention, the thickness of the first silicon oxide layer 2 used in the industrial successive approximation analog-to-digital converter front-end resistor divider network is relatively large, and the thickness of the first silicon oxide layer 2 is greater than 200nm. .
- the step S2 of forming the insulating isolation structure 4 on the silicon-on-insulator substrate further includes:
- an isolation trench T1 penetrating the second silicon substrate 3 along the first direction is formed on the insulating silicon substrate, and the isolation trench T1 divides the second silicon substrate 3 into mutually Discrete substrate isolation regions 301, 302, 303, 304, 305;
- step S21 photolithography and etching are performed using a pre-set mask plate, and the second silicon substrate is etched along the opposite direction of the first direction and penetrates the second silicon substrate.
- an isolation trench T1 is formed in the second silicon substrate 3 , and the isolation trench T1 divides the second silicon substrate 3 into substrate isolation regions 301 , 302 , 303 , 304 , and 305 .
- the isolation trench T1 is filled by first depositing an insulating material and then surface planarization treatment to obtain an insulating isolation structure 4, an insulating isolation structure 4 Physical isolation between the substrate isolation regions 301, 302, 303, 304, 305 is achieved.
- a second silicon oxide layer 5 is formed on the silicon-on-insulator substrate, and the second silicon oxide layer 5 covers the substrate isolation regions 301, 302, 303, 304, 305 and The isolation structure 4 is insulated, and the thickness of the second silicon oxide layer 5 is smaller than the thickness of the first silicon oxide layer 2, and the thickness of the second silicon oxide layer 5 is about 20nm-40nm.
- the step S4 of forming a polysilicon resistance layer on the second silicon oxide layer 5 further includes:
- step S41 a polysilicon material layer is formed on the second silicon oxide layer 5, and then the polysilicon material layer is ion-doped to obtain a doped polysilicon material layer 6, and the doped polysilicon material layer 6 as the body of the polysilicon resistor.
- the doped ion type and ion concentration can be selected according to actual needs, and are not limited here.
- step S42 photolithography and etching are performed using a pre-set mask, and the doped polysilicon material is etched along the reverse direction of the first direction and penetrates Layer 6, an isolation trench T2 is formed in the doped polysilicon material layer 6, and the isolation trench T2 divides the doped polysilicon material layer 6 into mutually separated polysilicon resistance blocks 601, 602, 603, 604, 605, and the polysilicon resistance blocks 601 , 602 , 603 , 604 , and 605 are set in one-to-one correspondence with the substrate isolation regions 301 , 302 , 303 , 304 , and 305 .
- Fig. 12 shows the top view after removing the second silicon oxide layer 5, as shown in Fig. 11-Fig. 304 and 305 are set in one-to-one correspondence: the polysilicon resistance block 601 is set corresponding to the substrate isolation area 301, the polysilicon resistance block 602 is set corresponding to the substrate isolation area 302, the polysilicon resistance block 603 is set corresponding to the substrate isolation area 303, and the polysilicon resistance block 603 is set corresponding to the substrate isolation area 303.
- 604 is set corresponding to the substrate isolation region 304 , and the polysilicon resistance block 605 is set corresponding to the substrate isolation region 305 .
- step S43 the polysilicon resistance blocks 601, 602, 603, 604, 605 are sequentially connected in series with the conductive metal 7 to form a resistor string, and the conductive metal 7 is used to electrically lead out the resistance ends of the string.
- FIG. 14 shows a top view after removing the second silicon oxide layer 5 .
- the first silicon oxide layer 2 is disposed on the first silicon substrate 1;
- the second silicon substrate 3 is arranged on the first silicon oxide layer 2, and an insulating isolation structure 4 penetrating through the second silicon substrate 3 is arranged therein, and the insulating isolation structure 4 divides the second silicon substrate 3 into separate substrates.
- the second silicon oxide layer 5 is disposed on the second silicon substrate 3 and covers the insulating isolation structure 4;
- the polysilicon resistance layer is arranged on the second silicon oxide layer 5, which includes mutually separated polysilicon resistance blocks 601, 602, 603, 604, 605, the polysilicon resistance blocks 601, 602, 603, 604, 605 and the substrate isolation region 301 , 302, 303, 304, 305 are set in one-to-one correspondence, and the polysilicon resistance blocks 601, 602, 603, 604, 605 are connected in series.
- the thickness of the first silicon oxide layer 2 is greater than the thickness of the second silicon oxide layer 5 .
- the polysilicon resistance blocks 601, 602, 603, 604, 605 are distributed in a row in a straight line, and the specifications of the polysilicon resistance blocks 601, 602, 603, 604, 605 equal in size; and two adjacent polysilicon resistance blocks are electrically connected through the conductive metal 7, so that the polysilicon resistance blocks 601, 602, 603, 604, 605 are connected in series through the conductive metal 7 to form a resistance string, and the two ends of the resistance string are respectively It is electrically drawn out through the conductive 7.
- the number of polysilicon resistance blocks is not limited to five, and the sizes and specifications of multiple polysilicon resistance blocks do not have to be exactly the same, and can be flexibly designed.
- the equivalent circuit of the polysilicon resistor shown in Figures 13-14 is shown in Figure 15: the resistor R601 represents the resistance of the polysilicon resistor block 601, and the capacitor C11 represents the resistance between the polysilicon resistor block 601 and the substrate isolation region 301.
- the thickness of the first silicon oxide layer 2 (more than 200nm) is greater than or much greater than the thickness of the second silicon oxide layer 5 (20nm-40nm), so that the capacitor C11 is much larger than the capacitor C12, and the capacitor C21 is much larger. Because of the capacitor C22, the capacitor C31 is much larger than the capacitor C32, the capacitor C41 is much larger than the capacitor C42, and the capacitor C51 is much larger than the capacitor C52.
- the potential of the substrate isolation region 301 will closely follow the potential of the polysilicon resistor block 601, and the substrate The potential of the isolation region 302 will closely follow the potential of the polysilicon resistance block 602, the potential of the substrate isolation region 303 will closely follow the potential of the polysilicon resistance block 603, and the potential of the substrate isolation region 304 will closely follow that of the polysilicon resistance block 604.
- Potential, the potential of the substrate isolation region 305 will closely follow the potential of the polysilicon resistance block 605, that is, the potential of the substrate isolation region will closely follow the potential of the polysilicon resistance block, so that the polysilicon resistance block and the substrate isolation region below No large electric field will be formed, which will not cause the edge effect.
- the present invention also provides a successive approximation analog-to-digital converter, similar to Fig. 1, which includes:
- a resistor divider unit one end of which is connected to the input voltage and the other end is grounded, which includes two polysilicon resistors and the two polysilicon resistors are arranged in series, and the common end of the two polysilicon resistors outputs a sampling voltage;
- the bandgap reference unit outputs a reference voltage
- the successive approximation analog-to-digital conversion unit is connected to the resistance voltage dividing unit and the bandgap reference unit respectively, and receives the sampling voltage and the reference voltage.
- the resistor voltage divider unit is designed based on the above-mentioned polysilicon resistors, and the edge polysilicon effect is basically not caused on the resistor voltage divider unit, and the linearity of the resistor voltage divider unit is improved, and the linearity of the front-end resistor voltage divider unit is improved.
- the integral nonlinearity (INL) of the successive approximation analog-to-digital conversion unit can meet the actual application requirements of the successive approximation analog-to-digital converter.
- the polysilicon resistor and its manufacturing method of the present invention utilize the characteristics of the silicon-on-insulator (SOI) process to divide the upper silicon substrate layer of the silicon-on-insulator substrate into insulated and isolated substrate isolation regions, and A silicon oxide layer and a polysilicon resistance layer are sequentially formed on the upper silicon substrate layer, and the polysilicon resistance layer is divided into several polysilicon resistance blocks, and several polysilicon resistance blocks are placed on several substrate isolation regions in a one-to-one correspondence, so that The potential of the substrate isolation area closely follows the potential of the polysilicon resistance block, so that the polysilicon resistance block and the underlying substrate isolation area cannot form a strong electric field, effectively eliminating the carrier edge effect on the polysilicon resistance;
- SOI silicon-on-insulator
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Abstract
一种多晶硅电阻及其制造方法、逐次逼近型模数转换器,在形成多晶硅电阻时,利用绝缘体上硅工艺的特点,把绝缘体上硅衬底的上层硅衬底层划分成一个个绝缘隔离的衬底隔离区,并在上层硅衬底层上依次形成氧化硅层和多晶硅电阻层,且多晶硅电阻层被划分成若干个多晶硅电阻块,若干个多晶硅电阻块被一一对应地置于若干个衬底隔离区上,使得衬底隔离区的电位紧紧跟随多晶硅电阻块的电位,使得多晶硅电阻块与下面的衬底隔离区无法形成较强的电场,消除了多晶硅电阻上的载流子聚边效应;将该多晶硅电阻应用到逐次逼近型模数转换器的前端电阻分压网络上时,可有效提高电阻分压网络的线性度,降低了逐次逼近型模数转换器的积分非线性度。
Description
本发明涉及集成电路技术领域,特别是涉及一种多晶硅电阻及其制造方法、逐次逼近型模数转换器。
工业用逐次逼近型模数转换器(SAR ADC)往往要求处理-10V~+10V的电压信号范围,甚至更宽的信号范围。这就要求SAR ADC的输入信号范围达到-10V~+10V,但一般集成带隙基准电路产生的参考电压为1.25V或者2.5V,且大多数工业用SAR ADC采用2.5V的基准电压,这就限制了SAR ADC信号输入范围为0~2.5V。为了解决这个问题,一般在SAR ADC前端集成一电阻分压网络,使得SAR ADC的信号处理范围能达到±10V。如图1所示,为一典型的工业用集成SAR ADC结构图,其包括电阻R1和电阻R2构成的电阻分压单元、输出基准电压的带隙基准单元以及逐次逼近型模数转换单元(SAR ADC单元),电阻分压单元集成设置在SAR ADC单元的模拟前端,电阻R1和电阻R2的阻值之比为3:1,电阻R3的阻值与电阻R2的阻值在同一个量级,经过该电阻分压单元分压后,-10V~+10V的信号范围到达SAR ADC单元前端时只有0~2.5V,同时,带隙基准单元向SAR ADC单元输出2.5V的基准电压。
对于高精度模数转换器如16位SAR ADC来说,该电阻分压单元的线性度十分重要,其直接影响了整个SAR ADC的线性度。目前国际上大的半导体厂家都采用金属薄膜电阻,但金属薄膜电阻需要额外的特殊工艺流程,一般商业代工制造厂的标准集成电路生产工艺不提供该器件,而对于没有生产线的集成电路设计厂商来说,又无法使用金属薄膜电阻研制工业用16位以上高性能SAR ADC。
基于此,近几年有人开始尝试用多晶硅电阻代替金属薄膜电阻来设计电阻分压单元。一般多晶硅电阻的结构如图2所示,多晶硅电阻层与p型衬底之间由绝缘的二氧化硅(SiO
2)层隔离,存在不可忽略的电容。在高压±10V的情况下多晶硅电阻层与p型衬底间会形成很强的电场E,该电场会引起多晶硅电阻层里的载流子(电子)发生聚边效应,从而使多晶硅电阻层的电阻率增加;在多晶硅电阻层的低压端(0~2.5V),电场较弱,聚边效应不明显,电阻率几乎不增加。多晶硅电阻层的电阻率在高压端和低压端的不一致会引起十分严重的非线性度。
有鉴于此,目前亟需一种线性度较好的多晶硅电阻分压网络技术方案。
发明内容
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种多晶硅电阻的分压网络线性化技术方案,用于解决上述技术问题。
首先,为实现上述目的及其他相关目的,本发明提供一种多晶硅电阻,包括:
第一硅衬底;
第一氧化硅层,设置在所述第一硅衬底上;
第二硅衬底,设置在所述第一氧化硅层上,其中设有贯穿所述第二硅衬底的绝缘隔离结构,所述绝缘隔离结构将所述第二硅衬底划分为多个相互分立的衬底隔离区;
第二氧化硅层,设置在所述第二硅衬底上;
多晶硅电阻层,设置在所述第二氧化硅层上,其包括多个相互分立的多晶硅电阻块,多个所述多晶硅电阻块与多个所述衬底隔离区一一对应设置,且多个所述多晶硅电阻块串联在一起。
可选地,所述第一氧化硅层的厚度大于所述第二氧化硅层的厚度。
可选地,多个所述多晶硅电阻块成排分布,且相邻两个所述多晶硅电阻块电连接。
可选地,多个所述多晶硅电阻块的规格大小相等。
可选地,多个所述多晶硅电阻块通过导电金属串联在一起,构成电阻串,且所述电阻串的两端通过导电金属电引出。
其次,为实现上述目的及其他相关目的,本发明还提供一种多晶硅电阻的制造方法,包括步骤:
提供绝缘体上硅衬底,所述绝缘体上硅衬底包括沿着第一方向依次堆叠设置的第一硅衬底、第一氧化硅层及第二硅衬底;
在所述绝缘体上硅衬底上形成绝缘隔离结构,所述绝缘隔离结构沿着所述第一方向贯穿所述第二硅衬底并将所述第二硅衬底划分为多个相互分立的衬底隔离区;
在所述绝缘体上硅衬底上形成第二氧化硅层,所述第二氧化硅层覆盖所述衬底隔离区和所述绝缘隔离结构;
在所述第二氧化硅层上形成多晶硅电阻层,所述多晶硅电阻层包括多个相互分立的多晶硅电阻块,多个所述多晶硅电阻块与多个所述衬底隔离区一一对应设置,且多个所述多晶硅电阻块串联在一起。
可选地,在所述绝缘体上硅衬底上形成所述绝缘隔离结构的步骤包括:
在所述绝缘硅衬底上形成沿着所述第一方向贯穿所述第二硅衬底的隔离沟槽,所述隔离 沟槽将所述第二硅衬底划分为多个相互分立的所述衬底隔离区;
用绝缘材料填充所述隔离沟槽,得到所述绝缘隔离结构。
可选地,所述第二氧化硅层的厚度小于所述第一氧化硅层的厚度。
可选地,在所述第二氧化硅层上形成所述多晶硅电阻层的步骤包括:
在所述第二氧化硅层上形成掺杂多晶硅材料层;
刻蚀所述掺杂多晶硅材料层,得到多个相互分立的所述多晶硅电阻块,且多个所述多晶硅电阻块与多个所述衬底隔离区一一对应设置;
将多个所述多晶硅电阻块依次串联起来,形成电阻串,并电引出所述电阻串的两端。
最后,为实现上述目的及其他相关目的,本发明还提供一种逐次逼近型模数转换器,包括:
电阻分压单元,其一端接输入电压、另一端接地,其包括两个如权利要求1-5中任意一项所述的且串联设置的多晶硅电阻,两个所述多晶硅电阻的公共端输出采样电压;
带隙基准单元,输出基准电压;
逐次逼近型模数转换单元,与所述电阻分压单元及所述带隙基准单元分别连接,接收所述采样电压与所述基准电压。
如上所述,本发明的多晶硅电阻及其制造方法至少具有以下有益效果:
利用绝缘体上硅工艺的特点,把绝缘体上硅衬底的上层硅衬底层划分成一个个绝缘隔离的衬底隔离区,并在上层硅衬底层上依次形成氧化硅层和多晶硅电阻层,且多晶硅电阻层被划分成若干个多晶硅电阻块,若干个多晶硅电阻块被一一对应地置于若干个衬底隔离区上,使得衬底隔离区的电位紧紧跟随多晶硅电阻块的电位,进而使得多晶硅电阻块与下面的衬底隔离区无法形成较强的电场,有效消除了多晶硅电阻上的载流子聚边效应;将该多晶硅电阻应用到逐次逼近型模数转换器的前端电阻分压网络上时,可有效提高电阻分压网络的线性度,进而降低了逐次逼近型模数转换器的积分非线性度,提高了逐次逼近型模数转换器的精度。
图1显示为现有技术中一种逐次逼近型模数转换器的结构示意图。
图2显示为现有技术中一种多晶硅电阻的的结构示意图。
图3显示为本发明中多晶硅电阻的制造方法的步骤示意图。
图4-图14显示为本发明中多晶硅电阻的制造方法的工艺流程图。
图15显示为图13-图4中多晶硅电阻的等效电路图。
1-第一硅衬底,2-第一氧化硅层,3-第二硅衬底,301、302、303、304、305-衬底隔离区,4-绝缘隔离结构,5-第二氧化硅层,6-掺杂多晶硅材料层,601、602、603、604、605-多晶硅电阻块,7-导电金属,C11、C12、C21、C22、C31、C32、C41、C42、C51、C52-电容,R1、R2、R3、R601、R602、R603、R604、R605-电阻,T1、T2-隔离沟槽。
发明人研究发现:如图1-图2所示,在目前的工业用逐次逼近型模数转换器中,在用传统的多晶硅电阻作分压网络设计的时候,高压端会形成很强的电场E而低压端的电场较弱,多晶硅电阻高压端的载流子发生聚边效应、电阻率增加,多晶硅电阻低压端的载流子聚边效应不明显、电阻率几乎不增加,使得多晶硅电阻的电阻率在高压端和低压端的不一致,引起十分严重的非线性度,而电阻分压网络的非线性度会引起逐次逼近型模数转换器的非线性度;实验证明,采用多晶硅电阻形成逐次逼近型模数转换器的分压网络后,16位逐次逼近型模数转换器的积分非线性度(INL)上升到上百个最低有效位(LSB),这样的逐次逼近型模数转换器已经无法达到应用要求。
基于此,本发明提供一种逐次逼近型模数转换器前端高压多晶硅电阻分压网络的线性化技术方案:利用绝缘体上硅(SOI)工艺的特点,把绝缘体上硅衬底的上层硅衬底层划分成一个个绝缘隔离的衬底隔离区,并在上层硅衬底层上依次形成氧化硅层和多晶硅电阻层,且多晶硅电阻层被划分成若干个多晶硅电阻块,若干个多晶硅电阻块被一一对应地置于若干个衬底隔离区上,使得衬底隔离区的电位紧紧跟随多晶硅电阻块的电位,进而使得多晶硅电阻块与下面的衬底隔离区无法形成较强的电场,以消除载流子聚边效应、提高逐次逼近型模数转换器前端电阻分压网络的线性度。
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图15。需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供熟悉此技术的人士了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响 本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
如图3-图14所示,本发明提供一种多晶硅电阻的制造方法,其包括步骤:
S1、如图4所示,提供绝缘体上硅衬底,绝缘体上硅衬底包括沿着第一方向依次堆叠设置的第一硅衬底1、第一氧化硅层2及第二硅衬底3;
S2、如图5-图8所示,在绝缘体上硅衬底上形成绝缘隔离结构4,绝缘隔离结构4沿着第一方向贯穿第二硅衬底3并将第二硅衬底3划分为多个相互分立的衬底隔离区301、302、303、304、305;
S3、如图9所示,在绝缘体上硅衬底上形成第二氧化硅层5,第二氧化硅层5覆盖衬底隔离区301、302、303、304、305和绝缘隔离结构4;
S4、如图10-图14所示,在第二氧化硅层5上形成多晶硅电阻层,多晶硅电阻层包括相互分立的多晶硅电阻块601、602、603、604、605,多晶硅电阻块601、602、603、604、605与衬底隔离区301、302、303、304、305一一对应设置,且多晶硅电阻块601、602、603、604、605串联在一起。
详细地,如图4所示,在步骤S1中,提供的绝缘体上硅衬底包括沿着第一方向(Z轴正方向)依次堆叠设置的第一硅衬底1、第一氧化硅层2及第二硅衬底3。
其中,绝缘体上硅材料(SOI)是利用SiO
2绝缘层实现器件硅和衬底硅完全隔离的一种新型半导体材料,其可由晶圆键合、氧离子注入等多种工艺制得,晶圆键合得到的绝缘体上硅材料中埋氧层(BOX)的厚度可根据器件的要求从几百纳米到40μm以上,高压集成电路及MEME器件一般要求埋氧层的厚度大于200nm,且埋氧层要求致密。因此,在本发明中,工业用逐次逼近型模数转换器前端电阻分压网络所使用的埋氧层即第一氧化硅层2的厚度相对较大,第一氧化硅层2的厚度大于200nm。
详细地,如图5-图8所示,在绝缘体上硅衬底上形成绝缘隔离结构4的步骤S2进一步包括:
S21、如图5-图6所示,在绝缘硅衬底上形成沿着第一方向贯穿第二硅衬底3的隔离沟槽T1,隔离沟槽T1将第二硅衬底3划分为相互分立的衬底隔离区301、302、303、304、305;
S22、如图7-图8所示,用绝缘材料填充隔离沟槽T1,得到绝缘隔离结构4。
更详细地,如图5-图6所示,在步骤S21中,利用预先设置好的掩膜版,进行光刻和刻蚀,沿着第一方向的反方向刻蚀并贯穿第二硅衬底3,在第二硅衬底3中形成隔离沟槽T1,隔离沟槽T1将第二硅衬底3划分为相互分立的衬底隔离区301、302、303、304、305。
其中,隔离沟槽T1的形状和个数等具体细节在此不作限定;同时,图5-图6中仅仅示意画出了5个衬底隔离区,而衬底隔离区的具体个数可根据实际需要灵活设计,不仅限于5个,如在本发明的一可选实施例中实验证明至少要将第二硅衬底3分成10个衬底隔离区才能满足16位SAR ADC要求。
更详细地,如图7-图8所示,在步骤S22中,通过先沉积形成绝缘材料后表面平坦化处理等工艺,实现隔离沟槽T1的填充,得到绝缘隔离结构4,绝缘隔离结构4实现了衬底隔离区301、302、303、304、305之间的物理隔绝。
详细地,如图9所示,在步骤S3中,在绝缘体上硅衬底上形成第二氧化硅层5,第二氧化硅层5覆盖衬底隔离区301、302、303、304、305和绝缘隔离结构4,且第二氧化硅层5的厚度小于第一氧化硅层2的厚度,第二氧化硅层5的厚度大约为20nm~40nm。
详细地,如图10-图14所示,在第二氧化硅层5上形成多晶硅电阻层的步骤S4进一步包括:
S41、如图10所示,在第二氧化硅层5上形成掺杂多晶硅材料层6;
S42、如图11-图12所示,刻蚀掺杂多晶硅材料层6,得到相互分立的多晶硅电阻块601、602、603、604、605,且多晶硅电阻块601、602、603、604、605与衬底隔离区301、302、303、304、305一一对应设置;
S43、将多晶硅电阻块601、602、603、604、605依次串联起来,形成电阻串,并电引出电阻串的两端。
更详细地,如图10所示,在步骤S41中,在第二氧化硅层5上形成多晶硅材料层而后对多晶硅材料层进行离子掺杂,得到掺杂多晶硅材料层6,掺杂多晶硅材料层6作为多晶硅电阻的主体。
其中,掺杂的离子类型和离子浓度可根据实际需要选择,在此不作限定。
更详细地,如图11-图12所示,在步骤S42中,利用预先设置好的掩膜版,进行光刻和刻蚀,沿着第一方向的反方向刻蚀并贯穿掺杂多晶硅材料层6,在掺杂多晶硅材料层6中形成隔离沟槽T2,隔离沟槽T2将掺杂多晶硅材料层6划分为相互分离的多晶硅电阻块601、602、603、604、605,且多晶硅电阻块601、602、603、604、605与衬底隔离区301、302、303、304、305一一对应设置。
其中,图12所示为去掉第二氧化硅层5后的俯视图,如图11-图12所示,多晶硅电阻块601、602、603、604、605与衬底隔离区301、302、303、304、305一一对应设置:多晶硅电阻块601与衬底隔离区301对应设置,多晶硅电阻块602与衬底隔离区302对应设置,多 晶硅电阻块603与衬底隔离区303对应设置,多晶硅电阻块604与衬底隔离区304对应设置,多晶硅电阻块605与衬底隔离区305对应设置。
更详细地,如图13-图14所示,在步骤S43中,用导电金属7将多晶硅电阻块601、602、603、604、605依次串联起来,形成电阻串,并用导电金属7电引出电阻串的两端。
其中,图14所示为去掉第二氧化硅层5后的俯视图。
根据上述制造方法,最终制造得到一种多晶硅电阻,如图13-图14所示,其包括:
第一硅衬底1;
第一氧化硅层2,设置在第一硅衬底1上;
第二硅衬底3,设置在第一氧化硅层2上,其中设有贯穿第二硅衬底3的绝缘隔离结构4,绝缘隔离结构4将第二硅衬底3划分为相互分立的衬底隔离区301、302、303、304、305;
第二氧化硅层5,设置在第二硅衬底3上,且覆盖绝缘隔离结构4;
多晶硅电阻层,设置在第二氧化硅层5上,其包括相互分立的多晶硅电阻块601、602、603、604、605,多晶硅电阻块601、602、603、604、605与衬底隔离区301、302、303、304、305一一对应设置,且多晶硅电阻块601、602、603、604、605串联在一起。
其中,第一氧化硅层2的厚度大于第二氧化硅层5的厚度。
可选地,如图13-图14所示,在XY平面内,多晶硅电阻块601、602、603、604、605成排呈直线分布,多晶硅电阻块601、602、603、604、605的规格大小相等;且相邻两个多晶硅电阻块通过导电金属7电连接,使得多晶硅电阻块601、602、603、604、605通过导电金属7串联在一起,构成电阻串,且电阻串的两端分别通过导电7电引出。
可以理解的是,多晶硅电阻块的数目不限于5个,多个多晶硅电阻块的大小规格不一定要完全一样,可以灵活设计。
详细地,如图13-图14所示的多晶硅电阻的等效电路如图15所示:电阻R601代表多晶硅电阻块601的电阻,电容C11代表多晶硅电阻块601与衬底隔离区301之间的电容,C12代表衬底隔离区301与第一硅衬底1之间的电容;电阻R602代表多晶硅电阻块602的电阻,电容C21代表多晶硅电阻块602与衬底隔离区302之间的电容,C22代表衬底隔离区302与第一硅衬底1之间的电容;电阻R603代表多晶硅电阻块603的电阻,电容C31代表多晶硅电阻块603与衬底隔离区303之间的电容,C32代表衬底隔离区303与第一硅衬底1之间的电容;电阻R604代表多晶硅电阻块604的电阻,电容C41代表多晶硅电阻块604与衬底隔离区304之间的电容,C42代表衬底隔离区304与第一硅衬底1之间的电容;电阻R605代表多晶硅电阻块605的电阻,电容C51代表多晶硅电阻块605与衬底隔离区305之间的电容, C52代表衬底隔离区305与第一硅衬底1之间的电容。
根据实际工艺参数的设计,第一氧化硅层2的厚度(200nm以上)大于或者远大于第二氧化硅层5的厚度(20nm~40nm),使得电容C11远远大于电容C12,电容C21远远大于电容C22,电容C31远远大于电容C32,电容C41远远大于电容C42,电容C51远远大于电容C52,因此,衬底隔离区301的电位会紧紧跟随多晶硅电阻块601的电位,衬底隔离区302的电位会紧紧跟随多晶硅电阻块602的电位,衬底隔离区303的电位会紧紧跟随多晶硅电阻块603的电位,衬底隔离区304的电位会紧紧跟随多晶硅电阻块604的电位,衬底隔离区305的电位会紧紧跟随多晶硅电阻块605的电位,即衬底隔离区的电位会紧紧跟随多晶硅电阻块的电位,使得多晶硅电阻块与下面的衬底隔离区之间不会形成较大的电场,从而不会引起聚边效应。
此外,本发明还提供一种逐次逼近型模数转换器,类似图1,其包括:
电阻分压单元,其一端接输入电压、另一端接地,其包括两个上述多晶硅电阻且两个多晶硅电阻串联设置,两个多晶硅电阻的公共端输出采样电压;
带隙基准单元,输出基准电压;
逐次逼近型模数转换单元,与电阻分压单元及带隙基准单元分别连接,接收采样电压与基准电压。
其中,电阻分压单元基于上述多晶硅电阻设计而成,电阻分压单元上基本不会引起聚边效应,进而电阻分压单元的线性度提高,前端电阻分压单元线性度的提高有效降低了后端逐次逼近型模数转换单元的积分非线性度(INL),可满足逐次逼近型模数转换器的实际应用需求。
综上所述,本发明的多晶硅电阻及其制造方法,利用绝缘体上硅(SOI)工艺的特点,把绝缘体上硅衬底的上层硅衬底层划分成一个个绝缘隔离的衬底隔离区,并在上层硅衬底层上依次形成氧化硅层和多晶硅电阻层,且多晶硅电阻层被划分成若干个多晶硅电阻块,若干个多晶硅电阻块被一一对应地置于若干个衬底隔离区上,使得衬底隔离区的电位紧紧跟随多晶硅电阻块的电位,进而使得多晶硅电阻块与下面的衬底隔离区无法形成较强的电场,有效消除了多晶硅电阻上的载流子聚边效应;将该多晶硅电阻应用到逐次逼近型模数转换器的前端电阻分压网络上时,可有效提高电阻分压网络的线性度,进而降低了逐次逼近型模数转换器的积分非线性度,提高了逐次逼近型模数转换器的精度。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡 所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
Claims (10)
- 一种多晶硅电阻,其特征在于,包括:第一硅衬底;第一氧化硅层,设置在所述第一硅衬底上;第二硅衬底,设置在所述第一氧化硅层上,其中设有贯穿所述第二硅衬底的绝缘隔离结构,所述绝缘隔离结构将所述第二硅衬底划分为多个相互分立的衬底隔离区;第二氧化硅层,设置在所述第二硅衬底上;多晶硅电阻层,设置在所述第二氧化硅层上,其包括多个相互分立的多晶硅电阻块,多个所述多晶硅电阻块与多个所述衬底隔离区一一对应设置,且多个所述多晶硅电阻块串联在一起。
- 根据权利要求1所述的多晶硅电阻,其特征在于,所述第一氧化硅层的厚度大于所述第二氧化硅层的厚度。
- 根据权利要求1或2所述的多晶硅电阻,其特征在于,多个所述多晶硅电阻块成排分布,且相邻两个所述多晶硅电阻块电连接。
- 根据权利要求3所述的多晶硅电阻,其特征在于,多个所述多晶硅电阻块的规格大小相等。
- 根据权利要求4所述的多晶硅电阻,其特征在于,多个所述多晶硅电阻块通过导电金属串联在一起,构成电阻串,且所述电阻串的两端通过导电金属电引出。
- 一种多晶硅电阻的制造方法,其特征在于,包括步骤:提供绝缘体上硅衬底,所述绝缘体上硅衬底包括沿着第一方向依次堆叠设置的第一硅衬底、第一氧化硅层及第二硅衬底;在所述绝缘体上硅衬底上形成绝缘隔离结构,所述绝缘隔离结构沿着所述第一方向贯穿所述第二硅衬底并将所述第二硅衬底划分为多个相互分立的衬底隔离区;在所述绝缘体上硅衬底上形成第二氧化硅层,所述第二氧化硅层覆盖所述衬底隔离区和所述绝缘隔离结构;在所述第二氧化硅层上形成多晶硅电阻层,所述多晶硅电阻层包括多个相互分立的多晶硅电阻块,多个所述多晶硅电阻块与多个所述衬底隔离区一一对应设置,且多个所述多晶硅 电阻块串联在一起。
- 根据权利要求6所述的多晶硅电阻的制造方法,其特征在于,在所述绝缘体上硅衬底上形成所述绝缘隔离结构的步骤包括:在所述绝缘硅衬底上形成沿着所述第一方向贯穿所述第二硅衬底的隔离沟槽,所述隔离沟槽将所述第二硅衬底划分为多个相互分立的所述衬底隔离区;用绝缘材料填充所述隔离沟槽,得到所述绝缘隔离结构。
- 根据权利要求6所述的多晶硅电阻的制造方法,其特征在于,所述第二氧化硅层的厚度小于所述第一氧化硅层的厚度。
- 根据权利要求7所述的多晶硅电阻的制造方法,其特征在于,在所述第二氧化硅层上形成所述多晶硅电阻层的步骤包括:在所述第二氧化硅层上形成掺杂多晶硅材料层;刻蚀所述掺杂多晶硅材料层,得到多个相互分立的所述多晶硅电阻块,且多个所述多晶硅电阻块与多个所述衬底隔离区一一对应设置;将多个所述多晶硅电阻块依次串联起来,形成电阻串,并电引出所述电阻串的两端。
- 一种逐次逼近型模数转换器,其特征在于,包括:电阻分压单元,其一端接输入电压、另一端接地,其包括两个如权利要求1-5中任意一项所述的且串联设置的多晶硅电阻,两个所述多晶硅电阻的公共端输出采样电压;带隙基准单元,输出基准电压;逐次逼近型模数转换单元,与所述电阻分压单元及所述带隙基准单元分别连接,接收所述采样电压与所述基准电压。
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