CN105226044B - 集成电路及形成集成电路的方法 - Google Patents
集成电路及形成集成电路的方法 Download PDFInfo
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Abstract
本发明公开一种集成电路及形成集成电路的方法。该集成电路包含一电容以及一无感电阻。一基底具有一电容区以及一电阻区。一图案化堆叠结构由下至上具有一底导电层、一绝缘层以及一顶导电层,夹置于依序设置于基底上的一第一介电层以及一第二介电层之间。一第一金属插塞以及一第二金属插塞分别接触电容区的顶导电层以及底导电层,因而使在电容区中的图案化堆叠结构构成电容。一第三金属插塞以及一第四金属插塞分别接触电阻区的底导电层以及顶导电层,且一第五金属插塞同时接触电阻区的底导电层以及顶导电层,因而使在电阻区中的图案化堆叠结构构成无感电阻。
Description
技术领域
本发明涉及一种集成电路及形成集成电路的方法,且特别涉及一种集成电路及形成集成电路的方法,其中此集成电路包含一电容以及一无感电阻。
背景技术
现今半导体产业已广泛地将电容以及电阻应用于数字电路中。随着电路积极度的提升,将晶体管单元、电容以及电阻整合于同一半导体基底中,而形成一半导体装置已成为主流。
在半导体制作工艺的电路中,电容元件(capacitor)的设计原理是于半导体芯片上设置两电极层作为上、下电极板,以及一隔绝层用来将两电极层隔开至一预定距离,当两电极层上被施予电压时,就会有电荷存储于电容中。其中,金属层-绝缘层-金属层(MIM)结构所构成的金属电容器已广泛地运用于极大型集成电路(Ultra Large ScaleIntegration,ULSI)的设计上。因为此种金属电容器具有较低的电阻值以及较不显著的寄生效应,且没有空乏区感应电压(Induced Voltage)偏移的问题,因此目前多采用MIM构造作为金属电容器的主要构造。再者,电阻元件的设计原理一般以端接导电材料形成,当电流通过导电材料时,则依据该导电材料的电阻率、电流通过的截面积及长度,决定电阻值。
以上,如何根据电容元件以及电阻元件的设计原理,将电容及电阻整合于同一半导体基底,甚至于同一半导体制作工艺中,即为现今半导体产业的一重要议题。
发明内容
本发明提供一种集成电路及形成集成电路的方法,其以同一半导体制作工艺,同时形成金属层-绝缘层-金属层(MIM)电容及无感电阻。
本发明提供一种集成电路包含一电容以及一无感电阻,包含有一基底、一第一介电层、一第二介电层、一图案化堆叠结构、一第一金属插塞、一第二金属插塞、一第三金属插塞、一第四金属插塞以及一第五金属插塞。基底具有一电容区以及一电阻区。第一介电层以及第二介电层依序设置于基底上。图案化堆叠结构位于电容区以及电阻区,由下至上具有一底导电层、一绝缘层以及一顶导电层,夹置于第一介电层以及第二介电层之间。第一金属插塞以及第二金属插塞设置于第二介电层中并分别接触电容区的顶导电层以及底导电层,因而使在电容区中的图案化堆叠结构构成电容。第三金属插塞以及第四金属插塞设置于第二介电层中并分别接触电阻区的底导电层以及顶导电层,且第五金属插塞设置于第二介电层中并同时接触电阻区的底导电层以及顶导电层,因而使在电阻区中的图案化堆叠结构构成无感电阻。
本发明提供一种形成一集成电路的方法,其中集成电路包含一电容以及一无感电阻,包含有下述步骤。首先,提供一基底,具有一电容区以及一电阻区。接着,全面沉积一第一介电层于基底上。接续,形成一图案化堆叠结构于电容区以及电阻区的第一介电层上,其中图案化堆叠结构由下至上具有一底导电层、一绝缘层以及一顶导电层。继之,沉积一第二介电层于图案化堆叠结构上。而后,同时形成一第一金属插塞、一第二金属插塞、一第三金属插塞以及一第五金属插塞于第二介电层中,其中第一金属插塞以及第二金属插塞分别接触电容区的顶导电层以及底导电层,因而在电容区的图案化堆叠结构构成电容,并且第三金属插塞以及第五金属插塞接触电阻区的底导电层以及顶导电层的其中之一,其中接触第三金属插塞以及第五金属插塞的顶导电层或底导电层在第三金属插塞以及第五金属插塞之间具有一对称的图案,因而在电阻区中的图案化堆叠结构构成无感电阻。
基于上述,本发明提出一种集成电路及形成集成电路的方法,其以同一制作工艺形成具有底导电层、绝缘层以及顶导电层的图案化堆叠结构,而能同时于电容区以及电阻区中形成电容及无感电阻。因此,本发明能简化制作工艺并降低制作工艺成本、相较于一般单层电阻结构可节省一半面积、电阻的布局设计更弹性、可直接整合于一般逻辑电路制作工艺、双镶嵌(dual damascene)制作工艺或者有机重布局(organic redistributionlayout)制作工艺等优点。
附图说明
图1-图5是本发明一第一实施例的集成电路的剖面示意图;
图6是本发明一实施例的集成电路的电阻区的布局图;
图7是本发明一第二实施例的集成电路的剖面示意图;
图8是本发明一实施例的集成电路的电阻区的布局图;
图9是本发明一实施例的集成电路的电阻区的布局图;
图10式本发明一第三实施例的集成电路的剖面示意图。
主要元件符号说明
110:基底
120:第一金属层
130:第一介电层
140a:图案化堆叠结构
142、142a、242a:底导电层
144、144a:绝缘层
146、146a、246a:顶导电层
150、150a:第二介电层
162:第一金属插塞
164:第二金属插塞
166、266:第三金属插塞
168、268:第四金属插塞
169、269:第五金属插塞
267:第六金属插塞
169a、169b:接触插塞
246aa、246ab:臂
246ac、246ad:U形图案
A:电容区
B:电阻区
C1:电容
d1、d2:距离
l1:长度
P1、P2、P3、P4:电流
R1、R2、R3:无感电阻
V1、V2、V3、V4、V5、V6:接触洞
具体实施方式
图1-图5绘示本发明一第一实施例的集成电路的剖面示意图。提供一基底110,具有一电容区A以及一电阻区B。基底110例如是一硅基底、一含硅基底、一三五族覆硅基底(例如GaN-on-silicon)、一石墨烯覆硅基底(graphene-on-silicon)或一硅覆绝缘(silicon-on-insulator,SOI)基底等半导体基底。在一例中,可在基底110中/上形成MOS晶体管等结构。然后,形成一第一金属层120于基底110上。在本实施例中,第一金属层120为一内连线结构,且第一金属层120可为多层内连线结构中的其中一层,但本发明不以此为限。详细而言,则可例如以热氧化(thermal oxide)制作工艺或化学氧化(chemical oxide)制作工艺先沉积一层间介电层(未绘示)于基底110上,再将层间介电层图案化,而填入金属(未绘示)于介电层中,如此即可形成一内连线结构。以此方法,则内连线结构可由铜所组成,但本发明不以此为限。第一金属层120可例如由铝或其他金属材料所组成。
接着,全面沉积一第一介电层130于第一金属层120上。第一介电层130可例如为一氧化层,其可例如以化学氧化(chemical oxide)制作工艺形成,但本发明不以此为限。而后,依序沉积一底导电层142、一绝缘层144以及一顶导电层146于第一介电层130上。本实施例欲形成一金属-绝缘层-金属电容以及一电阻,特别是一薄层金属-绝缘层-金属电容(thin film MIM capacitors)以及一薄层电阻(thin film resistors),故底导电层142以及顶导电层146都由金属组成,其中底导电层142以及顶导电层146可包含氮化钛、氮化钽、钛、钽、铜或铝等,但本发明不以此为限。绝缘层144可例如为一高介电常数介电层,其例如为氧化铪(hafnium oxide,HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttriumoxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafniumzirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconate titanate,PbZrxTi1-xO3,PZT)与钛酸钡锶(bariumstrontium titanate,BaxSr1-xTiO3,BST)等所组成的群组。
接着,图案化顶导电层146、绝缘层144以及底导电层142,而同时于电容区A以及电阻区B中形成一图案化堆叠结构140a,其中图案化堆叠结构140a由下至上包含一底导电层142a、一绝缘层144a以及一顶导电层146a,如图2所示。详细而言,可先例如进行一蚀刻暨光刻(photolithography)制作工艺图案化顶导电层146,而形成顶导电层146a;然后,再进行一蚀刻暨光刻(photolithography)制作工艺同时图案化绝缘层144以及底导电层142,而形成绝缘层144a以及底导电层142a,但本发明的制作工艺步骤非限于此。在其他实施例中,可进行多次蚀刻制作工艺分别图案化顶导电层146、绝缘层144以及底导电层142,或者依序沉积并蚀刻底导电层142、绝缘层144以及顶导电层146,视实际所需形成的图案化堆叠结构140a的图案而定。
如图3所示,沉积一第二介电层150于图案化堆叠结构140a上。第二介电层150可例如为一氧化层,其例如以化学氧化(chemical oxide)制作工艺形成,但本发明不以此为限。如此一来,图案化堆叠结构140a则夹置于第一介电层130以及第二介电层150之间。
接着,先例如以蚀刻制作工艺图案化第二介电层150,而于第二介电层150中形成多个接触洞V1、V2、V3、V4、V5、V6并形成第二介电层150a,其中各接触洞V1、V2、V3、V4、V5、V6分别暴露出下方的顶导电层146a或底导电层142a,如图4所示。在本实施例中,接触洞V1、V4、V5暴露出顶导电层146a,而接触洞V2、V3、V6暴露出底导电层142a,但本发明不以此为限,视后续欲连接的接触插塞的位置及分别在电容区A以及电阻区B所欲形成的结构而定。
接续,同时填入金属于接触洞V1、V2、V3、V4、V5、V6中,而于第二介电层150a中形成一第一金属插塞162、一第二金属插塞164、一第三金属插塞166、一第四金属插塞168以及一第五金属插塞169,如图5所示。所填入的金属可例如为铜,但本发明不以此为限。第一金属插塞162以及第二金属插塞164分别接触电容区A的顶导电层146a以及底导电层142a,因而使在电容区A中的图案化堆叠结构140a构成一电容C1。第三金属插塞166以及第四金属168分别接触电阻区B的底导电层142a以及顶导电层146a,并且第五金属插塞169则分别以二接触插塞169a以及169b接触电阻区B的顶导电层146a以及底导电层142a,因而使在电阻区B中的图案化堆叠结构140a构成一无感电阻R1。本实施例以双镶嵌(dual damascene)制作工艺形成第一金属插塞162、第二金属插塞164、第三金属插塞166、第四金属插塞168以及第五金属插塞169,但本发明不以此为限。
在本实施例中,第五金属插塞169以接触插塞169a以及169b分别连接顶导电层146a以及底导电层142a,但在其他实施例中,则可以单一接触插塞(未绘示)同时接触顶导电层146a以及底导电层142a。本发明的目的为将顶导电层146a以及底导电层142a电连接,使流经顶导电层146a以及底导电层142a的电流P1、P2方向相反且大小相等,以抵销二电流P1、P2所产生的磁场,因而形成无感电阻R1。
在一优选的实施例中,位于第三金属插塞166以及第五金属插塞169的接触插塞169b之间的底导电层142a,与位于第四金属插塞168以及第五金属插塞169的接触插塞169a之间的顶导电层146a,具有相同图案,如此更可对应抵销电流P1、P2所产生的局部磁场,而形成更佳的无感电阻R1。图6绘示本发明一实施例的集成电路的电阻区的布局图。如图6所示,第三金属插塞166、底导电层142a以及第五金属插塞169的接触插塞169b形成一半封闭的回路,而第四金属插塞168、顶导电层146a以及第五金属插塞169的接触插塞169a形成一半封闭的回路。再者,位于第三金属插塞166以及第五金属插塞169的接触插塞169b之间的底导电层142a,与位于第四金属插塞168以及第五金属插塞169的接触插塞169a之间的顶导电层146a,都具有相同的多个U形弯曲的图案,线宽相等且彼此上下对应,故能实质上完全彼此抵销电流P1、P2所产生的局部磁场。然而,图6仅为本发明所应用的一无感电阻R1的布局图案,本发明也可应用其他的布局图案。
在此一提,电容C1与无感电阻R1绝缘,能独立操作电容C1与无感电阻R1。在本实施例中,位于电容区A的图案化堆叠结构140a与位于电阻区B的图案化堆叠结构140a之间以第一介电层130接触第二介电层150a,而将电容C1与无感电阻R1绝缘。再者,在本实施例中,电容C1与无感电阻R1以同一制作工艺形成,而设置于同一水平高度中。更详细而言,电容C1的底导电层142a与无感电阻R1的底导电层142a设置于同一水平高度;电容C1的绝缘层144a与无感电阻R1的绝缘层144a设置于同一水平高度;电容C1的顶导电层146a与无感电阻R1的顶导电层146a设置于同一水平高度。
承上,本发明所应用的第一实施例以端接电阻区B的顶导电层146a与底导电层142a,而形成无感电阻R1。如此一来,本发明仅以同一制作工艺即可整合电容及无感电阻,因而能简化制作工艺并降低制作工艺成本。此外,第一实施例以双层的结构所形成的无感电阻,相较于一般单层电阻结构可节省一半面积。再者,第一实施例的电阻的布局图无特别限制,故具有布局图的设计弹性的优点。另外,本发明可直接整合于一般逻辑电路制作工艺、双镶嵌(dual damascene)制作工艺或者有机重布局(organic redistributionlayout)制作工艺等。
以下,再提出仅以单一层顶导电层146a或者单一层底导电层142a,形成无感电阻的方法。
图7绘示本发明一第二实施例的集成电路的剖面示意图。如图7所示,电容区A中所形成的电容C1与第一实施例相同。电阻区B中则以第三金属插塞266以及第五金属插塞269接触同一顶导电层246a,以形成一无感电阻R2。在此强调,接触第三金属插塞266以及第五金属插塞269的顶导电层246a在第三金属插塞266以及第五金属插塞269之间具有一对称的图案,使流经第三金属插塞266以及第五金属插塞269之间的顶导电层246a的电流P3,可在各局部处彼此抵销所形成的磁场,而形成无感电阻R2。
以下提出二第三金属插塞266以及第五金属插塞269之间的顶导电层246a的布局图案的实施例,但本发明不限于此。如图8所示,第三金属插塞266、顶导电层246a以及第五金属插塞269形成一半封闭的回路。第三金属插塞266以及第五金属插塞269之间的顶导电层246a具有一细长的U形图案,其中U形图案的两臂246aa、246ab互相平行对应且相距的距离d1远小于两臂246aa、246ab的长度l1,因此流经U形图案的臂246aa与流经U形图案的臂246ab的大小相等且方向相反的电流P3,可实质上完全抵销,而形成无感电阻R2。或者,如图9所示,第三金属插塞266、顶导电层246a以及第五金属插塞269形成一半封闭的回路。第三金属插塞266以及第五金属插塞269之间的顶导电层246a具有二细长的U形图案246ac、246ad,其中U形图案246ac、246ad彼此平行对应且相距的距离d2远小于各U形图案246ac、246ad的总长,因此流经U形图案246ac、246ad的大小相等且方向相反的电流P3,可实质上完全抵销,而形成无感电阻R2。
承上,第二实施例仅以单一层顶导电层246a形成无感电阻R2。然而,本发明也可改以将第三金属插塞266以及第五金属插塞269分别接触底导电层242a而得一无感电阻(未绘示)。如此一来,第二实施例也可具有同一制作工艺即可整合电容及无感电阻,因而能简化制作工艺并降低制作工艺成本的优点。再者,第一实施例的电阻的布局图无特别限制,故具有布局图的设计弹性的优点。另外,本发明可直接整合于一般逻辑电路制作工艺、双镶嵌(dual damascene)制作工艺或者有机重布局(organic redistribution layout)制作工艺等。
再者,如图10所示,除了以单一层顶导电层246a形成无感电阻R2之外,可再形成一第四金属插塞268以及一第六金属插塞267于第二介电层150a中,并接触电阻区B的底导电层242a。同样地,接触第四金属插塞268以及第六金属插塞267的底导电层242a在第四金属插塞268以及第六金属插塞267之间具有一对称的图案,使流经第四金属插塞268以及第六金属插塞267之间的底导电层242a的电流P4,可在各局部彼此抵销所形成的磁场,而形成另一无感电阻R3。再者,流经顶导电层246a的电流P3以及流经底导电层242a的电流P4较佳为方向相反,以更进一步抵销彼此所产生的磁场。因此,通过各形成无感电阻的双层结构设置,相较于一般单层电阻结构则可节省一半面积。
在一优选实施例中,位于第三金属插塞266以及第五金属插塞269之间的顶导电层246a,与位于第四金属插塞268以及第六金属插塞267之间的底导电层242a,具有相同布局图案且线宽相等,以实质上使流经顶导电层246a的电流P3以及流经底导电层242a的电流P4所产生的磁场互相完全抵销而形成一较佳的无感电阻。
再者,第二实施例的结构与制作工艺方法类似于第一实施例,其中仅第二实施例的图案化堆叠结构240a与第一实施例的堆叠结构140a的不同之处:第二实施例的图案化堆叠结构240a包含底导电层242a、绝缘层244a以及顶导电层246a,而导电层242a、绝缘层244a以及顶导电层246a的水平高度彼此切齐。因而,仅需调整第二实施例的图案化堆叠结构240a与第一实施例的堆叠结构140a的沉积及蚀刻步骤,或者蚀刻暨光刻的光掩模范围即可得第二实施例的结构,故第二实施例的结构与制作工艺步骤不再赘述。
综上所述,本发明提出一种集成电路及形成集成电路的方法,其以同一制作工艺形成具有底导电层、绝缘层以及顶导电层的图案化堆叠结构,而能同时于电容区以及电阻区中形成电容,特别是金属层-绝缘层-金属层(MIM)电容,及无感电阻。换言之,本发明位于电容区作为电容的下电极的底导电层与位于电阻区作为电阻层的底导电层具有相同材料;位于电容区作为电容的上电极的顶导电层与位于电阻区作为电阻层的顶导电层具有相同材料;位于电容区的电容上下电极之间的绝缘层与位于电阻区的电阻层之间的绝缘层具有相同材料。
更进一步而言,无感电阻可以由端接底导电层以及顶导电层形成,其例如将第一金属插塞以及第二金属插塞分别接触电容区的顶导电层以及底导电层,因而使在电容区中的图案化堆叠结构构成电容;第三金属插塞以及第四金属分别接触电阻区的底导电层以及顶导电层,且第五金属插塞同时接触电阻区的底导电层以及顶导电层,因而使在电阻区中的图案化堆叠结构构成无感电阻。
或者,无感电阻可仅以单一层底导电层或者单一层顶导电层形成,其例如将第一金属插塞以及第二金属插塞分别接触电容区的顶导电层以及底导电层,因而使在电容区的图案化堆叠结构构成电容;第三金属插塞以及第五金属插塞接触电阻区的底导电层以及顶导电层的其中之一,且接触第三金属插塞以及第五金属插塞的顶导电层或底导电层在第三金属插塞以及第五金属插塞之间具有一对称的图案,因而在电阻区中的图案化堆叠结构构成无感电阻。再者,也可以此方法,同时在底导电层以及顶导电层各形成一无感电阻,且此二无感电阻又通过将底导电层以及顶导电层设计为相对应的相同图案,且流经的电流彼此相反,而再进一步抵销磁场。
因此,本发明仅以同一制作工艺即可整合电容及无感电阻,因而能简化制作工艺并降低制作工艺成本;以双层的结构所形成的无感电阻,相较于一般单层电阻结构可节省一半面积;电阻的布局设计更弹性;可直接整合于一般逻辑电路制作工艺、双镶嵌(dualdamascene)制作工艺或者有机重布局(organic redistribution layout)制作工艺等优点。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (20)
1.一种集成电路,包含电容以及无感电阻,并还包含有:
基底,具有电容区以及电阻区;
第一介电层以及第二介电层,依序设置于该基底上;
图案化堆叠结构,位于该电容区以及该电阻区,由下至上具有底导电层、绝缘层以及顶导电层,夹置于该第一介电层以及该第二介电层之间;
第一金属插塞以及第二金属插塞,设置于该第二介电层中并分别接触该电容区的该顶导电层以及该底导电层,因而使在该电容区中的该图案化堆叠结构构成该电容;以及
第三金属插塞以及第四金属插塞设置于该第二介电层中并分别接触该电阻区的该底导电层以及该顶导电层,且一第五金属插塞设置于该第二介电层中并同时接触该电阻区的该底导电层以及该顶导电层,因而使在该电阻区中的该图案化堆叠结构构成该无感电阻;
其中该底导电层与该顶导电层具有相同图案,该顶导电层与该底导电层的电流方向相反且大小相等。
2.如权利要求1所述的集成电路,其中该电容包含金属-绝缘层-金属电容。
3.如权利要求2所述的集成电路,其中该绝缘层包含高介电常数介电层。
4.如权利要求1所述的集成电路,其中该电容与该无感电阻绝缘,且位于该电容以及该无感电阻之间的该第一介电层接触该第二介电层,以绝缘该电容以及该无感电阻。
5.如权利要求1所述的集成电路,其中该第三金属插塞、位于该第三金属插塞以及该第五金属插塞之间的该底导电层以及该第五金属插塞形成一半封闭的回路,而该第四金属插塞、位于该第四金属插塞以及该第五金属插塞之间的该顶导电层以及该第五金属插塞形成一半封闭的回路。
6.如权利要求1所述的集成电路,其中该底导电层位于该第三金属插塞以及该第五金属插塞之间,该顶导电层位于该第四金属插塞以及该第五金属插塞之间。
7.如权利要求1所述的集成电路,其中该第五金属插塞包含二金属插塞彼此接触并分别接触该顶导电层以及该底导电层。
8.如权利要求1所述的集成电路,其中该电容以及该无感电阻设置于同一水平高度。
9.如权利要求8所述的集成电路,其中该电容区以及该电阻区的该底导电层,该电容区以及该电阻区的该绝缘层,以及该电容区以及该电阻区的该顶导电层,分别设置于同一水平高度。
10.如权利要求1所述的集成电路,其中该顶导电层以及该底导电层包含氮化钛、氮化钽、钛、钽、铜或铝。
11.一种形成一集成电路的方法,其中该集成电路包含电容以及无感电阻,包含有:
提供一基底,具有电容区以及电阻区;
全面沉积一第一介电层于该基底上;
形成一图案化堆叠结构于该电容区以及该电阻区的该第一介电层上,其中该图案化堆叠结构由下至上具有底导电层、绝缘层以及顶导电层;
沉积一第二介电层于该图案化堆叠结构上;以及
同时形成一第一金属插塞、一第二金属插塞、一第三金属插塞以及一第五金属插塞于该第二介电层中,其中该第一金属插塞以及该第二金属插塞分别接触该电容区的该顶导电层以及该底导电层,因而在该电容区的该图案化堆叠结构构成该电容,并且该第三金属插塞以及该第五金属插塞接触该电阻区的该底导电层以及该顶导电层的其中之一,其中接触该第三金属插塞以及该第五金属插塞的该顶导电层或该底导电层在该第三金属插塞以及该第五金属插塞之间具有一对称的图案,因而在该电阻区中的该图案化堆叠结构构成该无感电阻;
该第三金属插塞以及该第五金属插塞之间的该顶导电层具有一U形图案,该U形图案的两臂互相平行对应且相距的距离远小于该两臂的长度。
12.如权利要求11所述的形成一集成电路的方法,其中该电容包含金属-绝缘层-金属电容。
13.如权利要求12所述的形成一集成电路的方法,其中该绝缘层包含高介电常数介电层。
14.如权利要求11所述的形成一集成电路的方法,其中该电容与该无感电阻绝缘,且位于该电容以及该无感电阻之间的该第一介电层接触该第二介电层,以绝缘该电容以及该无感电阻。
15.如权利要求11所述的形成一集成电路的方法,其中该第三金属插塞、接触该第三金属插塞以及该第五金属插塞的该顶导电层或该底导电层以及该第五金属插塞构成一半封闭的回路。
16.如权利要求11所述的形成一集成电路的方法,还包含:
在形成该第三金属插塞以及该第五金属插塞以接触该电阻区的该底导电层时,形成一第四金属插塞以及一第六金属插塞于该第二介电层中,以接触该电阻区的该顶导电层。
17.如权利要求16所述的形成一集成电路的方法,其中位于该第四金属插塞以及该第六金属插塞之间的该顶导电层具有一对称图案,因而该电容区中的该图案化堆叠结构构成另一无感电阻。
18.如权利要求16所述的形成一集成电路的方法,其中位于该第三金属插塞以及该第五金属插塞之间的该底导电层,与位于该第四金属插塞以及该第六金属插塞之间的该顶导电层,具有相同图案。
19.如权利要求11所述的形成一集成电路的方法,其中该顶导电层以及该底导电层包含氮化钛、氮化钽、钛、钽、铜或铝。
20.如权利要求11所述的形成一集成电路的方法,其中在形成该图案化堆叠结构时,蚀刻该顶导电层以暴露出部分的该绝缘层以及该底导电层,以同时形成该第一金属插塞、该第二金属插塞、该第三金属插塞以及该第五金属插塞,使该第一金属插塞、该第二金属插塞、该第三金属插塞以及该第五金属插塞分别接触该顶导电层以及该底导电层。
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