WO2022226883A1 - 显示基板及其制作方法、显示母板、显示装置 - Google Patents

显示基板及其制作方法、显示母板、显示装置 Download PDF

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Publication number
WO2022226883A1
WO2022226883A1 PCT/CN2021/090942 CN2021090942W WO2022226883A1 WO 2022226883 A1 WO2022226883 A1 WO 2022226883A1 CN 2021090942 W CN2021090942 W CN 2021090942W WO 2022226883 A1 WO2022226883 A1 WO 2022226883A1
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Prior art keywords
substrate
display
sub
binding
layer
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PCT/CN2021/090942
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English (en)
French (fr)
Inventor
刘家荣
王衡
姚之晓
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/090942 priority Critical patent/WO2022226883A1/zh
Priority to US17/753,246 priority patent/US20240111191A1/en
Priority to CN202180000974.8A priority patent/CN115552323A/zh
Publication of WO2022226883A1 publication Critical patent/WO2022226883A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133351—Manufacturing of individual cells out of a plurality of cells, e.g. by dicing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13336—Combining plural substrates to produce large-area displays, e.g. tiled displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/16—Materials and properties conductive
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/28—Adhesive materials or arrangements

Definitions

  • the present disclosure relates to the technical field of manufacturing liquid crystal products, and in particular, to a display substrate and a manufacturing method thereof, a display motherboard, and a display device.
  • Splicing screen products are a segment of the display industry that has become popular in recent years.
  • the display panels with narrow borders are spliced to achieve super-large display.
  • the joint of the two display panels is an invalid display, which has a great impact on the overall effect of the spliced display.
  • the border of the display panel is getting narrower and narrower.
  • the traditional display panel adopts front binding, and the border reaches about 1-2mm, which is already the limit of the process.
  • the side binding process gradually developed to further reduce the size of the bezel.
  • the side bonding technology requires vertical grinding of the glass section first. The side bonding process grinding will cause damage to the metal leads, the stability of the contact resistance of the metal leads will decrease, and changes in external temperature and humidity will easily induce wire defects.
  • the present disclosure provides a display substrate and a manufacturing method thereof, a display motherboard, and a display device, which solve the problems caused by the metal leads on the display substrate when the side surface of the display substrate is ground during the side bonding technology. Lifting, damage, etc.
  • a display substrate comprising an array substrate and a color filter substrate arranged oppositely, a liquid crystal layer and a frame sealant are arranged between the array substrate and the color filter substrate, The frame sealant is enclosed with the array substrate and the color filter substrate to form a sealing cavity filled with the liquid crystal layer,
  • the display substrate has a binding side surface for binding and connecting with the chip-on-chip film, and the frame sealant at least includes a first part disposed close to the binding side surface, and the first part includes a contact surface with the liquid crystal layer. a first side surface and a second side surface disposed opposite to the first side surface, the second side surface being flush with the binding side surface of the display substrate;
  • the array substrate includes a display area and a non-display area disposed on the periphery of the display area, and binding pins are provided on the non-display area, and the binding pins extend to the side surface of the display substrate and are exposed.
  • the frame sealant includes a first sub-frame sealant disposed on the periphery of the liquid crystal layer, and at least one second sub-frame sealant disposed on the periphery of the first sub-frame sealant, close to the The second sub-sealing glue of the first sub-sealing glue is arranged at intervals from the first sub-sealing glue.
  • the frame-sealing glue includes at least two second sub-sealing glues arranged at intervals.
  • the first sub-sealing glue and the second sub-sealing glue are formed by the same coating process.
  • the first part includes a third sub-sealing sealant in contact with the liquid crystal layer, and at least one fourth sub-sealing sealant disposed on a side of the third sub-sealing sealant away from the liquid crystal layer. sealant, the fourth sub-sealing sealant disposed close to the third sub-sealing sealant is arranged at intervals from the third sub-sealing sealant, the fourth sub-sealing glue
  • the shape structure is parallel to the binding side surface and parallel to the array substrate.
  • the first part includes at least two of the fourth sub-sealing sealants arranged at intervals.
  • the array substrate includes a base substrate and a thin film transistor array disposed on the base substrate, and the thin film transistor array includes a gate metal layer, a gate A pole insulating layer, a source-drain metal layer and an insulating protection layer, and the binding pins are arranged in the same layer as the gate metal layer.
  • the array substrate includes a base substrate and a thin film transistor array disposed on the base substrate, and the thin film transistor array includes a gate metal layer, a gate A polar insulating layer, a source-drain metal layer and an insulating protection layer, the binding pin includes a first lead and a second lead, the first lead and the gate metal layer are arranged in the same layer, and the second lead is connected to the gate metal layer.
  • the source and drain metal layers are disposed on the same layer, and the array substrate further includes a transparent electrode layer located in the non-display area and connecting the first lead and the second lead through a via hole.
  • the present disclosure also provides a display motherboard for cutting along a cutting line to form a plurality of the above-mentioned display substrates, and the display motherboard further includes a sealant located outside the cutting line and integrated with the frame sealant. Floor.
  • the present disclosure also provides a method for fabricating a display substrate, comprising:
  • the display substrate according to any one of claims 1-6 is formed by connecting the chip-on film and the metal leads through a conductive adhesive layer.
  • the present disclosure also provides a display device, comprising the above-mentioned display substrate, and further comprising:
  • metal leads located on the side of the above-mentioned display substrate and connected with the binding pins;
  • the chip-on-chip film is connected to the metal lead through a conductive adhesive layer
  • the circuit board is bound and connected with the chip-on-chip film.
  • the metal leads extend to the color filter substrate.
  • the frame sealant covers the grinding place, protects the binding pins on the array substrate during grinding, and prevents the binding pins from being lifted and damaged.
  • FIG. 1 shows a schematic structural diagram of a display substrate in the related art
  • FIG. 2 is a schematic structural diagram 1 of a display substrate in an embodiment of the present disclosure
  • FIG. 3 shows a second structural schematic diagram of a display substrate in an embodiment of the present disclosure
  • FIG. 4 shows a third structural schematic diagram of a display substrate in an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram 4 of the structure of the display substrate in the embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram 5 of a display substrate in an embodiment of the present disclosure.
  • FIG. 7 shows a sixth schematic structural diagram of a display substrate in an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram 6 of the structure of the display substrate in the embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a partial structure of a display motherboard in an embodiment of the present disclosure.
  • the side bonding technology requires vertical grinding of the glass cross-section (including the cross-section of the array substrate 1 and the cross-section of the color filter substrate 2).
  • the metal leads (ie the binding pins) 5 of the panel will be damaged.
  • the stability of the contact resistance of the metal lead 5 decreases, and the thermal expansion and contraction caused by the external temperature and humidity will induce wire defects.
  • the traditional display panel will set the organic film 4 above the metal lead 5 as the protective layer of the metal lead 5, as shown in FIG. 1, but considering that the thickness of the organic film 4 cannot exceed the thickness of the display area to cause over-support, resulting in uneven display , the organic film 4 cannot completely fill the gap between the array substrate 1 and the color filter substrate 2, so its protective effect is weak.
  • this embodiment provides a display substrate, including an array substrate 1 and a color filter substrate 2 that are arranged opposite to each other, and a space between the array substrate 1 and the color filter substrate 2 is arranged
  • the liquid crystal layer 100 and the frame sealant 3, the frame sealant 3, the array substrate 1 and the color filter substrate 2 are encircled to form a sealed cavity filled with the liquid crystal layer 100,
  • the display substrate has a bonding side surface for bonding and connecting with the chip on film 30
  • the frame sealant 3 at least includes a first part 301 disposed close to the bonding side surface, and the first part 301 includes the a first side surface in contact with the liquid crystal layer and a second side surface disposed opposite to the first side surface, the second side surface being flush with the binding side surface of the display substrate;
  • the array substrate 1 includes a display area and a non-display area disposed on the periphery of the display area.
  • the non-display area is provided with binding pins 4, and the binding pins 4 extend to the side of the display substrate. and exposed.
  • the frame sealing glue 3 is extended to the binding side of the display substrate by using the frame sealing glue 3 originally on the display substrate, that is, the second side of the frame sealing glue 3 is connected to the display substrate.
  • the binding sides are flush with each other.
  • the purpose of protecting the binding pins 4 is achieved by using the frame sealing glue 3, and the frame sealing glue 3 completely fills the The gap between the array substrate 1 and the color filter substrate 2 can effectively protect the binding pins 4 .
  • the specific structural forms of the frame sealant 3 can be various, as long as the sealing cavity is formed by enclosing the array substrate 1 and the color filter substrate 2, the binding pins 4 can be protected. purpose can be.
  • the frame sealing glue 3 can be an integral structure, as shown in FIG. 3 and FIG. 4 , or it can have a pattern structure (that is, the frame sealing glue 3 includes a hollow part), as shown in FIG. 6 and FIG. 7 .
  • the frame sealant 3 may completely cover the non-display area of the array substrate, and as shown in FIG.
  • the first portion 301 is formed by the fixed side surface, as shown in FIG. 4 .
  • the length of the first portion 301 is smaller than that of the array
  • the length of the corresponding side of the substrate but not limited thereto, for example, in the direction parallel to the binding side and parallel to the array substrate 1 (refer to the X direction in FIG. 4 ), so The length of the first portion 301 may be equal to the length of the corresponding side of the array substrate 1 , as long as the size of the first portion 301 meets the connection requirements with the chip on film.
  • the frame sealant 3 includes a first sub-frame sealant 31 disposed on the periphery of the liquid crystal layer 100 , and a first sub-frame sealant 31 disposed around the first sub-frame sealant 31 .
  • At least one second sub-frame glue 32 on the periphery of the frame-sealing glue 31, the second sub-sealing glue 32 adjacent to the first sub-sealing glue 31 and the first sub-sealing glue 31 are arranged at intervals.
  • the second sub-sealing glue 32 disposed away from the first sub-sealing glue 31 has the second side surface, and the arrangement of the second sub-sealing glue 32 disposed at intervals reduces the cost.
  • the number of the second sub-sealing glues 32 can be set according to actual needs.
  • the frame-sealing glue includes at least two of the second sub-sealing glues 32, at least 2 The second sub-sealing glues 32 are arranged at intervals.
  • the first sub-sealant 31 and the second sub-sealant 32 are formed by the same coating process.
  • the first sub-sealing glue 31 and the second sub-sealing glue 32 are formed at one time by the same coating process to ensure that the first sub-sealing glue 31 and the second sub-sealing glue 32 have the same thickness , that is, the side of the first sub-frame sealant 31 in contact with the color filter substrate 2 and the side of the second sub-frame sealant 32 in contact with the color filter substrate 2 are located on the same plane.
  • the first part 301 includes a third sub-frame sealant 33 in contact with the liquid crystal layer 100 , and a third sub-frame sealant 33 disposed on the third sub-frame sealant 33 At least one fourth sub-frame sealant 34 on the side away from the liquid crystal layer 100 , the fourth sub-frame sealant and the third sub-frame sealant disposed close to the third sub-frame sealant
  • the fourth sub-sealing glue 34 is a strip-shaped structure, and the extension direction of the strip-shaped structure is parallel to the binding side surface and parallel to the array substrate 1 (refer to the X direction in FIG. 7 ) .
  • Only the first part 301 corresponding to the binding side has the second side, and the other parts of the frame sealant 3 adjacent to or opposite to the first part 301 and the corresponding side of the display substrate There is a gap between them, that is to say, the side of the other parts of the frame sealant 3 adjacent to or opposite to the first part 301 away from the liquid crystal layer is located on the array substrate 1 or the color filter substrate. 2, saving costs.
  • the length of the fourth sub-sealing glue 34 in the X direction can be set according to actual needs.
  • the first part includes at least two of the fourth sub-frame sealants
  • at least two of the fourth sub-frame sealants are arranged at intervals.
  • the array substrate 1 includes a base substrate and a thin film transistor array disposed on the base substrate, and the thin film transistor array includes gates disposed in sequence along a direction away from the base substrate A pole metal layer, a gate insulating layer 12, a source-drain metal layer and an insulating protection layer 14, and the binding pins 4 are arranged in the same layer as the gate metal layer.
  • the array substrate 1 includes a base substrate and a thin film transistor array disposed on the base substrate.
  • the gate metal layer, the gate insulating layer 12, the source-drain metal layer and the insulating protection layer 14 are arranged in sequence in the direction of the substrate.
  • the binding pin 4 includes a first lead 11 and a second lead 13.
  • the first lead 11 The second lead 13 is arranged in the same layer as the gate metal layer, the second lead 13 is arranged in the same layer as the source-drain metal layer, and the array substrate 1 further includes a structure located in the non-display area.
  • a lead 11 and the second lead 13 are connected to the transparent electrode layer 15 .
  • the arrangement of the first lead 11 and the second lead 13 increases the connection area between the binding pin 4 and the chip on film 30, and improves the connection stability.
  • the present disclosure further provides a display motherboard for cutting and forming a plurality of the above-mentioned display substrates along a cutting line 200
  • the display motherboard further includes a display motherboard located outside the cutting line 200 and connected to the sealing board.
  • the sealant 3 is a sealant layer 5 of an integrated structure.
  • the sealant layer 5 and the frame sealant 3 have an integral structure, that is, the sealant layer 5 is formed by extending outward from the frame sealant 3, so as to ensure that after cutting along the cutting line 200, the sealant The second side of the sealant 3 is flush with the binding side of the display substrate, so as to effectively protect the binding pins 4 .
  • the present disclosure also provides a method for fabricating a display substrate, comprising:
  • the transfer of the metal leads 10 is performed on the binding side, so that the metal leads 10 are connected to the binding pins 4;
  • the chip on film 30 is connected with the metal lead 10 through a conductive adhesive layer 20 to form the display substrate according to any one of claims 1-6.
  • the present disclosure also provides a display device, comprising the above-mentioned display substrate, and further comprising:
  • the metal lead 10 is located on the side of the above-mentioned display substrate and is connected to the binding pin 4;
  • the chip on film 30 is connected to the metal lead 10 through the conductive adhesive layer 20;
  • the circuit board 40 is bound and connected to the chip on film 30 .
  • the metal leads 10 extend to the color filter substrate 2 .
  • the metal lead 10 extends to the color filter substrate 2 , which increases the connection area between the metal lead 10 and the bonding side surface of the display substrate, and improves the connection strength.
  • the display device can be any product or component with display function, such as LCD TV, LCD, digital photo frame, mobile phone, tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种显示基板，包括相对设置的阵列基板（1）和彩膜基板（2），阵列基板（1）和彩膜基板（2）之间设置有液晶层（100）和封框胶（3），封框胶（3）与阵列基板（1）、彩膜基板（2）合围形成填充液晶层（100）的密封腔，显示基板具有用于与覆晶薄膜（30）进行绑定连接的绑定侧面，封框胶（3）至少包括靠近绑定侧面设置的第一部分（301），第一部分（301）包括与液晶层（100）接触的第一侧面和与第一侧面相对设置的第二侧面，第二侧面与显示基板的绑定侧面相齐平；阵列基板（1）包括显示区和设置于显示区外围的非显示区，非显示区上设置有绑定引脚（4），绑定引脚（4）延伸至显示基板的侧面并外露。因此，可以在研磨时保护绑定引脚。

Description

显示基板及其制作方法、显示母板、显示装置 技术领域
本公开涉及液晶产品制作技术领域，尤其涉及一种显示基板及其制作方法、显示母板、显示装置。
背景技术
拼接屏产品是近几年流行起来的显示行业细分市场。通过窄边框的显示面板进行拼接达到超大尺寸的显示，两块显示面板接缝处，由于属于无效显示，对拼接显示的整体效果有很大影响。为了追求极致的拼接显示效果，显示面板的边框越来越窄，传统的显示面板采用正面绑定，边框达到1～2mm左右，已经是工艺极限了，在这种背景下，侧面绑定工艺逐渐发展起来，进一步减小了边框的尺寸。侧面绑定技术，需要先对玻璃断面进行垂直研磨，侧面绑定工艺研磨会对金属引线(lead)造成损伤，金属引线接触电阻稳定性下降，外界的温度、湿度变化容易诱发线不良。
发明内容
为了解决上述技术问题，本公开提供一种显示基板及其制作方法、显示母板、显示装置，解决在侧面绑定技术中，对显示基板侧面进行研磨时，对显示基板上的金属引线造成的翘起、损伤等问题。
为了达到上述目的，本公开实施例采用的技术方案是：一种显示基板，包括相对设置的阵列基板和彩膜基板，所述阵列基板和彩膜基板之间设置有液晶层和封框胶，所述封框胶与所述阵列基板、所述彩膜基板合围形成填充所述液晶层的密封腔，
所述显示基板具有用于与覆晶薄膜进行绑定连接的绑定侧面，所述封框胶至少包括靠近所述绑定侧面设置的第一部分，所述第一部分包括与所述液晶层接触的第一侧面和与所述第一侧面相对设置的第二侧面，所述第二侧面与所述显示基板的绑定侧面相齐平；
所述阵列基板包括显示区和设置于所述显示区外围的非显示区，所述非显 示区上设置有绑定引脚，所述绑定引脚延伸至所述显示基板的侧面并外露。
可选的，所述封框胶包括设置于所述液晶层外围的第一子封框胶，以及围设于所述第一子封框胶外围的至少1个第二子封框胶，靠近所述第一子封框胶的所述第二子封框胶与所述第一子封框胶间隔设置。
可选的，所述封框胶包括至少2个间隔设置的所述第二子封框胶。
可选的，所述第一子封框胶和所述第二子封框胶是通过同一涂覆工艺形成。
可选的，所述第一部分包括与所述液晶层接触的第三子封框胶，以及设置于所述第三子封框胶远离所述液晶层的一侧的至少1个第四子封框胶，靠近所述第三子封框胶设置的所述第四子封框胶与所述第三子封框胶间隔设置，所述第四子封框胶为条形结构，所述条形结构平行于所述绑定侧面，且平行于所述阵列基板设置。
可选的，所述第一部分包括至少2个间隔设置的所述第四子封框胶。
可选的，所述阵列基板包括衬底基板和设置于所述衬底基板上的薄膜晶体管阵列，所述薄膜晶体管阵列包括沿着远离所述衬底基板方向依次设置的栅极金属层、栅极绝缘层、源漏金属层和绝缘保护层，所述绑定引脚与所述栅极金属层同层设置。
可选的，所述阵列基板包括衬底基板和设置于所述衬底基板上的薄膜晶体管阵列，所述薄膜晶体管阵列包括沿着远离所述衬底基板方向依次设置的栅极金属层、栅极绝缘层、源漏金属层和绝缘保护层，所述绑定引脚包括第一引线和第二引线，所述第一引线与所述栅极金属层同层设置，所述第二引线与所述源漏金属层同层设置，且所述阵列基板还包括位于所述非显示区，通过过孔将所述第一引线和所述第二引线连接的透明电极层。
本公开还提供一种显示母板，用于沿切割线切割形成多个上述的显示基板，所述显示母板还包括位于所述切割线外侧且与所述封框胶为一体结构的密封胶层。
本公开还提供一种显示基板的制作方法，包括：
提供上述的显示母板；
沿切割线对所述显示母板进行切割形成多个子基板；
对所述子基板的侧面进行研磨处理以形成所述绑定侧面，且漏出所述绑定 引脚；
在所述绑定侧面进行金属引线的转印，使得所述金属引线与所述绑定引脚连接；
通过导电胶层将覆晶薄膜与所述金属引线连接形成权利要求1-6任一项所述的所述显示基板。
本公开还提供一种显示装置，包括上述所述的显示基板，还包括：
金属引线，位于上述的显示基板的侧面且与所述绑定引脚连接；
覆晶薄膜，通过导电胶层与所述金属引线连接；
电路板，与所述覆晶薄膜绑定连接。
可选的，在垂直于所述阵列基板的方向，所述金属引线延伸至所述彩膜基板。
本公开的有益效果是：使得封框胶覆盖研磨处，研磨时保护阵列基板上的绑定引脚，避免绑定引脚的翘起、损伤。
附图说明
图1表示相关技术中的显示基板的结构示意图；
图2表示本公开实施例中的显示基板的结构示意图一；
图3表示本公开实施例中的显示基板的结构示意图二；
图4表示本公开实施例中的显示基板的结构示意图三；
图5表示本公开实施例中的显示基板的结构示意图四；
图6表示本公开实施例中的显示基板的结构示意图五；
图7表示本公开实施例中的显示基板的结构示意图六；
图8表示本公开实施例中的显示基板的结构示意图六；
图9表示本公开实施例中的显示母板的部分结构示意图；
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的 本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。此外，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性。
侧面绑定技术，需要先对玻璃断面(包括阵列基板1的断面和彩膜基板2的断面)进行垂直研磨，在研磨的过程，会对面板的金属引线(即绑定引脚)5造成损伤，绑定完成后，金属引线5的接触电阻稳定性下降，外界的温度、湿度引起的热胀冷缩会诱发线不良发生。传统的显示面板会在金属引线5上方设置有机膜4作为金属引线5的保护层，如图1所示，但是考虑有机膜4的厚度不能超过显示区的厚度引发过支撑，从而造成显示不均，有机膜4不能完全填充阵列基板1和彩膜基板2之间的间隙，所以其保护效果较弱。
如图2-图8所示，针对上述技术问题，本实施例提供一种显示基板，包括相对设置的阵列基板1和彩膜基板2，所述阵列基板1和彩膜基板2之间设置有液晶层100和封框胶3，所述封框胶3与所述阵列基板1、所述彩膜基板2合围形成填充所述液晶层100的密封腔，
所述显示基板具有用于与覆晶薄膜30进行绑定连接的绑定侧面，所述封框胶3至少包括靠近所述绑定侧面设置的第一部分301，所述第一部分301包括与所述液晶层接触的第一侧面和与所述第一侧面相对设置的第二侧面，所述第二侧面与所述显示基板的绑定侧面相齐平；
所述阵列基板1包括显示区和设置于所述显示区外围的非显示区，所述非显示区上设置有绑定引脚4，所述绑定引脚4延伸至所述显示基板的侧面并外露。
采用上述技术方案，利用所述显示基板上原本具有的封框胶3，将至少部分封框胶3延伸至显示基板的绑定侧面，即使得封框胶3的所述第二侧面与显示基板的绑定侧面相齐平，相比相关技术中独立设置有机膜的设置，利用所述 封框胶3实现保护所述绑定引脚4的目的，所述封框胶3完全填充了所述阵列基板1和所述彩膜基板2之间的空隙，能够有效的保护所述绑定引脚4。
所述封框胶3的具体结构形式可以有多种，只要在实现与所述阵列基板1、所述彩膜基板2合围形成所述密封腔的基础上，实现保护所述绑定引脚4的目的即可。
所述封框胶3可以是一不可分割的整体结构，如图3和图4所示，也可以具有图案结构(即所述封框胶3包括镂空部分)，如图6和图7所示，所述封框胶3可以是完全覆盖所述阵列基板的非显示区，如图3所示，所述封框胶3也可以仅在靠近所述绑定侧面的一侧延伸至所述绑定侧面形成所述第一部分301，如图4所示。
需要说明的是，在图4中，在平行于所述绑定侧面且平行于所述阵列基板1的方向上(参考图4中的X方向)，所述第一部分301的长度小于所述阵列基板1的相应的侧边的长度，但并不以此为限，例如，在平行于所述绑定侧面且平行于所述阵列基板1的方向上(参考图4中的X方向)，所述第一部分301的长度可以等于所述阵列基板1的相应的侧边的长度，只要所述所述第一部分301的尺寸满足与覆晶薄膜的连接要求即可。
如图5-图6所示，本实施例中示例性的，所述封框胶3包括设置于所述液晶层100外围的第一子封框胶31，以及围设于所述第一子封框胶31外围的至少1个第二子封框胶32，靠近所述第一子封框胶31的所述第二子封框胶32与所述第一子封框胶31间隔设置。
远离所述第一子封框胶31设置的所述第二子封框胶32具有所述第二侧面，采用间隔设置的所述第二子封框胶32的设置，降低了成本。
所述第二子封框胶32的数量的设置可以根据实际需要设定，本实施例中示例性的，所述封框胶包括至少2个所述第二子封框胶32时，至少2个所述第二子封框胶32间隔设置。
本实施例中示例性的，所述第一子封框胶31和所述第二子封框胶32是通过同一涂覆工艺形成。
采用同一涂覆工艺一次性形成所述第一子封框胶31和所述第二子封框胶32，保证所述第一子封框胶31和所述第二子封框胶32等厚，即使得所述第一 子封框胶31与所述此彩膜基板2接触的一面和所述第二子封框胶32与所述彩膜基板2接触的一面位于同一平面。
如图5和图7所示，本实施例中示例性的，所述第一部分301包括与所述液晶层100接触的第三子封框胶33，以及设置于所述第三子封框胶33远离所述液晶层100的一侧的至少1个第四子封框胶34，靠近所述第三子封框胶设置的所述第四子封框胶与所述第三子封框胶间隔设置，所述第四子封框胶34为条形结构，所述条形结构的延伸方向平行于所述绑定侧面，且平行于所述阵列基板1设置(参考图7中X方向)。
只有与所述绑定侧面相对应的所述第一部分301具有所述第二侧面，而所述封框胶3上与所述第一部分301相邻或相对的其他部分与显示基板的相应的侧面之间是具有间隙的，也就是说，所述封框胶3上与所述第一部分301相邻或相对的其他部分远离所述液晶层的侧面位于所述阵列基板1或所述彩膜基板2内，节省成本。
需要说明的是，所述第四子封框胶34在X方向上的长度可根据实际需要设定。
本实施例中示例性的，所述第一部分包括至少2个所述第四子封框胶时，至少2个所述第四子封框胶间隔设置。
本实施例中示例性的，所述阵列基板1包括衬底基板和设置于所述衬底基板上的薄膜晶体管阵列，所述薄膜晶体管阵列包括沿着远离所述衬底基板方向依次设置的栅极金属层、栅极绝缘层12、源漏金属层和绝缘保护层14，所述绑定引脚4与所述栅极金属层同层设置。
如图8所示，本实施例中示例性的，所述阵列基板1包括衬底基板和设置于所述衬底基板上的薄膜晶体管阵列，所述薄膜晶体管阵列包括沿着远离所述衬底基板方向依次设置的栅极金属层、栅极绝缘层12、源漏金属层和绝缘保护层14，所述绑定引脚4包括第一引线11和第二引线13，所述第一引线11与所述栅极金属层同层设置，所述第二引线13与所述源漏金属层同层设置，且所述阵列基板1还包括位于所述非显示区，通过过孔将所述第一引线11和所述第二引线13连接的透明电极层15。
所述第一引线11和所述第二引线13的设置增加了所述绑定引脚4与所述 覆晶薄膜30的连接面积，提高了连接稳定性。
如图9所示，本公开还提供一种显示母板，用于沿切割线200切割形成多个上述的显示基板，所述显示母板还包括位于所述切割线200外侧且与所述封框胶3为一体结构的密封胶层5。
所述密封胶层5与所述封框胶3为一体结构，即所述密封胶层5是由所述封框胶3向外延伸形成，保证沿所述切割线200切割后，所述封框胶3的所述第二侧面与所述显示基板的绑定侧面齐平，以有效的保护所述绑定引脚4。
本公开还提供一种显示基板的制作方法，包括：
提供上述的显示母板；
沿切割线200对所述显示母板进行切割形成多个子基板；
对所述子基板的侧面进行研磨处理以形成所述绑定侧面，且漏出所述绑定引脚4；
在所述绑定侧面进行金属引线10的转印，使得所述金属引线10与所述绑定引脚4连接；
通过导电胶层20将覆晶薄膜30与所述金属引线10连接形成权利要求1-6任一项所述的所述显示基板。
本公开还提供一种显示装置，包括上述的显示基板，还包括：
金属引线10，位于上述的显示基板的侧面且与所述绑定引脚4连接；
覆晶薄膜30，通过导电胶层20与所述金属引线10连接；
电路板40，与所述覆晶薄膜30绑定连接。
本实施例中示例性的，在垂直于所述阵列基板1的方向，所述金属引线10延伸至所述彩膜基板2。
所述金属引线10延伸至所述彩膜基板2，增加了所述金属引线10与所述显示基板的绑定侧面的连接面积，提高了连接强度。
所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
以上所述为本公开较佳实施例，需要说明的是，对于本领域普通技术人员来说，在不脱离本公开所述原理的前提下，还可以做出若干改进和润饰，这些 改进和润饰也应视为本公开保护范围。

Claims (12)

  1. 一种显示基板，包括相对设置的阵列基板和彩膜基板，所述阵列基板和彩膜基板之间设置有液晶层和封框胶，所述封框胶与所述阵列基板、所述彩膜基板合围形成填充所述液晶层的密封腔，其中，
    所述显示基板具有用于与覆晶薄膜进行绑定连接的绑定侧面，所述封框胶至少包括靠近所述绑定侧面设置的第一部分，所述第一部分包括与所述液晶层接触的第一侧面和与所述第一侧面相对设置的第二侧面，所述第二侧面与所述显示基板的绑定侧面相齐平；
    所述阵列基板包括显示区和设置于所述显示区外围的非显示区，所述非显示区上设置有绑定引脚，所述绑定引脚延伸至所述显示基板的侧面并外露。
  2. 根据权利要求1所述的显示基板，其中，所述封框胶包括设置于所述液晶层外围的第一子封框胶，以及围设于所述第一子封框胶外围的至少1个第二子封框胶，靠近所述第一子封框胶的所述第二子封框胶与所述第一子封框胶间隔设置。
  3. 根据权利要求2所述的显示基板，其中，所述封框胶包括至少2个间隔设置的所述第二子封框胶。
  4. 根据权利要求2所述的显示基板，其中，所述第一子封框胶和所述第二子封框胶是通过同一涂覆工艺形成。
  5. 根据权利要求1所述的显示基板，其中，所述第一部分包括与所述液晶层接触的第三子封框胶，以及设置于所述第三子封框胶远离所述液晶层的一侧的至少1个第四子封框胶，靠近所述第三子封框胶设置的所述第四子封框胶与所述第三子封框胶间隔设置，所述第四子封框胶为条形结构，所述条形结构平行于所述绑定侧面，且平行于所述阵列基板设置。
  6. 根据权利要求5所述的显示基板，其中，所述第一部分包括至少2个间隔设置的所述第四子封框胶。
  7. 根据权利要求1所述的显示基板，其中，所述阵列基板包括衬底基板和设置于所述衬底基板上的薄膜晶体管阵列，所述薄膜晶体管阵列包括沿着远离所述衬底基板方向依次设置的栅极金属层、栅极绝缘层、源漏金属层和绝缘 保护层，所述绑定引脚与所述栅极金属层同层设置。
  8. 根据权利要求1所述的显示基板，其中，所述阵列基板包括衬底基板和设置于所述衬底基板上的薄膜晶体管阵列，所述薄膜晶体管阵列包括沿着远离所述衬底基板方向依次设置的栅极金属层、栅极绝缘层、源漏金属层和绝缘保护层，所述绑定引脚包括第一引线和第二引线，所述第一引线与所述栅极金属层同层设置，所述第二引线与所述源漏金属层同层设置，且所述阵列基板还包括位于所述非显示区，通过过孔将所述第一引线和所述第二引线连接的透明电极层。
  9. 一种显示母板，其中，用于沿切割线切割形成多个权利要求1-8任一项所述的显示基板，所述显示母板还包括位于所述切割线外侧且与所述封框胶为一体结构的密封胶层。
  10. 一种显示基板的制作方法，其中，包括：
    提供权利要求9所述的显示母板；
    沿切割线对所述显示母板进行切割形成多个子基板；
    对所述子基板的侧面进行研磨处理以形成所述绑定侧面，且漏出所述绑定引脚；
    在所述绑定侧面进行金属引线的转印，使得所述金属引线与所述绑定引脚连接；
    通过导电胶层将覆晶薄膜与所述金属引线连接形成权利要求1-6任一项所述的所述显示基板。
  11. 一种显示装置，其中，包括权利要求1-8任一项所述的显示基板，还包括：
    金属引线，位于权利要求1-6任一项所述的显示基板的侧面且与所述绑定引脚连接；
    覆晶薄膜，通过导电胶层与所述金属引线连接；
    电路板，与所述覆晶薄膜绑定连接。
  12. 根据权利要求11所述的显示装置，其中，在垂直于所述阵列基板的方向，所述金属引线延伸至所述彩膜基板。
PCT/CN2021/090942 2021-04-29 2021-04-29 显示基板及其制作方法、显示母板、显示装置 WO2022226883A1 (zh)

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