WO2023231682A1 - 阵列基板、显示装置 - Google Patents

阵列基板、显示装置 Download PDF

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Publication number
WO2023231682A1
WO2023231682A1 PCT/CN2023/091822 CN2023091822W WO2023231682A1 WO 2023231682 A1 WO2023231682 A1 WO 2023231682A1 CN 2023091822 W CN2023091822 W CN 2023091822W WO 2023231682 A1 WO2023231682 A1 WO 2023231682A1
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WIPO (PCT)
Prior art keywords
substrate
area
binding
groove
orthographic projection
Prior art date
Application number
PCT/CN2023/091822
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English (en)
French (fr)
Inventor
刘弘
谢建云
徐敬义
肖振宏
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2023231682A1 publication Critical patent/WO2023231682A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present application relates to the field of display technology, and in particular to an array substrate, an array substrate and a method for preparing a coding pattern.
  • an array substrate including: a substrate, a display area and a binding area located on the substrate, the binding area being located on one side of the display area;
  • the array substrate also includes:
  • An alignment layer extending from the display area to the binding area
  • the binding terminal is located in the binding area, and the orthographic projection of the alignment layer on the substrate and the orthographic projection of the binding terminal on the substrate do not overlap with each other;
  • the minimum distance between the binding terminal and the edge of the display area is less than or equal to
  • the alignment layer is located at a maximum distance from an edge of a portion of the binding area to an edge of the display area.
  • the array substrate includes a connection layer located in the binding area, the connection layer covers the surface of the side of the binding terminal away from the substrate, and extends Extending to the area outside the bonding terminal, the orthographic projection of the connection layer on the substrate overlaps with the orthographic projection of the portion of the alignment layer located in the bonding area on the substrate.
  • the binding area includes a first binding subarea and a second binding subarea, and the first binding subarea is located between the second binding subarea and the display Between areas, some of the binding terminals are located in the first binding sub-area, and some of the binding terminals are located in the second binding sub-area;
  • the orthographic projection of the connection layer on the substrate is consistent with the alignment layer on the substrate on the side of the first binding sub-region away from the second binding sub-region. There is overlap in orthographic projections.
  • the array substrate further includes a flat layer extending from the display area to the binding area, and the flat layer is disposed in a portion of the binding area. between the connection layer and the substrate; the portion of the flat layer located in the first binding sub-region is provided with a first groove, and the portion of the flat layer located in the second binding sub-region is provided with a first groove. second groove;
  • each binding terminal of the first binding sub-region is located in the first groove, and the second binding sub-region
  • Each of the binding terminals is located in the second groove, and the orthographic projection of the outer contour of the first groove on the substrate and the outer contour of the second groove are on the substrate.
  • the area between the orthographic projections on the base and the orthographic projection of the alignment layer on the substrate do not overlap with each other.
  • the area defined by the orthographic projection of the outer contour of each groove on the substrate at least partially overlaps with the orthographic projection of the connection layer on the substrate, and each of the grooves The area enclosed by the orthographic projection of the outer contour of the groove on the substrate does not overlap with the orthographic projection of the alignment layer on the substrate.
  • a third groove is further provided on the flat layer, the third groove is provided in communication with the first groove, and the third groove moves away from the first groove in the first direction.
  • the direction of the first binding sub-area extends, and the first direction is perpendicular to the display area and points to the binding area; in the direction along the display area to the binding area, the first direction
  • the size of the orthographic projection of the third groove on the substrate is smaller than the size of the orthographic projection of the first groove on the substrate.
  • the orthographic projection of the outer contour of the first groove on the substrate encircles the area
  • the orthographic projection of the outer contour of the second groove on the substrate encircles the area.
  • the areas are all located within the orthographic projection of the connection layer on the substrate;
  • the area defined by the orthographic projection of the outer contour of the third groove on the substrate overlaps with the orthographic projection of the connection layer on the substrate.
  • one end of the third groove away from the first groove to an edge of the connection layer is greater than or equal to 300 ⁇ m and less than or equal to 800 ⁇ m.
  • the array substrate includes a fan-out area located between the display area and the binding area; the array substrate further includes connection traces, and the connection traces are connected from the The fan-out area extends to the bonding area, and the portion of the connection trace located in the bonding area is provided in the bonding area except for the first bonding sub-area and the second bonding sub-area. Outside the area, the connecting trace is electrically connected to the binding terminal; the area delineated by the orthographic projection of the outer contour of the third groove on the substrate and part of the connecting trace are on the Orthographic overlay on the substrate.
  • the array substrate further includes a gate layer and a source and drain metal layer, and the gate layer and the source and drain metal layer are insulated from each other; the source and drain metal layer is located on the between the flat layer and the substrate, the gate layer is located between the source and drain metal layers and the substrate;
  • connection traces includes a first line segment and a second line segment, the first line segment is located on the gate layer, and the second line segment is located on the source and drain metal layer;
  • the orthographic projection of the first line segment on the substrate is located within the area circled by the orthographic projection of the outer contour of the third groove on the substrate, and the second line segment is located on the substrate.
  • the orthographic projection on the bottom is located outside the area circled by the orthographic projection of the outer contour of the third groove on the substrate, and the first line segment and the second line segment are electrically connected.
  • the second line segment includes a first sub-line segment and a second sub-line segment
  • the orthographic projection of the first line segment on the substrate is located at the position of the first sub-line segment. between the orthographic projection on the substrate and the orthographic projection of the second sub-line segment on the substrate; the first sub-line segment is electrically connected to the second sub-line segment through the first line segment;
  • the second sub-line segment is located on a side of the first sub-line segment away from the display area, and the orthographic projection of the alignment layer on the substrate is the same as the orthographic projection of the first sub-line segment on the substrate.
  • the orthographic projections of the alignment layer on the substrate overlap, and the orthographic projection of the alignment layer on the substrate does not overlap with the orthographic projection of at least part of the second sub-line segment on the substrate.
  • the array substrate further includes at least one conductive pattern, the conductive pattern is located between the bonding terminal and the connecting trace, and the conductive pattern is on the substrate.
  • the orthographic projection is located within the area enclosed by the orthographic projection of the outer contour of the first groove on the substrate.
  • the area enclosed by the orthographic projection of the outer contour of each groove on the substrate is located within the orthographic projection of the connection layer on the substrate.
  • the minimum distance between each of the binding terminals arranged along the side wall of the first groove in the first binding sub-region and the side wall of the first groove is less than or equal to the first preset value
  • the minimum distance between each binding terminal arranged along the second groove side wall in the second binding sub-region and the second groove side wall is less than or is equal to the first preset value
  • the first preset value is the process deviation value
  • the distance from the surface of the connection layer covering the binding terminal away from the surface of the substrate to the substrate in a direction perpendicular to the plane of the substrate is less than The distance between the rest of the connection layer and the surface of the substrate away from the substrate in a direction perpendicular to the plane of the substrate.
  • At least one fourth groove is further provided on the flat layer, and the fourth groove is disconnected from the first groove, and the array substrate further includes a At least one conductive pattern in the binding area, one conductive pattern is disposed in one of the fourth grooves, and the distance between the conductive pattern and the side wall of the fourth groove is less than or equal to the first a default value.
  • the flat layer is provided with two fourth grooves located on the same side of the first groove, and the first groove points in the direction of the fourth groove. Perpendicular to the direction in which the display area points to the binding area;
  • the orthographic projection of the portion of the flat layer located between two adjacent fourth grooves on the substrate overlaps with the orthographic projection of the alignment layer on the substrate.
  • embodiments of the present application provide a display device, including the array substrate as described above.
  • the display device further includes a driver chip, the driver chip is electrically connected to the binding terminal through the connection layer, the connection layer includes an anisotropic conductive adhesive film, and the The orthographic projection of the driver chip on the substrate is located within the orthographic projection of the connection layer on the substrate.
  • the display device further includes a flexible circuit board, the flexible circuit board is electrically connected to the binding electrode on the array substrate through a conductive layer, the conductive layer includes anisotropic conductive glue membrane.
  • the display device further includes an opposite substrate, the opposite substrate and the array substrate are arranged oppositely, and the orthographic projection of the opposite substrate on the substrate is not in line with the Binding areas overlap.
  • Figure 1 Figure 4A and Figure 4B are schematic structural diagrams of array substrates in three related technologies provided by embodiments of the present application;
  • Figure 4B is a cross-sectional view along the M1M12 direction of Figure 4A;
  • FIGS 2 and 3 are schematic structural diagrams of the binding areas of two narrow-frame array substrates provided by embodiments of the present application;
  • 5-14 are schematic diagrams of the groove structure design of the binding areas of ten types of array substrates provided by embodiments of the present application.
  • the edge PI Edge of the alignment layer in the display panel is located between the edge AA Edge of the display area and the upper edge of the driver chip IC in the bonding area BB, and the edge PI of the alignment layer
  • the distance D3 between Edge and the upper edge of the driver chip IC in the direction of the display area AA pointing to the binding area BB is usually about 1.57mm.
  • the distance D4 between the edge PI Edge of the alignment layer and the edge AA Edge of the display area is usually At about 0.6mm ⁇ 1.2mm, the distance D2 between the upper edge of the driver chip IC and the edge Panel Edge of the display panel is usually about 1.57mm. In this way, the distance between the edge AA Edge of the display area and the edge Panel Edge of the display panel is The range of distance D1 (bottom border size) is 2.8mm ⁇ 3.2mm.
  • a groove K1 is provided in the flat layer PLN in the binding area BB, so that the binding terminals of the output end are all provided in the groove K1, and the driver chip IC is set On each bonding terminal and electrically connected to each bonding terminal, in the process of preparing the alignment layer, when the process is unstable or abnormal, the alignment material PI flowing to the bonding area BB flows around the edge of the groove K1, so that The alignment material PI does not cover the bonding terminals on the output side.
  • the edge PI Edge of the alignment layer is set to have a certain distance from the upper edge of the driver chip IC. This is not conducive to the design and preparation of narrow-frame display products.
  • an array substrate as shown in FIG. 2 , including: a substrate, a display area AA located on the substrate, and a binding area BB.
  • the binding area BB is located one side of the display area AA. side; the array substrate also includes:
  • Alignment layer PI extends from display area AA to binding area BB;
  • the binding terminal 1 is located in the binding area BB, and the orthographic projection of the alignment layer PI on the substrate does not overlap with the orthographic projection of the binding terminal 1 on the substrate;
  • the minimum distance D5 between the binding terminal 1 and the edge of the display area AA is less than or equal to the alignment layer PI located at the binding area.
  • the dotted box marked IC in Figures 1 and 2 refers to the area enclosed by the outer contour of the driver chip after welding the driver chip, which is for illustration only.
  • the array substrate includes a display area AA and a peripheral area surrounding the display area.
  • the peripheral area includes at least one binding area BB, where between the display area AA and the binding area BB, there can also be A fan-out area CC is provided.
  • the above extension from the display area AA to the binding area BB can be understood as: extending from the display area AA to the fan-out area CC and then to the binding area BB.
  • the meanings of the relevant descriptions in the following text are similar to those here and will not be described again.
  • the area marked FPC refers to the area delineated by the outer contour of the bound flexible circuit board after the flexible circuit board is bound. Area.
  • the specific structure in the display area AA of the array substrate is not limited here, and the specific structure can be determined according to the actual situation.
  • the specific structure and number of the binding terminals 1 in the binding area BB are not limited here, and can be determined based on the actual design.
  • the minimum distance D5 between the binding terminal 1 and the edge of the display area AA refers to: among the binding terminals 1 , the binding terminal 1 closest to the display area AA points along the display area AA The distance from the direction of the binding area BB to the edge of the display area AA.
  • the range of D5 is 0.5mm ⁇ 1.1mm, for example, 1.05mm or 1.06mm.
  • the maximum distance D6 between the edge PI Edge of the part of the alignment layer PI located in the binding area BB and the edge AA Edge of the display area refers to: the edge PI Edge of the alignment layer is distanced from the edge AA of the display area. The distance between the farthest part of the Edge and the edge of the display area AA along the direction in which the display area AA points to the binding area BB.
  • the range of D6 is 0.6mm ⁇ 1.2mm, for example, 1.1mm or 1.06mm.
  • the alignment layer PI is set to extend toward the bonding area BB, and the alignment layer PI is set to bypass the area where the bonding terminal 1 is located, so that the alignment layer PI is parallel to the plane where the substrate is located, And along the direction from the display area AA to the binding area BB, the minimum distance D5 between the binding terminal 1 and the edge of the display area AA is less than or equal to the edge PI of the part of the alignment layer PI located in the binding area BB Edge to the display area The maximum distance D6 between the edges of AA Edge.
  • the alignment layer PI covering the bonding terminal 1 and affecting the normal conduction between the bonding terminal 1 and the driver chip.
  • it can greatly reduce the The distance between the area where the binding terminal 1 is located and the display area AA along the direction from the display area AA to the binding area BB is conducive to reducing the size of the frame on the side of the display device where the binding area BB is located.
  • edge PI Edge of the alignment layer is not entirely a straight line segment. Due to the fluidity of the alignment layer PI material, its edge will appear arcuate.
  • the alignment in the drawings provided in the embodiments of this application The edge of the layer PI Edge only shows the outline of the alignment layer. Set.
  • the distance D2 between the upper edge of the driver chip IC of the array substrate provided by the embodiment of the present application and the edge Panel Edge of the array substrate can be in the range of 1.4mm to 1.6mm, for example, about 1.57mm.
  • the embodiment of the present application provides the edge AA Edge of the display area of the array substrate to the edge Panel of the array substrate
  • the distance D7 (bottom frame size) between Edges ranges from 2.4mm to 2.8mm, for example, about 2.5mm.
  • the array substrate includes a connection layer 102 located in the bonding area BB, and the connection layer 102 covers the bonding terminal 1 away from the liner.
  • the surface of one side of the bottom 100 and extending to the area beyond the bonding terminals, the orthographic projection of the connection layer 102 on the substrate 100 intersects with the orthographic projection of the portion of the alignment layer PI located in the bonding area BB on the substrate 100 Stack.
  • the dotted box marked ACF refers to the area enclosed by the outer contour of the connection layer after the connection layer is formed.
  • the orthographic projection of the connection layer and the orthographic projection of the alignment layer exist. Overlapping areas are filled with diagonal lines, as an example only.
  • connection layer may be anisotropic conductive film (ACF), and the connection layer is used to electrically connect the driver chip and the bonding terminal together.
  • ACF anisotropic conductive film
  • the material of the alignment layer is not limited here.
  • the material of the alignment layer can be polyimide (PI).
  • PI polyimide
  • the structure marked PI in the drawings provided in the embodiments of this application represents the alignment layer. , but it does not mean that the material of the alignment layer can only be polyimide (PI).
  • the binding area BB includes a first binding sub-area B1 and a second binding sub-area B2, and the first binding sub-area B1 is located in the second binding sub-area Between B2 and display area AA, some binding terminals are located in the first binding sub-area B1, and some binding terminals are located in the first binding sub-area B1.
  • the terminal is located in the second binding sub-region B2; wherein, the orthographic projection of the connection layer 102, such as ACF, on the substrate 100 and the alignment layer PI are located on the side of the first binding sub-region B1 away from the second binding sub-region B2 There is overlap in the orthographic projections of the portions on the substrate 100 .
  • the binding terminal 1 in the first binding sub-area B1 is an output terminal
  • the binding terminal 1 in the second binding sub-area B2 is an input terminal
  • the orthographic projection of the connection layer on the substrate is aligned with the alignment layer located in the binding area.
  • the overlap of the orthographic projections on the substrate greatly reduces the distance between the connection layer and the edge of the display area in a direction parallel to the plane of the substrate and with the display area pointing towards the binding area, thereby reducing
  • the size of the binding area of the array substrate is reduced, thereby facilitating the preparation of narrow-frame display products.
  • the array substrate further includes a flat layer 101.
  • the flat layer 101 extends from the display area AA to the binding area BB.
  • the flat layer 101 is provided The portion of the binding area BB is located between the connection layer 102 and the substrate 100; the portion of the flat layer 101 located in the first binding sub-region B1 is provided with a first groove K1, and the flat layer 101 is located in the second binding sub-region B2.
  • a second groove K2 is provided in a part of Each binding terminal 1 in the stator area B2 is located in the second groove K2,
  • the flat layer plays the role of insulation and planarization, and the material of the flat layer is an organic insulating material, such as resin.
  • the area defined by the orthographic projection of the outer contour of each groove on the substrate 100 at least partially overlaps with the orthographic projection of the connection layer 102 on the substrate 100, and the outer contour of each groove is in The area enclosed by the orthographic projection on the substrate 100 does not overlap with the orthographic projection of the alignment layer PI on the substrate 100 .
  • the alignment layer in order to reduce the size between the edge of the array substrate and the edge of the display area, the alignment layer may be provided to extend into the binding area. However, after the alignment layer is formed In the subsequent process, all bonding terminals need to be bonded with the driver chip through the connection layer.
  • the alignment layer PI is set to extend to the vicinity of the left and right sides of the first groove K1, but the alignment layer PI cannot extend to the area between the first groove K1 and the second groove K2, thus reducing the
  • the frame size of the array substrate not only facilitates the preparation of display products with narrow frames, but also ensures the conduction stability between the binding terminals, connection layers and driver chips in the array substrate, improving the reliability and quality of the display products.
  • the alignment layer extends into the binding area. Since the coating capability of the alignment layer in the current process is 900 ⁇ m ⁇ 300 ⁇ m, the material of the alignment layer may be along the first groove K1 The edge flows into the area marked by the dotted oval circle in Figure 4A, so that the connection layers on both sides of the first groove K1 cover the alignment layer; on the other hand, after forming the connection layer and pressing the connection layer on the binding
  • the binding terminal located in the first groove K1 is The height of the fixed terminal 1 is relatively high, and the height of the conductive pattern (such as the first alignment mark pattern 2 and the second alignment mark pattern 3) located in the first groove K1 is relatively low.
  • FIG. 4B is a cross-sectional view along the M1M2 direction in FIG. 4A.
  • the connection layer peels off in local areas, eventually leading to poor conduction between the binding terminals and the driver chip, and abnormal display of the display device.
  • the poor conduction can be improved by improving the adhesion between the connection layer and the underlying film layer or by preventing the material of the alignment layer from flowing into the area shown by the dotted oval circle as shown in Figure 4A. Display abnormality problem.
  • the embodiment of the present application provides a solution in which the first groove K1 is retracted as shown in Figure 5 or a solution in which outwardly extending third grooves K3 are provided on both sides of the first groove K1 as shown in Figure 11. Make improvements.
  • a third groove K3 is also provided on the flat layer 101 .
  • the third groove K3 is connected with the first groove K1 .
  • the third groove K3 is arranged along the first groove K3 .
  • the direction OA extends away from the first binding sub-area B1, and the first direction OA is perpendicular to the display area AA and points to the binding area BB; in the direction along the display area AA and towards the binding area BB, the third groove
  • the size h2 of the orthographic projection of K3 on the substrate 100 is smaller than the size h1 of the orthogonal projection of the first groove K1 on the substrate 100 .
  • the size h1 of the orthographic projection of the first groove K1 on the substrate 100 can be determined according to the size of each binding terminal 1 in the first binding sub-region B1 and the arrangement of each binding terminal 1 The method and the spacing size between the binding terminals 1 are determined together to ensure that each binding terminal 1 in the first binding sub-area B1 is located in the first groove K1, which is not limited here.
  • the specific data of the orthographic projection size h2 of the third groove K3 on the substrate 100 is not limited here.
  • the specific data may be based on the size of the actual design space. Make sure.
  • the orthogonal projection size h2 of the third groove K3 on the substrate 100 can be set to a range of 20 ⁇ m ⁇ 5 ⁇ m.
  • each groove provided in the embodiment of the present application is provided on the flat layer PLN, and the flat layer plays a role of planarization and insulation in some areas, because some areas of the flat layer need to be provided with openings to expose The bottom film layer structure is used for electrical connection. Therefore, the grooves provided on the flat layer involved in the invention of this application are all penetrating grooves. Of course, non-penetrating grooves can also be provided in other areas of the flat layer of the array substrate, and the details can be determined according to actual conditions.
  • the area defined by the orthogonal projection of the outer contour of the first groove K1 on the substrate 100 and the orthogonal projection of the outer contour of the second groove K2 on the substrate 100 are shown.
  • the areas delineated by the projection are all located within the orthographic projection of the connection layer (such as ACF) on the substrate 100; the area delineated by the orthographic projection of the outer contour of the third groove K3 on the substrate 100 is within the area of the connection layer (such as ACF) on the substrate 100.
  • the orthographic projections on base 100 partially overlap.
  • the connected grooves act as a barrier to the material of the alignment layer, making the alignment
  • the material of the layer flows along the edge of the large groove (the groove formed after the first groove K1 and the third groove K3 are connected), and finally the alignment layer is located on the side of the large groove close to the display area, even in the first groove
  • the connection layer near the side wall of groove K1 has weak adhesion, the alignment layers on both sides of the large groove are far away from the binding terminals in the first groove K1, and the alignment layers on both sides of the large groove are far away from the binding terminals in the first groove K1.
  • the alignment layer on the side is far away from both sides of the first groove K1, thus weakening the impact of the water absorption characteristics of the alignment layer material on the connection layer near the binding terminal 1.
  • the reliability test of the display device prepared on the array substrate is carried out ( Under high temperature and high humidity conditions), the adhesion of the connection layer weakens slightly, the connection between the binding terminal and the driver chip is normal, and the display effect of the display device is improved.
  • the area defined by the orthographic projection of the outer contour of the third groove K3 on the substrate 100 overlaps with the orthographic projection of the connection layer (for example, ACF) on the substrate 100, and the third groove K3 is far away from the third groove K3.
  • the area enclosed by the orthographic projection of one end of the groove K1 on the substrate 100 does not overlap with the orthographic projection of the connection layer (such as ACF) on the substrate 100.
  • connection layer such as ACF
  • the area bounded by the connection layer (such as ACF ) on the substrate 100 does not overlap, which also greatly reduces the probability that the material of the alignment layer flows into the area where the connection layer (such as ACF) is located from the direction of the arrow as shown in Figure 11, thereby reducing the alignment
  • the influence of the water absorption characteristics of the layer material on the adhesion of the connection layer reduces the probability of poor conduction between the connection layer and the binding terminal, further improving the reliability of the array substrate.
  • the minimum distance h3 between an end of the third groove K3 away from the first groove K1 and an edge of the connection layer Greater than or equal to 300 ⁇ m and less than or equal to 800 ⁇ m.
  • the size of the third groove K3 along the first direction OA may be about 1000 ⁇ m.
  • the minimum distance h3 between the end of the third groove K3 away from the first groove K1 and the edge of the connection layer is set to be less than or equal to 800 ⁇ m. , to simplify the design and reduce the difficulty of the preparation process.
  • the array substrate also includes a connection trace L
  • the array substrate includes a fan-out area located between the display area AA and the binding area BB, and the connection line
  • the trace L extends from the fan-out area to the bonding area, and the portion of the connecting trace L located in the bonding area BB is provided in the bonding area BB except for the first bonding sub-area B1 and the second bonding sub-area B2. area
  • the connecting trace L is electrically connected to the binding terminal 1; the area enclosed by the orthographic projection of the outer contour of the third groove K3 on the substrate 100 overlaps with the orthographic projection of part of the connecting trace L on the substrate 100 .
  • the extension direction of the connecting wire L and the specific electrical connection method of the connecting wire L and the binding terminal 1 are not limited here, and the details can be determined according to the actual circuit layout design.
  • the array substrate further includes a gate layer and a source and drain metal layer.
  • the gate layer and the source and drain metal layers are insulated from each other; the source and drain metal layers are located between the flat layer and the substrate.
  • the layer is located between the source and drain metal layers and the substrate; as shown in Figure 12, part of the connection trace L includes a first line segment L1 and a second line segment L2.
  • the first line segment L1 is located at the gate layer Gate, and the second line segment L2 Located on the source and drain metal layer SD;
  • the orthographic projection of the first line segment L1 on the substrate 100 is located within the area circled by the orthographic projection of the outer contour of the third groove K3 on the substrate 100, and the orthographic projection of the second line segment L2 on the substrate 100 is located within The outer contour of the third groove K3 is outside the area circled by the orthographic projection on the substrate 100, and the first line segment L1 and the second line segment L2 are electrically connected.
  • the film layers in the array substrate include a gate layer, a gate insulating layer, a source and drain metal layer, a flat layer 101, a pixel electrode layer and a connection layer which are sequentially arranged on the substrate 100.
  • Layer 102 where, when the connection trace L is located on the source and drain metal layer as shown in Figure 12, because the third groove K3 will expose a part of the area that overlaps the connection trace L, part of the source and drain metal layer will Exposure causes corrosion.
  • the array substrate provided by the embodiment of the present application is provided with the first line segment L1 located in the orthographic projection of the outer contour of the third groove K3 and within the area circled by the orthographic projection on the substrate 100 and located at the gate electrode.
  • the first line segment L1 located in the gate layer is electrically connected to the second line segment L2 located in the source-drain metal layer SD through the via hole in the gate insulation layer, thereby avoiding the third groove K3.
  • the corrosion of the connecting traces L improves the reliability and quality of the array substrate. It should be noted that, in order to simplify the design, the connection vias between the first line segment L1 and the second line segment L2 are all set at positions that overlap with the projection of the second line segment L2 to avoid the area where the third groove K3 is located. , reducing the difficulty of design and preparation processes.
  • connection traces L as shown in Figure 12 are all located on the gate layer, since the gate layer is protected by the gate insulating layer, setting the third groove K3 on the flat layer will not If the connection traces are exposed, no jumper design is required.
  • the binding terminal 1 includes three sub-layers. Specifically, in the direction away from the substrate, the three sub-layers are respectively located in the gate layer, the source and drain metal layer and the pixel electrode layer. For details, please refer to the relevant technology, which will not be discussed here. Repeat.
  • the second line segment L2 includes a first sub-line segment L21 and a second sub-line segment L22.
  • the orthographic projection of the first line segment L1 on the substrate 100 is located at the first sub-line segment.
  • the first sub-line segment L21 is electrically connected to the second sub-line segment L22 through the first line segment L1;
  • the second sub-line segment L22 is located on the side of the first sub-line segment L21 away from the display area AA, and the orthographic projection of the alignment layer PI on the substrate 100 is the same as the orthographic projection of the first sub-line segment L21 on the substrate 100.
  • the orthographic projections overlap, and the orthographic projection of the alignment layer PI on the substrate 100 does not overlap with the orthographic projection of at least part of the second sub-line segment L22 on the substrate 100 .
  • the orthographic projection of the alignment layer PI on the substrate 100 does not overlap with the orthographic projection of at least part of the second sub-line segment L22 on the substrate, including the following situations:
  • the orthographic projection of the alignment layer PI on the substrate 100 does not overlap with the orthographic projection of part of the second sub-line segment L22 on the substrate 100;
  • the orthographic projection of the alignment layer PI on the substrate 100 does not overlap with the orthographic projection of each second sub-line segment L22 on the substrate 100 .
  • the array substrate further includes at least one conductive pattern (for example, a first alignment mark pattern 2 and a second alignment mark pattern 3 ), and the conductive pattern is located on the binding Between the terminal 1 and the connecting trace L, the orthographic projection of the conductive pattern on the substrate 100 is located within the area defined by the orthographic projection of the outer contour of the first groove K1 on the substrate 100 .
  • at least one conductive pattern for example, a first alignment mark pattern 2 and a second alignment mark pattern 3
  • the connected grooves are The material plays a blocking role, causing the material of the alignment layer to flow along the edge of the large groove (the groove formed after the first groove K1 and the third groove K3 are connected), and finally the alignment layer is located in the large groove close to the display area.
  • the distance between the alignment layers on both sides of the large groove K1 and the binding terminal in the first groove K1 is The distance is far, and the alignment layers on both sides of the large groove are far away from both sides of the first groove K1, which weakens the impact of the water absorption properties of the alignment layer material on the connection layer near the binding terminal 1.
  • the adhesion of the connection layer weakened slightly, the connection between the binding terminal and the driver chip was normal, and the display effect of the display device prepared from the array substrate was improved.
  • the area delineated by the orthographic projection of the outer contour of each groove (for example, K1, K2, K4) on the substrate 100 is located on the connection layer (for example, ACF) Within the orthographic projection on substrate 100.
  • the minimum distance between each binding terminal 1 arranged along the side wall of the first groove K1 in the first binding sub-area B1 and the side wall of the first groove K1 is The distance is less than or equal to the first preset value, and the minimum distance between each binding terminal 1 arranged along the side wall of the second groove K2 in the second binding sub-area B2 and the side wall of the second groove K2 is less than or equal to the first preset value.
  • a preset value, the first preset value is the process deviation value.
  • the first groove K1 can accommodate each element located in the first binding sub-area B1.
  • the size of the first groove K1 is reduced as much as possible, and in the case where the second groove K2 can accommodate each binding terminal 1 located in the second binding sub-area B2, the second groove K2
  • the size of the groove K2 is reduced as much as possible, so that, as shown in FIG. 6 , when the connection layer is formed and pressure is applied thereto, there is no binding of the marks K1-1 and K1-2 as shown in FIG. 4B in the related art.
  • the area where the terminal 1 is padded is determined, so that there is better adhesion between the connection layer and the binding terminal 1 in the first groove K1 and the second groove K2, and the connection between the connection layer 102 and the binding terminal 1 is improved. Therefore, even if the material of the alignment layer flows into the areas on the left and right sides of the first groove K1, causing the water absorption characteristics of the material of the alignment layer to have a negative impact on the connection layer 102, the connection layer 102 will not be affected. It is separated from the binding terminal 1, thereby improving the reliability and quality of the array substrate.
  • connection layer 102 covers the distance h4 from the part of the bonding terminal 1 away from the surface of the substrate 100 to the substrate 100 in a direction perpendicular to the plane of the substrate 100 . It is less than the distance h5 between the surface of the remaining portion of the connection layer 102 away from the substrate 100 and the substrate 100 in a direction perpendicular to the plane of the substrate 100 .
  • FIG. 6 is a cross-sectional view along the M3M4 direction of FIG. 5 .
  • grooves are provided only in areas where the binding terminals are located (for example, the first binding sub-area B1 and the second binding sub-area B2). ), because the minimum distance between each binding terminal 1 arranged along the side wall of the first groove K1 in the first binding sub-area B1 and the side wall of the first groove K1 is less than or equal to the first preset value , the minimum distance between each binding terminal 1 arranged along the side wall of the second groove K2 in the second binding sub-area B2 and the side wall of the second groove K2 is less than or equal to the first preset value, the first preset value The value is the process deviation value.
  • the distance between the upper surface of the connection layer 102 in the area where the binding terminal 1 is provided and the substrate 100 is smaller than that in other areas where the binding terminal 1 is not provided.
  • the distance between the upper surface of the connection layer 102 and the substrate 100 in the area is smaller than that in other areas where the binding terminal 1 is not provided.
  • connection layer 102 will not be separated from the bonding terminal 1 , thereby improving the reliability and quality of the array substrate.
  • At least one fourth groove K4 is also provided on the flat layer 101 , and the fourth groove K4 is disconnected from the first groove K1 , the array substrate also includes at least one conductive pattern located in the binding area BB, a conductive pattern is provided in a fourth groove K4, and the distance between the conductive pattern and the sidewall of the fourth groove K4 is less than or equal to the first default value.
  • FIG. 8 is a cross-sectional view along the M5M6 direction of FIG. 7 .
  • the conductive pattern may include an alignment mark pattern, such as a first alignment mark pattern 2 and a second alignment mark pattern 3 .
  • the conductive patterns may also include dummy patterns or other conductive islands.
  • the conductive pattern may be located on the source and drain metal layers, for example, the alignment mark pattern may be located on the source and drain metal layers.
  • the conductive pattern may be located on the gate layer.
  • the flat layer 101 is provided with two fourth grooves K4 located on the same side of the first groove K1 , and the first groove K1 points to The direction of the fourth groove K4 is perpendicular to the direction in which the display area AA points to the binding area BB; the orthographic projection of the portion of the flat layer 101 between the two adjacent fourth grooves K4 on the substrate 100 is consistent with the alignment layer PI. There is overlap in the orthographic projections on substrate 100.
  • the binding area when the binding area is provided with a fourth groove K1, the material of the alignment layer flows along the edge profile of the groove, so that the space between two adjacent grooves
  • An alignment layer is provided in an area, for example, between two adjacent fourth grooves K4, between the adjacent first groove K1 and the fourth groove K4. In this way, the binding area of the array substrate can be located
  • the size of the side bezel has been reduced to a great extent, which is conducive to the preparation of extremely narrow-bezel products.
  • An embodiment of the present application provides a display device, including the array substrate as described above.
  • the display device provided in the embodiment of the present application is a liquid crystal display device (LCD, Liquid Crystal Display), in addition, the display device can be a display device such as an LCD display, as well as any product or component with a display function such as a television, a digital camera, a mobile phone, a tablet computer, etc. including these display devices.
  • LCD liquid crystal display
  • the display device can be a display device such as an LCD display, as well as any product or component with a display function such as a television, a digital camera, a mobile phone, a tablet computer, etc. including these display devices.
  • the above-mentioned display device is a liquid crystal display device in the ADS (Advanced Super Dimension Switch) display mode, where ADS is a collective name for core technologies represented by wide viewing angle technology.
  • ADS Advanced Super Dimension Switch
  • the orthographic projection of the connection layer on the substrate is aligned with the alignment layer located in the binding area.
  • the overlap of the orthographic projections on the substrate greatly reduces the distance between the connection layer and the edge of the display area in a direction parallel to the plane of the substrate and with the display area pointing towards the binding area, thereby reducing The size of the binding area of the display device is reduced, thereby facilitating the preparation of narrow-frame display products.
  • connection layer covers the alignment layer, and the water-absorbing properties of the alignment layer material further weaken the adhesion of the connection layer at the edge of the first groove K1, thereby allowing the display device prepared on the array substrate to undergo a reliability test (high temperature and high humidity conditions)
  • a reliability test high temperature and high humidity conditions
  • the display device provided by the embodiments of the present application can be improved by improving the adhesion between the connection layer and the underlying film layer or by preventing the material of the alignment layer from flowing into the area shown by the dotted oval circle as shown in Figure 4A. Improve the display abnormality caused by poor conduction.
  • the array substrate also includes a driver chip IC.
  • the driver chip IC is electrically connected to the binding terminal 1 through the connection layer 102.
  • the connection layer 102 includes an anisotropic conductive adhesive film.
  • the driver chip IC is on the substrate 100.
  • the orthographic projection on is located within the orthographic projection of the connecting layer 102 on the substrate 100 .
  • the driver chip IC may be a Touch and Display Driver Integration (TDDI) chip, or it may be a non-TDDI chip.
  • TDDI Touch and Display Driver Integration
  • the orthographic projection of the driver chip IC on the substrate 100 is located within the orthographic projection of the connection layer 102 on the substrate 100, including the following situations:
  • the orthographic projection outer contour of the driver chip IC on the substrate 100 is located within the orthographic projection outer contour of the connection layer 102 on the substrate 100;
  • the orthographic projection outline of the driver chip IC on the substrate 100 overlaps with the orthographic projection outline of the connection layer 102 on the substrate 100 .
  • the display device further includes a flexible circuit board FPC.
  • the flexible circuit board is electrically connected to the binding electrodes on the array substrate through a conductive layer, and the conductive layer includes an anisotropic conductive adhesive film.
  • the binding electrodes are used to electrically connect the array substrate and the flexible circuit board, and the binding terminals described above are used to electrically connect the array substrate and the driving chip.
  • the structure of the binding electrode is not shown.
  • the film layer structure of the binding electrode may be similar to that of the binding terminal.
  • the relevant description of the binding terminal in the previous article please refer to the relevant description of the binding terminal in the previous article.
  • the conductive layer has a similar function to the connection layer mentioned above, and both can be anisotropic conductive adhesive films.
  • the display device further includes a counter substrate, the counter substrate and the array substrate are arranged oppositely, and the orthographic projection of the counter substrate on the substrate does not overlap with the binding area.
  • the orthographic projection of the opposing substrate on the substrate partially overlaps with the orthographic projection of the array substrate on the substrate, and the opposing substrate exposes part of the structure of the array substrate located in the binding area, so that The driving chip and the flexible circuit board are arranged in the binding area, so that the driving chip and the flexible circuit board transmit driving signals to the array substrate in the display device.

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Abstract

本申请提供了阵列基板、显示装置，涉及显示技术领域，该阵列基板包括衬底，位于衬底上的显示区和绑定区，绑定区位于显示区的一侧；阵列基板还包括：配向层，从显示区延伸至绑定区；绑定端子，位于绑定区，且配向层在衬底上的正投影与绑定端子在衬底上的正投影互不交叠；其中，在平行于衬底所在的平面、且沿显示区指向绑定区的方向上，绑定端子到显示区的边缘之间的最小距离小于或等于配向层位于绑定区的部分的边缘到显示区的边缘之间的最大距离。该阵列基板制备的显示装置的边框窄、且可靠性和品质高。

Description

阵列基板、显示装置
相关申请的交叉引用
本申请要求在2022年5月30日提交中国专利局、申请号为202210612206.4、名称为“阵列基板、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及阵列基板、阵列基板及编码图案的制备方法。
背景技术
随着显示技术的快速发展，窄边框显示逐渐成为市场追捧的焦点。然而，相关技术中的显示产品，由于显示产品的绑定区的走线排布密集，其尺寸难以缩减，从而使得显示产品中设置有绑定区的一侧的边框尺寸无法进一步减小。
发明内容
本申请的实施例采用如下技术方案：
第一方面，本申请的实施例提供了一种阵列基板，包括：衬底，位于所述衬底上的显示区和绑定区，所述绑定区位于所述显示区的一侧；
所述阵列基板还包括：
配向层，从所述显示区延伸至所述绑定区；
绑定端子，位于所述绑定区，且所述配向层在所述衬底上的正投影与所述绑定端子在所述衬底上的正投影互不交叠；
其中，在平行于所述衬底所在的平面、且沿所述显示区指向所述绑定区的方向上，所述绑定端子到所述显示区的边缘之间的最小距离小于或等于所述配向层位于所述绑定区的部分的边缘到所述显示区的边缘之间的最大距离。
在本申请的一些实施例中，所述阵列基板包括位于所述绑定区的连接层，所述连接层覆盖所述绑定端子远离所述衬底的一侧的表面，且延 伸至所述绑定端子以外的区域，所述连接层在所述衬底上的正投影与所述配向层位于所述绑定区的部分在所述衬底上的正投影部分交叠。
在本申请的一些实施例中，所述绑定区包括第一绑定子区和第二绑定子区，所述第一绑定子区位于所述第二绑定子区和所述显示区之间，部分所述绑定端子位于所述第一绑定子区，部分所述绑定端子位于所述第二绑定子区；
其中，所述连接层在所述衬底上的正投影与所述配向层位于所述第一绑定子区远离所述第二绑定子区的一侧的部分在所述衬底上的正投影存在交叠。
在本申请的一些实施例中，所述阵列基板还包括平坦层，所述平坦层从所述显示区延伸至所述绑定区，所述平坦层设置在所述绑定区的部分位于所述连接层与所述衬底之间；所述平坦层位于所述第一绑定子区的部分设置有第一凹槽，所述平坦层位于所述第二绑定子区的部分设置有第二凹槽；
所述第一凹槽和所述第二凹槽断开设置，所述第一绑定子区的各所述绑定端子均位于所述第一凹槽内，所述第二绑定子区的各所述绑定端子均位于所述第二凹槽内，且所述第一凹槽的外轮廓在所述衬底上的正投影和所述第二凹槽的外轮廓在所述衬底上的正投影之间的区域与所述配向层在所述衬底上的正投影互不交叠。
在本申请的一些实施例中，各凹槽的外轮廓在所述衬底上的正投影圈定的区域与所述连接层在所述衬底上的正投影至少部分交叠，各所述凹槽的外轮廓在所述衬底上的正投影圈定的区域与所述配向层在所述衬底上的正投影互不交叠。
在本申请的一些实施例中，所述平坦层上还设置有第三凹槽，所述第三凹槽与所述第一凹槽连通设置，所述第三凹槽沿第一方向朝远离所述第一绑定子区的方向延伸，所述第一方向垂直于所述显示区指向所述绑定区的方向；在沿所述显示区指向所述绑定区的方向上，所述第三凹槽在所述衬底上的正投影的尺寸小于所述第一凹槽在所述衬底上的正投影的尺寸。
在本申请的一些实施例中，所述第一凹槽的外轮廓在所述衬底上的正投影圈定的区域、所述第二凹槽的外轮廓在所述衬底上的正投影圈定的区域均位于所述连接层在所述衬底上的正投影以内；
所述第三凹槽的外轮廓在所述衬底上的正投影圈定的区域与所述连接层在所述衬底上的正投影部分交叠。
在本申请的一些实施例中，在平行于所述衬底所在的平面且沿所述第一方向上，所述第三凹槽远离所述第一凹槽的一端到所述连接层的边缘之间的最小距离大于或等于300μm，且小于或等于800μm。
在本申请的一些实施例中，所述阵列基板包括位于所述显示区和所述绑定区之间的扇出区；所述阵列基板还包括连接走线，所述连接走线从所述扇出区延伸至所述绑定区，所述连接走线位于所述绑定区的部分设置在所述绑定区中除所述第一绑定子区和所述第二绑定子区之外的区域，所述连接走线与所述绑定端子电连接；所述第三凹槽的外轮廓在所述衬底上的正投影圈定的区域与部分所述连接走线在所述衬底上的正投影交叠。
在本申请的一些实施例中，所述阵列基板还包括栅极层和源漏金属层，所述栅极层和所述源漏金属层之间绝缘设置；所述源漏金属层位于所述平坦层与所述衬底之间，所述栅极层位于所述源漏金属层与所述衬底之间；
部分所述连接走线包括第一线段和第二线段，所述第一线段位于所述栅极层，所述第二线段位于所述源漏金属层；
其中，所述第一线段在所述衬底上的正投影位于所述第三凹槽的外轮廓在所述衬底上的正投影圈定的区域以内，所述第二线段在所述衬底上的正投影位于所述第三凹槽的外轮廓在所述衬底上的正投影圈定的区域以外，所述第一线段和所述第二线段电连接。
在本申请的一些实施例中，所述第二线段包括第一子线段和第二子线段，所述第一线段在所述衬底上的正投影位于所述第一子线段在所述衬底上的正投影与所述第二子线段在所述衬底上的正投影之间；所述第一子线段通过所述第一线段与所述第二子线段电连接；
其中，所述第二子线段位于所述第一子线段远离所述显示区的一侧，所述配向层在所述衬底上的正投影与所述第一子线段在所述衬底上的正投影交叠，且所述配向层在所述衬底上的正投影与至少部分所述第二子线段在所述衬底上的正投影不交叠。
在本申请的一些实施例中，所述阵列基板还包括至少一个导电图案，所述导电图案位于所述绑定端子与所述连接走线之间，所述导电图案在所述衬底上的正投影位于所述第一凹槽的外轮廓在所述衬底上的正投影圈定的区域以内。
在本申请的一些实施例中，各凹槽的外轮廓在所述衬底上的正投影圈定的区域位于所述连接层在所述衬底上的正投影以内。
在本申请的一些实施例中，所述第一绑定子区中沿所述第一凹槽侧壁排列的各所述绑定端子到所述第一凹槽侧壁之间的最小距离小于或等于第一预设值，所述第二绑定子区中沿所述第二凹槽侧壁排列的各所述绑定端子到所述第二凹槽侧壁之间的最小距离小于或等于所述第一预设值，所述第一预设值为工艺偏差值。
在本申请的一些实施例中，所述连接层覆盖所述绑定端子的部分远离所述衬底的表面沿垂直于所述衬底所在平面的方向到所述衬底之间的距离小于所述连接层的其余部分远离所述衬底的表面沿垂直于所述衬底所在平面的方向到所述衬底之间的距离。
在本申请的一些实施例中，所述平坦层上还设置有至少一个第四凹槽，所述第四凹槽与所述第一凹槽断开设置，所述阵列基板还包括位于所述绑定区的至少一个导电图案，一个所述第四凹槽内设置有一个所述导电图案，且所述导电图案到所述第四凹槽的侧壁之间的距离小于或等于所述第一预设值。
在本申请的一些实施例中，所述平坦层上设置有位于所述第一凹槽同一侧的两个所述第四凹槽，所述第一凹槽指向所述第四凹槽的方向与所述显示区指向所述绑定区的方向垂直；
所述平坦层位于相邻两个所述第四凹槽之间的部分在所述衬底上的正投影与所述配向层在所述衬底上的正投影存在交叠。
第二方面，本申请的实施例提供了一种显示装置，包括如前文所述的阵列基板。
在本申请的一些实施例中，所述显示装置还包括驱动芯片，所述驱动芯片通过所述连接层与所述绑定端子电连接，所述连接层包括异方性导电胶膜，所述驱动芯片在所述衬底上的正投影位于所述连接层在所述衬底上的正投影以内。
在本申请的一些实施例中，所述显示装置还包括柔性电路板，所述柔性电路板通过导电层与所述阵列基板上的绑定电极电连接，所述导电层包括异方性导电胶膜。
在本申请的一些实施例中，所述显示装置还包括对置基板，所述对置基板和所述阵列基板相对设置，所述对置基板在所述衬底上的正投影不与所述绑定区重叠。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1、图4A和图4B为本申请实施例提供的三种相关技术中的阵列基板的结构示意图；其中，图4B为图4A沿M1M12方向的截面图；
图2和图3为本申请的实施例提供的两种窄边框的阵列基板的绑定区的结构示意图；
图5-图14为本申请的实施例提供的十种阵列基板的绑定区的凹槽结构设计示意图。
具体实施例
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在图中，为了清晰，可能夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本申请的示意性图解，并非一定是按比例绘制。
在本申请的实施例中，除非另有说明，“多个”的含义是两个或两个以上；术语“上”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的结构或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”、“特定示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本申请的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
随着显示技术的快速发展，极致窄边框的显示产品成为客户关注的热点。相关技术中，参考图1所示，显示面板中的配向层的边缘PI Edge位于的显示区的边缘AA Edge与绑定区BB中的驱动芯片IC的上边缘之间，且配向层的边缘PI Edge沿显示区AA指向绑定区BB的方向上到驱动芯片IC的上边缘之间的距离D3通常在1.57mm左右，配向层的边缘PI Edge到显示区的边缘AA Edge之间的距离D4通常在0.6mm～1.2mm左右，驱动芯片IC的上边缘到显示面板的边缘Panel Edge之间的距离D2通常在1.57mm左右，这样，显示区的边缘AA Edge到显示面板的边缘Panel Edge之间的距离D1(下边框尺寸)的范围为 2.8mm～3.2mm。
另外，在相关技术中，结合图1和图4A所示，在绑定区BB中的平坦层PLN中设置凹槽K1，使得输出端的绑定端子均设置在凹槽K1中，驱动芯片IC设置在各绑定端子上并与各绑定端子电连接，在制备配向层的过程中，当工艺不稳定或出现异常时，流向绑定区BB的配向材料PI围绕凹槽K1的边缘流动，使得配向材料PI不覆盖输出端的绑定端子。相关技术中，为了改善配向材料PI流向异常，设置配向层的边缘PI Edge与驱动芯片IC的上边缘具有一定的距离。这样，不利于窄边框显示产品的设计和制备。
基于此，本申请的实施例提供了一种阵列基板，参考图2所示，包括：衬底，位于衬底上的显示区AA和绑定区BB，绑定区BB位于显示区AA的一侧；阵列基板还包括：
配向层PI，从显示区AA延伸至绑定区BB；
绑定端子1，位于绑定区BB，且配向层PI在衬底上的正投影与绑定端子1在衬底上的正投影互不交叠；
其中，在平行于衬底所在的平面、且沿显示区AA指向绑定区BB的方向上，绑定端子1到显示区AA的边缘之间的最小距离D5小于或等于配向层PI位于绑定区BB的部分的边缘PI Edge到显示区的边缘AA Edge之间的最大距离D6。
其中，图1和图2中标记IC的虚线框指的是在焊接驱动芯片之后，驱动芯片的外轮廓所圈定的区域，仅以说明。
需要说明的是，在实际应用中，阵列基板包括显示区AA和围绕显示区的周边区域，周边区域包括至少一个绑定区BB，其中，在显示区AA与绑定区BB之间，还可以设置有扇出区CC。
上述从显示区AA延伸至绑定区BB可以理解为：从显示区AA先延伸至扇出区CC，再延伸到绑定区BB。后文中的相关描述的含义与此处类似，不再赘述。
另外，在本申请的实施例提供的阵列基板的相关附图中，标记FPC的区域指的是在绑定柔性电路板之后，绑定柔性电路板的外轮廓所圈定 的区域。
这里对于阵列基板的显示区AA中的具体结构不进行限定，具体可以根据实际情况确定。
这里对于绑定区BB中绑定端子1的具体结构和数量不进行限定，具体可以根据实际设计确定。
在示例性的实施例中，绑定端子1到显示区AA的边缘之间的最小距离D5指的是：各绑定端子1中，最靠近显示区AA的绑定端子1沿显示区AA指向绑定区BB的方向上到显示区AA的边缘之间的距离。
示例性的，D5的范围为0.5mm～1.1mm，例如，1.05mm或1.06mm。
在示例性的实施例中，配向层PI位于绑定区BB的部分的边缘PI Edge到显示区的边缘AA Edge之间的最大距离D6指的是：配向层的边缘PI Edge距离显示区边缘AA Edge最远的部分沿显示区AA指向绑定区BB的方向上到显示区AA的边缘之间的距离。
示例性的，D6的范围为0.6mm～1.2mm，例如，1.1mm或1.06mm。
在实际应用中，参考图2所示，由于设置配向层PI绕过绑定端子1所在的区域，配向层的边缘PI Edge距离显示区边缘AA Edge最远的部分通常位于绑定端子1所在的区域两侧。
参考图2和图3所示，本申请的实施例设置配向层PI向绑定区BB延伸，且设置配向层PI绕过绑定端子1所在的区域，使得在平行于衬底所在的平面、且沿显示区AA指向绑定区BB的方向上，绑定端子1到显示区AA的边缘之间的最小距离D5小于或等于配向层PI位于绑定区BB的部分的边缘PI Edge到显示区的边缘AA Edge之间的最大距离D6，这样，一方面，避免配向层PI覆盖在绑定端子1影响绑定端子1与驱动芯片的正常导通，另一方面，能够很大程度上减小绑定端子1所在的区域沿显示区AA指向绑定区BB的方向到显示区AA之间的距离，从而有利于缩小显示装置的绑定区BB所在侧的边框的尺寸。
需要说明的是，在实际应用中，配向层的边缘PI Edge不完全是直线线段，由于配向层PI材料的流动性，其边缘会出现弧形，本申请的实施例提供的附图中的配向层的边缘PI Edge仅为示意配向层的轮廓位 置。
另外，参考图2所示，本申请的实施例提供的阵列基板的驱动芯片IC的上边缘到阵列基板的边缘Panel Edge之间的距离D2可以在1.4mm～1.6mm范围内，例如1.57mm左右，结合绑定端子1到显示区AA的边缘之间的最小距离D5的尺寸，通过实际试验以及测量可知，本申请的实施例提供的阵列基板的显示区的边缘AA Edge到阵列基板的边缘Panel Edge之间的距离D7(下边框尺寸)的范围为2.4mm～2.8mm，例如，2.5mm左右。显然，相较于相关技术中阵列基板的下边框的尺寸，本申请的实施例提供的阵列基板的绑定区所在侧的边框的尺寸得到很大程度上的缩减，可以实现极致窄边框产品的制备。
需要说明的是，在本申请的实施例中，涉及“左右”相关的描述指的是在工艺允许范围内，相关尺寸的波动值，其波动范围可根据实际工艺的差异确定，这里不进行限定。
在本申请的一些实施例中，结合图3、图5、图6、图10和图11所示，阵列基板包括位于绑定区BB的连接层102，连接层102覆盖绑定端子1远离衬底100的一侧的表面，且延伸至绑定端子以外的区域，连接层102在衬底100上的正投影与配向层PI位于绑定区BB的部分在衬底100上的正投影部分交叠。
参考图3所示，标记ACF的虚线框指的是在形成连接层之后，连接层的外轮廓所圈定的区域，另外，在图3中，将连接层的正投影与配向层的正投影存在交叠的区域用斜线填充，仅以示例说明。
示例性的，连接层可以为异方性导电胶膜(Anisotropic Conductive Film，ACF)，连接层用于将驱动芯片和绑定端子电连接在一起。
这里对于配向层的材料不进行限定，示例性的，配向层的材料可以为聚酰亚胺(PI)，需要说明的是，本申请的实施例提供的附图中标记PI的结构代表配向层，但并不说明配向层的材料只能为聚酰亚胺(PI)。
在本申请的一些实施例中，参考图3所示，绑定区BB包括第一绑定子区B1和第二绑定子区B2，第一绑定子区B1位于第二绑定子区B2和显示区AA之间，部分绑定端子位于第一绑定子区B1，部分绑定 端子位于第二绑定子区B2；其中，连接层102，例如ACF，在衬底100上的正投影与配向层PI位于第一绑定子区B1远离第二绑定子区B2的一侧的部分在衬底100上的正投影存在交叠。
在示例性的实施例中，第一绑定子区B1中的绑定端子1为输出端子，第二绑定子区B2中的绑定端子1为输入端子。
相较于相关技术中的阵列基板，在本申请的实施例中，通过将连接层向靠近显示区AA的方向移动，使得连接层在衬底上的正投影与配向层位于绑定区的部分在衬底上的正投影部分交叠，很大程度上减小了沿平行于衬底所在平面且显示区指向绑定区的方向上，连接层到显示区的边缘之间的距离，从而减小了阵列基板的绑定区的尺寸，从而有利于窄边框显示产品的制备。
在本申请的一些实施例中，结合图5、图6、图10和图14所示，阵列基板还包括平坦层101，平坦层101从显示区AA延伸至绑定区BB，平坦层101设置在绑定区BB的部分位于连接层102与衬底100之间；平坦层101位于第一绑定子区B1的部分设置有第一凹槽K1，平坦层101位于第二绑定子区B2的部分设置有第二凹槽K2；第一凹槽K1和第二凹槽K2断开设置，第一绑定子区B1的各绑定端子1均位于第一凹槽K1内，第二绑定子区B2的各绑定端子1均位于第二凹槽K2内，
其中，参考图10和图14所示，第一凹槽K1的外轮廓在衬底100上的正投影和第二凹槽K2的外轮廓在衬底100上的正投影之间的区域与配向层PI在衬底100上的正投影互不交叠。
在示例性的实施例中，平坦层起到绝缘和平坦化的作用，平坦层的材料为有机绝缘材料，例如树脂。
在本申请的一些实施例中，各凹槽的外轮廓在衬底100上的正投影圈定的区域与连接层102在衬底100上的正投影至少部分交叠，各凹槽的外轮廓在衬底100上的正投影圈定的区域与配向层PI在衬底100上的正投影互不交叠。
在示例性的实施例中，为了减小阵列基板的边缘到显示区的边缘之间的尺寸，可以设置配向层延伸至绑定区中，然而，在形成配向层之后 的后续工艺中，所有绑定端子需要通过连接层与驱动芯片绑定在一起，考虑到配向层可能会影响绑定连接层与绑定端子之间的电连接稳定性，参考图10和图14所示，设置配向层PI延伸到第一凹槽K1左右两侧的位置附近，但配向层PI不能延伸到第一凹槽K1和第二凹槽K2之间的区域，这样，在减小了阵列基板的边框尺寸、利于制备窄边框的显示产品的同时，确保了阵列基板中绑定端子、连接层以及驱动芯片之间的导通稳定性，提高了显示产品的可靠性和品质。
在相关技术中，一方面，为了实现窄边框，配向层延伸至绑定区中，由于当前工艺中配向层的涂覆能力为900μm±300μm，配向层的材料可能沿着第一凹槽K1的边缘流到如图4A中虚线椭圆圈所标记的区域中，使得第一凹槽K1两侧的连接层覆盖在配向层上；另一方面，在形成连接层并将连接层压合在绑定端子的上表面上时，由于相关技术中的第一凹槽K1的外轮廓所圈定的区域远远大于第一凹槽K1中的绑定端子所在的区域，位于第一凹槽K1中的绑定端子1的高度较高，位于第一凹槽K1中的导电图案(例如第一对位标记图案2和第二对位标记图案3)的高度较低，两者之间存在高度差，使得压头在向连接层施加压力时，如图4B所示的K1-3区域中的连接层容易受力，且这部分连接层与绑定端子之间紧密接触，如图4B所示的K1-1区域和K1-2区域中的连接层不容易受力，这部分的连接层与导电图案或衬底的之间的接触粘附力不足。其中，图4B为图4A中沿M1M2方向的截面图。
在显示产品后期的使用和测试过程中，一方面，由于第一凹槽K1靠近侧壁位置处的连接层本身粘附力较弱，另一方面，由于第一凹槽K1两侧的连接层覆盖在配向层上，配向层材料的吸水特性使得第一凹槽K1边缘的连接层的粘附力进一步减弱，从而使得在阵列基板制备的显示装置在进行信赖性测试(高温高湿条件)时，局部区域的连接层剥离，最终导致绑定端子与驱动芯片之间导通不良，显示装置显示异常。
基于此，可以通过提高连接层与底层膜层的粘附力或者避免配向层的材料流到如图4A中所示的虚线椭圆圈所示的区域中这两种方式来改善该导通不良造成的显示异常的问题。
本申请的实施例提供了如图5所示的第一凹槽K1内缩的方案或如图11中所示的第一凹槽K1两侧设置向外延伸的第三凹槽K3的方案以进行改进。
在本申请的一些实施例中，参考图11所示，平坦层101上还设置有第三凹槽K3，第三凹槽K3与第一凹槽K1连通设置，第三凹槽K3沿第一方向OA朝远离第一绑定子区B1的方向延伸，第一方向OA垂直于显示区AA指向绑定区BB的方向；在沿显示区AA指向绑定区BB的方向上，第三凹槽K3在衬底100上的正投影的尺寸h2小于第一凹槽K1在衬底100上的正投影的尺寸h1。
在示例性的实施例中，第一凹槽K1在衬底100上的正投影的尺寸h1可以根据第一绑定子区B1中各绑定端子1的尺寸、各绑定端子1的排布方式和各绑定端子1之间的间距尺寸共同决定，以确保第一绑定子区B1中各绑定端子1均位于第一凹槽K1内，这里不进行限定。
在示例性的实施例中，在设置第三凹槽K3时，这里对于第三凹槽K3在衬底100上的正投影的尺寸h2的具体数据不进行限定，具体可以根据实际设计空间的大小进行确定。
示例性的，为了节约设计空间，可以设置第三凹槽K3在衬底100上的正投影的尺寸h2的范围为20μm±5μm。
需要说明的是，本申请的实施例提供的各凹槽均设置在平坦层PLN上，且平坦层在部分区域起到平坦化和绝缘的作用，由于平坦层的部分区域需要设置开口以暴露出底层的膜层结构，用以进行电连接，故而，本申请的发明点涉及的设置在平坦层上的这几种凹槽均为贯穿的凹槽。当然，该阵列基板的平坦层的其它区域还可以设置非贯穿的凹槽，具体可以根据实际情况确定。
在本申请的一些实施例中，参考图11所示，第一凹槽K1的外轮廓在衬底100上的正投影圈定的区域、第二凹槽K2的外轮廓在衬底100上的正投影圈定的区域均位于连接层(例如ACF)在衬底100上的正投影以内；第三凹槽K3的外轮廓在衬底100上的正投影圈定的区域与连接层(例如ACF)在衬底100上的正投影部分交叠。
在本申请的实施例中，通过在第一凹槽K1的两侧设置连通的第三凹槽K3，在实际制备工艺中，该连通的凹槽对配向层的材料起到阻挡作用，使配向层的材料沿大凹槽(第一凹槽K1和第三凹槽K3连通后形成的凹槽)的边缘流动，最终使得配向层位于大凹槽靠近显示区的一侧，即使在第一凹槽K1靠近侧壁位置处的连接层本身粘附力较弱的情况下，由于大凹槽两侧的配向层距离第一凹槽K1中的绑定端子的距离较远，且大凹槽两侧的配向层距离第一凹槽K1的两侧距离较远，从而减弱了配向层材料的吸水特性对绑定端子1附近的连接层的影响，在阵列基板制备的显示装置进行信赖性测试(高温高湿条件)时，连接层的粘附力减弱程度较轻，绑定端子与驱动芯片之间导通正常，显示装置的显示效果提高。
另外，通过设置第三凹槽K3的外轮廓在衬底100上的正投影圈定的区域与连接层(例如ACF)在衬底100上的正投影部分交叠，且第三凹槽K3远离第一凹槽K1的一端在衬底100上的正投影圈定的区域与连接层(例如ACF)在衬底100上的正投影不交叠，这样，即使在配向层的材料绕过第三凹槽K3远离第一凹槽K1的一端向第一凹槽K1方向流动时，由于第三凹槽K3远离第一凹槽K1的一端在衬底100上的正投影圈定的区域与连接层(例如ACF)在衬底100上的正投影不交叠，也很大程度上降低了配向层的材料从如图11中所示的箭头的方向流入连接层(例如ACF)所在区域的概率，从而降低配向层材料吸水特性对连接层的粘附力的影响，降低连接层与绑定端子导通不良的概率，进一步提高了阵列基板的可靠性。
在本申请的一些实施例中，在平行于衬底100所在的平面且沿第一方向OA上，第三凹槽K3远离第一凹槽K1的一端到连接层的边缘之间的最小距离h3大于或等于300μm，且小于或等于800μm。
示例性的，第三凹槽K3沿第一方向OA的尺寸可以为1000μm左右。
在本申请的实施例中，在配向层的材料沿着第三凹槽K3的外轮廓流动时，即使其绕过第三凹槽K3远离第一凹槽K1的一端流朝向位于 第一绑定子区B1和第三绑定子区B2之间的连接层流动时，由于两者之间的最小距离h3大于或等于300μm，配向层的材料很难再流到位于第一绑定子区B1和第三绑定子区B2之间的连接层的边缘处，从而避免了此处配向层材料对连接层的负面影响，提高了阵列基板的绑定端子通过连接层与驱动芯片电连接的稳定性。
另外，为了避免第三凹槽K3对阵列基板的走线排布设计的干扰，设置第三凹槽K3远离第一凹槽K1的一端到连接层的边缘之间的最小距离h3小于或等于800μm，以简化设计，降低制备工艺难度。
在本申请的一些实施例中，参考图12、图13和图14所示，阵列基板还包括连接走线L，阵列基板包括位于显示区AA和绑定区BB之间的扇出区，连接走线L从扇出区延伸至绑定区，且连接走线L位于绑定区BB的部分设置在绑定区BB中除第一绑定子区B1和第二绑定子区B2之外的区域，连接走线L与绑定端子1电连接；第三凹槽K3的外轮廓在衬底100上的正投影圈定的区域与部分连接走线L在衬底100上的正投影交叠。
在示例性的实施例中，这里对于连接走线L的延伸方向、连接走线L与绑定端子1的具体电连接方式不进行限定，具体可以根据实际的线路排布设计确定。
在本申请的一些实施例中，阵列基板还包括栅极层和源漏金属层，栅极层和源漏金属层之间绝缘设置；源漏金属层位于平坦层与衬底之间，栅极层位于源漏金属层与衬底之间；参考图12所示，部分连接走线L包括第一线段L1和第二线段L2，第一线段L1位于栅极层Gate，第二线段L2位于源漏金属层SD；
其中，第一线段L1在衬底100上的正投影位于第三凹槽K3的外轮廓在衬底100上的正投影圈定的区域以内，第二线段L2在衬底100上的正投影位于第三凹槽K3的外轮廓在衬底100上的正投影圈定的区域以外，第一线段L1和第二线段L2电连接。
在本申请的实施例中，阵列基板中的膜层包括依次设置在衬底100上的栅极层、栅绝缘层、源漏金属层、平坦层101、像素电极层和连接 层102，其中，当如图12中的连接走线L位于源漏金属层时，由于第三凹槽K3会暴露出与连接走线L交叠的部分区域，源漏金属层的部分区域会暴露在外造成腐蚀，为此，本申请的实施例提供的阵列基板设置正投影位于第三凹槽K3的外轮廓在衬底100上的正投影圈定的区域以内的第一线段L1位于栅极层，通过跳线设计，使得位于栅极层的第一线段L1通过栅绝缘层中的过孔与位于源漏金属层SD的第二线段L2电连接，从而避免设置第三凹槽K3造成对连接走线L的腐蚀，提高了阵列基板的可靠性和品质。需要说明的是，为了简化设计，第一线段L1与第二线段L2之间的连接过孔均设置在与第二线段L2投影交叠的位置，以避开第三凹槽K3所在的区域，降低设计和制备工艺难度。
另外，还需要说明的是，当如图12中的连接走线L均位于栅极层时，由于栅极层上有栅绝缘层进行保护，在平坦层上设置第三凹槽K3并不会暴露出连接走线，则可以不进行跳线设计。
其中，绑定端子1包括三个子层，具体的，沿远离衬底的方向上，三个子层分别依次位于栅极层、源漏金属层和像素电极层，具体可以参考相关技术，这里不再赘述。
在本申请的一些实施例中，参考图12所示，第二线段L2包括第一子线段L21和第二子线段L22，第一线段L1在衬底100上的正投影位于第一子线段L21在衬底100上的正投影与第二子线段L22在衬底100上的正投影之间；第一子线段L21通过第一线段L1与第二子线段L22电连接；
其中，参考图14所示，第二子线段L22位于第一子线段L21远离显示区AA的一侧，配向层PI在衬底100上的正投影与第一子线段L21在衬底100上的正投影交叠，且配向层PI在衬底100上的正投影与至少部分第二子线段L22在衬底100上的正投影不交叠。
在示例性的实施例中，配向层PI在衬底100上的正投影与至少部分第二子线段L22在衬底上的正投影不交叠包括以下情况：
配向层PI在衬底100上的正投影与部分第二子线段L22在衬底100上的正投影不交叠；
或者，配向层PI在衬底100上的正投影与各第二子线段L22在衬底100上的正投影均不交叠。
在本申请的一些实施例中，参考图11-图14所示，阵列基板还包括至少一个导电图案(例如第一对位标记图案2和第二对位标记图案3)，导电图案位于绑定端子1与连接走线L之间，导电图案在衬底100上的正投影位于第一凹槽K1的外轮廓在衬底100上的正投影圈定的区域以内。
在本申请的实施例中，参考图11-图14所示，通过在第一凹槽K1的两侧设置连通的第三凹槽K3，在实际制备工艺中，该连通的凹槽对配向层的材料起到阻挡作用，使配向层的材料沿大凹槽(第一凹槽K1和第三凹槽K3连通后形成的凹槽)的边缘流动，最终使得配向层位于大凹槽靠近显示区的一侧，即使在第一凹槽K1靠近侧壁位置处的连接层本身粘附力较弱的情况下，由于大凹槽两侧的配向层距离第一凹槽K1中的绑定端子的距离较远，且大凹槽两侧的配向层距离第一凹槽K1的两侧距离较远，从而减弱了配向层材料的吸水特性对绑定端子1附近的连接层的影响，在阵列基板进行信赖性测试(高温高湿条件)时，连接层的粘附力减弱程度较轻，绑定端子与驱动芯片之间导通正常，阵列基板制备的显示装置的显示效果提高。
在本申请的一些实施例中，参考图5-图10所示，各凹槽(例如K1、K2、K4)的外轮廓在衬底100上的正投影圈定的区域位于连接层(例如ACF)在衬底100上的正投影以内。
在本申请的一些实施例中，参考图5所示，第一绑定子区B1中沿第一凹槽K1侧壁排列的各绑定端子1到第一凹槽K1侧壁之间的最小距离小于或等于第一预设值，第二绑定子区B2中沿第二凹槽K2侧壁排列的各绑定端子1到第二凹槽K2侧壁之间的最小距离小于或等于第一预设值，第一预设值为工艺偏差值。
这里对于工艺偏差值的具体数值不进行限定，根据设备的不同，工艺稳定性的不同，工艺偏差值会有所差异，具体可以根据实际情况确定。
可以理解，在第一凹槽K1能够容纳位于第一绑定子区B1中的各 绑定端子1的情况下，第一凹槽K1的尺寸尽可能减小，在第二凹槽K2能够容纳位于第二绑定子区B2中的各绑定端子1的情况下，第二凹槽K2的尺寸尽可能减小，这样，参考图6所示，在形成连接层并对其施加压力时，不存在相关技术中如图4B所示的标记K1-1和K1-2的被绑定端子1垫空的区域，从而使得连接层与第一凹槽K1和第二凹槽K2中的绑定端子1之间具有更好的粘附力，提高了连接层102与绑定端子1之间的导通稳定性，故而，即使在配向层的材料流入到第一凹槽K1左右两侧的区域导致配向层材料的吸水特性对连接层102存在负面影响，也不会使得连接层102与绑定端子1之间分离，从而提高了阵列基板的可靠性和品质。
在本申请的一些实施例中，参考图6所示，连接层102覆盖绑定端子1的部分远离衬底100的表面沿垂直于衬底100所在平面的方向到衬底100之间的距离h4小于连接层102的其余部分远离衬底100的表面沿垂直于衬底100所在平面的方向到衬底100之间的距离h5。其中，图6是图5沿M3M4方向的截面图。
在示例性的实施例中，在仅在绑定端子所在区域(例如第一绑定子区B1和第二绑定子区B2)设置凹槽(包括第一凹槽K1和第二凹槽K2)的情况下，由于第一绑定子区B1中沿第一凹槽K1侧壁排列的各绑定端子1到第一凹槽K1侧壁之间的最小距离小于或等于第一预设值，第二绑定子区B2中沿第二凹槽K2侧壁排列的各绑定端子1到第二凹槽K2侧壁之间的最小距离小于或等于第一预设值，第一预设值为工艺偏差值，那么，不考虑工艺偏差的情况下，可以理解，设置有绑定端子1的区域的连接层102的上表面到衬底100之间的距离小于其它未设置绑定端子1的区域中的连接层102的上表面到衬底100之间的距离。这样，在绑定工艺过程中，连接层102与位于凹槽内的绑定端子之间具有较强的粘附力，从而提高了连接层102与绑定端子1之间的导通稳定性，故而，即使在配向层的材料流入到第一凹槽K1左右两侧的区域导致配向层材料的吸水特性对连接层102存在负面影响，也不会使得连接层102与绑定端子1之间分离，从而提高了阵列基板的可靠性和品质。
在本申请的一些实施例中，结合图7、图8和图9所示，平坦层101上还设置有至少一个第四凹槽K4，第四凹槽K4与第一凹槽K1断开设置，阵列基板还包括位于绑定区BB的至少一个导电图案，一个第四凹槽K4内设置有一个导电图案，且导电图案到第四凹槽K4的侧壁之间的距离小于或等于第一预设值。其中，图8是图7沿M5M6方向的截面图。
在示例性的实施例中，导电图案可以包括对位标记图案，例如第一对位标记图案2和第二对位标记图案3。
在示例性的实施例中，导电图案还可以包括Dummy图案或其它导电岛。
在示例性的实施例中，导电图案可以位于源漏金属层，例如，对位标记图案位于源漏金属层。
在示例性的实施例中，导电图案可以位于栅极层。
在本申请的一些实施例中，结合图7、图9和图10所示，平坦层101上设置有位于第一凹槽K1同一侧的两个第四凹槽K4，第一凹槽K1指向第四凹槽K4的方向与显示区AA指向绑定区BB的方向垂直；平坦层101位于相邻两个第四凹槽K4之间的部分在衬底100上的正投影与配向层PI在衬底100上的正投影存在交叠。
如图10中所示的配向层的边缘轮廓，在绑定区设置有第四凹槽K1的情况下，配向层的材料沿着凹槽的边缘轮廓流动，使得相邻两个凹槽之间的区域设置有配向层，例如，相邻的两个第四凹槽K4之间，相邻的第一凹槽K1和第四凹槽K4之间，这样，能够使得阵列基板的绑定区所在侧的边框的尺寸得到很大程度上的缩减，有利于实现极致窄边框产品的制备。
本申请的实施例提供了一种显示装置，包括如前文所述的阵列基板。
这里对于显示装置包括的阵列基板的具体结构不做赘述，具体可以参考前文的说明。
本申请的实施例提供的显示装置为液晶显示装置(LCD，Liquid  Crystal Display)，另外，该显示装置可以是LCD显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、平板电脑等任何具有显示功能的产品或者部件。
示例性的，上述显示装置是ADS(Advanced Super Dimension Switch，高级超维场转换技术)显示模式的液晶显示装置，其中，ADS是以宽视角技术为代表的核心技术统称。
相较于相关技术中的显示装置，在本申请的实施例中，通过将连接层向靠近显示区AA的方向移动，使得连接层在衬底上的正投影与配向层位于绑定区的部分在衬底上的正投影部分交叠，很大程度上减小了沿平行于衬底所在平面且显示区指向绑定区的方向上，连接层到显示区的边缘之间的距离，从而减小了显示装置的绑定区的尺寸，从而有利于窄边框显示产品的制备。
另外，在显示产品后期的使用和测试过程中，一方面，由于第一凹槽K1靠近侧壁位置处的连接层本身粘附力较弱，另一方面，由于第一凹槽K1两侧的连接层覆盖在配向层上，配向层材料的吸水特性使得第一凹槽K1边缘的连接层的粘附力进一步减弱，从而使得在阵列基板制备的显示装置进行信赖性测试(高温高湿条件)时，局部区域的连接层剥离，最终导致绑定端子与驱动芯片之间导通不良，阵列基板制备的显示装置显示异常。
本申请的实施例提供的显示装置可以通过提高连接层与底层膜层的粘附力或者避免配向层的材料流到如图4A中所示的虚线椭圆圈所示的区域中这两种方式来改善该导通不良造成的显示异常的问题。
在本申请的一些实施例中，阵列基板还包括驱动芯片IC，驱动芯片IC通过连接层102与绑定端子1电连接，连接层102包括异方性导电胶膜，驱动芯片IC在衬底100上的正投影位于连接层102在衬底100上的正投影以内。
在示例性的实施例中，驱动芯片IC可以为触控与显示驱动器集成(Touch and Display Driver Integration，TDDI)芯片，或者，也可以是非TDDI芯片。
在示例性的实施例中，驱动芯片IC在衬底100上的正投影位于连接层102在衬底100上的正投影以内包括以下情况：
驱动芯片IC在衬底100上的正投影的外轮廓位于连接层102在衬底100上的正投影外轮廓以内；
或者，驱动芯片IC在衬底100上的正投影的外轮廓与连接层102在衬底100上的正投影外轮廓重叠。
在本申请的一些实施例中，显示装置还包括柔性电路板FPC，柔性电路板通过导电层与阵列基板上的绑定电极电连接，导电层包括异方性导电胶膜。
在示例性的实施例中，绑定电极用于将阵列基板与柔性电路板电连接，前文中所述的绑定端子用于将阵列基板与驱动芯片电连接，在本申请的实施例提供的附图中，并未体现绑定电极的结构。
示例性的，绑定电极的膜层结构可以和绑定端子类似，具体可以参考前文中对绑定端子的相关描述。
另外，导电层与前文中提到的连接层的作用类似，且两者可以均为异方性导电胶膜。
在本申请的一些实施例中，显示装置还包括对置基板，对置基板和阵列基板相对设置，对置基板在衬底上的正投影不与绑定区重叠。
在示例性的实施例中，对置基板在衬底上的正投影与阵列基板在衬底上的正投影部分交叠，且对置基板暴露出阵列基板位于绑定区的部分结构，得能够在绑定区中设置驱动芯片和柔性电路板，以使得驱动芯片和柔性电路板向显示装置中的阵列基板传输驱动信号。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种阵列基板，其中，包括：衬底，位于所述衬底上的显示区和绑定区，所述绑定区位于所述显示区的一侧；
    所述阵列基板还包括：
    配向层，从所述显示区延伸至所述绑定区；
    绑定端子，位于所述绑定区，且所述配向层在所述衬底上的正投影与所述绑定端子在所述衬底上的正投影互不交叠；
    其中，在平行于所述衬底所在的平面、且沿所述显示区指向所述绑定区的方向上，所述绑定端子到所述显示区的边缘之间的最小距离小于或等于所述配向层位于所述绑定区的部分的边缘到所述显示区的边缘之间的最大距离。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括位于所述绑定区的连接层，所述连接层覆盖所述绑定端子远离所述衬底的一侧的表面，且延伸至所述绑定端子以外的区域，所述连接层在所述衬底上的正投影与所述配向层位于所述绑定区的部分在所述衬底上的正投影部分交叠。
  3. 根据权利要求2所述的阵列基板，其中，所述绑定区包括第一绑定子区和第二绑定子区，所述第一绑定子区位于所述第二绑定子区和所述显示区之间，部分所述绑定端子位于所述第一绑定子区，部分所述绑定端子位于所述第二绑定子区；
    其中，所述连接层在所述衬底上的正投影与所述配向层位于所述第一绑定子区远离所述第二绑定子区的一侧的部分在所述衬底上的正投影存在交叠。
  4. 根据权利要求3所述的阵列基板，其中，所述阵列基板还包括平坦层，所述平坦层从所述显示区延伸至所述绑定区，所述平坦层设置在所述绑定区的部分位于所述连接层与所述衬底之间；所述平坦层位于所述第一绑定子区的部分设置有第一凹槽，所述平坦层位于所述第二绑定子区的部分设置有第二凹槽；
    所述第一凹槽和所述第二凹槽断开设置，所述第一绑定子区的各所 述绑定端子均位于所述第一凹槽内，所述第二绑定子区的各所述绑定端子均位于所述第二凹槽内，且所述第一凹槽的外轮廓在所述衬底上的正投影和所述第二凹槽的外轮廓在所述衬底上的正投影之间的区域与所述配向层在所述衬底上的正投影互不交叠。
  5. 根据权利要求4所述的阵列基板，其中，各凹槽的外轮廓在所述衬底上的正投影圈定的区域与所述连接层在所述衬底上的正投影至少部分交叠，各所述凹槽的外轮廓在所述衬底上的正投影圈定的区域与所述配向层在所述衬底上的正投影互不交叠。
  6. 根据权利要求5所述的阵列基板，其中，所述平坦层上还设置有第三凹槽，所述第三凹槽与所述第一凹槽连通设置，所述第三凹槽沿第一方向朝远离所述第一绑定子区的方向延伸，所述第一方向垂直于所述显示区指向所述绑定区的方向；在沿所述显示区指向所述绑定区的方向上，所述第三凹槽在所述衬底上的正投影的尺寸小于所述第一凹槽在所述衬底上的正投影的尺寸。
  7. 根据权利要求6所述的阵列基板，其中，所述第一凹槽的外轮廓在所述衬底上的正投影圈定的区域、所述第二凹槽的外轮廓在所述衬底上的正投影圈定的区域均位于所述连接层在所述衬底上的正投影以内；
    所述第三凹槽的外轮廓在所述衬底上的正投影圈定的区域与所述连接层在所述衬底上的正投影部分交叠。
  8. 根据权利要求7所述的阵列基板，其中，在平行于所述衬底所在的平面且沿所述第一方向上，所述第三凹槽远离所述第一凹槽的一端到所述连接层的边缘之间的最小距离大于或等于300μm，且小于或等于800μm。
  9. 根据权利要求7所述的阵列基板，其中，所述阵列基板包括位于所述显示区和所述绑定区之间的扇出区；所述阵列基板还包括连接走线，所述连接走线从所述扇出区延伸至所述绑定区，所述连接走线位于所述绑定区的部分设置在所述绑定区中除所述第一绑定子区和所述第二绑定子区之外的区域，所述连接走线与所述绑定端子电连接；所述第 三凹槽的外轮廓在所述衬底上的正投影圈定的区域与部分所述连接走线在所述衬底上的正投影交叠。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括栅极层和源漏金属层，所述栅极层和所述源漏金属层之间绝缘设置；所述源漏金属层位于所述平坦层与所述衬底之间，所述栅极层位于所述源漏金属层与所述衬底之间；
    部分所述连接走线包括第一线段和第二线段，所述第一线段位于所述栅极层，所述第二线段位于所述源漏金属层；
    其中，所述第一线段在所述衬底上的正投影位于所述第三凹槽的外轮廓在所述衬底上的正投影圈定的区域以内，所述第二线段在所述衬底上的正投影位于所述第三凹槽的外轮廓在所述衬底上的正投影圈定的区域以外，所述第一线段和所述第二线段电连接。
  11. 根据权利要求10所述的阵列基板，其中，所述第二线段包括第一子线段和第二子线段，所述第一线段在所述衬底上的正投影位于所述第一子线段在所述衬底上的正投影与所述第二子线段在所述衬底上的正投影之间；所述第一子线段通过所述第一线段与所述第二子线段电连接；
    其中，所述第二子线段位于所述第一子线段远离所述显示区的一侧，所述配向层在所述衬底上的正投影与所述第一子线段在所述衬底上的正投影交叠，且所述配向层在所述衬底上的正投影与至少部分所述第二子线段在所述衬底上的正投影不交叠。
  12. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括至少一个导电图案，所述导电图案位于所述绑定端子与所述连接走线之间，所述导电图案在所述衬底上的正投影位于所述第一凹槽的外轮廓在所述衬底上的正投影圈定的区域以内。
  13. 根据权利要求5所述的阵列基板，其中，各凹槽的外轮廓在所述衬底上的正投影圈定的区域位于所述连接层在所述衬底上的正投影以内。
  14. 根据权利要求13所述的阵列基板，其中，所述第一绑定子区 中沿所述第一凹槽侧壁排列的各所述绑定端子到所述第一凹槽侧壁之间的最小距离小于或等于第一预设值，所述第二绑定子区中沿所述第二凹槽侧壁排列的各所述绑定端子到所述第二凹槽侧壁之间的最小距离小于或等于所述第一预设值，所述第一预设值为工艺偏差值。
  15. 根据权利要求14所述的阵列基板，其中，所述连接层覆盖所述绑定端子的部分远离所述衬底的表面沿垂直于所述衬底所在平面的方向到所述衬底之间的距离小于所述连接层的其余部分远离所述衬底的表面沿垂直于所述衬底所在平面的方向到所述衬底之间的距离。
  16. 根据权利要求14所述的阵列基板，其中，所述平坦层上还设置有至少一个第四凹槽，所述第四凹槽与所述第一凹槽断开设置，所述阵列基板还包括位于所述绑定区的至少一个导电图案，一个所述第四凹槽内设置有一个所述导电图案，且所述导电图案到所述第四凹槽的侧壁之间的距离小于或等于所述第一预设值。
  17. 根据权利要求16所述的阵列基板，其中，所述平坦层上设置有位于所述第一凹槽同一侧的两个所述第四凹槽，所述第一凹槽指向所述第四凹槽的方向与所述显示区指向所述绑定区的方向垂直；
    所述平坦层位于相邻两个所述第四凹槽之间的部分在所述衬底上的正投影与所述配向层在所述衬底上的正投影存在交叠。
  18. 一种显示装置，其中，包括如权利要求1-17中任一项所述的阵列基板。
  19. 根据权利要求18所述的显示装置，其中，所述显示装置还包括驱动芯片，所述驱动芯片通过所述连接层与所述绑定端子电连接，所述连接层包括异方性导电胶膜，所述驱动芯片在所述衬底上的正投影位于所述连接层在所述衬底上的正投影以内。
  20. 根据权利要求18所述的显示装置，其中，所述显示装置还包括柔性电路板，所述柔性电路板通过导电层与所述阵列基板上的绑定电极电连接，所述导电层包括异方性导电胶膜。
  21. 根据权利要求18所述的显示装置，所述显示装置还包括对置基板，所述对置基板和所述阵列基板相对设置，所述对置基板在所述衬 底上的正投影不与所述绑定区重叠。
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