WO2022226873A1 - 电路板装配件和电子设备 - Google Patents

电路板装配件和电子设备 Download PDF

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Publication number
WO2022226873A1
WO2022226873A1 PCT/CN2021/090896 CN2021090896W WO2022226873A1 WO 2022226873 A1 WO2022226873 A1 WO 2022226873A1 CN 2021090896 W CN2021090896 W CN 2021090896W WO 2022226873 A1 WO2022226873 A1 WO 2022226873A1
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WO
WIPO (PCT)
Prior art keywords
circuit board
chip
connector
board assembly
connection interfaces
Prior art date
Application number
PCT/CN2021/090896
Other languages
English (en)
French (fr)
Inventor
冯雪
王晨
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21938355.1A priority Critical patent/EP4318564A4/en
Priority to PCT/CN2021/090896 priority patent/WO2022226873A1/zh
Priority to CN202180093507.4A priority patent/CN116888728A/zh
Publication of WO2022226873A1 publication Critical patent/WO2022226873A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB

Definitions

  • the present application relates to the field of electronic equipment and chips, and more specifically, to circuit board assemblies and electronic equipment.
  • the electronic device may include a plurality of chip packaging structures, and by driving and controlling these chip packaging structures, the electronic device may have functions corresponding to the plurality of chip packaging structures.
  • the chip package structure can be arranged on a circuit board, for example.
  • the circuit board can transmit electrical signals for the chip package structure.
  • the chip package structure may generate heat, and then the chip package structure may be slightly deformed.
  • the heat generated by the chip package structure can be further transferred to the circuit board. Since the thermal expansion coefficient of the circuit board and the chip package structure may be different, the deformation amount of the circuit board and the chip package structure may not match when heated or cooled, thereby reducing the stability and reliability of the connection between the chip package structure and the circuit board. sex.
  • the present application provides a circuit board assembly and an electronic device, and the circuit board assembly may include a circuit board and a chip packaging structure.
  • the purpose of this application is to improve the mechanical stability and reliability of circuit board assemblies.
  • a circuit board assembly comprising:
  • the first circuit board assembly includes:
  • the first connector is disposed on the first circuit board and is electrically connected to the first circuit board, and the first connector includes a plurality of first connection interfaces;
  • the first chip packaging structure includes:
  • the second connector is disposed on the package substrate, the second connector includes a plurality of second connection interfaces, and the plurality of second connection interfaces are connected to all the first connectors.
  • the plurality of first connection interfaces correspond, and each of the second connection interfaces is connected to the corresponding one or more of the first connection interfaces through the corresponding one or more of the first cables;
  • a chip is provided on the packaging substrate, and the chip and the second connector are electrically connected through the packaging substrate.
  • the cable transmission signal can be, for example, an optical signal or an electrical signal. If the cables transmit electrical signals, the plurality of first cables may be electrically connected between the first circuit board assembly and the first chip package structure. If the cables transmit optical signals, the plurality of first cables may be optically connected between the first circuit board assembly and the first chip package structure.
  • connection traces may be implemented by cables, and the connection traces may not be integrated on the circuit board. This facilitates setting the thermal expansion coefficient of the circuit board provided with the chip to be the same as or close to the thermal expansion coefficient of the chip.
  • the difference between the thermal expansion coefficient of the chip and the thermal expansion coefficient of the package substrate is less than 5 ppm/°C.
  • the thermal expansion coefficient of the circuit board is set to be smaller than the thermal expansion coefficient of the chip, the difference between the size change of the circuit board and the size of the chip can be smaller.
  • the fixed connectors such as solder, glue, etc.
  • fix the chip on the circuit board can be pulled by the smallest possible size, which is beneficial to improve the connection stability between the circuit board and the chip.
  • the thermal expansion coefficient of the chip is 2-7 ppm/°C
  • the thermal expansion coefficient of the package substrate is 2-7 ppm/°C
  • the chip may be a silicon-based chip.
  • the thermal expansion coefficient of the circuit board can be the same or similar to that of the silicon-based chip.
  • the difference between the thermal expansion coefficient of the chip and the thermal expansion coefficient of the first circuit board is greater than 5ppm/°C.
  • the thermal expansion coefficient of the first circuit board and the thermal expansion coefficient of the chip are quite different, which is beneficial to widen the material selection range of the first circuit board, which in turn is beneficial to Improve the comprehensive performance of circuit board assemblies, such as mechanical performance, cost, etc.
  • the chip is a silicon-based chip
  • the packaging substrate includes a plurality of insulating layers and a plurality of conductive layers that are stacked and spaced apart, and two adjacent insulating layers One of the conductive layers is arranged between the layers, and one of the insulating layers is arranged between two adjacent conductive layers, and the materials of the insulating layers include at least one of the following: ceramics, glass, and diamond.
  • the thermal expansion coefficient of silicon-based chips is generally relatively small.
  • the insulating layer in the circuit board is a material with a relatively small thermal expansion coefficient, it is beneficial to make the thermal expansion coefficient of the circuit board the same as or similar to that of the silicon-based chip.
  • the chip includes a plurality of first chip interfaces and a plurality of second chip interfaces, and each of the first chip interfaces is connected to a corresponding one through the packaging substrate. one or more of the second connection interfaces are electrically connected;
  • the first circuit board assembly further includes:
  • the third connector is disposed on the first circuit board and is electrically connected to the first circuit board, and the third connector includes a plurality of third connection interfaces;
  • the first chip packaging structure further includes:
  • the fourth connector is disposed on the packaging substrate, the fourth connector includes a plurality of fourth connection interfaces, each of the fourth connection interfaces is connected to a corresponding one of the fourth connection interfaces through the packaging substrate or a plurality of the second chip interfaces are electrically connected, and the plurality of fourth connection interfaces correspond to the plurality of third connection interfaces;
  • the circuit board assembly also includes:
  • a plurality of second cables correspond to the plurality of third connection interfaces, and each of the third connection interfaces and the corresponding one or more of the fourth connection interfaces pass through a corresponding One or more of the second cables are connected.
  • connection relationship between the first chip packaging structure and the first circuit board assembly can be made more flexible, which is conducive to the realization of relatively complex connection and routing.
  • Wire For example, the number of traces between the first chip package structure and the first circuit board assembly can be increased. For another example, it is convenient to implement a tree-like, mesh-like and other wiring network.
  • the first circuit board assembly further includes a second chip package structure, the second chip package structure is disposed on the first circuit board, and the Signals between the first chip package structure and the second chip package structure are transmitted through the first circuit board, the first connector, and the plurality of first cables.
  • the circuit board assembly further includes a second circuit board assembly, a plurality of third cables, and the plurality of third cables are used to transmit the transmitting signals between the second circuit board assembly and the first chip packaging structure;
  • the second circuit board assembly includes:
  • the fifth connector is disposed on the third circuit board, and the plurality of fifth connection interfaces correspond to the plurality of third cables;
  • the third chip packaging structure is disposed on the third circuit board, and the third chip packaging structure and the fifth connector are electrically connected through the third circuit board;
  • the first chip packaging structure further includes:
  • the sixth connector is disposed on the packaging substrate, the sixth connector is electrically connected to the chip through the packaging substrate, and the sixth connector includes a plurality of sixth connection interfaces , the plurality of sixth connection interfaces correspond to the plurality of fifth connection interfaces of the fifth connector, and each of the sixth connection interfaces corresponds to one or more of the fifth connection interfaces through corresponding one or more of the third cables are connected.
  • the function of the third chip packaging structure is different from the function of the second chip packaging structure.
  • the functions of the multiple chip packaging structures are different, so that the functions of the hardware can be flexibly determined.
  • a chip may process signals from multiple chip packages.
  • Other chip packaging structures may provide different preprocessing functions for the chips, respectively.
  • the second chip package structure is a preprocessing unit of the first chip package structure.
  • the data processing functions of multiple chip package structures can be correspondingly implemented.
  • the first circuit board assembly further includes:
  • the seventh connector is provided on the first circuit board, the seventh connector is electrically connected to the first connector through the first circuit board, and the seventh connector including a plurality of seventh connection interfaces;
  • the circuit board assembly also includes a third circuit board assembly and a plurality of fourth cables for transmission between the third circuit board assembly and the first circuit board assembly signal, the plurality of fourth cables correspond to the plurality of seventh connection interfaces;
  • the third circuit board assembly includes:
  • the eighth connector is provided on the fourth circuit board, the eighth connector includes a plurality of eighth connection interfaces corresponding to the plurality of seventh connection interfaces, each of the The eighth connection interface is connected with the corresponding one or more of the seventh connection interfaces through the corresponding one or more of the fourth cables;
  • a fourth chip packaging structure, the fourth chip packaging structure is disposed on the fourth circuit board, and the fourth chip packaging structure and the eighth connector are electrically connected through the fourth circuit board.
  • a circuit breaker board can be used.
  • a line patch panel can be thought of as a signal patching node.
  • the circuit adapter board can realize a larger number of signal transmission methods, which is convenient to realize the tree-like, mesh-like and other wiring networks in the circuit board assembly.
  • the first circuit board is arranged in parallel with respect to the package substrate
  • the first circuit board and the package substrate are arranged in a direction perpendicular to the first circuit board;
  • the package substrate is arranged on the plane where the first circuit board is located.
  • the first chip package structure and the first circuit board assembly are distributed in parallel, which can help reduce the space occupied by the circuit board assembly in the thickness direction.
  • the stacked arrangement of the first chip package structure and the first circuit board assembly can help reduce the space occupied by the circuit board assembly in the horizontal and vertical directions (both the horizontal and vertical directions are perpendicular to the thickness direction).
  • the connector and/or the connection interface through which the signal sent and received by the chip passes is determined by the signal type of the signal.
  • connection interface identifier by associating the connection interface identifier with the signal type, it may be beneficial to enable the signal to be input to the corresponding connection interface relatively accurately.
  • the signal type includes at least one of the following associated modules, signal content, and signal properties.
  • the associated module may be, for example, a receiving/transmitting module through which the transmission signal passes.
  • the signal content may include, for example, image signals, audio signals, control signals, and the like.
  • Signal properties may include, for example, signals received by the chip, signals sent by the chip, and the like.
  • the first chip packaging structure is any of the following: a central processing unit, an application processor, a modem processor, a graphics processor, an image signal processor, a video codec, a digital signal processor, a baseband processor, Neural network processor, biometric identification module, memory, power management unit, optical chip.
  • the first cable is a flexible cable.
  • the flexible cable facilitates electrical connection between the plurality of electrical connections.
  • an electronic device including a housing, and the circuit board assembly according to any one of the implementation manners of the first aspect above, where the circuit board assembly is accommodated in the housing.
  • FIG. 1 is a schematic structural diagram of an electronic device.
  • FIG. 2 is a schematic structural diagram of a circuit board assembly.
  • FIG. 3 is a schematic structural diagram of another circuit board assembly.
  • FIG. 4 is a schematic structural diagram of a circuit board assembly provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a circuit board assembly provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a connector provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a circuit board assembly provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another circuit board assembly provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another circuit board assembly provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of still another circuit board assembly provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of still another circuit board assembly provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of an electronic device 100 provided by an embodiment of the present application.
  • the electronic device 100 may be a server, a base station, a computer host, or the like.
  • the electronic device 100 may also be a mobile phone, a tablet computer, an electronic reader, a notebook computer, a digital camera, an automobile, a vehicle-mounted device, an aviation instrument, a router, a smart speaker, a drone, a wearable device, and other devices.
  • the embodiment shown in FIG. 1 is described by taking the electronic device 100 as a server as an example.
  • the electronic device 100 includes a housing 10 and a circuit board assembly (not shown in FIG. 1 ).
  • the circuit board assembly can be accommodated in the housing 10 .
  • the housing 10 may also include a plurality of openings. Components on the circuit board assembly can be connected to openings on the housing 10 to connect the circuit board assembly with external components.
  • the circuit board assembly may include a universal serial bus (USB) interface.
  • the housing 10 may include an opening corresponding to the USB interface. The USB cable can be passed through the opening in the housing so that the end of the USB cable can be connected to the USB interface.
  • the interface of the circuit board assembly may also include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, Universal asynchronous receiver/transmitter (UART) interface, mobile industry processor interface (MIPI), general-purpose input/output (GPIO) interface, etc.
  • I2C inter-integrated circuit
  • I2S inter-integrated circuit sound
  • PCM pulse code modulation
  • UART Universal asynchronous receiver/transmitter
  • MIPI mobile industry processor interface
  • GPIO general-purpose input/output
  • the circuit board assembly may include one or more circuit boards and one or more chip package structures in electrical connection with the circuit boards.
  • 2 and 3 show schematic structural diagrams of two circuit board assemblies 20 .
  • one or more circuit boards of the circuit board assembly 20 may include the first circuit board 210 .
  • the one or more chip package structures of circuit board assembly 20 may include chip package structure 220 .
  • the chip package structure 220 may be disposed on the first circuit board 210 .
  • the circuit board may be a printed circuit board (PCB), a substrate, a flexible circuit board, or the like. Depending on the number of chip packaging structures carried on the circuit board, the circuit board may be single-sided or double-sided.
  • a single-sided board may refer to a circuit board that carries a chip package structure on one side.
  • a double-sided board may refer to a circuit board that carries a chip package structure on both sides.
  • the circuit board may, for example, be used to carry the chip package and transmit signals for the chip package.
  • the chip package structure may be, for example, a central processing unit, an application processor (application processor, AP), a modem processor, a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processor) , ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, neural network processor (neural-network processing unit, NPU), biometric identification module, system-on-chip (system on chip, SOC) module, double data rate (double data rate, DDR) memory, main power management unit (power management unit, PMU), auxiliary PMU, high-speed random access memory, non-volatile memory, optical chips, etc.
  • an application processor application processor, AP
  • modem processor graphics processing unit
  • graphics processing unit graphics processing unit
  • image signal processor image signal processor
  • ISP image signal processor
  • controller video codec
  • digital signal processor digital signal processor
  • DSP digital signal processor
  • baseband processor baseband processor
  • neural network processor neural network processor
  • biometric identification module system-on-
  • the chip package structure in addition to a single chip package structure, can also be obtained by stacking a plurality of chip package structures.
  • processors and memories can be stacked to form a package on package (PoP) module.
  • PoP package on package
  • the chip package structure 220 may include a chip 222 .
  • the chip 222 may be, for example, a silicon-based chip, a carbon-based chip, or the like.
  • the chip can be used as a chip package structure alone, for example.
  • the chip package structure may further include other components than the chip.
  • the chip package structure 220 may further include a package substrate 221 .
  • the chip 222 may be disposed on the package substrate 221 .
  • the package substrate 221 may be, for example, a substrate.
  • the package substrate 221 may be located between the first circuit board 210 and the chip 222 .
  • the chip 222 and the first circuit board 210 may be electrically connected through the package substrate 221 . That is, the circuit board may be part of the chip package structure.
  • the circuit board inside the chip package structure can be used for laying part of the circuit of the chip package structure and for carrying the chips of the chip package structure.
  • the chip 222 may include multiple chip interfaces.
  • the package substrate 221 may include a plurality of substrate interfaces corresponding to the plurality of chip interfaces.
  • the chip package structure may include a plurality of electrical connection lines electrically connected between the chip interface and the substrate interface.
  • the electrical connection lines may be, for example, lines provided on the package substrate 221 .
  • the chip 222 may include a chip interface A
  • the package substrate 221 may include a substrate interface A and an electrical connection line A
  • the electrical connection line A may be electrically connected between the chip interface A and the substrate interface A.
  • the substrate interface of the package substrate 221 and the chip interface of the chip 222 may be electrically connected one-to-one.
  • the substrate interface of the package substrate 221 and the chip interface of the chip 222 may be electrically connected in a many-to-one manner.
  • the chip 222 may include a chip interface A
  • the packaging substrate 221 may include a substrate interface A and a substrate interface B
  • the packaging substrate 221 may further include an electrical connection line A and an electrical connection line B
  • the electrical connection line A may be electrically connected to the chip interface A.
  • the electrical connection line B can be electrically connected between the chip interface A and the substrate interface B.
  • the substrate interface of the package substrate 221 and the chip interface of the chip 222 may be electrically connected one-to-many.
  • the chip 222 may include a chip interface A, a chip interface B, and the package substrate 221 may include a substrate interface A.
  • the package substrate 221 may further include an electrical connection line A and an electrical connection line C.
  • the electrical connection line A may be electrically connected between the chip interface A and the substrate interface A
  • the electrical connection line C may be electrically connected between the chip interface B and the substrate interface A. between.
  • the multiple substrate interfaces on the package substrate 221 may serve as multiple interfaces for the chip package structure.
  • the substrate interface may be located on a side of the package substrate 221 away from the chip 222 .
  • the solder 310 on the first circuit board 210 may interface with the substrate.
  • the signal from the first circuit board 210 may be transmitted to the chip 222 through the substrate interface and the chip interface.
  • the signal generated by the chip 222 can be transmitted to the first circuit board 210 through the chip interface and the substrate interface.
  • the components of the circuit board assembly can be held together by solder, for example.
  • solder for example, between the circuit board and the circuit board, between the chip package structure and the circuit board, between the chip of the chip package structure and the circuit board of the chip package structure, between the chip package structure 1 and the chip package structure 2, all can be Fastened by solder.
  • the solder can be used for mechanical connection and/or electrical connection, and the shape of the solder can be spherical, polyhedral, ellipsoidal, truncated, chamfered, bar-shaped, rod-shaped, and the like.
  • the package substrate 221 of the chip package structure 220 and the first circuit board can be fixed by solder 310 ;
  • Embodiments of the present application may not be limited to connecting multiple components of a circuit board assembly through solder.
  • the connection between the multiple components of the circuit board assembly can also be screwed, glued, or the like.
  • the chip package structure 220 may include a package substrate 221 , a chip 222 , and a cover member 223 .
  • the cover member 223 may include a cover body 2231 and a frame body 2232 .
  • the cover body 2231 and the frame body 2232 may be arranged relatively vertically.
  • the cover body 2231 and the package substrate 221 may be arranged in parallel with each other.
  • the frame body 2232 may be connected between the cover body 2231 and the packaging substrate 221 .
  • the cavity formed between the cover member 223 and the package substrate 221 may be used to accommodate the chip 222 .
  • the cover member 223 may be, for example, a heat dissipation cover.
  • the cover body 2231 of the cover member 223 may be in contact with the surface of the chip 222 away from the package substrate 221 .
  • the cover 223 can be used, for example, to conduct heat generated by the chip 222 to reduce the risk of overheating of the chip 222 .
  • the cover member 223 may shield the cover, for example.
  • the cover member 223 may be insulated from the chip 222 .
  • the cover member 223 can be used to shield the chip 222 from external interference signals.
  • the chip package structure 220 may include a package substrate 221 , a chip 222 , and a package material 224 .
  • the chip 222 may be disposed on the package substrate 221 by, for example, adhesive. In other examples, the chip 222 may also be fixed on the package substrate 221 by other means.
  • the chip 222 and the package substrate 221 may be electrically connected through one or more first electrical connection leads 3201 .
  • the first electrical connection lead 3201 may be electrically connected between the chip 222 and the package substrate 221 .
  • the chip package structure 220 and the first circuit board 210 can be electrically connected to each other through the solder 310 , and the chip package structure 220 and the first circuit board 210 can also be electrically connected through the electrical connection member 311 .
  • one end of the electrical connector 311 can be connected to the first circuit board 210
  • the other end of the electrical connector 311 can be connected to the chip 222 of the chip package structure 220 through one or more second connection leads 3202 electrical connection.
  • the electrical connector 311 may serve as an electrical connection trace between the chip package structure 220 and the first circuit board 210 .
  • the packaging material 224 may wrap around the periphery of the chip 222 and be in contact with the surface of the packaging substrate 221 on which the chip 222 is disposed. Electrical connectors 311 may be partially encapsulated within encapsulation material 224 . A portion of the electrical connector 311 may extend beyond the encapsulation material 224 . The encapsulation material 224 may also encapsulate at least part of the sides of the encapsulation substrate 221 . The surface of the package substrate 221 away from the chip 222 may expose the package material 224 . The packaging material 224 may be used to improve the connection stability between the chip 222 and the packaging substrate 221 . When the chip 222 is working, the chip 222 may be heated, and the chip 222 may be slightly deformed.
  • the heat generated by the chip 222 may be further transferred to the package substrate 221 and the first circuit board 210 .
  • the circuit board assembly 20 is heated or cooled, the deformation amounts of the package substrate 221 , the first circuit board 210 , and the chip 222 may not match.
  • the package substrate 221 can withstand the stress from the chip 222 and the first circuit board 210 , thereby reducing the connection stability between the chip 222 and the package substrate 221 and between the package substrate 221 and the first circuit board 210 .
  • the chip 222 may be a silicon-based chip, and the thermal expansion coefficient of the silicon-based chip may be, for example, about 2.6 ppm/°C; the package substrate 221 may be a substrate, and the thermal expansion coefficient of the substrate may be, for example, 10-15 ppm/°C.
  • the first circuit board 210 may be, for example, a printed circuit board, and the thermal expansion coefficient of the printed circuit board may be, for example, 15-20 ppm/°C. Under the same heating conditions, the thermal deformation of the printed circuit board can be relatively large, the thermal deformation of the substrate can be second, and the thermal deformation of the silicon-based chip can be relatively small.
  • the substrate can be subjected to the deformation traction force of the silicon-based chip and the printed circuit board, and thus the connection stability between the substrate and the silicon-based chip and between the substrate and the printed circuit board may be relatively poor.
  • FIG. 4 and FIG. 5 show a circuit board assembly 20 provided by an embodiment of the present application.
  • 4 and 5 are schematic structural diagrams of the circuit board assembly 20 from two viewing angles, respectively.
  • the circuit board assembly 20 may include a first circuit board assembly 21 , a first chip package structure 220 , and a plurality of first cables 331 .
  • a plurality of first cables 331 may be connected between the first circuit board assembly 21 and the first chip package structure 220 to transmit signals between the first circuit board assembly 21 and the first chip package structure 220 .
  • the signal may be, for example, an optical signal, an electrical signal. If the signal is an electrical signal, the plurality of first cables 331 may be electrically connected between the first circuit board assembly 21 and the first chip package structure 220 . If the signal is an optical signal, the plurality of first cables 331 may be optically connected between the first circuit board assembly 21 and the first chip package structure 220 .
  • "connection" may include, for example, one or more of the following: mechanical connection, electrical connection, and optical connection.
  • the first circuit board assembly 21 may include a first circuit board 210 and a first connector 230 .
  • the first connector 230 may be made of, for example, copper, aluminum, stainless steel and other materials.
  • the first connector 230 can transmit multiple signals in parallel, for example.
  • the first connector 230 may be disposed on the first circuit board 210 .
  • the first connector 230 may be fixed on the first circuit board 210 through the solder 310 , and the first connector 230 and the first circuit board 210 may be electrically connected through the solder 310 .
  • the first connector 230 may be fixed on the first circuit board 210 by crimping.
  • the first cable 331 may include an inner core and an outer layer, and the material of the inner core may be, for example, copper, aluminum, glass fiber, or the like.
  • the outer cladding can be, for example, an insulating material.
  • a plurality of first cables 331 may be connected between the first connector 230 and the first chip package structure 220 to realize signal transmission between the first circuit board 210 and the first chip package structure 220 .
  • the first connector 230 may include a plurality of first connection interfaces 2301 .
  • the plurality of first connection interfaces 2301 may correspond to the plurality of first cables 331 .
  • the first ends of the one or more first cables 331 can be plugged into the corresponding first connection interfaces 2301 , for example.
  • the first connectors 230 may be disposed in regions of opposite edges of the first circuit board 210 , so that the plurality of first connection interfaces 2301 can be respectively connected to the plurality of first cables 331 .
  • the first chip package structure 220 may be disposed outside the first circuit board 210 . That is, the first chip package structure 220 may not be disposed on the first circuit board 210 .
  • the first circuit board 210 can represent, for example, a general printed circuit board, wherein the thermal expansion coefficient of the general printed circuit board can be quite different from the thermal expansion coefficient of the chip package structure 220 .
  • the first chip package structure 220 may be fixed on the casing of the electronic device 100 as shown in FIG. 1 , or on a bracket in the electronic device 100 .
  • the first chip package structure 220 may include a package substrate 221 , a second connector 225 and a chip 222 .
  • the chip 222 and the second connector 225 may be disposed on the package substrate 221 and electrically connected to the package substrate 221 through the solder 310 .
  • the chip 222 and the second connector 225 may be electrically connected through the package substrate 221 .
  • the signals transmitted by the plurality of first cables 331 can be input to the first chip package structure 220 through the second connectors 225 , and the signals from the first chip package structure 220 can be output to the plurality of first cables 331 through the second connectors 225 .
  • the second connectors 225 may be disposed in regions of opposite edges of the package substrate 221 to facilitate connection with the plurality of first cables 331 .
  • the first chip package structure 220 may further include a cover member 223 as shown in FIG. 2 .
  • the first chip packaging structure 220 may further include a packaging material 224 as shown in FIG. 3 .
  • the chip 222 may include, for example, an integrated circuit on which, for example, a plurality of transistors (or logic gates) may be integrated.
  • the transistors may belong, for example, to processing units or computing units of the chip 222 .
  • the thermal expansion coefficients of the chip 222 and the packaging substrate 221 may be similar or the same, that is, the difference between the thermal expansion coefficient of the chip 222 and the thermal expansion coefficient of the packaging substrate 221 may be smaller than the first preset threshold.
  • the thermal expansion coefficients of the chip 222 and the package substrate 221 may both be in the range of 2-7 ppm/°C.
  • the thermal expansion coefficients of the chip 222 and the packaging substrate 221 are similar or the same, for example, the difference between the thermal expansion coefficient of the chip 222 and the thermal expansion coefficient of the packaging substrate 221 may be less than 5ppm/°C.
  • the difference between the thermal expansion coefficient of the chip 222 and the thermal expansion coefficient of the package substrate 221 is less than 0.5ppm/°C, or less than 1ppm/°C, or less than 2ppm/°C, or less than 3ppm/°C, or less than 4ppm/°C.
  • the thermal expansion coefficient of the chip 222 or the packaging substrate 221 may be significantly different from the thermal expansion coefficient of the first circuit board 210 , that is, the difference between the thermal expansion coefficient of the chip 222 and the thermal expansion coefficient of the packaging substrate 221 may be greater than the second preset threshold.
  • the second preset threshold may be greater than the first preset threshold.
  • the difference between the thermal expansion coefficient of the chip 222 and the thermal expansion coefficient of the first circuit board 210 may be greater than 1 ppm/° C., for example.
  • the difference between the thermal expansion coefficient of the chip 222 and the thermal expansion coefficient of the first circuit board 210 may be greater than 3 ppm/°C, or greater than 5 ppm/°C, or greater than 7 ppm/°C, or greater than 10 ppm/°C, or greater than 15 ppm/°C.
  • the deformation amount of the package substrate 221 when it is deformed by heat or cold can be relatively small, and the flatness of the package substrate 221 can be reduced. Relatively high.
  • the thermal expansion coefficients of the package substrate 221 and the chip 222 are the same as possible, the deformation amounts of the package substrate 221 and the chip 222 can be similar, and the deformation amounts of the package substrate 221 and the chip 222 caused by temperature changes can be similar or matched, which is beneficial to the improvement of Connection stability between the package substrate 221 and the chip 222 .
  • the influence of the deformation of the first chip package structure 220 on the first circuit board 210 can be relatively small, which is beneficial to reduce the stress on the first circuit board 210 , the mechanical stability of the first circuit board 210 is improved. It is also relatively difficult for the heat from the chip 222 to affect the first circuit board 210 , which is beneficial to reduce the amount of deformation of the first circuit board 210 and improve the flatness of the first circuit board 210 .
  • the package substrate 221 may include a plurality of conductive layers 2211 and a plurality of insulating layers 2212 .
  • the plurality of conductive layers 2211 and the plurality of insulating layers 2212 may be stacked and disposed at intervals.
  • An insulating layer 2212 is disposed between two adjacent conductive layers 2211 .
  • a conductive layer 2211 is disposed between two adjacent insulating layers 2212 .
  • the two conductive layers 2211 may be electrically connected, for example, through via holes 2213 .
  • the plurality of conductive layers 2211 may form electrical connection lines on the package substrate 221 .
  • the insulating layer 2212 can be made of materials such as ceramic materials, for example.
  • the conductive layer 2211 may be, for example, a copper material.
  • a pad 2214 may be provided between the solder 310 and the conductive layer 2211 .
  • the material of the pad 2214 may be different from the material of the conductive layer 2211, and the pad 2214 may be, for example, a tin plating layer, a nickel plating layer, or the like.
  • the pads 2214 are beneficial to improve soldering reliability, so that the chip 222 can be fixed on the package substrate 221 by the solder 310; on the other hand, the pads 2214 can be used to prevent the electrical connection lines on the conductive layer 2211 from being exposed to the air , to reduce air erosion and damage to electrical connection lines.
  • the chip 222 and the second connector 225 can be electrically connected through the solder 310 , the pads 2214 on the package substrate 221 and the at least one conductive layer 2211 .
  • the chip 222 may include a plurality of chip interfaces 2221 .
  • the chip interface 2221 may be formed by, for example, pins, pads 2214 and the like of an integrated circuit.
  • the chip interface 2221 can transmit signals, such as electrical signals, radio frequency signals, digital signals, and the like. Signals can be input to the chip 222 through the chip interface 2221 on the chip 222 .
  • Chip 222 may process the signal. Through the chip interface 2221 on the chip 222, the signal processed by the chip 222 can be output from the chip 222 to other modules.
  • Chip 222 may include a plurality of first chip interfaces.
  • the second connector 225 may include a plurality of second connection interfaces 2251 corresponding to the plurality of first chip interfaces.
  • the chip 222 may include the first chip interface A.
  • the second connector 225 may include a second connection interface 2251A.
  • the first chip package structure 220 may further include electrical connection lines electrically connected between the first chip interface A and the second connection interface 2251A.
  • the electrical connection lines may include, for example, lines provided on the package substrate 221 .
  • the second connection interface 2251 of the second connector 225 and the first chip interface of the chip 222 may be electrically connected one-to-one.
  • the second connection interface 2251 of the second connector 225 and the first chip interface of the chip 222 may be electrically connected in a many-to-one manner.
  • the chip 222 may include a first chip interface A
  • the second connector 225 may include a second connection interface 2251A and a second connection interface 2251B
  • the first chip package structure 220 may further include an electrical connection line A and an electrical connection line B
  • the electrical connection line A may be electrically connected between the first chip interface A and the second connection interface 2251A
  • the electrical connection line B may be electrically connected between the first chip interface A and the second connection interface 2251B.
  • the electrical connection lines A and B may include, for example, lines provided on the package substrate 221 .
  • the second connection interface 2251 of the second connector 225 and the first chip interface of the chip 222 may be electrically connected one-to-many.
  • the chip 222 may include a first chip interface A, a first chip interface B, and the second connector 225 may include a second connection interface 2251A.
  • the second connector 225 may further include an electrical connection line A and an electrical connection line C, the electrical connection line A may be electrically connected between the first chip interface A and the second connection interface 2251A, and the electrical connection line C may be electrically connected to the first chip interface A and the second connection interface 2251A.
  • the electrical connection lines A and C may include, for example, lines provided on the package substrate 221 .
  • the plurality of second connection interfaces 2251 on the second connector 225 may serve as the plurality of first interfaces of the chip package structure. That is to say, the first connector 230 is connected to the first interface of the first chip package structure 220 , which can be realized by connecting the first connector 230 to the second connection interface 2251 .
  • the plurality of first connection interfaces 2301 of the first connector 230 may correspond to the plurality of second connection interfaces 2251 of the second connector 225 .
  • the plurality of first connection interfaces 2301 and the plurality of second connection interfaces 2251 may be connected according to at least one of the following connection modes: one-to-many, many-to-one, and one-to-one.
  • connection modes of one-to-many, many-to-one, and one-to-one reference may be made to the three electrical connection modes of one-to-many, many-to-one, and one-to-one described in detail above, which will not be described in detail here.
  • the plurality of first connection interfaces 2301 of the first connector 230 may correspond to the plurality of second connection interfaces 2251 of the second connector 225 .
  • the plurality of first connection interfaces 2301 and the plurality of second connection interfaces 2251 may be connected, for example, in a one-to-one, one-to-many, and many-to-one manner.
  • Each of the first connection interfaces 2301 and the corresponding one or more second connection interfaces 2251 may be connected through corresponding one or more first cables 331 .
  • the second end of the first cable 331 can be plugged into the second connection interface 2251 of the second connector 225 .
  • the first circuit board assembly 21 may further include, for example, a second chip package structure 240 .
  • the second chip package structure 240 may be disposed on the first circuit board 210 and electrically connected to the first circuit board 210 .
  • signals between the second chip package structure 240 and the first chip package structure 220 may be transmitted through a plurality of first cables 331 , the first connectors 230 , and the first circuit board 210 .
  • the signal may be converted on the transmission path, for example, from an optical signal to an electrical signal, or from an electrical signal to an optical signal.
  • the signal from the second chip package structure 240 may be transmitted to the chip 222 via the first circuit board 210 , the first connector 230 , the first cable 331 , the second connector 225 , and the package substrate 221 .
  • the signal generated by the chip 222 may be transmitted to the chip 222 via the package substrate 221 , the second connector 225 , the first cable 331 , the first connector 230 , and the first circuit board 210 .
  • the thermal expansion coefficient of the second chip package structure 240 may be close to or the same as the thermal expansion coefficient of the first circuit board 210 .
  • FIG. 6 shows a schematic structural diagram of a connector 810 .
  • the connector 810 shown in FIG. 6 may be, for example, any connector provided in the embodiment of the present application.
  • the cable 820 shown in FIG. 6 may be, for example, any cable provided in the embodiment of the present application.
  • the connector 810 may include a plurality of first interfaces 811 and a plurality of second interfaces 812 . Inside the connector 810, the plurality of first interfaces 811 and the plurality of second interfaces 812 can be connected according to at least one of the following connection modes: one-to-many, many-to-one, and one-to-one.
  • the first interface 811 may be connected to the cable 820 . As shown in (a)-(c) of FIG. 6 , the cable 820 and the first interface 811 may be connected, for example, by crimping, plugging, or welding.
  • the second interface 812 may be electrically connected to the package substrate or circuit board, eg, through one or more electrical connections.
  • the second interface 812 may protrude from a side of the connector 810 close to the package substrate or the circuit board, and be electrically connected to the package substrate or the circuit board through the solder 831 .
  • the second interface 812 may protrude from the side of the connector 810 perpendicular to the package substrate or the circuit board, and be electrically connected to the package substrate or the circuit board through the solder 831 .
  • one or more electrical circuits connected between the second interface 812 and the package substrate may include solder 831 .
  • the solder 831 can be replaced with conductive materials such as conductive glue.
  • a socket 832 may be provided on the package substrate or the circuit board.
  • the socket 832 may be electrically connected with the package substrate or the circuit board through the solder 831 .
  • the second interface 812 may be electrically connected to the package substrate or the circuit board through the socket 832 .
  • the second interface 812 may be formed of, for example, a conductive elastic sheet; the conductive elastic sheet may be disposed on the end face of the connector 810 close to the package substrate or the circuit board, and abut on the socket 832 . In the example shown in (c) of FIG.
  • one or more electrical connectors connected between the second interface 812 and the package substrate may include Solder 831, socket 832 connected between socket 832 and package substrate or circuit board.
  • the conductive elastic sheet can be replaced with conductive materials such as solder 831, conductive glue, etc., for example.
  • the first interface 811 can be used to transmit optical signals
  • the second interface 812 can be used to transmit electrical signals.
  • the connector 810 may have a photoelectric conversion function.
  • both the first interface 811 and the second interface 812 can be used to transmit electrical signals.
  • the distance between the second connector 225 of the first chip package structure 220 and the first connector 230 may be smaller than a preset distance spacing. 4 and 7 , various arrangement forms between the first chip package structure 220 and the first circuit board assembly 21 will be described below.
  • the Z-axis direction may be parallel to the thickness direction of the first circuit board 210 .
  • the thickness direction of the first circuit board 210 may be a stacking direction of the plurality of conductive layers 2211 and the plurality of insulating layers 2212 of the first circuit board 210 .
  • the plane perpendicular to the Z-axis direction may be the XY plane.
  • the first circuit board 210 may be disposed in parallel with respect to the XY plane.
  • the faces of the first circuit board 210 that are disposed parallel to the XY plane may be used to place one or more components of the first circuit board assembly 21 .
  • the package substrate 221 of the first chip package structure 220 may be arranged in parallel with respect to the first circuit board 210 .
  • the package substrate 221 may be disposed on the plane where the first circuit board 210 is located.
  • the plane on which the first circuit board 210 is located may be a plane parallel to the first circuit board 210 and passing through the first circuit board 210 .
  • the packaging substrate 221 is disposed on the plane where the first circuit board 210 is located, which may mean that the plane where the packaging substrate 221 is located is the same plane as the plane where the first circuit board 210 is located, and the plane where the packaging substrate 221 is located may be parallel to the packaging substrate 221 . is disposed, and the plane where the package substrate 221 is located may pass through the package substrate 221 .
  • the projection area of the first circuit board 210 on the XY plane may be the first XY projection area
  • the projection area of the first chip package structure 220 on the XY plane may be the second XY projection area.
  • the first XY projection area and the second XY projection area may not be connected, intersected, or overlapped with each other.
  • the projection area of the first cable 331 on the XY plane may be connected between the first XY projection area and the second XY projection area.
  • the package substrate 221 of the first chip package structure 220 may be arranged in parallel with respect to the first circuit board 210 .
  • the package substrate 221 and the first circuit board 210 may be arranged in a direction perpendicular to the first circuit board 210 .
  • the direction perpendicular to the first circuit board 210 may be disposed parallel to the thickness direction of the first connector 230 .
  • the projection range of the first connector 230 on the Z-axis is the first Z-direction projection range
  • the projection range of the first chip package structure 220 on the Z-axis is the second Z-direction projection range
  • the first Z-direction projection range is The range and the second Z-direction projection range may not be connected, intersected, or overlapped with each other.
  • the projection range of the first cable 331 on the Z-axis may be connected between the first Z-direction projection range and the second Z-direction projection range.
  • the first chip package structure 220 and the first circuit board assembly 21 may also have other arrangement forms. Other placement forms may include, for example, ladder-shaped placement, bridge-shaped placement, and the like.
  • the positional relationship between the first chip package structure 220 and the first circuit board assembly 21 is not limited to the examples shown in FIGS. 4 and 7 .
  • FIG. 8 is a schematic structural diagram of another circuit board assembly 20 provided by an embodiment of the present application. Similar to the circuit board assembly 20 shown in FIG. 4 , the thermal expansion coefficient of the package substrate 221 may be the same as or similar to that of the chip 222 . Optionally, the thermal expansion coefficient of the second chip package structure 240 may be close to or the same as the thermal expansion coefficient of the first circuit board 210 .
  • the first circuit board assembly 21 may further include a third connector 250 , and the third connector 250 may be disposed on the first circuit board 210 .
  • the first chip package structure 220 may also include a fourth connector 226 .
  • the third connector 250 and the fourth connector 226 may be connected by a plurality of second cables 332 .
  • Chip 222 may also include a plurality of second chip interfaces.
  • the fourth connector 226 may include a plurality of fourth connection interfaces 2261 corresponding to the plurality of second chip interfaces.
  • the plurality of second chip interfaces and the plurality of fourth connection interfaces 2261 may be electrically connected, for example, in a one-to-one, one-to-many, and many-to-one manner.
  • the fourth connection interface 2261 may serve as at least part of the interface of the first chip package structure 220 .
  • the third connector 250 may include a plurality of third connection interfaces 2501 corresponding to the plurality of fourth connection interfaces 2261 .
  • the plurality of fourth connection interfaces 2261 and the plurality of third connection interfaces 2501 may be connected, for example, in a one-to-one, one-to-many, and many-to-one manner.
  • the third connector 250 may include a plurality of third connection interfaces 2501 corresponding to the plurality of fourth connection interfaces 2261 one-to-one.
  • the plurality of third connection interfaces 2501 may be in one-to-one correspondence with the plurality of second cables 332 .
  • Each third connection interface 2501 may be connected with corresponding one or more fourth connection interfaces 2261 through corresponding one or more second cables 332 .
  • chip 222 may include 300 chip interfaces.
  • the number of interfaces of a single connector provided on the first circuit board 210 and the first chip package structure 220 may be relatively limited, for example, one connector may include 10-50 interfaces.
  • the first chip package structure 220 may be configured with 6 connectors with 50 ports; correspondingly, the first circuit board 210 may also be configured with 6 connectors with 50 ports.
  • Signals between the first chip package structure 220 and the second chip package structure 240 may be transmitted through a certain connector on the first circuit board 210 .
  • the connector identification indicates the connector through which the signal travels. Through the connection interface identification, the connection interface through which the signal passes can be indicated.
  • the signal between the second chip package structure 240 and the first chip package structure 220 may be transmitted through the first circuit board 210, the first connector 230, or may be transmitted through the first circuit board 210, the third connector 250 transfers.
  • the connection interface identifier may, for example, correspond to a first connection interface 2301 of the first connector 230 (ie, corresponding to a second connection interface 2251 of the second connector 225 ), or a third connection interface 2501 of the third connector 250 (ie, corresponding to a second connection interface 2251 of the second connector 225 ) Corresponding to a fourth connection interface 2261 of the fourth connector 226).
  • connection interface identifier By associating the connection interface identifier with the signal type, it may be beneficial to enable the signal to be input to the corresponding connection interface relatively accurately.
  • Signal types may be determined, for example, by associated modules, signal content, signal properties, and the like.
  • the associated module may be, for example, a receiving/transmitting module through which the transmission signal passes.
  • the signal content may include, for example, image signals, audio signals, control signals, and the like.
  • Signal properties may include, for example, signals received by chip 222 , and signals transmitted by chip 222 .
  • connection interface identifier may correspond to a signal attribute. That is, the module that transmits the signal can determine the connection interface identifier according to the signal attribute.
  • the first connector 230 may be an output connector
  • the second connector 225 may be an input connector
  • the third connector 250 may be an input connector
  • the fourth connector 226 may be an output connector.
  • the second chip package structure 240 sends the signal A to the chip 222 of the first chip package structure 220
  • the signal property of the signal A may be the signal received by the chip 222 .
  • the second chip package structure 240 can determine that the signal A can be output through the first connector 230 and input from the second connector 225 to the chip 222 of the first chip package structure 220 .
  • the chip 222 of the first chip package structure 220 sends the signal B to the second chip package structure 240 , the chip 222 can determine that the signal B can be output through the fourth connector 226 and input from the third connector 250 to the second chip Package structure 240 .
  • FIG. 9 is a schematic structural diagram of another circuit board assembly 20 provided by an embodiment of the present application.
  • the circuit board assembly 20 may include a first circuit board assembly 21, a second circuit board assembly 31A, and a circuit board assembly 31B.
  • the first circuit board assembly 21 may include a first circuit board 210 , a first connector 230 , and a second chip package structure 240 .
  • the first connector 230 and the second chip package structure 240 may be disposed on the first circuit board 210 .
  • the thermal expansion coefficient of the second chip package structure 240 may be close to or the same as the thermal expansion coefficient of the first circuit board 210 .
  • the second circuit board assembly 31A may include a first circuit board 310A, a fifth connector 330A, and a third chip package structure 340A.
  • the fifth connector 330A and the third chip package structure 340A may be disposed on the first circuit board 310A.
  • the thermal expansion coefficient of the third chip package structure 340A may be close to or the same as the thermal expansion coefficient of the first circuit board 310A.
  • the second circuit board assembly 31B may include a first circuit board 310B, a fifth connector 330B, and a third chip package structure 340B.
  • the fifth connector 330B and the third chip package structure 340B may be disposed on the first circuit board 310B.
  • the thermal expansion coefficient of the third chip package structure 340B may be close to or the same as the thermal expansion coefficient of the first circuit board 310B.
  • the circuit board assembly 20 may also include a first chip package structure 220 .
  • the first chip package structure 220 may include a chip 222, a package substrate 221, a second connector 225, a sixth connector 321A, and a sixth connector 321B.
  • the second connector 225 , the sixth connector 321A, and the sixth connector 321B may all be disposed on the package substrate 221 .
  • the second connector 225 , the sixth connector 321A, and the sixth connector 321B can all be electrically connected to the chip 222 through the package substrate 221 .
  • the thermal expansion coefficient of the package substrate 221 may be the same as or similar to that of the chip 222 .
  • the circuit board assembly 20 may further include a first cable 331, a third cable 333A, and a third cable 333B.
  • the first cable 331 may be connected between the first connector 230 and the second connector 225.
  • the third cable 333A may be connected between the fifth connector 330A and the sixth connector 321A.
  • the third cable 333B may be connected between the fifth connector 330B and the sixth connector 321B.
  • the circuit board assembly 20 shown in FIG. 9 may provide a tree-like distributed module architecture.
  • the circuit board assembly 20 may include more or fewer chip packaging structures, and more or fewer connectors.
  • any one of the second chip packaging structure 240 , the third chip packaging structure 340A, and the third chip packaging structure 340B sends a signal to the chip 222 of the first chip packaging structure 220 , the chip 222 receives the signal due to the existing connection relationship. Connector conflicts usually do not occur.
  • the chip 222 of the first chip package structure 220 When the chip 222 of the first chip package structure 220 is ready to send a signal to any of the second chip package structure 240, the third chip package structure 340A, and the third chip package structure 340B, the chip 222 needs to determine the correct connector and/or or connection interface, so that the corresponding second chip package structure 240 can receive the signal.
  • the chip 222 may, for example, determine a connector identifier and/or an interface identifier corresponding to the signal according to one or more of the signal's associated device, signal content, and signal attribute.
  • the second chip packaging structure 240 may be, for example, a power management module.
  • the third chip packaging structure 340A may be, for example, an audio and video codec module.
  • the third chip packaging structure 340B may be, for example, a neural network processing module.
  • the first chip package structure 220 may be, for example, a central processing module of an electronic device.
  • the type of signal transmitted can vary.
  • the signal transmitted and received by the second chip packaging structure 240 ie, the power management module
  • the signals sent and received by the third chip packaging structure 340A may be, for example, audio and video signals.
  • the signals sent and received by the third chip package structure 340B may be, for example, artificial intelligence signals.
  • the chip 222 can determine a target connection corresponding to the target chip package structure (eg, any one of the second chip package structure 240 , the third chip package structure 340A, and the third chip package structure 340B ) from the plurality of connectors according to the signal content device.
  • the target chip package structure eg, any one of the second chip package structure 240 , the third chip package structure 340A, and the third chip package structure 340B .
  • the second chip package structure 240 , the third chip package structure 340A, and the third chip package structure 340B may also be chip package structures with other functions.
  • FIG. 10 is a schematic structural diagram of another circuit board assembly 20 provided by an embodiment of the present application.
  • the circuit board assembly 20 may include a first circuit board assembly 21, a third circuit board assembly 41A, a third circuit board assembly 41B, and a third circuit board assembly 41C.
  • the first circuit board assembly 21 may include a first circuit board 210, a first connector 230, a seventh connector 260A, a seventh connector 260B, and a seventh connector 260C.
  • the first connector 230 , the seventh connector 260A, the seventh connector 260B, and the seventh connector 260C may all be disposed on the first circuit board 210 .
  • the first connector 230 and the seventh connector 260A may be electrically connected through the first circuit board 210 .
  • the first connector 230 and the seventh connector 260B may be electrically connected through the first circuit board 210 .
  • the first connector 230 and the seventh connector 260C may be electrically connected through the first circuit board 210 .
  • the third circuit board assembly 41A may include a fourth circuit board 410A, an eighth connector 430A, and a fourth chip package structure 290A.
  • the eighth connector 430A and the fourth chip package structure 290A may be disposed on the fourth circuit board 410A.
  • the eighth connector 430A may include a plurality of eighth connection interfaces 4301A.
  • the thermal expansion coefficient of the fourth chip package structure 290A may be close to or the same as the thermal expansion coefficient of the fourth circuit board 410A.
  • the third circuit board assembly 41B may include a fourth circuit board 410B, an eighth connector 430B, and a fourth chip package structure 290B.
  • the eighth connector 430B and the fourth chip package structure 290B may be disposed on the fourth circuit board 410B.
  • the eighth connector 430B may include a plurality of eighth connection interfaces 4301B.
  • the thermal expansion coefficient of the fourth chip package structure 290B may be close to or the same as the thermal expansion coefficient of the fourth circuit board 410B.
  • the third circuit board assembly 41C may include a fourth circuit board 410C, an eighth connector 430C, and a fourth chip package structure 290C.
  • the eighth connector 430C and the fourth chip package structure 290C may be disposed on the fourth circuit board 410C.
  • the eighth connector 430C may include a plurality of eighth connection interfaces 4301C.
  • the thermal expansion coefficient of the fourth chip package structure 290C may be close to or the same as the thermal expansion coefficient of the fourth circuit board 410C.
  • the circuit board assembly 20 may also include a first chip package structure 220 .
  • the first chip package structure 220 may include a chip 222 , a package substrate 221 , and a second connector 225 .
  • the second connector 225 may be disposed on the package substrate 221 .
  • the second connector 225 may be electrically connected with the chip 222 through the package substrate 221 .
  • the second connector 225 may include a plurality of second connection interfaces 2251 . Similar to the circuit board assembly 20 shown in FIG. 4 , the thermal expansion coefficient of the package substrate 221 may be the same as or similar to that of the chip 222 .
  • the first connector 230 may include a plurality of first connection interfaces 2301 corresponding to the plurality of second connection interfaces 2251 .
  • the seventh connector 260A may include a plurality of seventh connection interfaces 2601A corresponding to the plurality of eighth connection interfaces 4301A.
  • the seventh connector 260B may include a plurality of seventh connection interfaces 2601B corresponding to the plurality of eighth connection interfaces 4301B.
  • the seventh connector 260C may include a plurality of seventh connection interfaces 2601C corresponding to the plurality of eighth connection interfaces 4301C.
  • the circuit board assembly 20 may also include a plurality of first cables 331 , a plurality of fourth cables 334A, a plurality of fourth cables 334B, and a plurality of fourth cables 334C.
  • a plurality of first cables 331 may be connected between the second connector 225 and the first connector 230 .
  • Each second connection interface 2251 and corresponding one or more first connection interfaces 2301 may be connected through one or more first cables 331 .
  • the fourth cable 334A may be connected between the eighth connector 430A and the seventh connector 260A.
  • Each of the eighth connection interfaces 4301A and the corresponding one or more seventh connection interfaces 2601A may be connected through one or more fourth cables 334A.
  • the fourth cable 334B may be connected between the eighth connector 430B and the second connector 225C.
  • Each eighth connection interface 4301B and the corresponding one or more seventh connection interfaces 2601B may be connected through one or more fourth cables 334B.
  • the fourth cable 334C may be connected between the eighth connector 430C and the second connector 225D.
  • Each eighth connection interface 4301C and corresponding one or more seventh connection interfaces 2601C may be connected through one or more fourth cables 334C.
  • the circuit board assembly 20 shown in FIG. 10 may provide a tree-like distribution of modules.
  • the circuit board assembly 20 may include more or fewer chip package structures 290 , and more or fewer connectors 230 .
  • the first part of the plurality of first connection interfaces 2301 may be connected to the seventh connector 260A; the second part of the plurality of first connection interfaces 2301 may be connected to the seventh connector 260B; the plurality of first connections The third portion of the interface 2301 may be connected to the seventh connector 260C.
  • the first part, the second part, and the third part may partially intersect, and may be completely different or completely the same.
  • any one of the fourth chip packaging structure 290A, the fourth chip packaging structure 290B, and the fourth chip packaging structure 290C sends a signal to the chip 222 of the first chip packaging structure 220, the chip 222 receives the signal due to the existing connection relationship. There will be no connector conflicts.
  • the chip 222 of the first chip package structure 220 When the chip 222 of the first chip package structure 220 is ready to send a signal to any one of the fourth chip package structure 290A, the fourth chip package structure 290B, and the fourth chip package structure 290C, the chip 222 at least needs to determine the first connector 230 The correct connector and/or interface is required so that the corresponding chip package structure can receive the signal.
  • the fourth chip packaging structure 290A, the fourth chip packaging structure 290B, and the fourth chip packaging structure 290C can be in charge of different functions of the electronic device, the fourth chip packaging structure 290A, the fourth chip packaging structure 290B, and the fourth chip packaging structure 290C are respectively
  • the types of signals to be transmitted may be different, for example, the related devices of the signals are different, the content of the signals, and the properties of the signals are different.
  • the chip 222 may determine the target chip package structure (eg, the fourth chip package structure 290A, the fourth chip package structure 290B, the fourth chip package structure 290B, the fourth chip package structure 290B, the fourth chip package structure 290B, the fourth chip package structure Any one of the package structures 290C) corresponds to the target connection interface.
  • FIG. 11 is a schematic structural diagram of still another circuit board assembly 20 provided by an embodiment of the present application.
  • the circuit board assembly 20 may include a first circuit board assembly 21 , a second circuit board assembly 31 , a third circuit board assembly 41 , and a fourth circuit board assembly 51 .
  • the first circuit board assembly 21 may include a first circuit board 210 , a second chip package structure 240 , a first connector 230 , and a seventh connector 260 .
  • the first connector 230 , the seventh connector 260 , and the second chip package structure 240 may all be disposed on the first circuit board 210 .
  • Both the first connector 230 and the seventh connector 260 may be electrically connected to the second chip package structure 240 through the first circuit board 210 .
  • the thermal expansion coefficient of the second chip package structure 240 may be close to or the same as the thermal expansion coefficient of the first circuit board 210 .
  • the second circuit board assembly 31 may include a third circuit board 310 , a third chip package structure 340 , a fifth connector 330 , a ninth connector 350 , and a tenth connector 360 .
  • the fifth connector 330 , the ninth connector 350 , the tenth connector 360 , and the third chip package structure 340 may all be disposed on the third circuit board 310 .
  • the fifth connector 330 , the ninth connector 350 , and the tenth connector 360 may all be electrically connected to the third chip package structure 340 through the third circuit board 310 .
  • the thermal expansion coefficient of the third chip package structure 340 may be close to or the same as the thermal expansion coefficient of the third circuit board 310 .
  • the third circuit board assembly 41 may include a fourth circuit board 410 , an eighth connector 430A, an eleventh connector 351 , and a fourth chip package structure 290 .
  • the eighth connector 430A, the eleventh connector 351 , and the fourth chip package structure 290 may all be disposed on the fourth circuit board 410 and electrically connected to the fourth circuit board 410 .
  • the thermal expansion coefficient of the fourth chip package structure 290 may be close to or the same as the thermal expansion coefficient of the fourth circuit board 410 .
  • the fourth circuit board assembly 51 may include a fifth circuit board 510 , a twelfth connector 361 , and a fifth chip package structure 540 . Both the twelfth connector 361 and the fifth chip package structure 540 may be disposed on the fifth circuit board 510 and electrically connected to the fifth circuit board 510 . Optionally, the thermal expansion coefficient of the fifth chip package structure 540 may be close to or the same as the thermal expansion coefficient of the fifth circuit board 510 .
  • the circuit board assembly 20 may also include a first chip package structure 220 .
  • the first chip package structure 220 may include a chip 222 , a package substrate 221 , a second connector 225 , and a sixth connector 321 . Both the second connector 225 and the sixth connector 321 may be disposed on the package substrate 221 . Both the second connector 225 and the sixth connector 321 may be electrically connected to the chip 222 through the package substrate 221 .
  • the second connector 225 may include a plurality of second connection interfaces 2251 .
  • the sixth connector 321 may include a plurality of sixth connection interfaces 3211 . Similar to the circuit board assembly 20 shown in FIG. 4 , the thermal expansion coefficient of the package substrate 221 may be the same as or similar to that of the chip 222 .
  • the second connector 225 of the first chip package structure 220 may be connected to the first connector 230 on the first circuit board 210 .
  • the second connector 225 may include a plurality of second connection interfaces 2251 .
  • the first connector 230 may include a plurality of first connection interfaces 2301 .
  • the plurality of second connection interfaces 2251 may correspond to the plurality of first connection interfaces 2301 .
  • the circuit board assembly 20 may include a plurality of first cables 331 .
  • the plurality of first cables 331 may correspond to the plurality of second connection interfaces 2251 .
  • Each second connection interface 2251 and corresponding one or more first connection interfaces 2301 may be connected through corresponding one or more first cables 331.
  • the sixth connector 321 of the first chip package structure 220 may be connected to the fifth connector 330 on the third circuit board 310 .
  • the sixth connector 321 may include a plurality of sixth connection interfaces 3211 .
  • the fifth connector 330 may include a plurality of fifth connection interfaces 3301 .
  • the plurality of sixth connection interfaces 3211 may correspond to the plurality of fifth connection interfaces 3301 .
  • the circuit board assembly 20 may include a plurality of third cables 333 .
  • the plurality of third cables 333 may correspond to the plurality of fifth connection interfaces 3301 .
  • Each fifth connection interface 3301 and corresponding one or more sixth connection interfaces 3211 may be connected through corresponding one or more third cables 333 .
  • the eighth connector 430 on the fourth circuit board 410 may be connected to the seventh connector 260 on the first circuit board 210 .
  • the eighth connector 430 may include a plurality of eighth connection interfaces 4301 .
  • the seventh connector 260 may include a plurality of seventh connection interfaces 2601 .
  • the plurality of eighth connection interfaces 4301 may correspond to the plurality of seventh connection interfaces 2601 .
  • the circuit board assembly 20 may include a plurality of fourth cables 334 .
  • the plurality of fourth cables 334 may correspond to the plurality of seventh connection interfaces 2601 .
  • Each seventh connection interface 2601 and corresponding one or more eighth connection interfaces 4301 may be connected through corresponding one or more fourth cables 334 .
  • the ninth connector 350 on the third circuit board 310 may be connected with the eleventh connector 351 on the fourth circuit board 410 .
  • the ninth connector 350 may include a plurality of ninth connection interfaces 3501 .
  • the eleventh connector 351 may include a plurality of eleventh connection interfaces 3511 .
  • the plurality of ninth connection interfaces 3501 may correspond to the plurality of eleventh connection interfaces 3511 .
  • the circuit board assembly 20 may include a plurality of fifth cables 335 .
  • the plurality of fifth cables 335 may correspond to the plurality of ninth connection interfaces 3501 .
  • Each of the ninth connection interfaces 3501 and the corresponding one or more eleventh connection interfaces 3511 may be connected through corresponding one or more fifth cables 335 .
  • the tenth connector 360 on the third circuit board 310 may be connected to the twelfth connector 361 on the fifth circuit board 510 .
  • the tenth connector 360 may include a plurality of tenth connection interfaces 3601 .
  • the twelfth connector 361 may include a plurality of twelfth connection interfaces 3611 .
  • the plurality of tenth connection interfaces 3601 may correspond to the plurality of twelfth connection interfaces 3611 .
  • the circuit board assembly 20 may include a plurality of sixth cables 336 .
  • the plurality of sixth cables 336 may correspond to the plurality of tenth connection interfaces 3601 .
  • Each tenth connection interface 3601 and corresponding one or more twelfth connection interfaces 3611 may be connected through corresponding one or more sixth cables 336 .
  • the first circuit board 210 may further include an electrical connection line A (not shown in FIG. 11 ) that is electrically connected between the first connector 230 and the seventh connector 260 . This may allow signals between the chip 222 and the fourth chip package structure 290 to be transmitted bypassing the second chip package structure 240 on the first circuit board 210 .
  • the third circuit board 310 may further include an electrical connection line B (not shown in FIG. 11 ) that is electrically connected between the sixth connector 321 and the fifth connector 330 . This may allow signals between the chip 222 and the fourth chip package structure 290 , and signals between the chip 222 and the fifth chip package structure 540 to bypass the third chip package structure 340 on the third circuit board 310 .
  • the circuit board assembly 20 shown in FIG. 11 may provide a mesh or patterned distribution of modules architecture.
  • the circuit board assembly 20 may include more or fewer chip packaging structures, and more or fewer connectors.
  • the second chip packaging structure 240 and the third chip packaging structure 340 may be, for example, distributed preprocessing units of the first chip packaging structure 220 .
  • Data from the fourth chip package structure 290 or the fifth chip package structure 540 may be preprocessed by the second chip package structure 240 and/or the third chip package structure 340 and then transmitted to the first chip package structure 220 .
  • the connector and interface through which the signal passes may be determined in advance.
  • the signal emitted by the fourth chip package structure 290 can be transmitted to the chip 222 via the first circuit board assembly 21 and can also be transmitted to the chip 222 via the second circuit board assembly 31 .
  • the signal sent by the fifth chip packaging structure 540 can be transmitted to the chip 222 via the second circuit board assembly 31 , or can be transmitted to the chip 222 via the second circuit board assembly 31 , the third circuit board assembly 41 , and the first circuit board assembly 21 .
  • the interface through which the signal is transmitted can be determined according to the signal type.
  • the signal from the chip 222 may be transmitted to the fourth chip package structure 290 and the fifth chip package structure 540 via the first circuit board assembly 21 and/or the second circuit board assembly 31 .
  • Chip 222 can determine the correct connector and/or the correct interface so that the corresponding chip package structure can receive the signal.
  • the fourth chip packaging structure 290 and the fifth chip packaging structure 540 may be in charge of different functions of the electronic device, and the signal types transmitted by the fourth chip packaging structure 290 and the fifth chip packaging structure 540 may be different.
  • the interface through which the signal is transmitted can be determined according to the signal type. For example, the related equipment of the signal is different, the content of the signal is different, and the signal attribute is different.
  • the chip may determine a plurality of connection interfaces corresponding to the target chip package structure (such as any one of the fourth chip package structure 290 and the fifth chip package structure 540 ) according to the signal type.
  • the chip packaging structure is arranged outside the circuit board, which is beneficial to reduce the thermal deformation influence of the chip packaging structure on the circuit board.
  • it is beneficial to reduce the stress on the first circuit board and improve the mechanical stability of the first circuit board; it is beneficial to reduce the deformation of the first circuit board due to temperature, and it is beneficial to improve the flatness of the first circuit board .
  • the thermal expansion coefficients of the multiple devices inside the chip package structure can be as similar as possible, and the deformation amounts of the multiple devices inside the chip package structure can be similar, which is beneficial to improve the connection stability between the multiple devices inside the chip package structure.
  • the thermal expansion coefficient of the device of the chip package structure can be similar or the same as the thermal expansion coefficient of the chip.
  • the thermal expansion coefficient of the chip is usually small, so it is beneficial to make the deformation of the chip package structure when heated or cold.
  • the amount of deformation can be relatively small.
  • the flatness of the circuit board inside the structure can be relatively high.

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Abstract

本申请提供了一种电路板装配件、电子设备。电路板装配件包括芯片封装结构、电路板。芯片封装结构设置在电路板以外。电路板、芯片封装结构均设置有连接器，电路板上的连接器和芯片封装结构的连接器可以通过线缆相连。芯片封装结构内的基板和芯片的热膨胀系数相近或相同。本申请实施例提供的电路板装配件有利于提升电路板装配件的机械稳定性。

Description

电路板装配件和电子设备 技术领域
本申请涉及电子设备领域及芯片领域，更为具体的，涉及电路板装配件和电子设备。
背景技术
电子设备可以包括多个芯片封装结构，通过驱动、控制这些芯片封装结构，可以使电子设备具有与该多个芯片封装结构相对应的功能。芯片封装结构例如可以是设置在电路板上。电路板可以为芯片封装结构传输电信号。在芯片封装结构工作时，芯片封装结构可能会发热，进而芯片封装结构可能发生略微的形变。芯片封装结构产生的热量可以进一步被传递至电路板。由于电路板与芯片封装结构的热膨胀系数可能不同，因此在受热或遇冷时，电路板与芯片封装结构的形变量可能不匹配，进而降低芯片封装结构与电路板之间的连接稳定性和可靠性。
发明内容
本申请提供一种电路板装配件和电子设备，电路板装配件可以包括电路板和芯片封装结构。本申请的目的是提高电路板装配件的机械稳定性和可靠性。
第一方面，提供了一种电路板装配件，包括：
第一电路板组件、第一芯片封装结构以及多个第一线缆，所述第一芯片封装结构设置在所述第一电路板组件以外，所述多个第一线缆用于在所述第一电路板组件与所述第一芯片封装结构之间传输信号；
所述第一电路板组件包括：
第一电路板；
第一连接器，所述第一连接器设置在所述第一电路板上，并与所述第一电路板电连接，所述第一连接器包括多个第一连接接口；
所述第一芯片封装结构包括：
封装基板；
第二连接器，所述第二连接器设置在所述封装基板上，所述第二连接器包括多个第二连接接口，所述多个第二连接接口与所述第一连接器的所述多个第一连接接口对应，每个所述第二连接接口与对应的一个或多个所述第一连接接口通过对应的一个或多个所述第一线缆相连；
芯片，所述芯片设置在所述封装基板上，所述芯片与所述第二连接器通过所述封装基板电连接。
线缆传输信号例如可以是光信号、电信号。如果线缆传输电信号，则多个第一线缆可以电连接在第一电路板组件和第一芯片封装结构之间。如果线缆传输光信号，则多个第一线缆可以光连接在第一电路板组件和第一芯片封装结构之间。
在本申请中，通过线缆连接两个电路板组件，使得两个电路板组件之间可以交互信号。从而，在不影响连接关系的情况下，可以使单个电路板组件具有数量更少的电路板。也就是说，连接走线可以通过线缆实现，连接走线可以不集成在电路板上。这样便于将设置有芯片的电路板的热膨胀系数设定为与该芯片的热膨胀系数相同或相近。
结合第一方面，在第一方面的某些实现方式中，所述芯片的热膨胀系数与所述封装基板的热膨胀系数的差值小于5ppm/℃。
在本申请中，在相同的温度变化情况下，如果电路板的热膨胀系数设定与该芯片的热膨胀系数相差越小，电路板的尺寸变化与芯片的尺寸变化可以相差越小。将芯片固定在电路板上的固定连接件(如焊料、胶体等)可以受到尽可能小的尺寸牵引，进而有利于提高电路板与芯片之间的连接稳定性。
结合第一方面，在第一方面的某些实现方式中，所述芯片的热膨胀系数为2～7ppm/℃，与所述封装基板的热膨胀系数为2～7ppm/℃。
在本申请中，芯片可以是硅基芯片。电路板的热膨胀系数可以硅基芯片相同或相近。
结合第一方面，在第一方面的某些实现方式中，所述芯片的热膨胀系数与所述第一电路板的热膨胀系数的差值大于5ppm/℃。
在本申请中，由于芯片与第一电路板之间没有直接的固定关系，第一电路板的热膨胀系数与芯片的热膨胀系数相差较大，有利于拓宽第一电路板的选材范围，进而有利于提升电路板装配件的综合性能，如机械性能、成本等。
结合第一方面，在第一方面的某些实现方式中，所述芯片为硅基芯片；所述封装基板包括层叠间隔设置的多个绝缘层、多个导电层，相邻两个所述绝缘层之间设置有一个所述导电层，相邻两个导电层之间设置有一个所述绝缘层，所述绝缘层的材料包括以下至少一种：陶瓷、玻璃、金刚石。
在本申请中，硅基芯片的热膨胀系数通常相对较小。通过将电路板中的绝缘层设置为热膨胀系数相对较小的材料，有利于使电路板的热膨胀系数与硅基芯片的热膨胀系数相同或相近。
结合第一方面，在第一方面的某些实现方式中，所述芯片包括多个第一芯片接口、多个第二芯片接口，每个所述第一芯片接口通过所述封装基板与对应的一个或多个所述第二连接接口电连接；
所述第一电路板组件还包括：
第三连接器，所述第三连接器设置在所述第一电路板上，并与所述第一电路板电连接，所述第三连接器包括多个第三连接接口；
所述第一芯片封装结构还包括：
第四连接器，所述第四连接器设置在所述封装基板上，所述第四连接器包括多个第四连接接口，每个所述第四连接接口通过所述封装基板与对应的一个或多个所述第二芯片接口电连接，所述多个第四连接接口与所述多个第三连接接口对应；
所述电路板装配件还包括：
多个第二线缆，所述多个第二线缆与所述多个第三连接接口对应，每个所述第三连接接口与对应的一个或多个所述第四连接接口通过对应的一个或多个所述第二线缆相连。
在本申请中，通过在第一电路板和封装基板上均上设置多个连接器，可以使得第一芯 片封装结构与第一电路板组件的连接关系更加灵活，有利于实现相对复杂的连接走线。例如，可以增加第一芯片封装结构与第一电路板组件之间的走线数量。又如，便于实现树状、网状等走线网络。
结合第一方面，在第一方面的某些实现方式中，所述第一电路板组件还包括第二芯片封装结构，所述第二芯片封装结构设置在所述第一电路板上，所述第一芯片封装结构与所述第二芯片封装结构之间的信号通过所述第一电路板、所述第一连接器、所述多个第一线缆传输。
结合第一方面，在第一方面的某些实现方式中，所述电路板装配件还包括第二电路板组件、多个第三线缆，所述多个第三线缆用于传输在所述第二电路板组件、所述第一芯片封装结构之间传输信号；
所述第二电路板组件包括：
第三电路板；
第五连接器，所述第五连接器设置在所述第三电路板上，所述多个第五连接接口与所述多个第三线缆对应；
第三芯片封装结构，所述第三芯片封装结构设置在所述第三电路板上，所述第三芯片封装结构与所述第五连接器通过所述第三电路板电连接；
所述第一芯片封装结构还包括：
第六连接器，所述第六连接器设置在所述封装基板上，所述第六连接器与所述芯片通过所述封装基板电连接，所述第六连接器包括多个第六连接接口，所述多个第六连接接口与所述第五连接器的所述多个第五连接接口对应，每个所述第六连接接口与对应的一个或多个所述第五连接接口通过对应的一个或多个所述第三线缆相连。
在本申请中，通过在多个连接器和多个线缆，便于在电路板装配件中实现树状走线网络。
结合第一方面，在第一方面的某些实现方式中，所述第三芯片封装结构的功能与所述第二芯片封装结构的功能不同。
在本申请中，多个芯片封装结构的功能不同，便于灵活地确定硬件的功能。例如，芯片可以处理来自多个芯片封装结构的信号。其他芯片封装结构可以分别为芯片提供不同的预处理功能。
结合第一方面，在第一方面的某些实现方式中，所述第二芯片封装结构为所述第一芯片封装结构的预处理单元。
在本申请中，通过规划芯片封装结构的电连接方式，可以对应实现多个芯片封装结构的数据处理功能。
结合第一方面，在第一方面的某些实现方式中，所述第一电路板组件还包括：
第七连接器，所述第七连接器设置在所述第一电路板上，所述第七连接器与所述第一连接器通过所述第一电路板电连接，所述第七连接器包括多个第七连接接口；
所述电路板装配件还包括第三电路板组件和多个第四线缆，所述多个第四线缆用于在所述第三电路板组件与所述第一电路板组件之间传输信号，所述多个第四线缆与所述多个第七连接接口对应；
所述第三电路板组件包括：
第四电路板；
第八连接器，所述第八连接器设置在所述第四电路板上，所述第八连接器包括与所述多个第七连接接口对应的多个第八连接接口，每个所述第八连接接口与对应的一个或多个所述第七连接接口通过对应的一个或多个所述第四线缆相连；
第四芯片封装结构，所述第四芯片封装结构设置在所述第四电路板上，所述第四芯片封装结构与所述第八连接器通过所述第四电路板电连接。
在本申请中，可以通过一个线路转接板。线路转接板可以被视为一个信号转接节点。线路转接板可以实现数量更多的信号传输方式，便于在电路板装配件中实现树状、网状等走线网络。
结合第一方面，在第一方面的某些实现方式中，所述第一电路板相对于所述封装基板平行设置，
所述第一电路板和所述封装基板在垂直于所述第一电路板的方向上排列；
或者，
所述封装基板设置在所述第一电路板所在的平面上。
在本申请中，第一芯片封装结构和第一电路板组件平行分散摆放，可以有利于减少电路板装配件在厚度方向上的占用空间。第一芯片封装结构和第一电路板组件叠层摆放，可以有利于减少电路板装配件在横纵方向(横纵方向均与厚度方向垂直设置)上的占用空间。
结合第一方面，在第一方面的某些实现方式中，所述芯片收发的信号所经过的连接器和/或连接接口由所述信号的信号类型确定。
在本申请中，通过将连接接口标识与信号类型关联起来，可以有利于使信号可以相对准确地输入至相对应的连接接口。
结合第一方面，在第一方面的某些实现方式中，所述信号类型包括以下至少一项关联模块、信号内容、信号属性。
关联模块例如可以是传输信号所经过的收/发模块。信号内容例如可以包括图像信号、音频信号、控制信号等。信号属性例如可以包括芯片接收的信号，芯片发送的信号等。
或者，
所述第一芯片封装结构为以下任一种：中央处理器，应用处理器，调制解调处理器，图形处理器，图像信号处理器，视频编解码器，数字信号处理器，基带处理器，神经网络处理器，生物特征识别模组，存储器，电源管理单元，光芯片。
结合第一方面，在第一方面的某些实现方式中，所述第一线缆为柔性线缆。
柔性线缆便于在多个电连接件之间电连接。
第二方面，提供了一种电子设备，包括壳体、如上述第一方面中的任意一种实现方式中所述的电路板装配件，所述电路板装配件收容于所述壳体内。
附图说明
图1是一种电子设备的示意性结构图。
图2是一种电路板装配件的示意性结构图。
图3是另一种电路板装配件的示意性结构图。
图4是本申请实施例提供的一种电路板装配件的示意性结构图。
图5是本申请实施例提供的一种电路板装配件的示意性结构图。
图6是本申请实施例提供的连接器的示意性结构图。
图7是本申请实施例提供的一种电路板装配件的示意性结构图。
图8是本申请实施例提供的另一种电路板装配件的示意性结构图。
图9是本申请实施例提供的又一种电路板装配件的示意性结构图。
图10是本申请实施例提供的还一种电路板装配件的示意性结构图。
图11是本申请实施例提供的再一种电路板装配件的示意性结构图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
图1是本申请实施例提供的一种电子设备100的结构示意图。
电子设备100可以是服务器、基站、电脑主机等。电子设备100还可以是手机、平板电脑、电子阅读器、笔记本电脑、数码相机、汽车、车载设备、航空仪器、路由器、智能音箱、无人机、可穿戴设备等设备。图1所示实施例以电子设备100是服务器为例进行说明。
电子设备100包括壳体10和电路板装配件(图1中未示出)。电路板装配件可以收容于壳体10内。壳体10还可以包括多个开口。电路板装配件上的部件可以与壳体10上的开口相连，以实现电路板装配件与外界部件相连。例如，电路板装配件可以包括通用串行总线(universal serial bus，USB)接口。壳体10可以包括与USB接口对应的开口。USB线缆可以穿过壳体上的开口，从而USB线缆的端部可以与USB接口相连。
电路板装配件的接口例如还可以包括集成电路间(inter-integrated circuit，I2C)接口，集成电路间音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口等。
电路板装配件可以包括一个或多个电路板以及与电路板电连接的一个或多个芯片封装结构。图2、图3示出了两种电路板装配件20的示意性结构图。在图2、图3所示的示例中，电路板装配件20的一个或多个电路板可以包括第一电路板210。电路板装配件20的一个或多个芯片封装结构可以包括芯片封装结构220。芯片封装结构220可以设置在第一电路板210上。
电路板可以是印刷电路板(printed circuit board，PCB)、基板、柔性电路板等。根据电路板上承载的芯片封装结构的数量，电路板可以是单面板、双面板。单面板可以指单侧承载芯片封装结构的电路板。双面板可以指双侧承载芯片封装结构的电路板。电路板例如可以用于承载芯片封装结构，并为芯片封装结构传输信号。
在一个示例中，芯片封装结构例如可以是中央处理器、应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，神经网络处理器(neural-network processing unit，NPU)，生物特征识别模组，片上系统(system on chip，SOC)模块，双倍数据率(double  data rate，DDR)存储器，主电源管理单元(power management unit，PMU)，辅PMU，高速随机存取存储器，非易失性存储器，光芯片等。
在另一个示例中，芯片封装结构除了可以是单个芯片封装结构，还可以是通过多个芯片封装结构堆叠得到。例如，处理器与存储器可以堆叠形成封装堆叠(package on package，PoP)模块。
如图2、图3所示，芯片封装结构220可以包括芯片222。芯片222例如可以是硅基芯片、碳基芯片等。
可选的，芯片例如可以单独作为芯片封装结构。
可选的，芯片封装结构还可以包括除芯片以外的其他部件。
如图2、图3所示，芯片封装结构220还可以包括封装基板221。芯片222可以设置在封装基板221上。封装基板221例如可以是基板。封装基板221可以位于第一电路板210与芯片222之间。芯片222与第一电路板210可以通过封装基板221电连接。也就是说，电路板可以是芯片封装结构的一部分。芯片封装结构内部的电路板可以用于铺设芯片封装结构的部分线路，并用于承载芯片封装结构的芯片。
可选的，芯片222可以包括多个芯片接口。封装基板221可以包括与该多个芯片接口对应的多个基板接口。芯片封装结构可以包括电连接在芯片接口与基板接口之间的多个电连接线路。电连接线路例如可以是设置在封装基板221上的线路。例如，芯片222可以包括芯片接口A，封装基板221可以包括基板接口A、电连接线路A，电连接线路A可以电连接在芯片接口A与基板接口A之间。
在一个示例中，封装基板221的基板接口与芯片222的芯片接口可以一对一地电连接。
在另一个示例中，封装基板221的基板接口与芯片222的芯片接口可以多对一地电连接。例如，芯片222可以包括芯片接口A，封装基板221可以包括基板接口A、基板接口B，封装基板221还可以包括电连接线路A、电连接线路B，电连接线路A可以电连接在芯片接口A与基板接口A之间，电连接线路B可以电连接在芯片接口A与基板接口B之间。
在又一个示例中，封装基板221的基板接口与芯片222的芯片接口可以一对多地电连接。例如，芯片222可以包括芯片接口A、芯片接口B，封装基板221可以包括基板接口A。封装基板221还可以包括电连接线路A、电连接线路C，电连接线路A可以电连接在芯片接口A与基板接口A之间，电连接线路C可以电连接在芯片接口B与基板接口A之间。
封装基板221上的多个基板接口可以充当芯片封装结构的多个接口。基板接口可以位于封装基板221的远离芯片222的一侧。第一电路板210上的焊料310可以与基板接口相连。来自第一电路板210的信号可以经过基板接口、芯片接口传输至芯片222。芯片222产生的信号可以经芯片接口、基板接口传输至第一电路板210。
电路板装配件的多个部件之间例如可以通过焊料固定。例如，在电路板与电路板之间，芯片封装结构与电路板之间，芯片封装结构的芯片与芯片封装结构的电路板之间，在芯片封装结构1与芯片封装结构2之间，均可以通过焊料固定。焊料可以用于机械连接和/或电连接，焊料的形状可以是球形、多面体、椭球形、圆台形、倒角形、条形、棒形等。
如图2、图3所示，芯片封装结构220的封装基板221与第一电路板可以通过焊料310 固定；芯片封装结构220的封装基板221与芯片封装结构220的芯片222可以通过焊料310固定。
本申请实施例可以不限于通过焊料连接电路板装配件的多个部件。电路板装配件的多个部件之间的连接方式例如还可以有螺钉连接、胶粘等方式。
在图2所示的示例中，芯片封装结构220可以包括封装基板221、芯片222、罩件223。罩件223可以包括盖体2231和框体2232。盖体2231和框体2232可以相对垂直设置。盖体2231和封装基板221可以相对平行设置。其中，框体2232可以连接在盖体2231和封装基板221之间。罩件223和封装基板221之间形成的空腔可以用于收容芯片222。
在一个示例中，罩件223例如可以是散热罩。罩件223的盖体2231可以与芯片222的远离封装基板221的表面接触。罩件223例如可以用于传导芯片222产生的热量，降低芯片222过热的风险。
在另一个示例中，罩件223例如可以屏蔽罩。罩件223可以与芯片222绝缘。罩件223例如可以用于为芯片222屏蔽外界的干扰信号。
在图3所示的示例中，芯片封装结构220可以包括封装基板221、芯片222、封装材料224。
芯片222例如可以通过粘胶设置在封装基板221上。在其他示例中，芯片222还可以通过其他方式固定在封装基板221上。芯片222与封装基板221可以通过一个或多个第一电连接引线3201电连接。第一电连接引线3201可以电连接在芯片222和封装基板221之间。
可选的，芯片封装结构220与第一电路板210除了可以通过焊料310电连接，芯片封装结构220与第一电路板210还可以通过电连接件311电连接。在图3所示的示例中，电连接件311的一端可以与第一电路板210相连，电连接件311的另一端可以与芯片封装结构220的芯片222通过一个或多个第二连接引线3202电连接。电连接件311可以充当芯片封装结构220和第一电路板210之间的电连接走线。
封装材料224可以包裹在芯片222的外周，且与封装基板221的设置有芯片222的表面接触。电连接件311可以部分包裹在封装材料224内。电连接件311的一部分可以伸出封装材料224。封装材料224还可以包裹封装基板221的至少部分侧面。封装基板221的远离芯片222的表面可以外露出封装材料224。封装材料224可以用于提高芯片222与封装基板221之间的连接稳定性。在芯片222工作时，芯片222可能会发热，进而芯片222可能发生略微的形变。芯片222产生的热量可以被进一步传递至封装基板221、第一电路板210。在电路板装配件20受热或遇冷时，封装基板221、第一电路板210、芯片222三者的形变量可能不匹配。封装基板221可以承受来自芯片222、第一电路板210的应力，降低芯片222与封装基板221之间，以及封装基板221与第一电路板210之间的连接稳定性。
例如，芯片222可以是硅基芯片，硅基芯片的热膨胀系数例如可以约为2.6ppm/℃；封装基板221可以是基板，基板的热膨胀系数例如可以是10-15ppm/℃。第一电路板210例如可以是印刷电路板，印刷电路板的热膨胀系数例如可以是15-20ppm/℃。在升温情况相同的情况下，印刷电路板的热变形量可以相对较大，基板的热变形量可以次之，硅基芯片的热变形量可以相对较小。基板可以受到硅基芯片、印刷电路板的变形牵引力，进而基 板与硅基芯片之间、基板与印刷电路板之间的连接稳定性可能相对较差。
图4、图5示出了本申请实施例提供的一种电路板装配件20。图4、图5分别是在两个视角下的电路板装配件20的示意性结构图。
电路板装配件20可以包括第一电路板组件21、第一芯片封装结构220、多个第一线缆331。多个第一线缆331可以连接在第一电路板组件21和第一芯片封装结构220之间，以在第一电路板组件21和第一芯片封装结构220之间传输信号。该信号例如可以是光信号、电信号。如果该信号为电信号，则多个第一线缆331可以电连接在第一电路板组件21和第一芯片封装结构220之间。如果该信号为光信号，则多个第一线缆331可以光连接在第一电路板组件21和第一芯片封装结构220之间。在本申请实施例中，“连接”例如可以包括以下一种或多种：机械连接、电连接、光连接。
第一电路板组件21可以包括第一电路板210、第一连接器230。
第一连接器230例如可以由铜、铝、不锈钢等材料制成。第一连接器230例如可以并行地传输多路信号。第一连接器230可以设置在第一电路板210上。例如通过焊料310，第一连接器230可以被固定在第一电路板210上，并且第一连接器230与第一电路板210可以通过焊料310电连接。又如，第一连接器230可以通过压接的方式固定在第一电路板上210。
第一线缆331可以包括内芯和外包层，内芯的材料例如可以是铜、铝、玻璃纤维等。外包层例如可以是绝缘材料。多个第一线缆331可以连接在第一连接器230和第一芯片封装结构220之间，以实现第一电路板210与第一芯片封装结构220之间的信号传输。
第一连接器230可以包括多个第一连接接口2301。多个第一连接接口2301可以与多个第一线缆331对应。一个或多个第一线缆331的第一端例如可以插接在对应的第一连接接口2301上。第一连接器230例如可以设置在第一电路板210的相对边缘的区域，以便于多个第一连接接口2301可以分别与多个第一线缆331相连。
第一芯片封装结构220可以设置在第一电路板210以外。也就是说，第一芯片封装结构220可以不设置在第一电路板210上。第一电路板210例如可以象征一般的印刷电路板，其中一般的印刷电路板的热膨胀系数可以与芯片封装结构220的热膨胀系数相差较大。第一芯片封装结构220例如可以固定在如图1所示的电子设备100的壳体上，或者固定在电子设备100内的支架上。
第一芯片封装结构220可以包括封装基板221、第二连接器225和芯片222。例如通过焊料310，芯片222、第二连接器225均可以设置在封装基板221上，并与封装基板221电连接。芯片222与第二连接器225可以通过封装基板221电连接。多个第一线缆331传输的信号可以通过第二连接器225输入至第一芯片封装结构220，来自第一芯片封装结构220的信号可以通过第二连接器225输出至多个第一线缆331。第二连接器225可以设置在封装基板221的相对边缘的区域，以便于与多个第一线缆331相连。可选的，第一芯片封装结构220还可以包括如图2所示的罩件223。可选的，第一芯片封装结构220还可以包括如图3所示的封装材料224。
芯片222例如可以包括集成电路，该集成电路上例如可以集成有多个晶体管(或逻辑门)。晶体管例如可以属于芯片222的处理单元或计算单元。
芯片222、封装基板221的热膨胀系数可以相近或相同，即芯片222的热膨胀系数、 封装基板221的热膨胀系数的差值可以小于第一预设阈值。例如芯片222、封装基板221的热膨胀系数可以均在2～7ppm/℃范围内。芯片222、封装基板221的热膨胀系数相近或相同例如可以指，芯片222的热膨胀系数、封装基板221的热膨胀系数的差值例如可以小于5ppm/℃。例如芯片222的热膨胀系数、封装基板221的热膨胀系数的差值小于0.5ppm/℃，或小于1ppm/℃，或小于2ppm/℃，或小于3ppm/℃，或小于4ppm/℃。
可选的，芯片222或封装基板221的热膨胀系数可以与第一电路板210的热膨胀系数相差较大，即芯片222的热膨胀系数、封装基板221的热膨胀系数的差值可以大于第二预设阈值，第二预设阈值可以大于第一预设阈值。例如，芯片222的热膨胀系数可以与第一电路板210的热膨胀系数的差值例如可以大于1ppm/℃。例如，芯片222的热膨胀系数与第一电路板210的热膨胀系数的差值可以大于3ppm/℃，或大于5ppm/℃，或大于7ppm/℃，或大于10ppm/℃，或大于15ppm/℃。
与图2、图3所示的示例相比，在图4、图5所示的示例中，封装基板221在受热或遇冷变形时的变形量可以相对较小，封装基板221的平整度可以相对较高。另外，由于封装基板221和芯片222的热膨胀系数尽可能相同，封装基板221和芯片222的变形量可以相似，封装基板221和芯片222因温度变化引起的变形量可以相似或匹配，因此有利于提升封装基板221与芯片222之间的连接稳定性。由于第一芯片封装结构220可以设置在第一电路板210以外，第一芯片封装结构220的变形对第一电路板210的影响可以相对较小，有利于减小第一电路板210承受的应力，提高第一电路板210的机械稳定性。来自芯片222的热量也相对较难影响第一电路板210，有利于减小第一电路板210的变形量，有利于提升第一电路板210的平整度。
如图4中的局部放大图所示，封装基板221可以包括多个导电层2211和多个绝缘层2212。多个导电层2211和多个绝缘层2212可以层叠间隔设置。相邻两个导电层2211之间设置有一个绝缘层2212。相邻两个绝缘层2212之间设置有一个导电层2211。两个导电层2211之间例如可以通过导通孔2213电连接。多个导电层2211可以形成封装基板221上的电连接线路。其中，为使封装基板221的热膨胀系数可以与芯片222的热膨胀系数接近，绝缘层2212例如可以采用陶瓷材料等材料。
导电层2211例如可以是铜材。在焊料310和导电层2211之间可以设置有焊盘2214。焊盘2214的材料可以不同于导电层2211的材料，焊盘2214例如可以是锡镀层、镍镀层等。一方面，焊盘2214有利于提高焊接可靠性，使得芯片222可以通过焊料310固定在封装基板221上；另一方面，焊盘2214可以用于避免导电层2211上的电连接线路外露在空气中，减少空气对电连接线路的侵蚀、破坏。如图4所示，通过焊料310、封装基板221上的焊盘2214以及至少一个导电层2211，可以使芯片222和第二连接器225电连接。
芯片222可以包括多个芯片接口2221。芯片接口2221例如可以由集成电路的引脚、焊盘2214等形成。芯片接口2221例如可以传输信号，如电信号、射频信号、数字信号等。通过芯片222上的芯片接口2221，信号可以被输入至芯片222。芯片222可以对信号进行处理。通过芯片222上的芯片接口2221，经芯片222处理后的信号可以从芯片222输出至其他模块。
芯片222可以包括多个第一芯片接口。第二连接器225可以包括与该多个第一芯片接口对应的多个第二连接接口2251。
例如，芯片222可以包括第一芯片接口A。第二连接器225可以包括第二连接接口2251A。第一芯片封装结构220还可以包括电连接在第一芯片接口A与第二连接接口2251A之间的电连接线路。电连接线路例如可以包括设置在封装基板221上的线路。
在一个示例中，第二连接器225的第二连接接口2251与芯片222的第一芯片接口可以一对一地电连接。
在另一个示例中，第二连接器225的第二连接接口2251与芯片222的第一芯片接口可以多对一地电连接。例如，芯片222可以包括第一芯片接口A，第二连接器225可以包括第二连接接口2251A、第二连接接口2251B，第一芯片封装结构220还可以包括电连接线路A、电连接线路B，电连接线路A可以电连接在第一芯片接口A与第二连接接口2251A之间，电连接线路B可以电连接在第一芯片接口A与第二连接接口2251B之间。电连接线路A、电连接线路B例如可以包括设置在封装基板221上的线路。
在又一个示例中，第二连接器225的第二连接接口2251与芯片222的第一芯片接口可以一对多地电连接。例如，芯片222可以包括第一芯片接口A、第一芯片接口B，第二连接器225可以包括第二连接接口2251A。第二连接器225还可以包括电连接线路A、电连接线路C，电连接线路A可以电连接在第一芯片接口A与第二连接接口2251A之间，电连接线路C可以电连接在第一芯片接口B与第二连接接口2251A之间。电连接线路A、电连接线路C例如可以包括设置在封装基板221上的线路。
第二连接器225上的多个第二连接接口2251可以充当芯片封装结构的多个第一接口。也就是说，第一连接器230与第一芯片封装结构220的第一接口相连，可以通过第一连接器230与第二连接接口2251相连实现。第一连接器230的多个第一连接接口2301可以与第二连接器225的多个第二连接接口2251对应。多个第一连接接口2301与多个第二连接接口2251例如可以按照以下至少一种连接模式相连：一对多、多对一、一对一。一对多、多对一、一对一这三种连接模式可以分别参照上文中详细阐述的一对多、多对一、一对一的3种电连接模式，在此就不再详细赘述。
如图4、图5所示，第一连接器230的多个第一连接接口2301可以与第二连接器225的多个第二连接接口2251对应。多个第一连接接口2301与多个第二连接接口2251例如可以按照一对一、一对多、多对一等方式相连。每个第一连接接口2301与对应的一个或多个第二连接接口2251可以通过对应的一个或多个第一线缆331相连。第一线缆331的第二端可以插接在第二连接器225的第二连接接口2251上。
可选的，第一电路板组件21例如还可以包括第二芯片封装结构240。可选的，第二芯片封装结构240可以设置在第一电路板210上，并与第一电路板210电连接。如图4所示，第二芯片封装结构240与第一芯片封装结构220之间的信号可以通过多个第一线缆331、第一连接器230、第一电路板210传输。可选的，信号可以在传输路径上发生变换，例如由光信号转变为电信号，又如由电信号转变为光信号。来自第二芯片封装结构240的信号可以经第一电路板210、第一连接器230、第一线缆331、第二连接器225、封装基板221传输至芯片222。相应地，芯片222产生的信号可以经封装基板221、第二连接器225、第一线缆331、第一连接器230、第一电路板210传输至芯片222。可选的，第二芯片封装结构240的热膨胀系数可以与第一电路板210的热膨胀系数相近或相同。
图6示出了一种连接器810的示意性结构图。图6所示的连接器810例如可以是本申 请实施例提供的任一连接器。图6所示的线缆820例如可以是本申请实施例提供的任一线缆。
连接器810可以包括多个第一接口811和多个第二接口812。在连接器810内部，多个第一接口811可以与多个第二接口812可以按照以下至少一种连接模式相连：一对多、多对一、一对一。
第一接口811可以与线缆820相连。如图6中的(a)-(c)所示，线缆820与第一接口811例如可以通过压接、插接或焊接等方式相连。
第二接口812可以与封装基板或电路板例如通过一个或多个电连接件电连接。
如图6中的(a)所示，第二接口812可以从连接器810的靠近封装基板或电路板的一侧伸出，并通过焊料831与封装基板或电路板电连接。
如图6中的(b)所示，第二接口812可以从连接器810的垂直于封装基板或电路板的侧面伸出，并通过焊料831与封装基板或电路板电连接。
在图6中的(a)、(b)所示的示例中，连接在第二接口812与封装基板之间的，或者，连接在第二接口812与封装基板之间的一个或多个电连接件可以包括焊料831。在其他示例中，焊料831例如可以替代为导电胶等导电材料。
如图6中的(c)所示，封装基板或电路板上可以设置有插座832。插座832可以与封装基板或电路板通过焊料831电连接。第二接口812可以通过插座832与封装基板或电路板电连接。其中，第二接口812例如可以由导电弹片形成；导电弹片可以设置在连接器810的靠近封装基板或电路板的端面，并抵接在插座832上。在图6中的(c)所示的示例中，连接在第二接口812与封装基板之间的，或者，连接在第二接口812与封装基板之间的一个或多个电连接件可以包括连接在插座832与封装基板或电路板之间的焊料831、插座832。在其他示例中，导电弹片例如可以替代为焊料831、导电胶等导电材料。
在线缆820为光线缆820的情况下，第一接口811可以用于传输光信号，第二接口812可以用于传输电信号。连接器810可以具有光电转换功能。在线缆820为电线缆820的情况下，第一接口811、第二接口812均可以用于传输电信号。
为便于第一线缆331连接在第一连接器230和第二连接器225之间，第一芯片封装结构220的第二连接器225可以与第一连接器230之间的间距可以小于预设间距。下面结合图4、图7，阐述第一芯片封装结构220和第一电路板组件21之间的多种摆放形式。
假设空间中存在XYZ坐标系。Z轴方向可以相对于第一电路板210的厚度方向平行设置。第一电路板210的厚度方向可以是第一电路板210的多个导电层2211和多个绝缘层2212的堆叠方向。相对于Z轴方向垂直的平面可以为XY平面。第一电路板210可以相对于XY平面平行设置。第一电路板210的相对于XY平面平行设置的面可以用于设置第一电路板组件21的一个或多个部件。
在图4所示的示例中，第一芯片封装结构220的封装基板221可以相对于第一电路板210平行设置。封装基板221例如可以设置在第一电路板210所在的平面上。第一电路板210所在的平面可以是沿第一电路板210平行，且穿过第一电路板210的一个平面。封装基板221设置在第一电路板210所在的平面上，可以指封装基板221所在的平面与第一电路板210所在的平面为同一平面，其中封装基板221所在的平面可以相对于封装基板221平行设置，且封装基板221所在的平面可以穿过封装基板221。
如图4所示，第一电路板210在XY平面的投影区域可以为第一XY投影区域，第一芯片封装结构220在XY平面的投影区域为第二XY投影区域。第一XY投影区域可以与第二XY投影区域互不相连、互不交叉、互不重叠。在图4所示的示例中，第一线缆331在XY平面的投影区域可以连接在第一XY投影区域与第二XY投影区域之间。
在图7所示的示例中，第一芯片封装结构220的封装基板221可以相对于第一电路板210平行设置。封装基板221和第一电路板210可以沿垂直于第一电路板210的方向排列。垂直于第一电路板210的方向可以与第一连接器230的厚度方向平行设置。
如图7所示，第一连接器230在Z轴的投影范围为第一Z向投影范围，第一芯片封装结构220在Z轴的投影范围为第二Z向投影范围，第一Z向投影范围可以与第二Z向投影范围互不相连、互不交叉、互不重叠。在图4所示的示例中，第一线缆331在Z轴的投影范围可以连接在第一Z向投影范围与第二Z向投影范围之间。
图4、图7仅仅是对第一芯片封装结构220和第一电路板组件21之间的位置关系的两个示例。第一芯片封装结构220和第一电路板组件21还可以有其他摆放形式。其他摆放形式例如可以包括阶梯形摆放、桥形摆放等形式。第一芯片封装结构220和第一电路板组件21之间的位置关系不限于图4、图7所示的示例。
图8是本申请实施例提供的另一种电路板装配件20的示意性结构图。与图4所示的电路板装配件20类似，封装基板221的热膨胀系数可以与芯片222的热膨胀系数相同或相近。可选的，第二芯片封装结构240的热膨胀系数可以与第一电路板210的热膨胀系数相近或相同。
与图4所示的电路板装配件20不同，第一电路板组件21还可以包括第三连接器250，第三连接器250可以设置在第一电路板210上。第一芯片封装结构220还可以包括第四连接器226。第三连接器250与第四连接器226可以通过多个第二线缆332相连。
芯片222还可以包括多个第二芯片接口。第四连接器226可以包括与该多个第二芯片接口对应的多个第四连接接口2261。多个第二芯片接口与多个第四连接接口2261例如可以按照一对一、一对多、多对一等方式电连接。第四连接接口2261可以充当第一芯片封装结构220的至少部分接口。
第三连接器250可以包括与多个第四连接接口2261对应的多个第三连接接口2501。多个第四连接接口2261与多个第三连接接口2501例如可以按照一对一、一对多、多对一等方式相连。在图8所示的示例中，第三连接器250可以包括与多个第四连接接口2261一一对应的多个第三连接接口2501。该多个第三连接接口2501可以与多个第二线缆332一一对应。每个第三连接接口2501可以与对应的一个或多个第四连接接口2261通过对应的一个或多个第二线缆332相连。
假设芯片222可以包括300个芯片接口。第一电路板210和第一芯片封装结构220上设置的单个连接器的接口数量可能相对有限，例如一个连接器可以包括10～50个接口。为了和芯片接口数量匹配，第一芯片封装结构220例如可以配置6个具有50个接口的连接器；相应地，第一电路板210上也可以配置6个具有50个接口的连接器。通过在第一芯片封装结构220内配置多个连接器，有利于芯片接口被充分利用。
第一芯片封装结构220和第二芯片封装结构240之间的信号可以通过第一电路板210上的某个连接器传输。通过连接器标识，可以指示信号所经过的连接器。通过连接接口标 识，可以指示信号所经过的连接接口。
在一个示例中，第二芯片封装结构240与第一芯片封装结构220之间的信号可以通过第一电路板210、第一连接器230传输，或者可以通过第一电路板210、第三连接器250传输。连接接口标识例如可以对应第一连接器230的一个第一连接接口2301(即对应第二连接器225的一个第二连接接口2251)，或者第三连接器250的一个第三连接接口2501(即对应第四连接器226的一个第四连接接口2261)。
通过将连接接口标识与信号类型关联起来，可以有利于使信号可以相对准确地输入至相对应的连接接口。信号类型例如可以由关联模块、信号内容、信号属性等确定。关联模块例如可以是传输信号所经过的收/发模块。信号内容例如可以包括图像信号、音频信号、控制信号等。信号属性例如可以包括芯片222接收的信号，以及芯片222发送的信号。
在一个可能的示例中，连接接口标识可以与信号属性对应。即传输信号的模块可以根据信号属性确定连接接口标识。
例如，第一连接器230可以为输出连接器，第二连接器225可以为输入连接器；第三连接器250可以为输入连接器，第四连接器226可以为输出连接器。在第二芯片封装结构240向第一芯片封装结构220的芯片222发送信号A时，该信号A的信号属性可以是芯片222接收的信号。第二芯片封装结构240可以确定该信号A可以通过第一连接器230输出，并从第二连接器225输入至第一芯片封装结构220的芯片222。在第一芯片封装结构220的芯片222向第二芯片封装结构240发送信号B时，芯片222可以确定该信号B可以通过第四连接器226输出，并从第三连接器250输入至第二芯片封装结构240。
图9是本申请实施例提供的又一种电路板装配件20的示意性结构图。电路板装配件20可以包括第一电路板组件21、第二电路板组件31A、电路板组件31B。
第一电路板组件21可以包括第一电路板210、第一连接器230、第二芯片封装结构240。第一连接器230、第二芯片封装结构240可以设置在第一电路板210上。可选的，第二芯片封装结构240的热膨胀系数可以与第一电路板210的热膨胀系数相近或相同。
第二电路板组件31A可以包括第一电路板310A、第五连接器330A、第三芯片封装结构340A。第五连接器330A、第三芯片封装结构340A可以设置在第一电路板310A上。可选的，第三芯片封装结构340A的热膨胀系数可以与第一电路板310A的热膨胀系数相近或相同。
第二电路板组件31B可以包括第一电路板310B、第五连接器330B、第三芯片封装结构340B。第五连接器330B、第三芯片封装结构340B可以设置在第一电路板310B上。可选的，第三芯片封装结构340B的热膨胀系数可以与第一电路板310B的热膨胀系数相近或相同。
电路板装配件20还可以包括第一芯片封装结构220。第一芯片封装结构220可以包括芯片222、封装基板221、第二连接器225、第六连接器321A、第六连接器321B。第二连接器225、第六连接器321A、第六连接器321B均可以设置在封装基板221上。第二连接器225、第六连接器321A、第六连接器321B均可以与芯片222通过封装基板221电连接。与图4所示的电路板装配件20类似，封装基板221的热膨胀系数可以与芯片222的热膨胀系数相同或相近。
电路板装配件20还可以包括第一线缆331、第三线缆333A、第三线缆333B。第一线 缆331可以连接在第一连接器230和第二连接器225之间。第三线缆333A可以连接在第五连接器330A和第六连接器321A之间。第三线缆333B可以连接在第五连接器330B和第六连接器321B之间。
图9所示的电路板装配件20可以提供一种树状分布的模块架构。在其他示例中，电路板装配件20可以包括更多或更少的芯片封装结构，以及更多或更少的连接器。
在第二芯片封装结构240、第三芯片封装结构340A、第三芯片封装结构340B中的任一个向第一芯片封装结构220的芯片222发送信号时，由于既有的连接关系，芯片222接收信号时通常不会出现连接器冲突。
在第一芯片封装结构220的芯片222准备向第二芯片封装结构240、第三芯片封装结构340A、第三芯片封装结构340B中的任一个发送信号时，芯片222需要确定正确的连接器和/或连接接口，才可以使对应的第二芯片封装结构240可以接收到信号。芯片222例如可以根据信号的关联设备、信号内容、信号属性中的一个或多个，确定信号对应的连接器标识和/或接口标识。
在一个可能的示例中，第二芯片封装结构240例如可以为电源管理模块。第三芯片封装结构340A例如可以为音视频编解码模块。第三芯片封装结构340B例如可以为神经网络处理模块。第一芯片封装结构220例如可以为电子设备的中央处理模块。
由于第二芯片封装结构240、第三芯片封装结构340A、第三芯片封装结构340B可以分管电子设备的不同功能，第二芯片封装结构240、第三芯片封装结构340A、第三芯片封装结构340B分别传输的信号类型可以不同。第二芯片封装结构240(即电源管理模块)收发的信号例如可以为电源控制信号。第三芯片封装结构340A(音视频编码模块)收发的信号例如可以是音视频信号。第三芯片封装结构340B(神经网络处理模块)收发的信号例如可以是人工智能信号。芯片222可以根据信号内容，从多个连接器中确定与目标芯片封装结构(如第二芯片封装结构240、第三芯片封装结构340A、第三芯片封装结构340B中的任一个)对应的目标连接器。
在其他示例中，第二芯片封装结构240、第三芯片封装结构340A、第三芯片封装结构340B还可以是具有其他功能的芯片封装结构。
图10是本申请实施例提供的还一种电路板装配件20的示意性结构图。电路板装配件20可以包括第一电路板组件21、第三电路板组件41A、第三电路板组件41B、第三电路板组件41C。
第一电路板组件21可以包括第一电路板210、第一连接器230、第七连接器260A、第七连接器260B、第七连接器260C。第一连接器230、第七连接器260A、第七连接器260B、第七连接器260C均可以设置在第一电路板210上。第一连接器230与第七连接器260A可以通过第一电路板210电连接。第一连接器230与第七连接器260B可以通过第一电路板210电连接。第一连接器230与第七连接器260C可以通过第一电路板210电连接。
第三电路板组件41A可以包括第四电路板410A、第八连接器430A、第四芯片封装结构290A。第八连接器430A、第四芯片封装结构290A可以设置在第四电路板410A上。第八连接器430A可以包括多个第八连接接口4301A。可选的，第四芯片封装结构290A的热膨胀系数可以与第四电路板410A的热膨胀系数相近或相同。
第三电路板组件41B可以包括第四电路板410B、第八连接器430B、第四芯片封装结 构290B。第八连接器430B、第四芯片封装结构290B可以设置在第四电路板410B上。第八连接器430B可以包括多个第八连接接口4301B。可选的，第四芯片封装结构290B的热膨胀系数可以与第四电路板410B的热膨胀系数相近或相同。
第三电路板组件41C可以包括第四电路板410C、第八连接器430C、第四芯片封装结构290C。第八连接器430C、第四芯片封装结构290C可以设置在第四电路板410C上。第八连接器430C可以包括多个第八连接接口4301C。可选的，第四芯片封装结构290C的热膨胀系数可以与第四电路板410C的热膨胀系数相近或相同。
电路板装配件20还可以包括第一芯片封装结构220。第一芯片封装结构220可以包括芯片222、封装基板221、第二连接器225。第二连接器225可以设置在封装基板221上。第二连接器225可以与芯片222通过封装基板221电连接。第二连接器225可以包括多个第二连接接口2251。与图4所示的电路板装配件20类似，封装基板221的热膨胀系数可以与芯片222的热膨胀系数相同或相近。
第一连接器230可以包括与该多个第二连接接口2251对应的多个第一连接接口2301。第七连接器260A可以包括与该多个第八连接接口4301A对应的多个第七连接接口2601A。第七连接器260B可以包括与该多个第八连接接口4301B对应的多个第七连接接口2601B。第七连接器260C可以包括与该多个第八连接接口4301C对应的多个第七连接接口2601C。
电路板装配件20还可以包括多个第一线缆331、多个第四线缆334A、多个第四线缆334B、多个第四线缆334C。多个第一线缆331可以连接在第二连接器225和第一连接器230之间。每个第二连接接口2251与对应的一个或多个第一连接接口2301可以通过一个或多个第一线缆331相连。第四线缆334A可以连接在第八连接器430A和第七连接器260A之间。每个第八连接接口4301A与对应的一个或多个第七连接接口2601A可以通过一个或多个第四线缆334A相连。第四线缆334B可以连接在第八连接器430B和第二连接器225C之间。每个第八连接接口4301B与对应的一个或多个第七连接接口2601B可以通过一个或多个第四线缆334B相连。第四线缆334C可以连接在第八连接器430C和第二连接器225D之间。每个第八连接接口4301C与对应的一个或多个第七连接接口2601C可以通过一个或多个第四线缆334C相连。
图10所示的电路板装配件20可以提供一种树状分布的模块架构。在其他示例中，电路板装配件20可以包括更多或更少的芯片封装结构290，以及更多或更少的连接器230。
可选的，多个第一连接接口2301中的第一部分可以与第七连接器260A相连；多个第一连接接口2301中的第二部分可以与第七连接器260B相连；多个第一连接接口2301中的第三部分可以与第七连接器260C相连。该第一部分、该第二部分、该第三部分可以部分交叉，可以完全不同，也可以完全相同。在第四芯片封装结构290A、第四芯片封装结构290B、第四芯片封装结构290C中的任一个向第一芯片封装结构220的芯片222发送信号时，由于既有的连接关系，芯片222接收信号时不会出现连接器冲突。
在第一芯片封装结构220的芯片222准备向第四芯片封装结构290A、第四芯片封装结构290B、第四芯片封装结构290C中的任一个发送信号时，芯片222至少需要确定第一连接器230的正确连接器和/或接口，才可以使对应的芯片封装结构可以接收到信号。由于第四芯片封装结构290A、第四芯片封装结构290B、第四芯片封装结构290C可以分管 电子设备的不同功能，第四芯片封装结构290A、第四芯片封装结构290B、第四芯片封装结构290C分别传输的信号类型可以不同，例如信号的关联设备不同、信号内容、信号属性不同等。芯片222可以根据关联设备、信号内容、信号属性中的一个或多个，从多个连接接口中确定与目标芯片封装结构(如第四芯片封装结构290A、第四芯片封装结构290B、第四芯片封装结构290C中的任一个)对应的目标连接接口。
图11是本申请实施例提供的再一种电路板装配件20的示意性结构图。
电路板装配件20可以包括第一电路板组件21、第二电路板组件31、第三电路板组件41、第四电路板组件51。
第一电路板组件21可以包括第一电路板210、第二芯片封装结构240、第一连接器230、第七连接器260。第一连接器230、第七连接器260、第二芯片封装结构240均可以设置在第一电路板210上。第一连接器230、第七连接器260均可以与第二芯片封装结构240通过第一电路板210电连接。可选的，第二芯片封装结构240的热膨胀系数可以与第一电路板210的热膨胀系数相近或相同。
第二电路板组件31可以包括第三电路板310、第三芯片封装结构340、第五连接器330、第九连接器350、第十连接器360。第五连接器330、第九连接器350、第十连接器360、第三芯片封装结构340均可以设置在第三电路板310上。第五连接器330、第九连接器350、第十连接器360均可以与第三芯片封装结构340通过第三电路板310电连接。可选的，第三芯片封装结构340的热膨胀系数可以与第三电路板310的热膨胀系数相近或相同。
第三电路板组件41可以包括第四电路板410、第八连接器430A、第十一连接器351、第四芯片封装结构290。第八连接器430A、第十一连接器351、第四芯片封装结构290均可以设置在第四电路板410上，并与第四电路板410电连接。可选的，第四芯片封装结构290的热膨胀系数可以与第四电路板410的热膨胀系数相近或相同。
第四电路板组件51可以包括第五电路板510、第十二连接器361、第五芯片封装结构540。第十二连接器361、第五芯片封装结构540均可以设置在第五电路板510上，并与第五电路板510电连接。可选的，第五芯片封装结构540的热膨胀系数可以与第五电路板510的热膨胀系数相近或相同。
电路板装配件20还可以包括第一芯片封装结构220。第一芯片封装结构220可以包括芯片222、封装基板221、第二连接器225、第六连接器321。第二连接器225、第六连接器321均可以设置在封装基板221上。第二连接器225、第六连接器321均可以与芯片222通过封装基板221电连接。第二连接器225可以包括多个第二连接接口2251。第六连接器321可以包括多个第六连接接口3211。与图4所示的电路板装配件20类似，封装基板221的热膨胀系数可以与芯片222的热膨胀系数相同或相近。
下面介绍各个电路板组件之间的连接关系。
第一芯片封装结构220的第二连接器225可以与第一电路板210上的第一连接器230相连。第二连接器225可以包括多个第二连接接口2251。第一连接器230可以包括多个第一连接接口2301。多个第二连接接口2251可以与多个第一连接接口2301对应。电路板装配件20可以包括多个第一线缆331。该多个第一线缆331可以与多个第二连接接口2251对应。每个第二连接接口2251与对应的一个或多个第一连接接口2301可以通过对 应的一个或多个第一线缆331相连。
第一芯片封装结构220的第六连接器321可以与第三电路板310上的第五连接器330相连。第六连接器321可以包括多个第六连接接口3211。第五连接器330可以包括多个第五连接接口3301。多个第六连接接口3211可以与多个第五连接接口3301对应。电路板装配件20可以包括多个第三线缆333。该多个第三线缆333可以与多个第五连接接口3301对应。每个第五连接接口3301与对应的一个或多个第六连接接口3211可以通过对应的一个或多个第三线缆333相连。
第四电路板410上的第八连接器430可以与第一电路板210上的第七连接器260相连。第八连接器430可以包括多个第八连接接口4301。第七连接器260可以包括多个第七连接接口2601。多个第八连接接口4301可以与多个第七连接接口2601对应。电路板装配件20可以包括多个第四线缆334。该多个第四线缆334可以与多个第七连接接口2601对应。每个第七连接接口2601与对应的一个或多个第八连接接口4301可以通过对应的一个或多个第四线缆334相连。
第三电路板310上的第九连接器350可以与第四电路板410上的上的第十一连接器351相连。第九连接器350可以包括多个第九连接接口3501。第十一连接器351可以包括多个第十一连接接口3511。多个第九连接接口3501可以与多个第十一连接接口3511对应。电路板装配件20可以包括多个第五线缆335。该多个第五线缆335可以与多个第九连接接口3501对应。每个第九连接接口3501与对应的一个或多个第十一连接接口3511可以通过对应的一个或多个第五线缆335相连。
第三电路板310上的第十连接器360可以与第五电路板510上的第十二连接器361相连。第十连接器360可以包括多个第十连接接口3601。第十二连接器361可以包括多个第十二连接接口3611。多个第十连接接口3601可以与多个第十二连接接口3611对应。电路板装配件20可以包括多个第六线缆336。该多个第六线缆336可以与多个第十连接接口3601对应。每个第十连接接口3601与对应的一个或多个第十二连接接口3611可以通过对应的一个或多个第六线缆336相连。
可选的，第一电路板210还可以包括电连接在第一连接器230和第七连接器260之间的电连接线路A(图11未示出)。这可以使得芯片222和第四芯片封装结构290之间的信号可以绕过第一电路板210上的第二芯片封装结构240传输。
可选的，第三电路板310还可以包括电连接在第六连接器321和第五连接器330之间的电连接线路B(图11未示出)。这可以使得芯片222和第四芯片封装结构290之间的信号，以及芯片222和第五芯片封装结构540之间的信号可以绕过第三电路板310上的第三芯片封装结构340传输。
图11所示的电路板装配件20可以提供一种网状或图状分布的模块架构。在其他示例中，电路板装配件20可以包括更多或更少的芯片封装结构，以及更多或更少的连接器。第二芯片封装结构240和第三芯片封装结构340例如可以是第一芯片封装结构220的分布式预处理单元。来自第四芯片封装结构290或第五芯片封装结构540的数据可以经第二芯片封装结构240和/或第三芯片封装结构340预处理后传输至第一芯片封装结构220。
在第四芯片封装结构290、第五芯片封装结构540中的任一个向第一芯片封装结构220的芯片222发送信号时，或者，在第一芯片封装结构220的芯片222准备向第四芯片封装 结构290、第五芯片封装结构540中的任一个发送信号时，信号所经过的连接器和接口可以被提前确定。例如，如图11所示，第四芯片封装结构290发出的信号既可以经由第一电路板组件21传输至芯片222，也可以经由第二电路板组件31传输至芯片222。第五芯片封装结构540发出的信号既可以经由第二电路板组件31传输至芯片222，也可以经由第二电路板组件31、第三电路板组件41、第一电路板组件21传输至芯片222。信号传输所经过的接口可以根据信号类型确定。
芯片222发出的信号可以经由第一电路板组件21和/或第二电路板组件31传输至第四芯片封装结构290、第五芯片封装结构540。芯片222可以确定正确的连接器和/或正确接口，以使对应的芯片封装结构可以接收到信号。
在一个示例中，第四芯片封装结构290、第五芯片封装结构540可以分管电子设备的不同功能，第四芯片封装结构290、第五芯片封装结构540分别传输的信号类型可以不同。信号传输所经过的接口可以根据信号类型确定。例如信号的关联设备不同、信号内容不同、信号属性不同等。例如，在图11所示的示例中，芯片可以根据信号类型，确定与目标芯片封装结构(如第四芯片封装结构290、第五芯片封装结构540中的任一个)对应的多个连接接口。
在本申请实施例中，将芯片封装结构设置在电路板以外，有利于减少芯片封装结构对电路板的热变形影响。例如，有利于减小第一电路板承受的应力，提高第一电路板的机械稳定性；有利于减小第一电路板因温度而产生的变形量，有利于提升第一电路板的平整度。芯片封装结构内部多个器件的热膨胀系数可以尽可能相似，芯片封装结构内部多个器件的变形量可以相似，有利于提升芯片封装结构内部多个器件之间的连接稳定性。芯片封装结构的器件的热膨胀系数可以与芯片的热膨胀系数相似或相同，芯片的热膨胀系数通常较小，因此有利于使芯片封装结构在受热或遇冷变形时的变形量可以相对较小，芯片封装结构内部的电路板的平整度可以相对较高。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种电路板装配件，其特征在于，包括：
    第一电路板组件、第一芯片封装结构以及多个第一线缆，所述第一芯片封装结构设置在所述第一电路板组件以外，所述多个第一线缆用于在所述第一电路板组件与所述第一芯片封装结构之间传输信号；
    所述第一电路板组件包括：
    第一电路板；
    第一连接器，所述第一连接器设置在所述第一电路板上，并与所述第一电路板电连接，所述第一连接器包括多个第一连接接口；
    所述第一芯片封装结构包括：
    封装基板；
    第二连接器，所述第二连接器设置在所述封装基板上，所述第二连接器包括多个第二连接接口，所述多个第二连接接口与所述第一连接器的所述多个第一连接接口对应，每个所述第二连接接口与对应的一个或多个所述第一连接接口通过对应的一个或多个所述第一线缆相连；
    芯片，所述芯片设置在所述封装基板上，所述芯片与所述第二连接器通过所述封装基板电连接。
  2. 如权利要求所述的1电路板装配件，其特征在于，所述芯片的热膨胀系数与所述封装基板的热膨胀系数的差值小于5ppm/℃。
  3. 如权利要求1或2所述的电路板装配件，其特征在于，所述芯片的热膨胀系数为2～7ppm/℃，与所述封装基板的热膨胀系数为2～7ppm/℃。
  4. 如权利要求1至3中任一项所述的电路板装配件，其特征在于，所述芯片的热膨胀系数与所述第一电路板的热膨胀系数的差值大于5ppm/℃。
  5. 如权利要求1至4中任一项所述的电路板装配件，其特征在于，所述芯片为硅基芯片；所述封装基板包括层叠间隔设置的多个绝缘层、多个导电层，相邻两个所述绝缘层之间设置有一个所述导电层，相邻两个导电层之间设置有一个所述绝缘层，所述绝缘层的材料包括以下至少一种：陶瓷、玻璃、金刚石。
  6. 如权利要求1至5中任一项所述的电路板装配件，其特征在于，所述芯片包括多个第一芯片接口、多个第二芯片接口，每个所述第一芯片接口通过所述封装基板与对应的一个或多个所述第二连接接口电连接；
    所述第一电路板组件还包括：
    第三连接器，所述第三连接器设置在所述第一电路板上，并与所述第一电路板电连接，所述第三连接器包括多个第三连接接口；
    所述第一芯片封装结构还包括：
    第四连接器，所述第四连接器设置在所述封装基板上，所述第四连接器包括多个第四连接接口，每个所述第四连接接口通过所述封装基板与对应的一个或多个所述第二芯片接口电连接，所述多个第四连接接口与所述多个第三连接接口对应；
    所述电路板装配件还包括：
    多个第二线缆，所述多个第二线缆与所述多个第三连接接口对应，每个所述第三连接接口与对应的一个或多个所述第四连接接口通过对应的一个或多个所述第二线缆相连。
  7. 如权利要求1至6中任一项所述的电路板装配件，其特征在于，所述第一电路板组件还包括第二芯片封装结构，所述第二芯片封装结构设置在所述第一电路板上，所述第一芯片封装结构与所述第二芯片封装结构之间的信号通过所述第一电路板、所述第一连接器、所述多个第一线缆传输。
  8. 如权利要求7所述的电路板装配件，其特征在于，所述电路板装配件还包括第二电路板组件、多个第三线缆，所述多个第三线缆用于在所述第二电路板组件、所述第一芯片封装结构之间传输信号；
    所述第二电路板组件包括：
    第三电路板；
    第五连接器，所述第五连接器设置在所述第三电路板上，所述多个第五连接接口与所述多个第三线缆对应；
    第三芯片封装结构，所述第三芯片封装结构设置在所述第三电路板上，所述第三芯片封装结构与所述第五连接器通过所述第三电路板电连接；
    所述第一芯片封装结构还包括：
    第六连接器，所述第六连接器设置在所述封装基板上，所述第六连接器与所述芯片通过所述封装基板电连接，所述第六连接器包括多个第六连接接口，所述多个第六连接接口与所述第五连接器的所述多个第五连接接口对应，每个所述第六连接接口与对应的一个或多个所述第五连接接口通过对应的一个或多个所述第三线缆相连。
  9. 如权利要求8所述的电路板装配件，其特征在于，所述第三芯片封装结构的功能与所述第二芯片封装结构的功能不同。
  10. 如权利要求7至9中任一项所述的电路板装配件，其特征在于，所述第二芯片封装结构为所述第一芯片封装结构的预处理单元。
  11. 如权利要求1至10中任一项所述的电路板装配件，其特征在于，所述第一电路板组件还包括：
    第七连接器，所述第七连接器设置在所述第一电路板上，所述第七连接器与所述第一连接器通过所述第一电路板电连接，所述第七连接器包括多个第七连接接口；
    所述电路板装配件还包括第三电路板组件和多个第四线缆，所述多个第四线缆用于在所述第三电路板组件、所述第一电路板组件之间传输信号，所述多个第四线缆与所述多个第七连接接口对应；
    所述第三电路板组件包括：
    第四电路板；
    第八连接器，所述第八连接器设置在所述第四电路板上，所述第八连接器包括与所述多个第七连接接口对应的多个第八连接接口，每个所述第八连接接口与对应的一个或多个所述第七连接接口通过对应的一个或多个所述第四线缆相连；
    第四芯片封装结构，所述第四芯片封装结构设置在所述第四电路板上，所述第四芯片封装结构与所述第八连接器通过所述第四电路板电连接。
  12. 如权利要求1至11中任一项所述的电路板装配件，其特征在于，所述第一电路板相对于所述封装基板平行设置，
    所述第一电路板和所述封装基板在垂直于所述第一电路板的方向上排列；
    或者，
    所述封装基板设置在所述第一电路板所在的平面上。
  13. 如权利要求1至12中任一项所述的电路板装配件，其特征在于，所述芯片收发的信号所经过的连接器和/或连接接口由所述信号的信号类型确定。
  14. 如权利要求1至13中任一项所述的电路板装配件，其特征在于，所述信号类型包括以下至少一项关联模块、信号内容、信号属性。
  15. 如权利要求1至14中任一项所述的电路板装配件，其特征在于，所述第一芯片封装结构为以下任一种：中央处理器，应用处理器，调制解调处理器，图形处理器，图像信号处理器，视频编解码器，数字信号处理器，基带处理器，神经网络处理器，生物特征识别模组，存储器，电源管理单元，光芯片。
  16. 如权利要求1至15中任一项所述的电路板装配件，其特征在于，所述第一线缆为柔性线缆。
  17. 一种电子设备，其特征在于，包括壳体、如权利要求1至16中任一项所述的电路板装配件，所述电路板装配件收容于所述壳体内。
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