WO2022217635A1 - 一种阵列基板及其制备方法、显示装置 - Google Patents

一种阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022217635A1
WO2022217635A1 PCT/CN2021/088843 CN2021088843W WO2022217635A1 WO 2022217635 A1 WO2022217635 A1 WO 2022217635A1 CN 2021088843 W CN2021088843 W CN 2021088843W WO 2022217635 A1 WO2022217635 A1 WO 2022217635A1
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Prior art keywords
layer
gate
thin film
insulating layer
disposed
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PCT/CN2021/088843
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English (en)
French (fr)
Inventor
白丹
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武汉华星光电技术有限公司
武汉华星光电半导体显示技术有限公司
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Priority to US17/293,792 priority Critical patent/US11973084B2/en
Publication of WO2022217635A1 publication Critical patent/WO2022217635A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Definitions

  • the present application relates to the field of display, and in particular, to an array substrate, a preparation method thereof, and a display device.
  • LTPO Low Temperature Polycrystalline Oxide
  • IGZO oxide TFTs
  • the present invention provides an array substrate, a preparation method thereof, and a display device to solve the problem that the diffusion of hydrogen in the low-temperature polycrystalline oxide technology in the prior art causes the oxide conductor layer to be conductorized, resulting in the failure of the array substrate. technical issues.
  • the present invention provides an array substrate, comprising: a substrate; a plurality of first thin film transistors, which are arranged on the substrate, and the first thin film transistors include a first gate layer and a second thin film transistor. Two gate layers, the second gate layer is disposed on the side of the first gate layer away from the substrate; a plurality of second thin film transistors are disposed on the substrate, and the second thin film transistors include a third gate layer; a gate insulating layer, disposed between the first gate layer and the second gate layer, and a surface of the third gate layer close to the substrate, the The gate insulating layer is made of silicon nitride material.
  • the array substrate further includes a first insulating layer, a first dielectric layer, a second insulating layer, a second dielectric layer, and a passivation layer that are stacked in sequence.
  • the first thin film transistor further includes: a first active layer disposed on the substrate, and the first insulating layer covers the first active layer;
  • the first gate layer is arranged on a side surface of the first insulating layer away from the substrate;
  • the gate insulating layer is arranged on a side surface of the first gate layer away from the first insulating layer ;
  • the second gate layer is arranged on the side surface of the first gate layer away from the gate insulating layer;
  • the first dielectric layer is arranged on the side of the first insulating layer away from the substrate surface, and covers the first gate layer, the gate insulating layer and the second gate layer;
  • the first source and drain electrodes are arranged on the second dielectric layer away from the second insulating layer one side surface and connected to the first active layer.
  • the second thin film transistor further includes: a metal layer disposed on the substrate and disposed in the same layer as the first active layer; the third gate electrode layer is arranged on the gate insulating layer; the second active layer is arranged on the side surface of the first dielectric layer away from the first insulating layer, and the second insulating layer covers the second active layer.
  • a source layer a source layer; a fourth gate layer, disposed on a surface of the second insulating layer away from the first dielectric layer, the second dielectric layer covers the fourth gate layer; a second source-drain A pole is arranged on a surface of the second dielectric layer away from the second insulating layer, and is connected to the second active layer and the metal layer.
  • the materials of the second gate layer and the third gate layer are molybdenum-titanium alloys.
  • the array substrate further includes: a first flat layer disposed on a surface of the passivation layer away from the second dielectric layer; pixel electrodes disposed on the passivation layer on the first flat layer and partially penetrated through the first flat layer and connected to the first source-drain electrode; the second flat layer is disposed on a surface of the first flat layer away from the passivation layer, and covering the pixel electrode; a pixel definition layer, disposed on the side surface of the second flat layer away from the first flat layer, the pixel definition layer is provided with pixel openings corresponding to the pixel electrode; the light emitting layer, It is arranged in the pixel opening and connected to the pixel electrode.
  • the array substrate includes a display area and a bending area
  • the first thin film transistor and the second thin film transistor are arranged in the display area, the substrate, the first insulating layer, the first dielectric layer, the second insulating layer, the second dielectric layer and the passivation layer extend from the display area into the bending area; in An opening is formed in the bending region, and the opening penetrates the passivation layer, the second dielectric layer, the second insulating layer, the first dielectric layer, and the first insulating layer layer and part of the substrate, the first planar layer fills the opening.
  • an embodiment of the present application also provides a method for preparing an array substrate, including the following steps:
  • a substrate is provided; a plurality of first thin film transistors and a plurality of second thin film transistors are prepared on the substrate, wherein the preparation steps of the first thin film transistor and the second thin film transistor include: preparing a first thin film transistor of the first thin film transistor gate layer; prepare a layer of gate insulating material on the first gate layer, the gate insulating material is silicon nitride material; etch on the gate insulating material and the first insulating layer a contact hole, the contact hole corresponds to the first active layer and the metal layer, and is annealed at a temperature of 350 degrees Celsius to 400 degrees Celsius; the second thin film transistor of the first thin film transistor is prepared on the gate insulating material A gate layer and a third gate layer of the second thin film transistor; using the second gate layer and the third gate layer to self-align the gate insulating material to obtain a gate insulating layer .
  • the following step is further included: preparing a layer of semiconductor material on the substrate, and patterning to form a layer of semiconductor material. the first active layer of the first thin film transistor and the metal layer of the second thin film transistor; a first insulating layer is prepared on the substrate, and the first insulating layer covers the first active layer and the the metal layer.
  • the step of obtaining the gate insulating layer further includes the following step: preparing a first dielectric layer on the first insulating layer, the first dielectric layer covering the first gate electrode layer, the gate insulating layer, the second gate electrode layer and the third gate electrode layer; the second gate electrode layer of the second thin film transistor is prepared on the first dielectric layer an active layer; a second insulating layer is prepared on the first dielectric layer, the second insulating layer covers the second active layer; a fourth gate layer is prepared on the second insulating layer , the fourth gate layer corresponds to the third gate layer; a second dielectric layer is prepared on the second insulating layer, and the second dielectric layer covers the fourth gate layer; Several first via holes and second via holes are etched on the second dielectric layer, the second insulating layer, the first dielectric layer and the first insulating layer, the first via holes Corresponding to the first active layer of the first thin film transistor, the second via hole corresponds to the metal layer and the second active
  • an embodiment of the present application further provides a display device including a color filter substrate, the above-mentioned array substrate and a backlight module.
  • the beneficial effect of the embodiments of the present application is that an array substrate, a preparation method thereof, and a display device of the embodiments of the present application use a silicon nitride material with a relatively high hydrogen content as the gate insulating layer, which can prevent polysilicon under high temperature conditions.
  • the active layer of the material is subjected to hydrogen supplementation, and the gate insulating layer is arranged under the active layer of the oxide thin film transistor, and is completely covered by the gate layer of the oxide thin film transistor, which will not cause the active layer in the oxide thin film transistor. Therefore, while improving the performance of the low temperature polysilicon thin film transistor, it will not cause adverse effects of the oxide thin film transistor, and improve the device performance of the oxide thin film transistor and the polysilicon thin film transistor.
  • FIG. 1 is a schematic structural diagram of a display device in an embodiment
  • FIG. 2 is a schematic structural diagram of an array substrate in an embodiment
  • FIG. 3 is a schematic structural diagram of the array substrate after step S201 in the embodiment.
  • FIG. 4 is a schematic structural diagram of the array substrate after step S204 in the embodiment.
  • FIG. 5 is a schematic structural diagram of the array substrate after step S205 in the embodiment.
  • FIG. 6 is a schematic structural diagram of the array substrate after step S213 in the embodiment.
  • FIG. 7 is a schematic diagram of the structure of the array substrate after step S4 in the embodiment.
  • the second thin film transistor 300 the first insulating layer 410;
  • the first pixel electrode 600 the second pixel electrode 700;
  • the first active layer 210 the first gate layer 220;
  • the second via hole 413 The second via hole 413 .
  • the display device of the present invention includes an array substrate 10 and a color filter substrate 20.
  • the array substrate 10 includes a substrate 100, a first thin film transistor 200, a second Thin film transistor 300, first insulating layer 410, first dielectric layer 420, second insulating layer 430, second dielectric layer 440, passivation layer 450, first planarization layer 460, gate insulating layer 500, first pixel The electrode 600 , the second pixel electrode 700 , the second flat layer 470 , the blocking wall 480 and the light emitting layer 800 .
  • the substrate 100 is a double-layer flexible substrate, and includes a first flexible layer 110 , a first buffer layer 120 , a second flexible layer 130 , a second buffer layer 140 and a barrier layer 150 that are stacked.
  • the first thin film transistor 200 and the second thin film transistor 300 are disposed on a surface of the barrier layer 150 away from the second buffer layer 140 , and the first thin film transistor 200 and the second thin film transistor 300 are adjacent to each other arranged and insulated from each other, wherein the first thin film transistor 200 is a low temperature polysilicon thin film transistor, the first thin film transistor 200 is a driving thin film transistor, and plays the role of driving a pixel circuit.
  • the second thin film transistor 300 is an oxide thin film transistor, and the second thin film transistor 300 is a switching thin film transistor, which plays the role of controlling the signal switch of the pixel circuit.
  • the first thin film transistor 200 includes a first active layer 210 , a first gate layer 220 , a second gate layer 230 and a first source-drain electrode 240 that are stacked.
  • the second thin film transistor 300 includes a stacked metal layer 301 , a third gate layer 310 , a second active layer 320 , a fourth gate layer 330 and a second source-drain electrode 340 .
  • the first active layer 210 is made of low temperature polysilicon technology (Low Temperature Polysilicon). Poly-silicon) After uniformly irradiating amorphous silicon with laser light, the amorphous silicon absorbs internal atoms and undergoes energy level transitions and then forms into a polycrystalline structure. The use of low-temperature polysilicon technology can greatly increase the electrons of the first thin film transistor 200. mobility, so that the display device has higher resolution, faster response speed and higher brightness.
  • Low Temperature Polysilicon Low Temperature Polysilicon
  • the first insulating layer 410 covers the first active layer 210, and the material of the first insulating layer 410 is silicon oxide material, which has the technical effect of isolating water and oxygen, effectively preventing the first active layer 210 from being damaged. Water oxygen corrosion.
  • the first gate layer 220 is disposed on the upper surface of the first insulating layer 410 .
  • the material of the first gate layer 220 is a metal material, and the metal material includes molybdenum (Mo), aluminum (Al), Copper (Cu), titanium (Ti), etc., or alloys, or multilayer thin film structures.
  • the thickness of the first gate layer 220 is 2000 angstroms ⁇ 8000 angstroms.
  • the single-gate thin-film transistor Since the single-gate thin-film transistor has weak control over the carriers of the active layer, the carrier mobility is not high and the threshold voltage drifts, which in turn leads to poor electrical performance of the driving circuit on the array substrate. Stablize.
  • both the first thin film transistor 200 and the second thin film transistor 300 adopt a double gate structure, and by applying electrical signals to the double gate layers at the same time, the first thin film transistor 200 can be greatly improved. and the carrier mobility of the second thin film transistor 300, solve the threshold voltage drift problem of the first thin film transistor 200 and the second thin film transistor 300, and achieve the effect of improving the electrical performance stability of the thin film transistor, and then The stability of the electrical performance of the driving circuit on the array substrate is improved.
  • a gate insulating layer is generally added between the two gates.
  • the material of the gate insulating layer 500 is silicon nitride material.
  • the silicon nitride material has a relatively high hydrogen content, can supply hydrogen under high temperature conditions, and can perform hydrogen supplementation on the first active layer 210 prepared by using low temperature polysilicon technology, so as to meet the requirements of low temperature polysilicon technology and ensure that the first active layer 210 has a high hydrogen content. performance of the source layer 210 .
  • the second thin film transistor 300 is an oxide thin film transistor, and the second active layer 320 is made of an oxide conductor material.
  • the material of the second active layer 320 is indium gallium zinc oxide
  • the indium gallium zinc oxide material is sensitive to the surrounding atmosphere, such as hydrogen, oxygen, water, etc., the diffusion of hydrogen into the channel of the second active layer 320 will lead to the conduction of the indium gallium zinc oxide, and the intrusion of water and oxygen will cause The threshold voltage of the second thin film transistor 300 is shifted to cause TFT failure.
  • the second thin film transistor 300 has a The third gate layer 310 and the second gate layer 230 of the first thin film transistor 200 are provided in the same layer, and the gate insulating layer 500 is provided on the second gate layer 230 and the third gate layer 310 , and is completely covered by the second gate layer 230 and the third gate layer 310 .
  • the first dielectric layer 420 is disposed on the upper surface of the first insulating layer 410 , and the first dielectric layer 420 covers the first gate layer 220 , the gate insulating layer 500 , and the first gate layer 220 .
  • the first dielectric layer 420 is an interlayer insulating layer, and the material of the first dielectric layer 420 is an inorganic material, and the inorganic material includes silicon oxide or silicon nitride or a multi-layer thin film structure. Insulation to prevent circuit short circuit.
  • the thickness of the first dielectric layer 420 is 2,000 angstroms to 10,000 angstroms.
  • the second active layer 320 is disposed on the upper surface of the first dielectric layer 420 , the second insulating layer 430 covers the second active layer 320 , and the second insulating layer 430 is connected to the first dielectric layer 420 .
  • the material and function of an insulating layer 410 are similar, and both have the technical effect of isolating water and oxygen.
  • the fourth gate layer 330 is disposed on the upper surface of the second insulating layer 430 and is disposed opposite to the third gate layer 310 . 330 simultaneously applies an electrical signal, which can greatly improve the carrier mobility of the second thin film transistor 300, solve the problem of threshold voltage drift of the second thin film transistor 300, and achieve the effect of improving the electrical performance stability of the thin film transistor, Further, the stability of the electrical performance of the driving circuit on the array substrate is improved.
  • the second dielectric layer 440 is disposed on the upper surface of the second insulating layer 430 and covers the fourth gate layer 330 .
  • the material and function are the same, and both play an insulating role to prevent short circuits.
  • the first source-drain electrode 240 and the second source-drain electrode 340 are disposed on the upper surface of the second dielectric layer 440 , the first source-drain electrode 240 corresponds to the first active layer 210 , and Parts of the second dielectric layer 440 , the second insulating layer 430 , the first dielectric layer 420 , and the first insulating layer 410 are connected to the first active layer 210 .
  • the second source-drain electrode 340 corresponds to the second active layer 320 and partially penetrates the second dielectric layer 440 and the second insulating layer 430 and is connected to the second active layer 320 .
  • the metal layer 301 is disposed on the upper surface of the substrate 100 , and is disposed in the same layer as the first active layer 210 , the metal layer 301 is a conductorized semiconductor layer, and the second source-drain electrode 340 is partially
  • the second dielectric layer 440, the second insulating layer 430, the first dielectric layer 420, and the first insulating layer 410 are connected to the metal layer 301 to avoid Schottky contact strips adverse effects.
  • the passivation layer 450 is disposed on the upper surface of the second dielectric layer 440 , the material of the passivation layer 450 includes silicon oxide material, and the thickness of the passivation layer 450 is 1000 angstroms to 5000 angstroms Meter.
  • the passivation layer 450 plays a role of insulating and isolating external water and oxygen.
  • the array substrate 10 includes a display area 101 and a bending area 102 disposed under the display area 101 , the first thin film transistor 200 , the second thin film transistor 300 and the gate insulation
  • the layer 500 is disposed in the display area 101, the substrate 100, the first insulating layer 410, the first dielectric layer 420, the second insulating layer 430, the second dielectric layer 440,
  • the passivation layer 450 , the first flat layer 460 , the second flat layer 470 and the blocking wall 480 extend from the display area 101 to the bending area 102 .
  • An opening 1021 is formed in the bending region 102, and the opening 1021 penetrates through the passivation layer 450, the second dielectric layer 440, the second insulating layer 430, and the first dielectric layer 420 , the first insulating layer 410 and part of the substrate 100 .
  • the first flat layer 460 is disposed on the upper surface of the passivation layer 450 and extends from the display area 101 to the bending area 102 , and the first flat layer 460 fills the opening 1021 .
  • the first flat layer 460 is made of inorganic material with high toughness, which effectively avoids the fracture problem caused by the bending stress when the bending region 102 is bent, and improves the service life of the array substrate 10 .
  • the first pixel electrode 600 is disposed on the upper surface of the first flat layer 460, the first pixel electrode 600 corresponds to the first thin film transistor 200, and penetrates through the first flat layer 460 and the passivation
  • the layer 450 is connected to the first source-drain electrode 240 .
  • a plurality of metal traces are also provided on the upper surface of the first flat layer 460 , and the metal traces are arranged on the openings. above the hole.
  • the second flat layer 470 is disposed on the upper surface of the first flat layer 460 and covers the first pixel electrode 600 .
  • the second pixel electrode 700 is disposed on the upper surface of the second flat layer 470 , the second pixel electrode 700 corresponds to the first pixel electrode 600 and partially penetrates the second flat layer 470 and is connected to the The first pixel electrode 600 . In order to realize the electrical signal transmission between the first pixel electrode 600 and the second pixel electrode 700 .
  • the blocking wall 480 is disposed on the upper surface of the second flat layer 470 , the blocking wall 480 is provided with a pixel opening corresponding to the second pixel electrode 700 , and the light emitting layer 800 is disposed in the pixel opening inside, and is electrically connected to the second pixel electrode 700 .
  • this embodiment also provides a method for preparing the above-mentioned array substrate 10 , and the specific steps are as follows:
  • the substrate 100 is a double-layer flexible substrate, including a first flexible layer 110 , a first buffer layer 120 , a second flexible layer 130 , a second buffer layer 140 and a barrier layer 150 arranged in layers.
  • a layer of semiconductor material is prepared on the substrate 100, and after patterning, the first active layer 210 of the first thin film transistor 200 and the metal layer 301 of the second thin film transistor are formed.
  • a first insulating layer 410 is prepared on the substrate 100 , and the first insulating layer 410 covers the first active layer 210 and the metal layer 301 .
  • a layer of gate material is prepared on the upper surface of the first insulating layer 410, and the first gate layer 220 of the first thin film transistor 200 is formed after patterning.
  • a layer of gate insulating material is prepared on the first gate layer 220, and the gate insulating material is a silicon nitride material.
  • the gate insulating material is annealed at a temperature of 350 degrees Celsius to 400 degrees Celsius, and the hydrogen in the gate insulating material is detached at high temperature, and the first contact hole 411 is used to anneal the gate insulating material.
  • the first active layer 210 and the metal layer 301 are filled with hydrogen, and the gate material and the first insulating layer 410 are etched in the bending region 102 while the first contact hole 411 is etched.
  • a layer of gate material is prepared on the gate insulating material, and after patterning, the second gate layer 230 of the first thin film transistor and the third gate layer 310 of the second thin film transistor are formed.
  • a first dielectric layer 420 is prepared on the first insulating layer 410, and the first dielectric layer 420 covers the first gate layer 220, the gate insulating layer 500, and the second gate electrode layer 230 and the third gate layer 310 .
  • a second active layer 320 of the second thin film transistor 300 is prepared on the first dielectric layer 420 , and the second active layer 320 corresponds to the third gate layer 310 .
  • a second insulating layer 430 is prepared on the first dielectric layer 420 , and the second insulating layer 430 covers the second active layer 320 .
  • a fourth gate layer 330 is prepared on the second insulating layer 430 , and the fourth gate layer 330 corresponds to the third gate layer 310 .
  • a second dielectric layer 440 is prepared on the second insulating layer 430 , and the second dielectric layer 440 covers the fourth gate layer 330 .
  • the first via hole 412 corresponds to the first active layer 210 of the first thin film transistor, and coincides with the first contact hole 411
  • the second via hole 413 corresponds to the The metal layer 301 and the second active layer 320 of the second thin film transistor are described.
  • a passivation layer 450 is formed on the upper surface of the second dielectric layer 440 , and the passivation layer 450 covers the first source-drain electrodes 240 and the second source-drain electrodes 340 .
  • a first flat layer 460 is formed on the upper surface of the passivation layer, and the first flat layer 460 extends to the bending region 102 and fills the opening 1021 .
  • the beneficial effect of this embodiment is that, in the array substrate, the preparation method thereof, and the display device in this embodiment, a silicon nitride material with a relatively high hydrogen content is used as the gate insulating layer, and under high temperature conditions, the polysilicon material can be affected.
  • the source layer is filled with hydrogen, and the gate insulating layer is arranged under the active layer of the oxide thin film transistor, and is completely covered by the gate layer of the oxide thin film transistor, which will not cause conduction of the active layer in the oxide thin film transistor. Therefore, while improving the performance of the low-temperature polysilicon thin film transistor, it will not cause adverse effects of the oxide thin film transistor, and improve the device performance of the oxide thin film transistor and the polysilicon thin film transistor.

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Abstract

本发明公开了一种阵列基板及其制备方法、显示装置，所述阵列基板包括：基板；多个第一薄膜晶体管，所述第一薄膜晶体管包括第一栅极层和第二栅极层；多个第二薄膜晶体管，第二薄膜晶体管包括第三栅极层；栅极绝缘层，设于第一栅极层和第二栅极层之间，以及第三栅极层靠近所述基板的一侧表面，栅极绝缘层为氮化硅材料。

Description

一种阵列基板及其制备方法、显示装置 技术领域
本申请涉及显示领域，具体涉及一种阵列基板及其制备方法、显示装置。
 背景技术
当前，市场对长续航产品的需求越来越多，LTPO（Low Temperature Polycrystalline Oxide，即低温多晶氧化物）技术作为一种低功耗的显示技术被业界广泛关注。LTPO技术结合了LTPS（低温多晶硅）TFT和氧化物TFT（IGZO，铟镓锌氧化物），与目前使用的LTPS背板相比，LTPO可以降低约5-15%的功耗。
 技术问题
为了解决上述技术问题，本发明提供了一种阵列基板及其制备方法、显示装置用以解决现有技术中低温多晶氧化物技术中氢扩散导致氧化物导体层被导体化，导致阵列基板失效的技术问题。
 技术解决方案
解决上述技术问题的技术方案是：本发明提供了一种阵列基板，包括：基板；多个第一薄膜晶体管，设于所述基板上，所述第一薄膜晶体管包括第一栅极层和第二栅极层，所述第二栅极层设于所述第一栅极层远离所述基板的一侧；多个第二薄膜晶体管，设于所述基板上，所述第二薄膜晶体管包括第三栅极层；栅极绝缘层，设于所述第一栅极层和所述第二栅极层之间，以及所述第三栅极层靠近所述基板的一侧表面，所述栅极绝缘层为氮化硅材料。
可选的，在本申请的一些实施例中，阵列基板还包括依次叠层设置的第一绝缘层、第一介电层、第二绝缘层、第二介电层以及钝化层。
可选的，在本申请的一些实施例中，所述第一薄膜晶体管还包括：第一有源层，设于所述基板上，所述第一绝缘层覆盖所述第一有源层；所述第一栅极层设于所述第一绝缘层远离所述基板的一侧表面；所述栅极绝缘层设于所述第一栅极层远离所述第一绝缘层的一侧表面；第二栅极层，设于所述第一栅极层远离所述栅极绝缘层的一侧表面；所述第一介电层设于所述第一绝缘层远离所述基板的一侧表面，且覆盖所述第一栅极层、所述栅极绝缘层和所述第二栅极层；第一源漏电极，设于所述第二介电层远离所述第二绝缘层的一侧表面，并连接至所述第一有源层。
可选的，在本申请的一些实施例中，所述第二薄膜晶体管还包括：金属层，设于所述基板上，与所述第一有源层同层设置；所述第三栅极层设于所述栅极绝缘层上；第二有源层，设于所述第一介电层远离所述第一绝缘层的一侧表面，所述第二绝缘层覆盖所述第二有源层；第四栅极层，设于所述第二绝缘层远离所述第一介电层的一侧表面，所述第二介电层覆盖所述第四栅极层；第二源漏电极，设于所述第二介电层远离所述第二绝缘层的一侧表面，并连接至所述第二有源层和所述金属层。
可选的，在本申请的一些实施例中，所述第二栅极层和所述第三栅极层的材料为钼钛合金。
可选的，在本申请的一些实施例中，阵列基板还包括：第一平坦层，设于所述钝化层远离所述第二介电层的一侧表面；像素电极，设于所述第一平坦层上，且部分贯穿所述第一平坦层连接至所述第一源漏电极；第二平坦层，设于所述第一平坦层远离所述钝化层的一侧表面，且覆盖所述像素电极；像素定义层，设于所述第二平坦层远离所述第一平坦层的一侧表面，所述像素定义层对应所述像素电极处设有像素开孔；发光层，设于所述像素开孔内，且连接至所述像素电极。
可选的，在本申请的一些实施例中，所述阵列基板包括显示区和弯折区，所述第一薄膜晶体管和所述第二薄膜晶体管设于所述显示区中，所述基板、所述第一绝缘层、所述第一介电层、所述第二绝缘层、所述第二介电层以及所述钝化层从所述显示区延伸至所述弯折区中；在所述弯折区中设有一开孔，所述开孔贯穿所述钝化层、所述第二介电层、所述第二绝缘层、所述第一介电层、所述第一绝缘层以及部分所述基板，所述第一平坦层填充所述开孔。
相应的，本申请实施例还提供一种阵列基板的制备方法，包括以下步骤：
提供一基板；在所述基板上制备若干第一薄膜晶体管和若干第二薄膜晶体管，其中，所述第一薄膜晶体管和第二薄膜晶体管的制备步骤包括：制备所述第一薄膜晶体管的第一栅极层；在所述第一栅极层上制备一层栅极绝缘材料，所述栅极绝缘材料为氮化硅材料；在所述栅极绝缘材料和所述第一绝缘层上刻蚀接触孔，所述接触孔对应所述第一有源层和所述金属层，采用350摄氏度～400摄氏度的温度进行退火；在所述栅极绝缘材料上制备所述第一薄膜晶体管的第二栅极层和所述第二薄膜晶体管的第三栅极层；利用所述第二栅极层和所述第三栅极层自对准刻蚀所述栅极绝缘材料，获得栅极绝缘层。
可选的，在本申请的一些实施例中，所述第一薄膜晶体管的第一栅极层的制备步骤之前还包括以下步骤：在所述基板上制备一层半导体材料，图案化后形成所述第一薄膜晶体管的第一有源层和所述第二薄膜晶体管的金属层；在所述基板上制备一层第一绝缘层，所述第一绝缘层覆盖所述第一有源层和所述金属层。
可选的，在本申请的一些实施例中，所述获得栅极绝缘层步骤之后还包括以下步骤：在所述第一绝缘层上制备第一介电层，所述第一介电层覆盖所述第一栅极层、所述栅极绝缘层、所述第二栅极层和所述第三栅极层；在所述第一介电层上制备所述第二薄膜晶体管的第二有源层；在所述第一介电层上制备一层第二绝缘层，所述第二绝缘层覆盖所述第二有源层；在所述第二绝缘层上制备第四栅极层，所述第四栅极层与所述第三栅极层相对应；在所述第二绝缘层上制备第二介电层，所述第二介电层覆盖所述第四栅极层；在所述第二介电层、所述第二绝缘层、所述第一介电层和所述第一绝缘层上刻蚀若干第一过孔和第二过孔，所述第一过孔对应所述第一薄膜晶体管的第一有源层，所述第二过孔对应所述第二薄膜晶体管的金属层以及第二有源层；在所述第二介电层上制备第一源漏电极以及第二源漏电极，所述第一源漏电极穿过所述第一过孔连接至所述第一有源层，所述第二源漏电极穿过所述第二过孔连接至所述金属层和所述第二有源层。
相应的，本申请实施例还提供一种显示装置，包括彩膜基板、上述阵列基板和背光模组。
 有益效果
本申请实施例的有益效果在于，本申请实施例的一种阵列基板及其制备方法、显示装置，采用含氢量较高的氮化硅材料作为栅极绝缘层，在高温条件下能够对多晶硅材料的有源层进行补氢，且栅极绝缘层设于氧化物薄膜晶体管的有源层的下方，被氧化物薄膜晶体管的栅极层完全覆盖，不会造成氧化物薄膜晶体管中有源层的导体化，从而在提升低温多晶硅薄膜晶体管性能的同时，不会造成氧化物薄膜晶体管的不良影响，提升了氧化物薄膜晶体管和多晶硅薄膜晶体管的器件性能。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1是实施例中的显示装置结构示意图；
图2是实施例中的阵列基板结构示意图；
图3是实施例中步骤S201之后的阵列基板结构示意图；
图4是实施例中步骤S204之后的阵列基板结构示意图；
图5是实施例中步骤S205之后的阵列基板结构示意图；
图6是实施例中步骤S213之后的阵列基板结构示意图；
图7是实施例中步骤S4之后的阵列基板结构示意图。
图中标号如下：
阵列基板10；彩膜基板20；
显示区101；弯折区102；
基板100；第一薄膜晶体管200；
第二薄膜晶体管300；第一绝缘层410；
第一介电层420；第二绝缘层430；
第二介电层440；钝化层450；
第一平坦层460；栅极绝缘层500；
第一像素电极600；第二像素电极700；
第二平坦层470；挡墙480；
发光层800；第一柔性层110；
第一缓冲层120；第二柔性层130；
第二缓冲层140；阻隔层150；
第一有源层210；第一栅极层220；
第二栅极层230；第一源漏电极240；
金属层301；第三栅极层310；
第二有源层320；第四栅极层330；
第二源漏电极340；开孔1021；
第一接触孔411；第一过孔412；
第二过孔413。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。在本申请中，在未作相反说明的情况下，使用的方位词如“上”和“下”通常是指装置实际使用或工作状态下的上和下，具体为附图中的图面方向；而“内”和“外”则是针对装置的轮廓而言的。
实施例
如图1所示，本实施例中，本发明的显示装置包括阵列基板10和彩膜基板20，如图2所示，其中所述阵列基板10包括基板100、第一薄膜晶体管200、第二薄膜晶体管300、第一绝缘层410、第一介电层420、第二绝缘层430、第二介电层440、钝化层450、第一平坦层460、栅极绝缘层500、第一像素电极600、第二像素电极700、第二平坦层470、挡墙480以及发光层800。
所述基板100为双层柔性基板，包括叠层设置的第一柔性层110、第一缓冲层120、第二柔性层130、第二缓冲层140以及阻隔层150。
所述第一薄膜晶体管200和所述第二薄膜晶体管300设于阻隔层150远离所述第二缓冲层140的一侧表面，所述第一薄膜晶体管200和所述第二薄膜晶体管300相邻设置且相互绝缘，其中，所述第一薄膜晶体管200为低温多晶硅薄膜晶体管，所述第一薄膜晶体管200为驱动薄膜晶体管，起到驱动像素电路的作用。所述第二薄膜晶体管300为氧化物薄膜晶体管，所述第二薄膜晶体管300为开关薄膜晶体管，起到控制像素电路信号开关的作用。
具体的，所述第一薄膜晶体管200包括层叠设置的第一有源层210、第一栅极层220、第二栅极层230以及第一源漏电极240。
所述第二薄膜晶体管300包括层叠设置的金属层301、第三栅极层310、第二有源层320、第四栅极层330以及第二源漏电极340。
所述第一有源层210是采用低温多晶硅技术（Low Temperature Poly-silicon）将非晶硅经过镭射光均匀照射后，所述非晶硅吸收内部原子发生能级跃迁后形变成为多晶结构，采用低温多晶硅技术可以大大增加所述第一薄膜晶体管200的电子迁移率，从而使得显示装置的分辨率更高、反应速度更快、亮度更高。
所述第一绝缘层410覆盖所述第一有源层210，所述第一绝缘层410的材料为氧化硅材料，具有隔绝水氧的技术效果，有效避免所述第一有源层210被水氧腐蚀。
所述第一栅极层220设于所述第一绝缘层410的上表面，所述第一栅极层220的材质为金属材料，所述金属材料包括钼（Mo）、铝（Al）、铜（Cu）、钛（Ti）等，或者是合金，或者是多层薄膜结构。所述第一栅极层220的厚度为2000埃米~8000埃米。
由于单栅结构的薄膜晶体管对于有源层的载流子控制较弱，从而会导致载流子迁移率不高和阈值电压出现漂移的问题，进而导致所述阵列基板上的驱动电路电学性能不稳定。
故本实施例中，所述第一薄膜晶体管200和所述第二薄膜晶体管300均采用双栅结构，通过对双层栅极层同时施加电信号，可以大幅度提升所述第一薄膜晶体管200和所述第二薄膜晶体管300的载流子迁移率、解决所述第一薄膜晶体管200和所述第二薄膜晶体管300的阈值电压漂移问题，达到了提高薄膜晶体管电学性能稳定性的效果，进而提高了阵列基板上的驱动电路电学性能的稳定性。
为了避免所述第一栅极层220和所述第二栅极层230之间出现短路现象，一般会在两层栅极之间添加一层栅极绝缘层，本实施例中，在所述第一栅极层220和所述第二栅极层230设有栅极绝缘层500，所述栅极绝缘层500的材料为氮化硅材料。所述氮化硅材料氢含量较高，能够在高温条件能够氢气，能够对采用低温多晶硅技术制备的第一有源层210进行补氢，从而满足低温多晶硅技术的要求，保证所述第一有源层210的性能。
但所述第二薄膜晶体管300为氧化物薄膜晶体管，其第二有源层320采用的是氧化物导体材料，本实施例中，所述第二有源层320采用的材料是铟镓锌氧化物（IGZO），铟镓锌氧化物材料对周围气氛比较敏感，如氢、氧气、水等，氢扩散到第二有源层320沟道中会导致铟镓锌氧化物导体化，水氧入侵导致所述第二薄膜晶体管300阈值电压偏移而造成TFT失效，为避免栅极绝缘层500在高温制程下脱离的氢进入到所述第二有源层320中，所述第二薄膜晶体管300的第三栅极层310和所述第一薄膜晶体管200的第二栅极层230同层设置，所述栅极绝缘层500设在所述第二栅极层230和所述第三栅极层310的下表面，且完全被所述第二栅极层230和所述第三栅极层310覆盖。
所述第一介电层420设于所述第一绝缘层410的上表面，所述第一介电层420覆盖所述第一栅极层220、所述栅极绝缘层500、所述第二栅极层230以及所述第三栅极层310。所述第一介电层420为层间绝缘层，所述第一介电层420的材质为无机材料，所述无机材料包括硅的氧化物或硅的氮化物或是多层薄膜结构，起到绝缘作用，防止电路短路。所述第一介电层420的厚度为2000埃米~10000埃米。
所述第二有源层320设于所述第一介电层420的上表面，所述第二绝缘层430覆盖所述第二有源层320，所述第二绝缘层430与所述第一绝缘层410的材料和功能相似，均具有隔绝水氧的技术效果。
所述第四栅极层330设于所述第二绝缘层430的上表面，且与所述第三栅极层310相对设置，通过对第三栅极层310和所述第四栅极层330同时施加电信号，可以大幅度提升所述第二薄膜晶体管300的载流子迁移率、解决所述第二薄膜晶体管300的阈值电压漂移问题，达到了提高薄膜晶体管电学性能稳定性的效果，进而提高了阵列基板上驱动电路的电学性能的稳定性。
所述第二介电层440设于所述第二绝缘层430的上表面，且覆盖所述第四栅极层330，所述第二介电层440与所述第一介电层420的材料和功能相同，均起到绝缘作用，防止电路短路。
所述第一源漏电极240和所述第二源漏电极340设于所述第二介电层440的上表面，所述第一源漏电极240对应所述第一有源层210，且部分贯穿所述第二介电层440、所述第二绝缘层430、所述第一介电层420以及所述第一绝缘层410连接至所述第一有源层210。
所述第二源漏电极340对应所述第二有源层320，且部分贯穿所述第二介电层440、所述第二绝缘层430连接至所述第二有源层320。
所述金属层301设于所述基板100的上表面，与所述第一有源层210同层设置，所述金属层301为导体化后的半导体层，所述第二源漏电极340部分贯穿所述第二介电层440、所述第二绝缘层430、所述第一介电层420以及所述第一绝缘层410连接至所述金属层301，用以避免肖特基接触带来的不良影响。
所述钝化层450设于所述第二介电层440的上表面，所述钝化层450的材质包括硅的氧化物材料，所述钝化层450的厚度为1000埃米~5000埃米。所述钝化层450起到绝缘作用及隔绝外界水氧的作用。
本实施例中，所述阵列基板10包括显示区101和设于所述显示区101下方的弯折区102，所述第一薄膜晶体管200、所述第二薄膜晶体管300和所述栅极绝缘层500设于所述显示区101中，所述基板100、所述第一绝缘层410、所述第一介电层420、所述第二绝缘层430、所述第二介电层440、所述钝化层450、所述第一平坦层460、所述第二平坦层470和所述挡墙480从所述显示区101延伸至所述弯折区102中。
所述弯折区102中设有一开孔1021，所述开孔1021贯穿所述钝化层450、所述第二介电层440、所述第二绝缘层430、所述第一介电层420、所述第一绝缘层410以及部分所述基板100。
所述第一平坦层460设于所述钝化层450的上表面，且从所述显示区101延伸至所述弯折区102中，所述第一平坦层460填充所述开孔1021，所述第一平坦层460采用韧性较高的无机材料，有效避免所述弯折区102弯折时，弯折应力导致的断裂问题，提升了所述阵列基板10的使用寿命。
所述第一像素电极600设于所述第一平坦层460的上表面，所述第一像素电极600对应所述第一薄膜晶体管200，且贯穿所述第一平坦层460和所述钝化层450连接至所述第一源漏电极240，在所述弯折区102中，所述第一平坦层460的上表面还设有若干金属走线，所述金属走线设于所述开孔上方。
所述第二平坦层470设于所述第一平坦层460的上表面，且覆盖所述第一像素电极600。所述第二像素电极700设于所述第二平坦层470的上表面，所述第二像素电极700对应所述第一像素电极600，且部分贯穿所述第二平坦层470连接至所述第一像素电极600。以实现第一像素电极600和第二像素电极700之间的电信号传输。
所述挡墙480设于所述第二平坦层470的上表面，所述挡墙480对应所述第二像素电极700处设有像素开孔，所述发光层800设于所述像素开孔内，且与所述第二像素电极700电连接。
为了更好的解释本发明，本实施例还提供了上述阵列基板10的制备方法，具体步骤如下：
S1) 提供一基板，所述基板100为双层柔性基板，包括叠层设置的第一柔性层110、第一缓冲层120、第二柔性层130、第二缓冲层140以及阻隔层150。
S2) 在所述基板100上制备若干第一薄膜晶体管200和若干第二薄膜晶体管300，其中，所述第一薄膜晶体管200和第二薄膜晶体管300的制备步骤包括：
S201) 如图3所示，在所述基板100上制备一层半导体材料，图案化后形成所述第一薄膜晶体管200的第一有源层210和所述第二薄膜晶体管的金属层301。
S202) 在所述基板100上制备一层第一绝缘层410，所述第一绝缘层410覆盖所述第一有源层210和所述金属层301。
S203) 在所述第一绝缘层410的上表面制备一层栅极材料，图案化后形成所述第一薄膜晶体管200的第一栅极层220。
S204) 如图4所示，在所述第一栅极层220上制备一层栅极绝缘材料，所述栅极绝缘材料为氮化硅材料。
S205) 如图5所示，在所述栅极绝缘材料和所述第一绝缘层410上刻蚀第一接触孔411，所述第一接触孔411对应所述第一有源层210和所述金属层301，采用350摄氏度～400摄氏度的温度对所述栅极绝缘材料进行退火处理，所述栅极绝缘材料中的氢在高温下被脱离出来，通过所述第一接触孔411对所述第一有源层210和所述金属层301进行补氢，在刻蚀第一接触孔411的同时，在弯折区102中刻蚀所述栅极材料和所述第一绝缘层410形成第一深孔。
S206) 在所述栅极绝缘材料上制备一层栅极材料，图案化后形成所述第一薄膜晶体管的第二栅极层230和所述第二薄膜晶体管的第三栅极层310。
S207) 利用所述第二栅极层230和所述第三栅极层310进行自对准，刻蚀所述栅极绝缘材料，获得栅极绝缘层500。
S208) 在所述第一绝缘层410上制备第一介电层420，所述第一介电层420覆盖所述第一栅极层220、所述栅极绝缘层500、所述第二栅极层230和所述第三栅极层310。
S209) 在所述第一介电层420上制备所述第二薄膜晶体管300的第二有源层320，所述第二有源层320对应所述第三栅极层310。
S210) 在所述第一介电层420上制备一层第二绝缘层430，所述第二绝缘层430覆盖所述第二有源层320。
S211) 在所述第二绝缘层430上制备第四栅极层330，所述第四栅极层330与所述第三栅极层310相对应。
S212) 在所述第二绝缘层430上制备第二介电层440，所述第二介电层440覆盖所述第四栅极层330。
S213) 如图6所示，在所述第二介电层440、所述第二绝缘层430、所述第一介电层420和所述第一绝缘层410上刻蚀若干第一过孔412和第二过孔413，所述第一过孔412对应所述第一薄膜晶体管的第一有源层210，且与所述第一接触孔411重合，所述第二过孔413对应所述第二薄膜晶体管的金属层301以及第二有源层320。
S214) 在所述第二介电层440上制备第一源漏电极240以及第二源漏电极340，所述第一源漏电极240穿过所述第一过孔412连接至所述第一有源层210，所述第二源漏电极340穿过所述第二过孔413连接至所述金属层301和所述第二有源层320。在刻蚀所述第一过孔412和所述第二过孔413时，同时在所述弯折区102中刻蚀开孔1021。
S3) 在所述第二介电层440的上表面制备钝化层450，所述钝化层450覆盖所述第一源漏电极240以及第二源漏电极340。
S4) 如图7所示，在所述钝化层的上表面制备第一平坦层460，所述第一平坦层460延伸至所述弯折区102并填充所述开孔1021。
本实施例的有益效果在于，本实施例中的阵列基板及其制备方法、显示装置，采用含氢量较高的氮化硅材料作为栅极绝缘层，在高温条件下能够对多晶硅材料的有源层进行补氢，且栅极绝缘层设于氧化物薄膜晶体管的有源层的下方，被氧化物薄膜晶体管的栅极层完全覆盖，不会造成氧化物薄膜晶体管中有源层的导体化，从而在提升低温多晶硅薄膜晶体管性能的同时，不会造成氧化物薄膜晶体管的不良影响，提升了氧化物薄膜晶体管和多晶硅薄膜晶体管的器件性能。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (15)

  1. 一种阵列基板，其中，包括：
    基板；
    多个第一薄膜晶体管，设于所述基板上，所述第一薄膜晶体管包括第一栅极层和第二栅极层，所述第二栅极层设于所述第一栅极层远离所述基板的一侧；
    多个第二薄膜晶体管，设于所述基板上，所述第二薄膜晶体管包括第三栅极层；
    栅极绝缘层，设于所述第一栅极层和所述第二栅极层之间，以及所述第三栅极层靠近所述基板的一侧表面，所述栅极绝缘层为氮化硅材料。
  2. 根据权利要求1所述的阵列基板，其中，还包括依次叠层设置的第一绝缘层、第一介电层、第二绝缘层、第二介电层以及钝化层。
  3. 根据权利要求1所述的阵列基板，其中，
    所述第一薄膜晶体管还包括：
    第一有源层，设于所述基板上，所述第一绝缘层覆盖所述第一有源层；
    所述第一栅极层设于所述第一绝缘层远离所述基板的一侧表面；
    所述栅极绝缘层设于所述第一栅极层远离所述第一绝缘层的一侧表面；
    第二栅极层，设于所述第一栅极层远离所述栅极绝缘层的一侧表面；
    所述第一介电层设于所述第一绝缘层远离所述基板的一侧表面，且覆盖所述第一栅极层、所述栅极绝缘层和所述第二栅极层；
    第一源漏电极，设于所述第二介电层远离所述第二绝缘层的一侧表面，并连接至所述第一有源层。
  4. 根据权利要求1所述的阵列基板，其中，
    所述第二薄膜晶体管还包括：
    金属层，设于所述基板上，与所述第一有源层同层设置；
    所述第三栅极层设于所述栅极绝缘层上；
    第二有源层，设于所述第一介电层远离所述第一绝缘层的一侧表面，所述第二绝缘层覆盖所述第二有源层；
    第四栅极层，设于所述第二绝缘层远离所述第一介电层的一侧表面，所述第二介电层覆盖所述第四栅极层；
    第二源漏电极，设于所述第二介电层远离所述第二绝缘层的一侧表面，并连接至所述第二有源层和所述金属层。
  5. 根据权利要求1所述的阵列基板，其中，还包括：
    第一平坦层，设于所述钝化层远离所述第二介电层的一侧表面；
    像素电极，设于所述第一平坦层上，且部分贯穿所述第一平坦层连接至所述第一源漏电极；
    第二平坦层，设于所述第一平坦层远离所述钝化层的一侧表面，且覆盖所述像素电极；
    像素定义层，设于所述第二平坦层远离所述第一平坦层的一侧表面，所述像素定义层对应所述像素电极处设有像素开孔；
    发光层，设于所述像素开孔内，且连接至所述像素电极。
  6. 根据权利要求5所述的阵列基板，其中，所述阵列基板还包括显示区和弯折区，所述第一薄膜晶体管和所述第二薄膜晶体管设于所述显示区中，所述基板、所述第一绝缘层、所述第一介电层、所述第二绝缘层、所述第二介电层以及所述钝化层从所述显示区延伸至所述弯折区中；
    在所述弯折区中设有一开孔，所述开孔贯穿所述钝化层、所述第二介电层、所述第二绝缘层、所述第一介电层、所述第一绝缘层以及部分所述基板，所述第一平坦层填充所述开孔。
  7. 一种阵列基板的制备方法，其中，包括以下步骤：
    提供一基板；
    在所述基板上制备若干第一薄膜晶体管和若干第二薄膜晶体管，其中，所述第一薄膜晶体管和第二薄膜晶体管的制备步骤包括：
    制备所述第一薄膜晶体管的第一栅极层；
    在所述第一栅极层上制备一层栅极绝缘材料，所述栅极绝缘材料为氮化硅材料；
    在所述栅极绝缘材料和所述第一绝缘层上刻蚀接触孔，所述接触孔对应所述第一有源层和所述金属层，采用350摄氏度～400摄氏度的温度进行退火；
    在所述栅极绝缘材料上制备所述第一薄膜晶体管的第二栅极层和所述第二薄膜晶体管的第三栅极层；
    利用所述第二栅极层和所述第三栅极层自对准刻蚀所述栅极绝缘材料，获得栅极绝缘层。
  8. 根据权利要求7所述的阵列基板的制备方法，其中，在制备所述第一薄膜晶体管的第一栅极层步骤之前还包括以下步骤：
    在所述基板上制备一层半导体材料，图案化后形成所述第一薄膜晶体管的第一有源层和所述第二薄膜晶体管的金属层；
    在所述基板上制备一层第一绝缘层，所述第一绝缘层覆盖所述第一有源层和所述金属层。
  9. 根据权利要求7所述的阵列基板的制备方法，其中，在所述获得栅极绝缘层步骤之后还包括以下步骤：
    在所述第一绝缘层上制备第一介电层，所述第一介电层覆盖所述第一栅极层、所述栅极绝缘层、所述第二栅极层和所述第三栅极层；
    在所述第一介电层上制备所述第二薄膜晶体管的第二有源层；
    在所述第一介电层上制备一层第二绝缘层，所述第二绝缘层覆盖所述第二有源层；
    在所述第二绝缘层上制备第四栅极层，所述第四栅极层与所述第三栅极层相对应；
    在所述第二绝缘层上制备第二介电层，所述第二介电层覆盖所述第四栅极层；
    在所述第二介电层、所述第二绝缘层、所述第一介电层和所述第一绝缘层上刻蚀若干第一过孔和第二过孔，所述第一过孔对应所述第一薄膜晶体管的第一有源层，所述第二过孔对应所述第二薄膜晶体管的金属层以及第二有源层；
    在所述第二介电层上制备第一源漏电极以及第二源漏电极，所述第一源漏电极穿过所述第一过孔连接至所述第一有源层，所述第二源漏电极穿过所述第二过孔连接至所述金属层和所述第二有源层。
  10. 一种显示装置，其中，包括彩膜基板、阵列基板和背光模组，所述阵列基板为权利要求1所述的阵列基板。
  11. 根据权利要求10所述的显示装置，其中，所述阵列基板还包括依次叠层设置的第一绝缘层、第一介电层、第二绝缘层、第二介电层以及钝化层。
  12. 根据权利要求10所述的显示装置，其中，所述第一薄膜晶体管还包括：
    第一有源层，设于所述基板上，所述第一绝缘层覆盖所述第一有源层；
    所述第一栅极层设于所述第一绝缘层远离所述基板的一侧表面；
    所述栅极绝缘层设于所述第一栅极层远离所述第一绝缘层的一侧表面；
    第二栅极层，设于所述第一栅极层远离所述栅极绝缘层的一侧表面；
    所述第一介电层设于所述第一绝缘层远离所述基板的一侧表面，且覆盖所述第一栅极层、所述栅极绝缘层和所述第二栅极层；
    第一源漏电极，设于所述第二介电层远离所述第二绝缘层的一侧表面，并连接至所述第一有源层。
  13. 根据权利要求10所述的显示装置，其中，所述第二薄膜晶体管还包括：
    金属层，设于所述基板上，与所述第一有源层同层设置；
    所述第三栅极层设于所述栅极绝缘层上；
    第二有源层，设于所述第一介电层远离所述第一绝缘层的一侧表面，所述第二绝缘层覆盖所述第二有源层；
    第四栅极层，设于所述第二绝缘层远离所述第一介电层的一侧表面，所述第二介电层覆盖所述第四栅极层；
    第二源漏电极，设于所述第二介电层远离所述第二绝缘层的一侧表面，并连接至所述第二有源层和所述金属层。
  14. 根据权利要求10所述的显示装置，其中，所述阵列基板还包括：
    第一平坦层，设于所述钝化层远离所述第二介电层的一侧表面；
    像素电极，设于所述第一平坦层上，且部分贯穿所述第一平坦层连接至所述第一源漏电极；
    第二平坦层，设于所述第一平坦层远离所述钝化层的一侧表面，且覆盖所述像素电极；
    像素定义层，设于所述第二平坦层远离所述第一平坦层的一侧表面，所述像素定义层对应所述像素电极处设有像素开孔；
    发光层，设于所述像素开孔内，且连接至所述像素电极。
  15. 根据权利要求14所述的显示装置，其中，所述阵列基板还包括显示区和弯折区，所述第一薄膜晶体管和所述第二薄膜晶体管设于所述显示区中，所述基板、所述第一绝缘层、所述第一介电层、所述第二绝缘层、所述第二介电层以及所述钝化层从所述显示区延伸至所述弯折区中；
    在所述弯折区中设有一开孔，所述开孔贯穿所述钝化层、所述第二介电层、所述第二绝缘层、所述第一介电层、所述第一绝缘层以及部分所述基板，所述第一平坦层填充所述开孔。
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