WO2022205694A1 - 电容器阵列结构及制备方法 - Google Patents

电容器阵列结构及制备方法 Download PDF

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Publication number
WO2022205694A1
WO2022205694A1 PCT/CN2021/107821 CN2021107821W WO2022205694A1 WO 2022205694 A1 WO2022205694 A1 WO 2022205694A1 CN 2021107821 W CN2021107821 W CN 2021107821W WO 2022205694 A1 WO2022205694 A1 WO 2022205694A1
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Prior art keywords
layer
capacitor
support layer
capacitor hole
hole
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PCT/CN2021/107821
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English (en)
French (fr)
Inventor
郭帅
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长鑫存储技术有限公司
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Priority to US17/474,054 priority Critical patent/US11778804B2/en
Publication of WO2022205694A1 publication Critical patent/WO2022205694A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/312—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with a bit line higher than the capacitor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Definitions

  • the present application relates to the field of chip manufacturing, and in particular, to a capacitor array structure and a preparation method.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the capacitance linewidth is a key approach.
  • the line width of the capacitor is reduced, the size of the capacitor will also decrease, which will cause the storage capacitor to further decrease relative to the parasitic capacitance of the bit line, resulting in inability to distinguish the signal of the stored data.
  • the strategy of increasing the capacitor height is adopted.
  • increasing the capacitor height will increase the difficulty of etching the capacitor process, which has become an important research direction for the development of DRAM manufacturing.
  • a first aspect of the present application proposes a capacitor array structure, including:
  • a first capacitor hole which penetrates the first support layer at least along the thickness direction to expose the semiconductor structure
  • a second support layer which is bonded to the semiconductor structure and has a distance from the first support layer on the top layer;
  • a third support layer located on the second support layer and having a distance from the second support layer;
  • a second capacitor hole is provided corresponding to the first capacitor hole, and the second capacitor hole penetrates through the third support layer and the second support layer at least along the thickness direction to communicate with the first capacitor hole ;
  • a first electrode layer covering the sidewall of the first capacitor hole, the bottom of the first capacitor hole and the sidewall of the second capacitor hole;
  • the second electrode layer covers the surface of the capacitor dielectric layer.
  • a second aspect of the present application provides a method for preparing a capacitor array structure, including:
  • a stack structure including a first sacrificial layer and a first support layer that are alternately stacked up and down in sequence on the semiconductor structure;
  • first capacitor hole penetrating the stacked structure at least along the thickness direction
  • a bonded wafer including a second substrate, a second support layer and a second sacrificial layer stacked in sequence;
  • the second capacitor hole penetrates the bonding wafer at least along the thickness direction to communicate with the first capacitor hole;
  • a second electrode layer is formed on the surface of the capacitor medium layer.
  • a bonding wafer including a second substrate, a second support layer and a second sacrificial layer stacked in sequence is provided, and Bonding the bonding wafer on the laminated structure, wherein the surface of the second sacrificial layer away from the second supporting layer is the bonding surface; forming a second capacitor hole, the second capacitor hole penetrates through the bonding wafer at least along the thickness direction , so as to expose the first capacitor hole, so that the first capacitor hole and the second capacitor hole communicate with each other.
  • the wafer bonding process effectively reduces the difficulty of etching the capacitor process, increases the height of the capacitor while reducing the line width of the capacitor, increases the capacity of the storage capacitor and the storage density of DRAM, and provides technical ideas for the development of the DRAM process.
  • FIG. 1 is a schematic flowchart of a method for fabricating a capacitor array structure provided in an embodiment of the present application
  • FIG. 2-3 are schematic structural diagrams of a semiconductor structure provided in an embodiment of the application, wherein FIG. 2 is a top view of the semiconductor structure, FIG. 3 is a schematic cross-sectional structure diagram of FIG. 2 , and (a) in FIG. A schematic diagram of a partial cross-sectional structure taken in the direction AA' in Fig. 2, and (b) in Fig. 3 is a schematic diagram of a partial cross-sectional structure taken in the direction of BB' in Fig. 3 (a);
  • FIG. 4 is a schematic diagram of a partial cross-sectional structure of forming a laminated structure provided in an embodiment of the application, wherein (a) in FIG. 4 is a schematic diagram of a partial cross-sectional structure taken along the direction AA' in FIG. (b) Figure 3(a) is a schematic diagram of a partial cross-sectional structure taken along the BB' direction;
  • FIG. 5 is a schematic diagram of a partial cross-sectional structure of forming a first capacitor hole provided in an embodiment of the application, wherein (a) in FIG. 5 is a schematic diagram of a partial cross-sectional structure taken along the direction AA' in FIG. Figure (b) is a schematic diagram of a partial cross-sectional structure taken along the BB' direction in Figure 3 (a);
  • FIG. 6 is a schematic diagram of a partial cross-sectional structure of forming a protective layer at the bottom of the first capacitor hole provided in an embodiment of the application, wherein (a) in FIG. 6 is a partial cross-sectional structure taken along the direction AA' in FIG. 2 Schematic diagram, (b) in Figure 6 is a schematic diagram of a partial cross-sectional structure taken along the BB' direction in Figure 3 (a);
  • FIG. 7 is a schematic diagram of a partial cross-sectional structure of forming a filling sacrificial layer in the first capacitor hole according to an embodiment of the application, wherein (a) in FIG. 7 is a partial cross-sectional structure taken along the direction AA' in FIG. 2 Schematic diagram, (b) in Figure 7 is a schematic diagram of a partial cross-sectional structure taken along the BB' direction in Figure 3 (a);
  • FIG. 8 is a schematic diagram of a partial cross-sectional structure of forming a fourth support layer on the surface of the laminated structure provided in an embodiment of the application, wherein (a) in FIG. 8 is a partial cross-section taken along the direction AA' in FIG. 2 Schematic diagram of the structure, Figure (b) in Figure 8 is a schematic diagram of a partial cross-sectional structure taken along the BB' direction in Figure 3 (a);
  • FIG. 9 is a schematic structural diagram of a bonded wafer provided in an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a partial cross-sectional structure of a bonded wafer bonded to a laminated structure provided in an embodiment of the application, wherein (a) in FIG. 10 is a partial cross-sectional structure taken along the AA' direction in FIG. 2 Schematic diagram, (b) in Figure 10 is a schematic diagram of a partial cross-sectional structure taken along the BB' direction in Figure 3 (a);
  • FIG. 11 is a schematic diagram of a partial cross-sectional structure of the second substrate after the thinning process provided in an embodiment of the application, wherein (a) in FIG. 11 is a schematic diagram of a partial cross-sectional structure taken along the AA' direction in FIG. 2 , Figure (b) in Figure 11 is a schematic diagram of a partial cross-sectional structure taken along the BB' direction in Figure 3 (a);
  • FIG. 12 is a schematic partial cross-sectional structural diagram of forming a third support layer on the surface of the second substrate provided in an embodiment of the application, wherein (a) in FIG. 12 is a partial section taken along the AA' direction in FIG. 2 Schematic diagram of cross-sectional structure, Figure 12 (b) is a schematic diagram of a partial cross-sectional structure taken along the BB' direction in Figure 3 (a);
  • FIG. 13 is a schematic diagram of a partial cross-sectional structure of forming a second capacitor hole provided in an embodiment of the application, wherein (a) in FIG. 13 is a schematic diagram of a partial cross-sectional structure taken along the AA' direction in FIG. Figure (b) is a schematic diagram of a partial cross-sectional structure taken along the BB' direction in Figure 3 (a);
  • FIG. 14 is a schematic diagram of a partial cross-sectional structure after removing the filling sacrificial layer provided in an embodiment of the application, wherein (a) in FIG. 14 is a schematic diagram of a partial cross-sectional structure taken along the AA' direction in FIG. Figure (b) is a schematic diagram of a partial cross-sectional structure taken along the BB' direction in Figure 3 (a);
  • FIG. 15 is a schematic diagram of a partial cross-sectional structure provided in an embodiment of the application after removing the protective layer, wherein (a) in FIG. 15 is a schematic diagram of a partial cross-sectional structure taken along the AA' direction in FIG. (b) Figure 3(a) is a schematic diagram of a partial cross-sectional structure taken along the BB' direction;
  • FIG. 16 is a schematic diagram of a partial cross-sectional structure of forming a first electrode layer provided in an embodiment of the application, wherein (a) in FIG. 16 is a schematic diagram of a partial cross-sectional structure taken along the AA' direction in FIG. Figure (b) is a schematic diagram of a partial cross-sectional structure taken along the BB' direction in Figure 3 (a);
  • FIG. 17 is a schematic diagram of a partial cross-sectional structure of the second substrate, the second sacrificial layer, and the first sacrificial layer that are sequentially removed based on the openings provided in an embodiment of the application, wherein (a) in FIG. 17 is along the lines of FIG. 2 Schematic diagram of the partial cross-sectional structure taken in the direction of AA' in Fig. 17, (b) in Fig. 17 is a schematic diagram of the partial cross-sectional structure taken along the direction of BB' in Fig. 3(a);
  • FIG. 18 is a schematic diagram of a partial cross-sectional structure of forming a capacitor dielectric layer provided in an embodiment of the application, wherein (a) in FIG. 18 is a schematic diagram of a partial cross-sectional structure taken along the AA' direction in FIG. (b) Figure 3(a) is a schematic diagram of a partial cross-sectional structure taken along the BB' direction;
  • FIG. 19 is a schematic diagram of a partial cross-sectional structure of forming a second electrode layer provided in an embodiment of the application, wherein (a) in FIG. 19 is a schematic diagram of a partial cross-sectional structure taken along the AA' direction in FIG. Figure (b) is a schematic diagram of a partial cross-sectional structure taken along the BB' direction in Figure 3 (a).
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in It may be used herein for convenience of description to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing, the regions shown in the figures are schematic in nature and their shapes are not intended to The actual shapes of the regions of the device are shown and are not intended to limit the scope of this application.
  • a method for preparing a capacitor array structure is provided, as shown in FIG. 1 , including the following steps:
  • Step S1 providing a semiconductor structure
  • Step S2 forming a stack structure including a first sacrificial layer and a first support layer alternately stacked up and down on the semiconductor structure;
  • Step S3 forming a first capacitor hole, and the first capacitor hole penetrates the stacked structure at least along the thickness direction;
  • Step S4 providing a bonded wafer including a second substrate, a second support layer and a second sacrificial layer stacked in sequence;
  • Step S5 bonding the bonding wafer on the laminated structure, wherein the surface of the second sacrificial layer away from the second supporting layer is the bonding surface;
  • Step S6 forming a third support layer on the surface of the second substrate away from the second support layer;
  • Step S7 forming a second capacitor hole, the second capacitor hole penetrates the bonding wafer at least along the thickness direction to communicate with the first capacitor hole;
  • Step S8 forming a first electrode layer on the sidewall of the first capacitor hole, the bottom of the first capacitor hole and the sidewall of the second capacitor hole;
  • Step S9 sequentially removing the second substrate, the second sacrificial layer and the first sacrificial layer
  • Step S10 forming a capacitor dielectric layer on the surface of the first electrode layer
  • Step S11 forming a second electrode layer on the surface of the capacitor dielectric layer.
  • a bonding wafer including a second substrate, a second support layer and a second sacrificial layer stacked in sequence is provided, and Bonding the bonding wafer on the laminated structure, wherein the surface of the second sacrificial layer away from the second supporting layer is the bonding surface; forming a second capacitor hole, the second capacitor hole penetrates through the bonding wafer at least along the thickness direction , so as to expose the first capacitor hole, so that the first capacitor hole and the second capacitor hole communicate with each other.
  • the wafer bonding process effectively reduces the difficulty of etching the capacitor process, increases the height of the capacitor while reducing the line width of the capacitor, increases the capacity of the storage capacitor and the storage density of DRAM, and provides technical ideas for the development of the DRAM process.
  • the semiconductor structure provided in step S1 includes a first substrate 11 , and the first substrate 11 may include, but is not limited to, a Si substrate.
  • a shallow trench isolation structure 17 is formed in the first substrate 11 , and a plurality of shallow trench isolation structures 17 are isolated in the first substrate 11 and arranged in an array
  • the semiconductor structure also includes a plurality of buried gate word lines 12 and a plurality of bit lines 15, the buried gate word lines 12 extend along the first direction, and the bit lines 15 extend along the second direction,
  • the first direction and the second direction have an included angle greater than 0° and less than or equal to 90°; specifically, the included angle is 1°, 2°, 10°, 30°, 50°, 70° or 90° and so on.
  • Each active region 18 straddles two buried gate word lines 12 , an active region S and a drain region D are formed in each active region 18 , and the source region S is located in the two buried gate word lines 18 across the active region 18 . Between the buried gate word lines 12 , the drain region D is located outside the two buried gate word lines 12 spanned by the active region 18 .
  • the buried gate word line 12 includes a gate dielectric layer 121 and a word line conductive layer 122 .
  • the word line conductive layer 122 and the gate dielectric layer 121 are formed in the shallow trench (not shown), the word line conductive layer 122 is located on the sidewall and bottom of the trench, and covers the gate dielectric layer 121, wherein the word line conductive layer
  • the upper surface of the 122 is lower than the upper surface of the first substrate 11 .
  • the material of the first word line conductive layer 233 may include As (arsenic) or B (boron) doped silicon, P (phosphorus) or As doped germanium, W (tungsten), Ti (titanium), TiN (titanium nitride) or Au (gold).
  • the material of the gate dielectric layer 121 may include but not limited to silicon oxide or silicon nitride; the gate dielectric is formed by atomic layer deposition process, plasma vapor deposition process (Chemical Vapor Deposition, CVD) or Rapid Thermal Oxidation (Rapid Thermal Oxidation, RTO). Layer 121.
  • a first insulating layer 13 is formed in the semiconductor structure, and the first insulating layer 13 is located on the upper surface of the buried gate word line 12 and the upper surface of the first substrate 11;
  • the bit line 15 is connected to the source region S via the bit line contact structure 14 .
  • the material of the first insulating layer 13 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the material of the bit line contact structure 14 may include, but is not limited to, polysilicon.
  • the bit line 15 includes a first conductive layer 151 , a second conductive layer 152 and a bit line insulating layer 153 sequentially stacked from bottom to top, and the first conductive layer 151 is located in the first insulating layer On the upper surface of 13 , the first conductive layer 151 is connected to the source region S via the bit line contact structure 14 .
  • the material of the first conductive layer 151 may include, but is not limited to, polysilicon, metal tungsten, metal copper, etc.
  • the material of the first conductive layer 151 may be polysilicon.
  • the material of the second conductive layer 152 may include, but is not limited to, W, Ti, Al (aluminum) or Pt (platinum), and the material of the first conductive layer 151 is different from that of the second conductive layer 152;
  • the material may include but not limited to silicon oxide, silicon nitride or silicon oxynitride, etc.
  • the material of the bit line insulating layer 153 may be the same as that of the first insulating layer 13 .
  • the semiconductor structure further includes a second insulating layer 16 , a second insulating layer 16 is formed on the upper surface of the first insulating layer 13 , and the second insulating layer 16 is filled with gaps between the bit lines 15 and expose the bit line insulating layer 153 .
  • the material of the second insulating layer 16 may include, but is not limited to, silicon oxide, silicon nitride or silicon oxynitride, etc.
  • the material of the second insulating layer 16 may be the same as the material of the bit line insulating layer 153 and/or the first insulating layer
  • the material of layer 13 is the same.
  • a first support layer 21 and a first sacrificial layer 22 that are alternately stacked up and down are formed.
  • the first support layer 21 and the first sacrificial layer 22 may be formed by an atomic layer deposition (ALD) process or a plasma vapor deposition process.
  • ALD atomic layer deposition
  • the materials of the first support layer 21 and the first sacrificial layer 22 are different, and the etching rate of the first support layer 21 is different from the etching rate of the first sacrificial layer 22 in the same etching process, which is embodied in the same etching process.
  • the etching rate of the first sacrificial layer 22 is much higher than that of the first supporting layer 21 , so that when the first sacrificial layer 22 is completely removed, the first supporting layer 21 is almost completely retained.
  • the first sacrificial layer 22 is a silicon oxide layer, and the material of the first support layer 21 can be selected from silicon nitride.
  • the first capacitor hole 23 formed in step S3 penetrates through the stacked structure (not shown) at least along the thickness direction to expose the first substrate 11 , and the drain region D is exposed.
  • the longitudinal cross-sectional shape of the first capacitor hole 23 can be set according to actual needs, and the longitudinal cross-sectional shape of the first capacitor hole 23 can include a U-shape, a rectangle or an inverted trapezoid.
  • the shape is an inverted trapezoid as an example to facilitate the subsequent process, and is not limited thereto.
  • a photoresist can be formed on the upper surfaces of the alternately stacked first support layer 21 and the first sacrificial layer 22 as a mask layer, of course, in other examples, a mask layer of other materials can also be formed (for example, Silicon nitride hard mask layer, etc.); then, the mask layer is patterned by a photolithography process to obtain a patterned mask layer for defining capacitor holes; finally, according to the pattern used for defining capacitor holes
  • the mask layer etches the first support layer 21 and the first sacrificial layer 22 by using a dry etching process, a wet etching process or a combination of the dry etching process and the wet etching process, so that the first support layer 21 and the first sacrificial layer 22 are etched in the first support layer.
  • a first capacitor hole 23 is formed in the layer 21 and the first sacrificial layer 22 .
  • the step of forming a protective layer 231 at the bottom of the first capacitor hole 23 is further included.
  • the step of removing the protective layer 231 is also included.
  • the first capacitor hole 23 penetrates the bit line 15 along the thickness direction, and the protective layer 231 is formed at the bottom of the first capacitor hole 23 penetrating the bit line 15 .
  • the material of the filling sacrificial layer 24 and the material of the first substrate 11 are both Si.
  • a protective layer 231 with a thickness of less than 1 nm is formed at the bottom of the first capacitor hole in advance to effectively prevent the subsequent removal of the filling sacrificial layer 24 , the first substrate 11 is damaged.
  • the protective layer 231 includes a silicon oxide layer, and the thickness of the silicon oxide layer is Specifically, the thickness of the silicon oxide layer may be or and many more.
  • a filling sacrificial layer 24 is formed in the first capacitor hole 23 , and the filling sacrificial layer 24 fills the first capacitor hole 23 .
  • the filling sacrificial layer 24 is a polysilicon layer; an atomic layer deposition process, a plasma vapor deposition process or a rapid thermal oxidation process can be used to deposit polysilicon one or more times, and the first capacitor hole 23 is filled in an etching cycle, and then through a chemical mechanical polishing process (Chemical Mechanical Polish, CMP) smoothes the upper surface of the filling sacrificial layer 24 to ensure that the upper surface of the filling sacrificial layer 24 is flush with the upper surface of the first support layer 21.
  • CMP chemical mechanical polishing process
  • the fourth support layer 25 covers the upper surface of the stacked structure and fills the upper surface of the sacrificial layer 24, so as to increase the bonding force of the bonding wafer on the stacked structure and improve the DRAM device stability.
  • the material of the fourth support layer 25 can be selected from silicon nitride, and the preparation process of the fourth support layer 25 can be the same as that of the first support layer 21 .
  • a bonding wafer 31 is provided in step S4 , and the bonding wafer 31 includes a second substrate 311 , a second support layer 312 and a second sacrificial layer 313 stacked in sequence.
  • the material of the second substrate 311 may include but not limited to Si, and the material of the second substrate 311 may be the same as the material of the first substrate 11 ; the material of the second support layer 312 may be silicon nitride; the second sacrificial layer 313 and the first sacrificial layer 22 are both silicon oxide layers.
  • the bonding wafer 31 is bonded on the laminated structure, wherein the surface of the second sacrificial layer 313 away from the second supporting layer 312 is the bonding surface.
  • the bonding wafer 31 is bonded to the stacked structure and before the third support layer 32 is formed on the surface of the second substrate 311 away from the second support layer 312 , the method further includes: : thinning process is performed on the second substrate 311 .
  • the thickness of the second substrate 311 remaining after the thinning process is a quarter of the total depth of the first capacitor hole 23 and the second capacitor hole 33 .
  • a third support layer 32 is formed on the surface of the second substrate 311 away from the second support layer 312 , so that the second substrate 311 , The second sacrificial layer 313 and the first sacrificial layer 22 play a supporting role.
  • the third support layer 32 can be selected from silicon nitride.
  • a second capacitor hole 33 is formed, and the second capacitor hole 33 penetrates through the bonding wafer 31 at least along the thickness direction to expose the first capacitor hole 23 .
  • the etching process of the second capacitor hole 33 is the same as the etching process of the first capacitor hole 23, which is not repeated here.
  • the longitudinal cross-sectional shape of the second capacitor hole 33 is an inverted trapezoid, which is convenient for subsequent deposition, and the sidewall of the first capacitor hole 23 and the sidewall of the second capacitor hole 33 are inclined relative to the direction perpendicular to the upper surface of the semiconductor structure.
  • the angle is 5° ⁇ 10°; specifically, the angle of inclination of the side wall of the first capacitor hole 23 and the side wall of the second capacitor hole 33 is 5°, 6°, 7°, and 7° from the direction perpendicular to the upper surface of the semiconductor structure. °, 8°, 9° or 10°, etc.
  • the filling sacrificial layer 24 is removed, so that the first capacitor hole 23 and the second capacitor hole 33 are connected; a wet or dry etching process can be used to remove the filling sacrificial layer 24, It is well known to those skilled in the art and will not be repeated here.
  • a first electrode layer 26 is formed on the sidewall of the first capacitor hole 23 , the bottom of the first capacitor hole 23 and the sidewall of the second capacitor hole 33 .
  • the first electrode layer 26 is deposited on the sidewall of the first capacitor hole 23 , the bottom of the first capacitor hole 23 and the sidewall of the second capacitor hole 33 by using an atomic layer deposition process or a plasma vapor deposition process.
  • the first electrode layer 26 may include, but is not limited to, a compound formed by one or both of metal nitrides and metal silicides, such as titanium nitride (Titanium Nitride), titanium silicide (Titanium Silicide), and nickel silicide (Titanium Silicide). ), titanium silicon nitride ( TiSixNy ).
  • step S9 the step of sequentially removing the second substrate 311 , the second sacrificial layer 313 and the first sacrificial layer 22 , further comprising:
  • Step S91 forming a patterned mask layer (not shown) on the upper surface of the third support layer 32, the patterned mask layer has a plurality of opening patterns, and the opening patterns define the shape and position of the opening 34;
  • Step S92 etching the third support layer 32 based on the patterned mask layer to form a first opening in the third support layer 32 , and the first opening exposes the space between the third support layer 32 and the second support layer 312 . the second substrate 311;
  • Step S93 removing the second substrate 311 based on the first opening
  • Step S94 forming a second opening in the second support layer 312 based on the first opening, and the second opening exposes the second sacrificial layer 313 ;
  • Step S95 removing the second sacrificial layer 313;
  • Step S96 forming a third opening on the fourth support layer 25 and the first support layer 21 based on the second opening, and the third opening exposes the first sacrificial layer 22 ;
  • Step S97 removing the first sacrificial layer 22 based on the third opening.
  • a capacitor dielectric layer 27 is formed on the surface of the first electrode layer 26 .
  • the material of the capacitor dielectric layer 27 can be selected as a high-K dielectric material to improve the capacitance value of the capacitor per unit area, which includes one of ZrO x , HfO x , ZrTiO x , RuO x , SbO x , AlO x or all of the above materials.
  • the second electrode layer 28 is formed on the surface of the capacitor dielectric layer 27 in step S11 .
  • the material of the second electrode layer 28 may include one of tungsten, titanium, nickel, aluminum, platinum, titanium nitride, N-type polysilicon, P-type polysilicon, or two or more of the above materials. formed stack.
  • a capacitor array structure including: a semiconductor structure; a plurality of first support layers arranged in parallel and spaced apart on the semiconductor structure; and a first capacitor hole, the first capacitor hole at least along the The thickness direction runs through the first support layer to expose the semiconductor structure; the second support layer is bonded to the semiconductor structure and has a distance from the first support layer located on the top layer; the third support layer is located on the second support layer, and has a distance from the second support layer; the second capacitor hole is arranged corresponding to the first capacitor hole, and the second capacitor hole penetrates the third support layer and the second support layer at least along the thickness direction to communicate with the first capacitor hole;
  • the first electrode layer covers the sidewall of the first capacitor hole, the bottom of the first capacitor hole and the sidewall of the second capacitor hole; the capacitor dielectric layer covers the surface of the first electrode layer; the second electrode layer covers the capacitor dielectric layer s surface.
  • the longitudinal cross-sectional shape of the second capacitor hole 33 is an inverted trapezoid, and the sidewall of the first capacitor hole 23 and the sidewall of the second capacitor hole 33 are inclined at an angle of 5° with respect to the direction perpendicular to the upper surface of the semiconductor structure. ⁇ 10°; specifically, the sidewalls of the first capacitor hole 23 and the sidewalls of the second capacitor hole 33 are inclined at angles of 5°, 6°, 7°, 8° compared to the direction perpendicular to the upper surface of the semiconductor structure , 9° or 10°, etc.
  • the capacitor array structure further includes a fourth support layer 25, the fourth support layer 25 covers the upper surface of the first support layer 21 on the top layer; there is a distance between the second support layer 312 and the fourth support layer 25 .

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  • Semiconductor Integrated Circuits (AREA)

Abstract

本申请公开了一种电容器阵列结构及制备方法，电容器阵列结构的制备方法包括：在形成第一电容孔的步骤之后，提供包括依次层叠的第二衬底、第二支撑层及第二牺牲层的键合晶圆，并将键合晶圆键合于叠层结构上，其中，第二牺牲层远离第二支撑层的表面为键合面；形成第二电容孔，第二电容孔至少沿厚度方向贯穿键合晶圆，以暴露出第一电容孔，以使第一电容孔和第二电容孔相连通。采用晶圆键合工艺，有效降低刻蚀电容工艺的难度，使得在降低电容线宽的同时，增加电容高度，提高存储电容的容量和DRAM存储密度。

Description

电容器阵列结构及制备方法
本申请要求于2021年04月02日提交中国专利局、申请号为2021103606634、申请名称为“电容器阵列结构及制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及芯片制造领域，尤其涉及一种电容器阵列结构及制备方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，简称：DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。随着DRAM器件向更高的存储密度发展，降低电容线宽是关键手段。但降低电容线宽的同时，电容大小也将随之降低，引发存储电容相对于位线寄生电容进一步减小，导致存储数据的信号无法分辨。现如今，为了维持电容大小不变，减小存储电容的线宽，采取增加电容高度的策略，但增加电容高度，则会增加刻蚀电容工艺的难度，成为DRAM制成发展的重要研究方向。
发明内容
本申请的第一方面提出一种电容器阵列结构，包括：
半导体结构；
若干层平行间隔排布的第一支撑层，位于所述半导体结构上；
第一电容孔，所述第一电容孔至少沿厚度方向贯穿所述第一支撑层，以暴露出所述半导体结构；
第二支撑层，键合于所述半导体结构上，且与位于顶层的所述第一支撑层具有间距；
第三支撑层，位于所述第二支撑层上，且与所述第二支撑层具有间距；
第二电容孔，与所述第一电容孔对应设置，所述第二电容孔至少沿厚度方向贯穿所述第三支撑层及所述第二支撑层，以与所述第一电容孔相连通；
第一电极层，覆盖所述第一电容孔的侧壁、所述第一电容孔的底部及所述第二电容孔的侧壁；
电容介质层，覆盖所述第一电极层的表面；
第二电极层，覆盖所述电容介质层的表面。
本申请的第二方面提出一种电容器阵列结构的制备方法，包括：
提供半导体结构；
于所述半导体结构上形成包括依次上下交替层叠的第一牺牲层及第一支撑层的叠层结构；
形成第一电容孔，所述第一电容孔至少沿厚度方向贯穿所述叠层结构；
提供包括依次层叠的第二衬底、第二支撑层及第二牺牲层的键合晶圆；
将所述键合晶圆键合于所述叠层结构上，其中，所述第二牺牲层远离所述第二支撑层的表面为键合面；
于所述第二衬底远离所述第二支撑层的表面形成第三支撑层；
形成第二电容孔，所述第二电容孔至少沿厚度方向贯穿所述键合晶圆，以与所述第一电容孔相连通；
于所述第一电容孔的侧壁、所述第一电容孔的底部及所述第二电容孔的侧壁形成第一电极层；
依次去除所述第二衬底、所述第二牺牲层及所述第一牺牲层；
于所述第一电极层的表面形成电容介质层；
于所述电容介质层的表面形成第二电极层。
于上述实施例提供的电容器阵列结构的制备方法中，在形成第一电容孔的步骤之后，提供包括依次层叠的第二衬底、第二支撑层及第二牺牲层的键合晶圆，并将键合晶圆键合于叠层结构上，其中，第二牺牲层远离第二支撑层的表面为键合面；形成第二电容孔，第二电容孔至少沿厚度方向贯穿键合晶圆，以暴露出第一电容孔，以使第一电容孔和第二电容孔相连通。采用晶圆键合工艺，有效降低刻蚀电容工艺的难度，使得在降低电容线宽的同时，增加电容高度，提高存储电容的容量和DRAM存储密度，并为DRAM制程发展提供了技术思路。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，并可依照说明书的内容予以实施，以下以本申请的较佳实施例并配合附图详细说明如后。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附 图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为本申请一实施例中提供的电容器阵列结构的制备方法的流程示意图；
图2-3为本申请一实施例中提供的半导体结构的结构示意图，其中，图2中为半导体结构的俯视图，图3为图2的截面结构示意图，图3中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图3中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图4为本申请一实施例中提供的形成叠层结构的局部截面结构示意图，其中，图4中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图4中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图5为本申请一实施例中提供的形成第一电容孔的局部截面结构示意图，其中，图5中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图5中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图6为本申请一实施例中提供的于第一电容孔的底部形成保护层的局部截面结构示意图，其中，图6中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图6中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图7为本申请一实施例中提供的于第一电容孔内形成填充牺牲层的局部截面结构示意图，其中，图7中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图7中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图8为本申请一实施例中提供的于叠层结构的表面形成第四支撑层的局部截面结构示意图，其中，图8中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图8中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图9为本申请一实施例中提供的键合晶圆的结构示意图；
图10为本申请一实施例中提供的键合晶圆键合于叠层结构的局部截面结构示意图，其中，图10中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图10中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图11为本申请一实施例中提供的对第二衬底减薄处理后的局部截面结构示意图，其中，图11中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图11中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图12为本申请一实施例中提供的于第二衬底的表面形成第三支撑层的局部截面结构示意图，其中，图12中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图12中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图13为本申请一实施例中提供的形成第二电容孔的局部截面结构示意图，其中，图13中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图13中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图14为本申请一实施例中提供的去除填充牺牲层后的局部截面结构示意图，其中，图14中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图14中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图15为本申请一实施例中提供的去除保护层后的局部截面结构示意图，其中，图15中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图15中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图16为本申请一实施例中提供的形成第一电极层的局部截面结构示意图，其中，图16中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图16中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图17为本申请一实施例中提供的基于开口依次去除第二衬底、第二牺牲层及第一牺牲层后的局部截面结构示意图，其中，图17中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图17中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图18为本申请一实施例中提供的形成电容介质层的局部截面结构示意图，其中，图18中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图18中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图；
图19为本申请一实施例中提供的形成第二电极层的局部截面结构示意图，其中，图19中的(a)图为沿图2中AA’方向截取的局部截面结构示意图，图19中的(b)图为图3(a)中沿BB’方向截取的局部截面结构示意图。
附图标记说明：11-第一衬底，12-埋入式栅极字线，121-栅介质层，122-字线导电层，13-第一绝缘层，14-位线接触结构，15-位线，151-第一导电层，152-第二导电层，153-位线绝缘层，16-第二绝缘层，17-浅沟槽隔离结构，18-有源区，21-第一支撑层，22-第一牺牲层，23-第一电容孔，231-保护层，24-填充牺牲层，25-第四支撑层，26-第一电极层，27-电容介质层，28-第二电极层，31-键合晶圆，311-第二衬底，312-第二支撑层，313-第二牺 牲层，32-第三支撑层，33-第二电容孔，34-开口。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任 何及所有组合。
这里参考作为本申请的理想实施例(和中间结构)的示意图的横截面图来描述申请的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本申请的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本申请的范围。
在本申请的一个实施例中，提供的一种电容器阵列结构的制备方法，如图1所示，包括如下步骤：
步骤S1：提供半导体结构；
步骤S2：于半导体结构上形成包括依次上下交替层叠的第一牺牲层及第一支撑层的叠层结构；
步骤S3：形成第一电容孔，第一电容孔至少沿厚度方向贯穿叠层结构；
步骤S4：提供包括依次层叠的第二衬底、第二支撑层及第二牺牲层的键合晶圆；
步骤S5：将键合晶圆键合于叠层结构上，其中，第二牺牲层远离第二支撑层的表面为键合面；
步骤S6：于第二衬底远离第二支撑层的表面形成第三支撑层；
步骤S7：形成第二电容孔，第二电容孔至少沿厚度方向贯穿键合晶圆，以与第一电容孔相连通；
步骤S8：于第一电容孔的侧壁、第一电容孔的底部及第二电容孔的侧壁形成第一电极层；
步骤S9：依次去除第二衬底、第二牺牲层及第一牺牲层；
步骤S10：于第一电极层的表面形成电容介质层；
步骤S11：于电容介质层的表面形成第二电极层。
于上述实施例提供的电容器阵列结构的制备方法中，在形成第一电容孔的步骤之后，提供包括依次层叠的第二衬底、第二支撑层及第二牺牲层的键合晶圆，并将键合晶圆键合于叠层结构上，其中，第二牺牲层远离第二支撑层的表面为键合面；形成第二电容孔，第二电容孔至少沿厚度方向贯穿键合晶圆，以暴露出第一电容孔，以使第一电容孔和第二电容孔相连通。采用晶圆键合工艺，有效降低刻蚀电容工艺的难度，使得在降低电容线宽的同时，增加电容高度，提高存储电容的容量和DRAM存储密度，并为DRAM制程发展提供了技术思路。
在一个实施例中，如图2-3所示，步骤S1中提供的半导体结构包括第一衬底11，第一衬底11可以包括但不仅限于Si衬底。
在一个实施例中，请继续参考图2-3，第一衬底11内形成有浅沟槽隔离结构17，浅沟槽隔离结构17在第一衬底11内隔离出多个呈阵列排布的有源区18；半导体结构还包括若干条埋入式栅极字线12及若干条位线15，埋入式栅极字线12沿第一方向延伸，位线15沿第二方向延伸，第一方向与第二方向具有大于0°且小于等于90°的夹角；具体地，夹角为1°、2°、10°、30°、50°、70°或90°等等。各有源区18均横跨两条埋入式栅极字线12，各有源区18内均形成有源区S及漏区D，源区S位于有源区18横跨的两条埋入式栅极字线12之间，漏区D位于有源区18横跨的两条埋入式栅极字线12的外侧。
在一个实施例中，请继续参考图3，埋入式栅极字线12包括栅介质层121和字线导电层122。字线导电层122和栅介质层121形成于浅沟槽内(未标示出)，字线导电层122位于沟槽的侧壁及底部，并包覆栅介质层121，其中，字线导电层122的上表面低于第一衬底11的上表面。
作为示例，第一字线导电层233的材料可以包括As(砷)或B(硼)掺杂的硅、P(磷)或As掺杂的锗、W(钨)、Ti(钛)、TiN(氮化钛)或Au(金)。栅介质层121的材料可以包括但不仅限于氧化硅或氮化硅；采用原子层沉积工艺、等离子蒸汽沉积工艺(Chemical Vapor Deposition，CVD)或快速热氧化工艺(Rapid Thermal Oxidation，RTO)形成栅介质层121。
在一个实施例中，请继续参考图3，半导体结构内形成有第一绝缘层13，第一绝缘层13位于埋入式栅极字线12的上表面及第一衬底11的上表面；位线15经由位线接触结构14与源区S相连接。
作为示例，第一绝缘层13的材料可以包括但不仅限于氧化硅、氮化硅或氮氧化硅等等。位线接触结构14的材料可以包括但不仅限于多晶硅。
在一个实施例中，请继续参考图3，位线15包括由下至上依次层叠的第一导电层151、第二导电层152及位线绝缘层153，第一导电层151位于第一绝缘层13的上表面，第一导电层151经由位线接触结构14与源区S相连接。
作为示例，第一导电层151的材料可以包括但不仅限于多晶硅、金属钨或金属铜等等，本实施例中，第一导电层151的材料可以选用多晶硅。第二导电层152的材料可以包括但不仅限于W、Ti、Al(铝)或Pt(铂)，且第一导电层151的材料与第二导电层152的材料不同；位线绝缘层153的材料可以包括但不仅限于氧化硅、氮化硅或氮氧化硅等等，位 线绝缘层153的材料可以与第一绝缘层13的材料相同。
在一个实施例中，请参考图3中的(b)图，半导体结构还包括第二绝缘层16，于第一绝缘层13的上表面形成第二绝缘层16，第二绝缘层16填满位线15之间的间隙，并暴露出位线绝缘层153。
作为示例，第二绝缘层16的材料可以包括但不仅限于氧化硅、氮化硅或氮氧化硅等等，第二绝缘层16的材料可以与位线绝缘层153的材料及/或第一绝缘层13的材料相同。
作为示例，后续结构图示均基于图2和图3所示的两种截取方向上示意。
在一个实施例中，如图4所示，步骤S2中形成上下交替层叠的第一支撑层21及第一牺牲层22。可采用原子层沉积工艺(Atomic Layer Deposition，ALD)或等离子蒸气沉积工艺形成第一支撑层21及第一牺牲层22。其中，第一支撑层21及第一牺牲层22的材料不同，且在同一刻蚀制程中第一支撑层21的刻蚀速率与第一牺牲层22的刻蚀速率不同，具体表现为同一刻蚀制程中，第一牺牲层22的刻蚀速率远远大于第一支撑层21的刻蚀速率，使得当第一牺牲层22被完全去除时，第一支撑层21几乎被完全保留。第一牺牲层22为氧化硅层，第一支撑层21的材料可选用氮化硅。
在一个实施例中，如图5所示，步骤S3中形成的第一电容孔23，第一电容孔23至少沿厚度方向贯穿叠层结构(未标示出)，以暴露出第一衬底11，且暴露出漏区D。第一电容孔23的纵截面形状可以根据实际需求进行设定，第一电容孔23的纵截面形状可以包括U型、矩形或倒梯形，其中，图5中以第一电容孔23的纵截面形状为倒梯形作为示例，以便于后续工艺的进行，并不以此限定。
作为示例，可在交替叠置的第一支撑层21及第一牺牲层22的上表面形成光刻胶作为掩膜层，当然，在其他示例中也可以形成其他材料的掩膜层(譬如，氮化硅硬掩膜层等等)；然后，采用光刻工艺将掩膜层图形化，以得到用于定义电容孔的图形化掩膜层；最后，可依据用于定义电容孔的图形化掩膜层采用干法刻蚀工艺、湿法刻蚀工艺或干法刻蚀工艺与湿法刻蚀工艺相结合的工艺刻蚀第一支撑层21及第一牺牲层22，以在第一支撑层21及第一牺牲层22内形成第一电容孔23。
在一个实施例中，如图6所示，形成第一电容孔23之后且于第一电容孔23内形成填充牺牲层24之前，还包括于第一电容孔23的底部形成保护层231的步骤；如图15所示，去除填充牺牲层24之后且形成第一电极层26之前，还包括去除保护层231的步骤。其中，第一电容孔23沿厚度方向贯穿位线15，保护层231形成于贯穿位线15的第一电容孔23的底部。填充牺牲层24的材料与第一衬底11的材料均为Si，形成填充牺牲层24之前， 预先在第一电容孔的底部形成低于1nm的保护层231，有效防止后续去除填充牺牲层24时，对第一衬底11造成损伤。
作为示例，保护层231包括氧化硅层，氧化硅层的厚度为
Figure PCTCN2021107821-appb-000001
具体地，氧化硅层的厚度可以为
Figure PCTCN2021107821-appb-000002
或
Figure PCTCN2021107821-appb-000003
等等。
在一个实施例中，如图7所示，于第一电容孔23内形成填充牺牲层24，填充牺牲层24填满第一电容孔23。填充牺牲层24为多晶硅层；可采用原子层沉积工艺、等离子蒸汽沉积工艺或快速热氧化工艺单次或多次沉积多晶硅，刻蚀循环填充第一电容孔23，再经由化学机械研磨工艺(Chemical Mechanical Polish，CMP)磨平填充牺牲层24的上表面，确保填充牺牲层24的上表面与第一支撑层21的上表面齐平。
在一个实施例中，如图8所示，于第一电容孔23内形成填充牺牲层24之后，且将键合晶圆31键合于叠层结构上之前还包括于叠层结构的表面形成第四支撑层25的步骤，第四支撑层25覆盖叠层结构的上表面及填充牺牲层24的上表面，以增大键合晶圆键合于叠层结构上的键合力，提高DRAM器件的稳定性。
作为示例，第四支撑层25的材料可选用氮化硅，第四支撑层25的制备工艺可以与第一支撑层21的制备工艺相同。
在一个实施例中，如图9所示，步骤S4中提供键合晶圆31，键合晶圆31包括依次层叠的第二衬底311、第二支撑层312及第二牺牲层313。第二衬底311的材料可以包括但不仅限于Si，第二衬底311的材料可以与第一衬底11的材料相同；第二支撑层312的材料可选用氮化硅；第二牺牲层313和第一牺牲层22均为氧化硅层。如图10所示，步骤S5中将键合晶圆31键合于叠层结构上，其中，第二牺牲层313远离第二支撑层312的表面为键合面。
在一个实施例中，如图11所示，将键合晶圆31键合于叠层结构上且于第二衬底311远离第二支撑层312的表面形成第三支撑层32之前，还包括：对第二衬底311进行减薄处理。具体地，减薄处理后保留的第二衬底311的厚度为第一电容孔23及第二电容孔33总深度的四分之一。
在一个实施例中，如图12所示，步骤S6中于第二衬底311远离第二支撑312层的表面形成第三支撑层32，以便于后续形成开口后，去除第二衬底311、第二牺牲层313及第一牺牲层22，起到支撑作用。作为示例，第三支撑层32可选用氮化硅。
在一个实施例中，如图13所示，步骤S7中形成第二电容孔33，第二电容孔33至少沿厚度方向贯穿键合晶圆31，以暴露出第一电容孔23。第二电容孔33的刻蚀工艺与第一 电容孔23的刻蚀工艺相同，此处不再赘述。第二电容孔33的纵截面形状为倒梯形，便于后续沉积的进行，且第一电容孔23的侧壁及第二电容孔33的侧壁相较于垂直于半导体结构上表面的方向倾斜的角度为5°～10°；具体地，第一电容孔23的侧壁及第二电容孔33的侧壁相较于垂直于半导体结构上表面的方向倾斜的角度为5°、6°、7°、8°、9°或10°等等。
在一个实施例中，如图14所示，去除填充牺牲层24，以使第一电容孔23和第二电容孔33连通；可采用湿法或干法刻蚀工艺，去除填充牺牲层24，为本领域技术人员所熟知，不再赘述。
在一个实施例中，如图16所示，步骤S8中于第一电容孔23的侧壁、第一电容孔23的底部及第二电容孔33的侧壁形成第一电极层26。作为示例，采用原子层沉积工艺或等离子蒸气沉积工艺于第一电容孔23的侧壁、第一电容孔23的底部及第二电容孔33的侧壁沉积第一电极层26。第一电极层26可以包括但不仅限于金属氮化物及金属硅化物中的一种或两种所形成的化合物，如氮化钛(Titanium Nitride)，硅化钛(Titanium Silicide)，硅化镍(Titanium Silicide)，硅氮化钛(TiSi xN y)。
在一个实施例中，如图17所示，步骤S9：依次去除第二衬底311、第二牺牲层313及第一牺牲层22的步骤，还包括：
步骤S91：于第三支撑层32的上表面形成图形化掩膜层(未示出)，图形化掩膜层具有多个开口图形，开口图形定义出开口34的形状及位置；
步骤S92：基于图形化掩膜层刻蚀第三支撑层32，以于第三支撑层32内形成第一开口，第一开口暴露出位于第三支撑层32与第二支撑层312之间的第二衬底311；
步骤S93：基于第一开口去除第二衬底311；
步骤S94：基于第一开口于第二支撑层312内形成第二开口，第二开口暴露出第二牺牲层313；
步骤S95：去除第二牺牲层313；
步骤S96：基于第二开口于第四支撑层25及第一支撑层21上形成第三开口，第三开口暴露出第一牺牲层22；
步骤S97：基于第三开口去除第一牺牲层22。
在一个实施例中，如图18所示，步骤S10中于第一电极层26的表面形成电容介质层27。电容介质层27的材料可以选用为高K介质材料，以提高单位面积电容器的电容值，其包括ZrO x、HfO x、ZrTiO x、RuO x、SbO x、AlO x中的一种或上述材料所组成群组中的两种以上所形成的叠层。
在一个实施例中，如图19所示，步骤S11中于电容介质层27的表面形成第二电极层28。作为示例，第二电极层28的材料可以包括钨、钛、镍、铝、铂、氮化钛、N型多晶硅、P型多晶硅中的一种或上述材料所组成群组中的两种以上所形成的叠层。
在本申请的一个实施例中，还提出一种电容器阵列结构，包括：半导体结构；若干层平行间隔排布的第一支撑层，位于半导体结构上；第一电容孔，第一电容孔至少沿厚度方向贯穿第一支撑层，以暴露出半导体结构；第二支撑层，键合于半导体结构上，且与位于顶层的第一支撑层具有间距；第三支撑层，位于第二支撑层上，且与第二支撑层具有间距；第二电容孔，与第一电容孔对应设置，第二电容孔至少沿厚度方向贯穿第三支撑层及第二支撑层，以与第一电容孔相连通；第一电极层，覆盖第一电容孔的侧壁、第一电容孔的底部及第二电容孔的侧壁；电容介质层，覆盖第一电极层的表面；第二电极层，覆盖电容介质层的表面。该电容器阵列结构有效降低刻蚀电容工艺的难度，使得在降低电容线宽的同时，增加电容高度，提高存储电容的容量和DRAM存储密度，并为DRAM制程发展提供了技术思路。
作为示例，第二电容孔33的纵截面形状为倒梯形，第一电容孔23的侧壁及第二电容孔33的侧壁相较于垂直于半导体结构上表面的方向倾斜的角度为5°～10°；具体地，第一电容孔23的侧壁及第二电容孔33的侧壁相较于垂直于半导体结构上表面的方向倾斜的角度为5°、6°、7°、8°、9°或10°等等。
在一个实施例中，电容器阵列结构还包括第四支撑层25，第四支撑层25覆盖位于顶层的第一支撑层21的上表面；第二支撑层312与第四支撑层25之间具有间距。
请注意，上述实施例仅出于说明性目的而不意味对本申请的限制。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种电容器阵列结构，包括：
    半导体结构；
    若干层平行间隔排布的第一支撑层，位于所述半导体结构上；
    第一电容孔，所述第一电容孔至少沿厚度方向贯穿所述第一支撑层，以暴露出所述半导体结构；
    第二支撑层，键合于所述半导体结构上，且与位于顶层的所述第一支撑层具有间距；
    第三支撑层，位于所述第二支撑层上，且与所述第二支撑层具有间距；
    第二电容孔，与所述第一电容孔对应设置，所述第二电容孔至少沿厚度方向贯穿所述第三支撑层及所述第二支撑层，以与所述第一电容孔相连通；
    第一电极层，覆盖所述第一电容孔的侧壁、所述第一电容孔的底部及所述第二电容孔的侧壁；
    电容介质层，覆盖所述第一电极层的表面；
    第二电极层，覆盖所述电容介质层的表面。
  2. 根据权利要求1所述的电容器阵列结构，其中，所述第一电容孔及所述第二电容孔的纵截面形状均为倒梯形，所述第一电容孔的侧壁及所述第二电容孔的侧壁相较于垂直于所述半导体结构上表面的方向倾斜的角度为5°～10°。
  3. 根据权利要求1所述的电容器阵列结构，其中，所述半导体结构包括第一衬底，所述第一衬底内形成有浅沟槽隔离结构，所述浅沟槽隔离结构在所述第一衬底内隔离出多个呈阵列排布的有源区；所述半导体结构还包括若干条埋入式栅极字线及若干条位线，所述埋入式栅极字线沿第一方向延伸，所述位线沿第二方向延伸，所述第一方向与所述第二方向具有大于0°且小于等于90°的夹角；各所述有源区均横跨两条所述埋入式栅极字线，各所述有源区内均形成有源区及漏区，所述源区位于所述有源区横跨的两条所述埋入式栅极字线之间，所述漏区位于所述有源区横跨的两条所述埋入式栅极字线的外侧。
  4. 根据权利要求3所述的电容器阵列结构，其中，所述半导体结构内形成有第一绝缘层，所述第一绝缘层位于所述所述埋入式栅极字线的上表面及所述第一衬底的上表面；所述位线经由位线接触结构与所述源区相连接，所述第一电容孔暴露出所述漏区。
  5. 根据权利要求4所述的电容器阵列结构，其中，所述位线包括由下至上依次层叠的第一导电层、第二导电层及位线绝缘层，所述第一导电层位于所述第一绝缘层的上表面，所述第一导电层经由所述位线接触结构与所述源区相连接。
  6. 根据权利要求1至5中任一项所述的电容器阵列结构，其中，还包括第四支撑层，所述第四支撑层覆盖位于顶层的所述第一支撑层的上表面；所述第二支撑层与第四支撑层之间具有间距。
  7. 一种电容器阵列结构的制备方法，包括：
    提供半导体结构；
    于所述半导体结构上形成包括依次上下交替层叠的第一牺牲层及第一支撑层的叠层结构；
    形成第一电容孔，所述第一电容孔至少沿厚度方向贯穿所述叠层结构；
    提供包括依次层叠的第二衬底、第二支撑层及第二牺牲层的键合晶圆；
    将所述键合晶圆键合于所述叠层结构上，其中，所述第二牺牲层远离所述第二支撑层的表面为键合面；
    于所述第二衬底远离所述第二支撑层的表面形成第三支撑层；
    形成第二电容孔，所述第二电容孔至少沿厚度方向贯穿所述键合晶圆，以与所述第一电容孔相连通；
    于所述第一电容孔的侧壁、所述第一电容孔的底部及所述第二电容孔的侧壁形成第一电极层；
    依次去除所述第二衬底、所述第二牺牲层及所述第一牺牲层；
    于所述第一电极层的表面形成电容介质层；
    于所述电容介质层的表面形成第二电极层。
  8. 根据权利要求7所述的电容器阵列结构的制备方法，其中，形成第一电容孔之后，且提供键合晶圆之前还包括于所述第一电容孔内形成填充牺牲层，所述填充牺牲层填满所述第一电容孔的步骤；形成第二电容孔之后，且形成第一电极层之前还包括去除所述填充牺牲层的步骤。
  9. 根据权利要求8所述的电容器阵列结构的制备方法，其中，所述第一牺牲层及所述第二牺牲层为氧化硅层，所述填充牺牲层为多晶硅层。
  10. 根据权利要求8所述的电容器阵列结构的制备方法，其中，所述于所述第一电容孔内形成填充牺牲层之后，且将所述键合晶圆键合于所述叠层结构上之前还包括于所述叠层结构的表面形成第四支撑层的步骤，所述第四支撑层覆盖所述叠层结构的上表面及所述填充牺牲层的上表面；所述第二牺牲层远离所述第二支撑层的表面及所述第四支撑层远离所述第一支撑层的表面为键合面。
  11. 根据权利要求8所述的电容器阵列结构的制备方法，其中，将所述键合晶圆键合于所述叠层结构上且于所述第二衬底远离所述第二支撑层的表面形成第三支撑层之前，还包括：
    对所述第二衬底进行减薄处理。
  12. 根据权利要求11所述的电容器阵列结构的制备方法，其中，减薄处理后保留的第二衬底的厚度为所述第一电容孔及所述第二电容孔总深度的四分之一。
  13. 根据权利要求10所述的电容器阵列结构的制备方法，其中，所述依次去除所述第二衬底、所述第二牺牲层及所述第一牺牲层，包括：
    于所述第三支撑层的上表面形成图形化掩膜层，所述图形化掩膜层具有多个开口图形，所述开口图形定义出开口的形状及位置；
    基于所述图形化掩膜层刻蚀所述第三支撑层，以于所述第三支撑层内形成第一开口，所述第一开口暴露出位于所述第三支撑层与所述第二支撑层之间的所述第二衬底；
    基于所述第一开口去除所述第二衬底；
    基于所述第一开口于所述第二支撑层内形成第二开口，所述第二开口暴露出所述第二牺牲层；
    去除所述第二牺牲层；
    基于第二开口于所述第四支撑层及所述第一支撑层上形成第三开口，所述第三开口暴露出所述第一牺牲层；
    基于所述第三开口去除所述第一牺牲层。
  14. 根据权利要求10所述的电容器阵列结构的制备方法，其中，形成第一电容孔之后且于所述第一电容孔内形成填充牺牲层之前，还包括于所述第一电容孔的底部形成保护层的步骤；去除所述填充牺牲层之后且形成所述第一电极层之前，还包括去除所述保护层的步骤。
  15. 根据权利要求14所述的电容器阵列结构的制备方法，其中，所述保护层包括氧化硅层，所述氧化硅层的厚度为
    Figure PCTCN2021107821-appb-100001
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128773A1 (en) * 2006-12-04 2008-06-05 Peter Moll Storage capacitor, a memory device and a method of manufacturing the same
CN107863351A (zh) * 2017-11-21 2018-03-30 长江存储科技有限责任公司 一种高堆叠层数3d nand闪存的制作方法及3d nand闪存
CN210296415U (zh) * 2019-10-11 2020-04-10 长鑫存储技术有限公司 存储单元及电容器结构
CN111106095A (zh) * 2018-10-29 2020-05-05 长鑫存储技术有限公司 沟槽及其形成方法、电容器的制备方法及电容器
CN111223843A (zh) * 2018-11-26 2020-06-02 长鑫存储技术有限公司 电容器阵列结构及其制造方法和包含它的半导体存储器
CN111799273A (zh) * 2020-06-11 2020-10-20 长江存储科技有限责任公司 一种半导体器件及其制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128773A1 (en) * 2006-12-04 2008-06-05 Peter Moll Storage capacitor, a memory device and a method of manufacturing the same
CN107863351A (zh) * 2017-11-21 2018-03-30 长江存储科技有限责任公司 一种高堆叠层数3d nand闪存的制作方法及3d nand闪存
CN111106095A (zh) * 2018-10-29 2020-05-05 长鑫存储技术有限公司 沟槽及其形成方法、电容器的制备方法及电容器
CN111223843A (zh) * 2018-11-26 2020-06-02 长鑫存储技术有限公司 电容器阵列结构及其制造方法和包含它的半导体存储器
CN210296415U (zh) * 2019-10-11 2020-04-10 长鑫存储技术有限公司 存储单元及电容器结构
CN111799273A (zh) * 2020-06-11 2020-10-20 长江存储科技有限责任公司 一种半导体器件及其制造方法

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