WO2022205683A1 - 存储器电路、存储器预充电的控制方法及设备 - Google Patents

存储器电路、存储器预充电的控制方法及设备 Download PDF

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Publication number
WO2022205683A1
WO2022205683A1 PCT/CN2021/106734 CN2021106734W WO2022205683A1 WO 2022205683 A1 WO2022205683 A1 WO 2022205683A1 CN 2021106734 W CN2021106734 W CN 2021106734W WO 2022205683 A1 WO2022205683 A1 WO 2022205683A1
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Prior art keywords
terminal
unit
memory
data
control
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PCT/CN2021/106734
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English (en)
French (fr)
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张良
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长鑫存储技术有限公司
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Priority to US17/470,895 priority Critical patent/US11705167B2/en
Publication of WO2022205683A1 publication Critical patent/WO2022205683A1/zh

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to a memory circuit, a control method for precharging memory, an electronic device, and a computer device.
  • the data line needs to be precharged to a predetermined voltage, that is, a precharge operation is performed.
  • the present application provides a memory circuit, including: a precharge circuit, including a first precharge unit, a second precharge unit, a first power supply terminal, a second power supply terminal, a first control terminal, a second control terminal and a data terminal ;
  • the first pre-charging unit is connected to the first power terminal, the first control terminal and the data terminal;
  • the second pre-charging unit is connected to the second power terminal and the second control terminal is connected to the data terminal;
  • the first power terminal is input with a first precharge voltage
  • the second power terminal is input with a second precharge voltage;
  • control circuit the first output end of the control circuit is connected to the first control end, and the second output end of the control circuit is connected to the second control end; the control circuit is used for:
  • the second precharging unit controls the conduction between the data terminal and the second power terminal
  • the first precharging unit controls the data terminal and the second power terminal. Disconnect between a power supply terminal;
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal
  • the first precharging unit controls the disconnection between the data terminal and the second power terminal. controlling the disconnection between the data terminal and the first power terminal
  • the second precharge unit controls the disconnection between the data terminal and the second power terminal, and the second precharge unit controls the disconnection between the data terminal and the second power terminal
  • a pre-charging unit controls conduction between the data terminal and the first power terminal
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal
  • the first precharging unit controls the disconnection between the data terminal and the second power terminal.
  • the charging unit controls the disconnection between the data terminal and the first power terminal.
  • the present application also provides an electronic device including the memory circuit as described above.
  • the present application also provides a control method for precharging a memory, which is applied to a precharging circuit of a memory, where the precharging circuit includes a first precharging unit, a second precharging unit, a first power supply terminal, a second power supply terminal, a first power supply terminal, and a second power supply terminal. a control terminal, a second control terminal and a data terminal; the first precharging unit is connected to the first power terminal, the first control terminal and the data terminal; the second precharging unit is connected to the The second power terminal, the second control terminal and the data terminal are connected; the first power terminal is input with a first precharge voltage, and the second power terminal is input with a second precharge voltage; the method includes:
  • the second precharging unit controls the conduction between the data terminal and the second power terminal, and the first precharging unit controls the data terminal and all The first power supply terminal is disconnected;
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal
  • the first precharging unit controls the disconnection between the data terminal and the second power terminal. controlling the disconnection between the data terminal and the first power terminal
  • the second precharge unit controls the disconnection between the data terminal and the second power terminal, and the second precharge unit controls the disconnection between the data terminal and the second power terminal
  • a pre-charging unit controls conduction between the data terminal and the first power terminal
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal
  • the first precharging unit controls the disconnection between the data terminal and the second power terminal.
  • the charging unit controls the disconnection between the data terminal and the first power terminal.
  • the present application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the control methods described above when the processor executes the computer program.
  • the second precharge unit is used to control the disconnection between the data terminal and the second power terminal , and the disconnection between the data terminal and the first power terminal is controlled by the first pre-charging unit. At this time, neither the first charging voltage nor the second charging voltage is input to the data terminal, so that the data line will not be charged. Precharge, so as to avoid the waste of current when the memory is in a row active state and no read or write operations are performed.
  • FIG. 1 is a structural block diagram of a memory circuit provided in an embodiment
  • FIG. 2 is a waveform diagram of each signal in a memory circuit provided in an embodiment
  • FIG. 3 is a circuit diagram of a control circuit provided in an embodiment
  • FIG. 4 is a circuit diagram of a precharge circuit provided in an embodiment
  • FIG. 5 is a flowchart of a method for controlling memory precharging provided in an embodiment.
  • Precharge circuit 11, First precharge unit; 111, First switch unit; 112, Second switch unit; 12, Second precharge unit; 121, Third switch unit; 122, Fourth switch unit; 20, a control circuit; 21, a first inversion unit; 22, a delay unit; 23, a second inversion unit; 24, a NOR gate; 25, a third inversion unit; 26, an inverter.
  • first, second, etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.
  • a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of this application.
  • Both the first resistor and the second resistor are resistors, but they are not the same resistor.
  • connection in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, units, units, etc. have electrical signals or data transmission between them.
  • FIG. 1 is a structural block diagram of a memory circuit in an embodiment.
  • the memory circuit includes a precharge circuit 10 and a control circuit 20 .
  • the precharging circuit 10 includes a first precharging unit 11 , a second precharging unit 12 , a first power terminal J11 , a second power terminal J12 , a first control terminal J13 , a second control terminal J14 and a data terminal J15 .
  • the first precharging unit 11 is connected to the first power terminal J11 , the first control terminal J13 and the data terminal J15 , and the first control terminal J13 is the control terminal of the first precharging unit 11 .
  • the second precharging unit 12 is connected to the second power terminal J12 , the second control terminal J14 and the data terminal J15 , and the second control terminal J14 is the control terminal of the second precharging unit 12 .
  • the first power terminal J11 is input with a first precharge voltage
  • the second power terminal J12 is input with a second precharge voltage.
  • the first output terminal J21 of the control circuit 20 is connected to the first control terminal J13, and the control circuit 20 controls the operation of the first precharging unit 11 by controlling the signal of the first output terminal J21 thereof. Specifically, the first precharging unit 11 controls the first precharging unit 11. A power terminal J11 and the data terminal J15 are turned on, so as to input the first precharge voltage to the data terminal J15, or the first precharge unit 11 controls the disconnection between the first power terminal J11 and the data terminal J15, so as to stop the voltage to the data terminal J15.
  • the data terminal J15 inputs the first precharging voltage; the second output terminal J22 of the control circuit 20 is connected to the second control terminal J14, and the control circuit 20 also controls the second precharging unit 12 to work by controlling the signal of the second output terminal J22 thereof, Specifically, the second precharging unit 12 controls the conduction between the second power terminal J12 and the data terminal J15, so as to input the second precharging voltage to the data terminal J15, or controls the second power terminal J12 through the second precharging unit 12. It is disconnected from the data terminal J15, thereby stopping the input of the second precharge voltage to the data terminal J15.
  • the first precharge voltage and the second precharge voltage can be set according to actual requirements, and the two can be set to be unequal.
  • the data terminal J15 can be connected to the data line in the memory.
  • the data line in this embodiment may be a local data line (LIO, local input output, also referred to as a local input output line) in the memory.
  • the control circuit 20 is used to control the conduction between the data terminal J15 and the second power terminal J12 through the second precharging unit 12, and control the data terminal J15 and the second power terminal J12 through the first precharging unit 11 when the memory is not in the row active state.
  • the first power terminal J11 is disconnected; when the memory is in the row active state and no read and write operations are performed, the second precharge unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12, and the first precharge unit 12 is used to control the disconnection between the data terminal J15 and the second power terminal J12
  • the charging unit 11 controls the disconnection between the data terminal J15 and the first power terminal J11; when the memory is in the row active state, and within a preset time after the start of the read and write operations, the second precharging unit 12 controls the data terminal J15 and the second power terminal J15.
  • the power terminals J12 are disconnected, and the first precharging unit 11 controls the conduction between the data terminal J15 and the first power terminal J11; when the memory is in the row active state, and after a preset time after the start of the read and write operations, the The second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12, and the first precharging unit 11 controls the disconnection between the data terminal J15 and the first power terminal J11.
  • control circuit 20 may have a first input (not shown in FIG. 1 ) and a second input (not shown in FIG. 1 ).
  • the first input terminal of the control circuit 20 can be connected to the row activation signal line of the memory to obtain the row activation signal of the memory.
  • the control circuit 20 can determine whether the memory is in the row activation state according to the row activation signal of the memory.
  • the second input terminal of the control circuit 20 can be connected to the read and write signal lines of the memory to obtain the read and write signals of the memory.
  • the control circuit 20 can determine whether the memory starts to read and write according to the read and write signals of the memory.
  • control circuit 20 can also determine whether the memory is in a row active state and whether to start a read-write operation by other methods.
  • control circuit 20 determines whether the memory is in the row active state according to the row activation signal of the memory, and determines whether the memory starts to read or write according to the read and write signals of the memory, please refer to FIG. 1 and FIG. 2 , when the row activation signal When Row active is high level, the memory is in the row active state, when the row active signal Row active is low level, the memory is not in the row active state; when the read and write signal Read/Write is high, the memory performs read and write operations, when the read and write signal Read When /Write is low, the memory is not being read or written.
  • the control circuit 20 controls the first control signal EqHigh output to the first control terminal J13 of the precharge circuit 10 (the control terminal of the first precharge unit 11 ) according to the row activation signal Row active, and the first precharge unit 11 according to the first control
  • the signal EqHigh controls whether the connection between the first power terminal J11 and the data terminal J15 is conducted, thereby controlling whether to input the first precharge voltage to the data terminal J15.
  • the control circuit 20 controls the second control signal Eq output to the second control terminal J14 of the precharge circuit 10 (the control terminal of the second precharge unit 12 ) according to the read/write signal Read/Write.
  • the control signal Eq controls whether the connection between the second power terminal J12 and the data terminal J15 is conducted, thereby controlling whether to input the second precharge voltage to the data terminal J15.
  • the row active signal Row active is at a low level, and the memory is not in a row active state.
  • the control circuit 20 controls the second control signal Eq output by the second output terminal J22 to be a high level, and the control terminal of the second pre-charging unit 12 controls the conduction between the second power terminal J12 and the data terminal J15 after receiving the high level.
  • the control circuit 20 also controls the first control signal EqHigh output by the first output terminal J21 to be a high level, and the control terminal of the first pre-charging unit 11 controls the first power terminal J11 and the data terminal J15 after receiving the high level Therefore, when the memory is not in the row active state, the memory circuit inputs the second precharge voltage to the data line through the data terminal J15.
  • the row activation signal Row active is high, and the memory is in the row activation state; and the read and write signal Read/Write is low, and the memory does not perform read and write operations.
  • the control circuit 20 controls the second control signal Eq output by the second output terminal J22 to be a low level, and the control terminal of the second pre-charging unit 12 controls the disconnection between the second power terminal J12 and the data terminal J15 after receiving the low level ;
  • the control circuit 20 also controls the first control signal EqHigh output by its first output terminal J21 to be a high level, and the control terminal of the first pre-charging unit 11 controls the connection between the first power supply terminal J11 and the data terminal J15 after receiving the high level Therefore, when the memory is in the row active state and no read and write operations are performed, the memory circuit does not input the first precharge voltage to the data line through the data terminal J15, nor does it input the second precharge voltage to the data line through the data terminal J15. voltage, no precharge operation is performed at this time.
  • the row activation signal Row active is at a high level, and the memory is in a row activation state; and the read/write signal Read/Write is at a high level, and the memory starts to perform read and write operations.
  • the control circuit 20 controls the second control signal Eq output by the second output terminal J22 to be a low level, and the control terminal of the second pre-charging unit 12 controls the disconnection between the second power terminal J12 and the data terminal J15 after receiving the low level
  • the control circuit 20 also controls the first control signal EqHigh output by its first output terminal J21 to be a low level, and the control terminal of the first pre-charging unit 11 controls the first power supply terminal J11 and the data terminal J15 after receiving the low level Therefore, when the memory is in the row active state and within the preset time t3 after the start of the read and write operation, the memory circuit inputs the first precharge voltage to the data line through the data terminal J15 to prepare for subsequent data read and write.
  • the row activation signal Row active is at a high level, and the memory is in a row activation state; and after the read and write operations start (when the rising edge of the read and write signal Read/Write comes, the memory begins to read and write operations).
  • the control circuit 20 controls the second control signal Eq output by the second output terminal J22 to be a low level, and the control terminal of the second pre-charging unit 12 controls the disconnection between the second power terminal J12 and the data terminal J15 after receiving the low level ;
  • the control circuit 20 also controls the first control signal EqHigh output by its first output terminal J21 to be a high level, and the control terminal of the first pre-charging unit 11 controls the connection between the first power supply terminal J11 and the data terminal J15 after receiving the high level Therefore, when the memory is in the row active state, and after the preset time t3 after the start of the read and write operation, the memory circuit does not input the first precharge voltage to the data line through the data terminal J15, nor does it pass the data terminal J15 to the data line.
  • the storage array is reading and writing data.
  • the voltage on the data line is determined by the data (0 or 1) stored in the memory cell; during the write operation, the voltage on the data line is determined by the externally written data. Decide.
  • the row activation signal Row active is at a low level, the memory is in a row activated state, and when the read/write signal Read/Write is at a high level, the memory does not perform read and write operations, and the control circuit 20 controls the first output terminal J21 of its own to output the first output.
  • a control signal EqHigh is at a high level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be at a low level.
  • the row activation signal Row active is at a low level, the memory is in a row activated state, and when the read/write signal Read/Write is at a low level, the memory performs a read and write operation, and within a preset time period after the start of the read and write operation, the control circuit 20 controls The first control signal EqHigh output by its own first output terminal J21 is low level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be low level.
  • the memory When the row activation signal Row active is at a low level, the memory is in a row activated state, and when the read/write signal Read/Write is at a low level, the memory performs a read and write operation, and after a preset time after the start of the read and write operation, the control circuit 20 controls its The first control signal EqHigh output by its own first output terminal J21 is high level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be low level.
  • the memory When the row activation signal Row active is at a high level, the memory is in a row activated state, and when the read/write signal Read/Write is at a low level, the memory does not perform read and write operations, and the control circuit 20 controls the first output terminal J21 of its own to output the first output.
  • a control signal EqHigh is at a low level, and when the control terminal of the first pre-charging unit 11 receives a low level, it controls the disconnection between the first power terminal J11 and the data terminal J15; the control circuit 20 also controls its own second output terminal J22
  • the outputted second control signal Eq is at a high level, and when the control terminal of the second precharging unit 12 receives a high level, it controls the connection between the second power terminal J12 and the data terminal J15 to be disconnected.
  • the control circuit 20 controls The first control signal EqHigh output by its own first output terminal J21 is a high level, and when the control terminal of the first pre-charging unit 11 receives a high level, it controls the conduction between the first power supply terminal J11 and the data terminal J15; control The circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be a high level, and when the control terminal of the second precharging unit 12 receives a high level, it controls the second power supply terminal J12 and the data terminal J15 to be disconnected.
  • the control circuit 20 controls the The first control signal EqHigh output by the first output terminal J21 of its own is a low level, and when the control terminal of the first pre-charging unit 11 receives a low level, it controls the disconnection between the first power supply terminal J11 and the data terminal J15; the control circuit 20 It also controls the second control signal Eq output by its own second output terminal J22 to be at a high level, and when the control terminal of the second precharging unit 12 receives a high level, it controls the second power supply terminal J12 and the data terminal J15 to be disconnected.
  • the row activation signal Row active and the row activation state of the memory can also be There are other ways, which will not be repeated here.
  • the second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12, and the first precharging unit 11 controls the data terminal.
  • the connection between J15 and the first power terminal J11 is disconnected.
  • the first charging voltage is not input to the data terminal J15
  • the second charging voltage is not input to the data terminal J15, so that the data line will not be pre-charged, so as to avoid the The waste of current when the memory is row-active and not being read or written.
  • the first precharge voltage is the power supply voltage VCCA of the memory
  • the second precharge voltage is half the power supply voltage of the memory, ie, 1/2 VCCA.
  • the magnitudes of the first precharge voltage and the second precharge voltage may also be set according to actual requirements.
  • the memory performs multiple reads and writes in one cycle of the row active state of the memory, and in one cycle of the row active state of the memory, the control circuit 20 controls the data terminal through the first precharge unit 11 when each read and write starts.
  • the connection between J15 and the first power terminal J11 is turned on and turned off after a preset time.
  • the first control signal EqHigh output by the first output terminal J21 of the control circuit 20 jumps to a low level again and remains low The level jumps to a high level after a preset time t3. And so on until the memory is not row active.
  • the first precharge circuit 10 controls the conduction between the first power terminal J11 and the data terminal J15, and the first power terminal J11 inputs the first precharge to the data terminal J15.
  • the first pre-charging circuit 10 controls the disconnection between the first power terminal J11 and the data terminal J15, and the first power terminal J11 stops inputting the first pre-charging voltage to the data terminal J15 .
  • the row activation signal Row active is input to the first input terminal J23 of the control circuit 20, and the read/write signal Read/Write is input to the second input terminal J24 of the control circuit 20.
  • the row activation signal Row active is at a low level, the memory is not in a row activation state; when the row activation signal Row active is at a high level, the memory is in a row activation state.
  • the read/write signal Read/Write is at a low level, the memory does not perform a read/write operation; when the read/write signal Read/Write is at a high level, the memory performs a read/write operation.
  • the control circuit 20 includes a first inversion unit 21 , a delay unit 22 , a second inversion unit 23 , a NOR gate 24 and a third inversion unit 25 .
  • the input terminal of the first inverting unit 21 is the first input terminal J23 of the control circuit 20, that is, the input signal of the input terminal of the first inverting unit 21 is the row activation signal Row active.
  • the first inverting unit 21 has a first output terminal, and the first output terminal of the first inverting unit 21 is the second output terminal J22 of the control circuit 20 .
  • the first output terminal of the first inversion unit 21 is used to output the inverted signal of the row activation signal Row active, so that the second control signal Eq output by the control circuit 20 to the control terminal of the second precharge unit 12 is the row activation signal Row active Inverted signal.
  • the row activation signal Row active input to the input terminal of the first inversion unit 21 is at a low level, and the memory is not in the row activation state.
  • the first inversion unit The second control signal Eq output by the first output terminal of 21 is a high level, and the control terminal of the second precharging unit 12 controls the conduction between the second power terminal J12 and the data terminal J15 after receiving the high level, and the second The power terminal J12 inputs the second precharge voltage to the data terminal J15.
  • the row activation signal Row active input to the input terminal of the first inversion unit 21 is at a high level, and the memory is in the row activation state.
  • the first inversion unit 21 The second control signal Eq outputted by the first output terminal of the second pre-charging unit 12 is low level, the control terminal of the second precharging unit 12 controls the disconnection between the second power terminal J12 and the data terminal J15 after receiving the low level, and the second power terminal J12 stops inputting the second precharge voltage to the data terminal J15.
  • the first inverting unit 21 also has a second output terminal (refer to point A in FIG. 3 ), and the second output terminal of the first inverting unit 21 is used to output the inverted signal of the row activation signal Row active.
  • the NOR gate 24 can be a three-input NOR gate, the second output terminal of the first inverting unit 21 is connected to the first input terminal of the NOR gate 24, and the signal input to the first input terminal of the NOR gate 24 is row activation. Signal Row active inverted signal.
  • the input terminal of the delay unit 22 is connected to the input terminal of the second inversion unit 23 and is used as the second input terminal J24 of the control circuit 20, that is, the input terminal of the delay unit 22 and the input terminal of the second inversion unit 23 are input.
  • the signals are both read and write signals Read/Write.
  • the delay unit 22 is used to output the read/write signal Read/Write after a preset time delay, and the second input end of the NOR gate 24 is connected to the output end of the delay unit 22 (see point B in FIG.
  • the signal input to the second input terminal of the gate 24 is the signal after the read/write signal Read/Write is delayed by a preset time.
  • the second inversion unit 23 is used for outputting the inverted signal of the read/write signal Read/Write, and the third input end of the NOR gate 24 is connected to the output end of the second inversion unit 23 (refer to point C in FIG.
  • the signal input to the third input terminal of the NOR gate 24 is the inverted signal of the read/write signal Read/Write.
  • the output terminal of the NOR gate 24 (see point D in FIG. 3 ) is connected to the input terminal of the third inverting unit 25 .
  • the third inversion unit 25 is configured to invert and output the signal input from the input terminal of the third inversion unit 25 , and the output terminal of the third inversion unit 25 is the first output terminal J21 of the control circuit 20 .
  • the row activation signal Row active input to the input terminal of the first inversion unit 21 is at a high level, and the memory is in a row activation state.
  • the first inversion unit 21 The signal output from the second output terminal of , that is, the signal at point A is low level, that is, the signal input to the first input terminal of the NOR gate 24 is low level.
  • the input terminal of the delay unit 22 and the input terminal of the second inversion unit 23 input the read/write signal Read/Write as low level, the memory does not perform read and write operations, and the delay unit 22 is the second input of the NOR gate 24.
  • the signal output from the terminal is the signal after the read/write signal Read/Write is delayed by a preset time, that is, the signal at point B, which is still low.
  • the signal input by the third input terminal of the NOR gate 24, that is, the signal at point C is high, so the signal output by the output terminal of the NOR gate 24 is D point signal is low level.
  • the output terminal of the third inversion unit 25 inputs a high level to the control terminal of the first precharging unit 11, so that the first precharging unit 11 controls the first power supply terminal J11 and the The data terminals J15 are disconnected, and the first power terminal J11 stops inputting the first precharge voltage to the data terminal J15.
  • the row activation signal Row active input from the input terminal of the first inversion unit 21 is at a high level, the memory is in a row activation state, and the first inversion unit 21 reverses the phase Afterwards, the signal output from the second output terminal of the first inverting unit 21 , that is, the signal at point A is low level, that is, the signal input to the first input terminal of the NOR gate 24 is low level.
  • the input terminal of the delay unit 22 and the input terminal of the second inversion unit 23 input the read/write signal Read/Write as a high level, the memory performs read and write operations, and the delay unit 22 sends to the second input terminal of the NOR gate 24
  • the output signal is the signal after the read/write signal Read/Write is delayed by the preset time, that is, the signal at point B, which is still low level.
  • the signal input from the third input terminal of the NOR gate 24, that is, the signal at point C is low, so the signal output from the output terminal of the NOR gate 24 is D point signal is high level.
  • the output terminal of the third inversion unit 25 inputs a low level to the control terminal of the first precharging unit 11, so that the first precharging unit 11 controls the first power supply terminal J11 and the The data terminals J15 are turned on, and the first power terminal J11 inputs a first precharge voltage to the data terminal J15.
  • the row activation signal Row active input by the input terminal of the first inverting unit 21 is at a high level, and the memory is in a row activation state.
  • the signal output by the second output terminal of the first inversion unit 21 that is, the signal at point A is low level, that is, the signal input to the first input terminal of the NOR gate 24 is low level.
  • the input terminal of the delay unit 22 and the input terminal of the second inversion unit 23 input the read/write signal Read/Write as a high level, the memory performs read and write operations, and the delay unit 22 sends to the second input terminal of the NOR gate 24
  • the output signal is the signal after the read/write signal Read/Write is delayed by the preset time t3, that is, the signal at point B, which is a high level.
  • the signal input by the third input terminal of the NOR gate 24, that is, the signal at point C is low level, so the signal output by the output terminal of the NOR gate 24 is low level.
  • the output terminal of the third inversion unit 25 inputs a high level to the control terminal of the first precharging unit 11, so that the first precharging unit 11 controls the first power supply terminal J11 and the The data terminals J15 are disconnected, and the first power terminal J11 stops inputting the first precharge voltage to the data terminal J15.
  • the row activation signal Row active input by the input terminal of the first inverting unit 21 is at a high level, and the memory is in the row activation state.
  • the signal output by the second output terminal of the first inversion unit 21 that is, the signal at point A is low level, that is, the signal input to the first input terminal of the NOR gate 24 is low level.
  • the input terminal of the delay unit 22 and the input terminal of the second inversion unit 23 input the read/write signal Read/Write as low level, the memory does not perform read and write operations, and the delay unit 22 is the second input of the NOR gate 24.
  • the signal output from the terminal is the signal after the read/write signal Read/Write is delayed for a preset time t3, that is, the signal at point B. After the read/write signal Read/Write jumps to a low level, it still maintains a high level for a preset time t3 Then jump to low level again.
  • the signal input from the third input terminal of the NOR gate 24, that is, the signal at point C is at a high level. Therefore, regardless of whether the signal at point B is at a high level or a low level in the time period of t6, the signal output by the output terminal of the NOR gate 24, that is, the signal at point D is always at a low level.
  • the output terminal of the third inversion unit 25 inputs a high level to the control terminal of the first precharging unit 11, so that the first precharging unit 11 controls the first power supply terminal J11 and the The data terminals J15 are disconnected, and the first power terminal J11 stops inputting the first precharge voltage to the data terminal J15.
  • the first inverter unit 21 includes N inverters 26 connected in series in sequence, and the output terminal of the last inverter 26 in the first inverter unit 21 is the first inverter unit 21 , the output end of the Nxth inverter 26 in the first inversion unit 21 is the second output end of the first inversion unit 21 .
  • N and Nx are positive odd numbers and Nx is less than or equal to N.
  • N is equal to 3 and Nx is equal to 1.
  • the delay unit 22 includes M inverters 26 connected in series. Among them, M is a positive even number. In the example of Figure 3, M is equal to six. In other examples, the delay unit 22 may also adopt any other circuit structure well known to those skilled in the art.
  • the second inverter unit 23 includes Q inverters 26 connected in series. where Q is a positive odd number. In the example of Figure 3, Q is equal to one.
  • the third inverter unit 25 includes P inverters 26 connected in series. Among them, P is a positive odd number. In the example of Figure 3, P is equal to 1.
  • N and N x in the first inversion unit 21 , M in the delay unit 22 , Q in the second inversion unit 23 , and P in the third inversion unit 25 are not limited to the numbers in the example in FIG. 3 . .
  • the data terminal J15 includes a first data terminal J151 and a second data terminal J152 , and the first data terminal J151 and the second data terminal J152 receive mutually opposite data signals.
  • the first data terminal J151 may be connected to the local data line to receive the LIO signal; the second data terminal J152 may be connected to the complementary local data line to receive the LIO_ signal.
  • the first precharging unit 11 includes a first switching unit 111 and a second switching unit 112 .
  • the first electrical connection terminal of the first switch unit 111 and the first electrical connection terminal of the second switch unit 112 are both connected to the first power terminal J11, and the first power terminal J11 inputs the first precharge voltage V1.
  • the control terminal of the first switch unit 111 and the control terminal of the second switch unit 112 are both connected to the first control terminal J13 to obtain the first control signal EqHigh.
  • the second electrical connection terminal of the first switch unit 111 is connected to the first data terminal J151, and the second electrical connection terminal of the second switch unit 112 is connected to the second data terminal J152.
  • the switching characteristics of the first switch unit 111 and the second switch unit 112 may be the same, and the first control signal EqHigh output by the first output terminal J21 of the control circuit 20 controls the first electrical connection terminal and the second electrical connection of the first switch unit 111 Conduction between the terminals, and also controls the conduction between the first electrical connection terminal and the second electrical connection terminal of the second switch unit 112, so that the first power terminal J11 is connected to the first data terminal J151 and the second data terminal J152 at the same time.
  • the first precharge voltage V1 is input; or the first control signal EqHigh output by the first output terminal J21 of the control circuit 20 controls the disconnection between the first electrical connection terminal and the second electrical connection terminal of the first switching unit 111, and also controls the The first electrical connection terminal and the second electrical connection terminal of the second switch unit 112 are disconnected, so that the first power supply terminal J11 simultaneously stops inputting the first precharge voltage V1 to the first data terminal J151 and the second data terminal J152.
  • the second precharging unit 12 includes a third switching unit 121 and a fourth switching unit 122 .
  • the first electrical connection terminal of the third switch unit 121 and the first electrical connection terminal of the fourth switch unit 122 are both connected to the second power terminal J12, so that the second precharge voltage V2 is input.
  • the control terminal of the third switch unit 121 and the control terminal of the fourth switch unit 122 are both connected to the second control terminal J14, so as to obtain the second control signal Eq.
  • the second electrical connection terminal of the third switch unit 121 is connected to the first data terminal J151, and the second electrical connection terminal of the fourth switch unit 122 is connected to the second data terminal J152.
  • the switching characteristics of the third switch unit 121 and the fourth switch unit 122 may be the same, and the second control signal Eq output by the second output terminal J22 of the control circuit 20 controls the first electrical connection terminal and the second electrical connection of the third switch unit 121 Conduction between the terminals, and also controls the conduction between the first electrical connection terminal and the second electrical connection terminal of the fourth switch unit 122, so that the second power terminal J12 is connected to the first data terminal J151 and the second data terminal J152 at the same time.
  • the second precharge voltage V2 is input; or the second control signal Eq output by the second output terminal J22 of the control circuit 20 controls the disconnection between the first electrical connection terminal and the second electrical connection terminal of the third switch unit 121, and also controls the The first electrical connection terminal and the second electrical connection terminal of the fourth switch unit 122 are disconnected, so that the second power terminal J12 simultaneously stops inputting the second precharge voltage V2 to the first data terminal J151 and the second data terminal J152.
  • both the first switch unit 111 and the second switch unit 112 include PMOS transistors.
  • the first electrical connection terminal of the first switch unit 111 and the first electrical connection terminal of the second switch unit 112 are both the source of the PMOS transistor, and the second electrical connection terminal of the first switch unit 111 and the second electrical connection terminal of the second switch unit 112
  • the two electrical connection terminals are both the drains of the PMOS transistors, and the control terminal of the first switch unit 111 and the control terminal of the second switch unit 112 are both the gates of the PMOS transistors.
  • the first switch unit includes a PMOS transistor P1
  • the second switch unit includes a PMOS transistor P2.
  • the first control signal EqHigh When the first control signal EqHigh is at a high level, the source and drain of the PMOS transistor P1 are disconnected and the source and drain of the PMOS transistor P2 are disconnected, and the first power supply terminal J11 stops connecting to the first data terminal J151 and the first data terminal J151.
  • the second data terminal J152 inputs the first precharge voltage V1; when the first control signal EqHigh is at a low level, the source and the drain of the PMOS transistor P1 are conductive and the source and the drain of the PMOS transistor P2 are conductive
  • the first power terminal J11 inputs the first precharge voltage V1 to the first data terminal J151 and the second data terminal J152.
  • Both the third switch unit 121 and the fourth switch unit 122 include NMOS transistors.
  • the first electrical connection terminal of the third switch unit 121 and the first electrical connection terminal of the fourth switch unit 122 are both the sources of the NMOS transistors.
  • the third switch The second electrical connection terminal of the unit 121 and the second electrical connection terminal of the fourth switch unit 122 are both the drains of the NMOS transistors, and the control terminal of the third switch unit 121 and the control terminal of the fourth switch unit 122 are both NMOS transistors. gate.
  • the third switch unit includes an NMOS transistor N1
  • the fourth switch unit includes an NMOS transistor N2 .
  • the second control signal Eq When the second control signal Eq is at a high level, the source and the drain of the NMOS transistor N1 are conducting and the source and the drain of the NMOS transistor N2 are conducting, and the second power supply terminal J12 is connected to the first data terminal J151 and the second data terminal J152 input the second precharge voltage V2; when the second control signal Eq is low level, the source and drain of the NMOS transistor N1 are disconnected and the source and drain of the NMOS transistor N2 are disconnected , the second power terminal J12 stops inputting the second precharge voltage V2 to the first data terminal J151 and the second data terminal J152.
  • the present application also provides an electronic device.
  • the electronic device includes a memory circuit as in any of the above-described embodiments.
  • the second pre-charging unit controls the disconnection between the data terminal and the second power terminal
  • the first pre-charging unit controls the data terminal and the second power terminal.
  • a power supply terminal is disconnected, at this time, neither the first charging voltage nor the second charging voltage is input to the data terminal, so that the data line will not be precharged, so as to avoid the memory being in the row active state and the Waste of current when no read and write operations are performed.
  • the electronic device may be a memory, and further, the electronic device may be a dynamic random access memory (DRAM, Dynamic Random Access Memory) or the like. In other examples, the electronic device may also be any device that includes a storage device.
  • DRAM Dynamic Random Access Memory
  • the present application also provides a method for controlling memory precharge.
  • the control method of the memory precharge is applied to the precharge circuit of the memory.
  • the pre-charging circuit includes a first pre-charging unit, a second pre-charging unit, a first power terminal, a second power terminal, a first control terminal, a second control terminal and a data terminal; the first pre-charging unit and the first power terminal, The first control terminal is connected with the data terminal; the second precharging unit is connected with the second power terminal, the second control terminal and the data terminal; the first power terminal is input with the first precharge voltage, and the second power terminal is input with the second precharge voltage .
  • the control method of memory precharge includes:
  • step S51 it is determined whether the memory is in a row active state.
  • step S53 If yes, go to step S53; otherwise, go to step S52.
  • Step S52 the second precharging unit controls the conduction between the data terminal and the second power terminal, and the first precharging unit controls the disconnection between the data terminal and the first power terminal.
  • Step S53 it is judged whether the memory is performing a read and write operation.
  • step S55 If yes, go to step S55; otherwise, go to step S54.
  • Step S54 the second precharging unit controls the disconnection between the data terminal and the second power terminal
  • the first precharging unit controls the disconnection between the data terminal and the first power terminal
  • Step S55 within a preset time after the start of the read-write operation, the second pre-charging unit controls the disconnection between the data terminal and the second power terminal, and the first pre-charging unit controls the conduction between the data terminal and the first power terminal. Pass.
  • Step S56 after a preset time after the start of the read-write operation, the second precharging unit controls the disconnection between the data terminal and the second power supply terminal, and the first precharging unit controls the disconnection between the data terminal and the first power supply terminal .
  • the second precharge unit is used to control the disconnection between the data terminal and the second power terminal, and the first precharge unit controls the disconnection between the data terminal and the second power terminal.
  • the data terminal is disconnected from the first power terminal.
  • the first charging voltage is not input to the data terminal, nor the second charging voltage is input to the data terminal, so that the data line will not be pre-charged, so as to avoid the memory in the memory. Waste of current when the row is active and no read or write operations are in progress.
  • the first precharge voltage is the power supply voltage of the memory
  • the second precharge voltage is half the power supply voltage of the memory
  • the memory performs multiple reads and writes in one cycle of the row active state, and in one cycle of the row active state of the memory, the first precharge unit controls the data terminal and the first power terminal at the beginning of each read and write Turn on between and turn off after a preset time. In this way, it is not only ensured that the data lines are precharged to the power supply voltage before each data read and write to prepare for subsequent data read and write, but also current waste can be avoided when the memory is in a row-activated state and no read and write operations are performed.
  • the memory when the row activation signal is at a low level, the memory is not in a row activation state; when the row activation signal is at a high level, the memory is in a row activation state; when the read and write signal is at a low level, the memory is not in a read or write operation; When the read and write signal is high, the memory performs read and write operations.
  • steps in the flowchart of FIG. 5 are sequentially displayed according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 5 may include multiple steps or multiple stages, these steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution sequence of these steps or stages is also It does not have to be performed sequentially, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages within the other steps.
  • the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the control method in any one of the foregoing embodiments when the processor executes the computer program.

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Abstract

一种存储器电路、存储器预充电的控制方法、电子设备及计算机设备,包括:预充电电路(10),包括第一预充电单元(11)、第二预充电单元(12)、第一电源端(J11)、第二电源端(J12)、第一控制端(J13)、第二控制端(J14)及数据端(J15);第一预充电单元(11)与第一电源端(J11)、第一控制端(J13)及数据端(J15)连接;第二预充电单元(12)与第二电源端(J12)、第二控制端(J14)及数据端(J15)连接;第一电源端(J11)输入第一预充电压,第二电源端(J12)输入第二预充电压;及控制电路(20),控制电路(20)用于:当存储器处于行激活状态,且未进行读写操作时,通过第二预充电单元(12)控制数据端(J15)与第二电源端(J12)之间断开,且通过第一预充电单元(11)控制数据端(J15)与第一电源端(J11)之间断开。上述存储器电路能够避免在存储器处于行激活状态且未进行读写操作时对电流的浪费。

Description

存储器电路、存储器预充电的控制方法及设备
本申请要求于2021年3月31日提交中国专利局,申请号为2021103525016,申请名称为“存储器电路、存储器预充电的控制方法及设备”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域,特别是涉及一种存储器电路、存储器预充电的控制方法、电子设备及计算机设备。
背景技术
在存储器工作过程中需要将数据线预充电到预定的电压,即进行预充电(precharge)操作。
传统的存储器每次进入行激活状态,则存储阵列(array)中的数据线被输入预定的电压,从而为后续的读写操作做准备。如此,会增加激活(active)电流IDD0,若在行激活状态下没有进行后续的读写操作,则这部分电流被浪费掉。
发明内容
本申请提供了一种存储器电路,包括:预充电电路,包括第一预充电单元、第二预充电单元、第一电源端、第二电源端、第一控制端、第二控制端及数据端;所述第一预充电单元与所述第一电源端、所述第一控制端及所述数据端连接;所述第二预充电单元与所述第二电源端、所述第二控制端及所述数据端连接;所述第一电源端输入第一预充电压,所述第二电源端输入第二预充电压;及
控制电路,所述控制电路的第一输出端与所述第一控制端连接,所述控制电路的第二输出端与所述第二控制端连接;所述控制电路用于:
当存储器未处于行激活状态时,通过所述第二预充电单元控制所述数据端与第二电源端之间导通,且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开;
当所述存储器处于行激活状态,且未进行读写操作时,通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开,且通过所述第一预充电单元控制所述数据端与第 一电源端之间断开;
当所述存储器处于行激活状态,且读写操作开始后的预设时间内,通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开,且通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通;
当所述存储器处于行激活状态,且读写操作开始后的预设时间之后,通过所述第二预充电单元控制所述数据端与第二电源端之间断开,且通过所述第一预充电单元控制所述数据端与第一电源端之间断开。
本申请还提供一种电子设备,包括如上述所述的存储器电路。
本申请还提供一种存储器预充电的控制方法,应用于存储器的预充电电路,所述预充电电路包括第一预充电单元、第二预充电单元、第一电源端、第二电源端、第一控制端、第二控制端及数据端;所述第一预充电单元与所述第一电源端、所述第一控制端及所述数据端连接;所述第二预充电单元与所述第二电源端、所述第二控制端及所述数据端连接;所述第一电源端输入第一预充电压,所述第二电源端输入第二预充电压;所述方法包括:
当所述存储器未处于行激活状态时,通过所述第二预充电单元控制所述数据端与第二电源端之间导通,且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开;
当所述存储器处于行激活状态,且未进行读写操作时,通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开,且通过所述第一预充电单元控制所述数据端与第一电源端之间断开;
当所述存储器处于行激活状态,且读写操作开始后的预设时间内,通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开,且通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通;
当所述存储器处于行激活状态,且读写操作开始后的预设时间之后,通过所述第二预充电单元控制所述数据端与第二电源端之间断开,且通过所述第一预充电单元控制所述数据端与第一电源端之间断开。
本申请还提供一种计算机设备,包括存储器和处理器,所述存储器存储有计算机程序,所述处理器执行所述计算机程序时实现如上任一项所述的控制方法的步骤。
上述存储器电路、存储器预充电的控制方法、电子设备及计算机设备当存储器处于行激活状态,且未进行读写操作时,通过第二预充电单元控制数据端与所述第二电源端之间断开,且通过第一预充电单元控制数据端与第一电源端之间断开,此时没有向数据端输入 第一充电电压,也没有向数据端输入第二充电电压,使得不会向数据线进行预充电,从而能够避免在存储器处于行激活状态且未进行读写操作时对电流的浪费。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案,下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为一实施例中提供的存储器电路的结构框图;
图2为一实施例中提供的存储器电路中各信号的波形图;
图3为一实施例中提供的控制电路的电路图;
图4为一实施例中提供的预充电电路的电路图;
图5为一实施例中提供的存储器预充电的控制方法的流程图。
附图标记说明:
10、预充电电路;11、第一预充电单元;111、第一开关单元;112、第二开关单元;12、第二预充电单元;121、第三开关单元;122、第四开关单元;20、控制电路;21、第一反相单元;22、延时单元;23、第二反相单元;24、或非门;25、第三反相单元;26、反相器。
具体实施方式
为了便于理解本申请,下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是,本申请可以以许多不同的形式来实现,并不限于本文所描述的实施例。相反地,提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义,本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本申请。
可以理解,本申请所使用的术语“第一”、“第二”等可在本文中用于描述各种元件,但这些元件不受这些术语限制。这些术语仅用于将第一个元件与另一个元件区分。举例来说,在不脱离本申请的范围的情况下,可以将第一电阻称为第二电阻,且类似地,可将第二电阻称为第一电阻。第一电阻和第二电阻两者都是电阻,但其不是同一电阻。
可以理解,以下实施例中的“连接”,如果被连接的电路、单元、单元等相互之间具有电信号或数据的传递,则应理解为“电连接”、“通信连接”等。
在此使用时,单数形式的“一”、“一个”和“所述/该”也可以包括复数形式,除非上下文清楚指出另外的方式。还应当理解的是,术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在,但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时,在本说明书中使用的术语“和/或”包括相关所列项目的任何及所有组合。
图1为一实施例中的存储器电路的结构框图。如图1所示,存储器电路包括预充电电路10及控制电路20。预充电电路10包括第一预充电单元11、第二预充电单元12、第一电源端J11、第二电源端J12、第一控制端J13、第二控制端J14及数据端J15。第一预充电单元11与第一电源端J11、第一控制端J13及数据端J15连接,第一控制端J13即为第一预充电单元11的控制端。第二预充电单元12与第二电源端J12、第二控制端J14及数据端J15连接,第二控制端J14即为第二预充电单元12的控制端。第一电源端J11输入第一预充电压,第二电源端J12输入第二预充电压。
控制电路20的第一输出端J21与第一控制端J13连接,控制电路20通过控制其第一输出端J21的信号控制第一预充电单元11工作,具体为通过第一预充电单元11控制第一电源端J11与数据端J15之间导通,从而向数据端J15输入第一预充电压,或者通过第一预充电单元11控制第一电源端J11与数据端J15之间断开,从而停止向数据端J15输入第一预充电压;控制电路20的第二输出端J22与第二控制端J14连接,控制电路20还通过控制其第二输出端J22的信号控制第二预充电单元12工作,具体为通过第二预充电单元12控制第二电源端J12与数据端J15之间导通,从而向数据端J15输入第二预充电压,或者通过第二预充电单元12控制第二电源端J12与数据端J15之间断开,从而停止向数据端J15输入第二预充电压。第一预充电压和第二预充电压可以根据实际需求进行设置,两者可以设置为不相等。数据端J15可以连接存储器中的数据线。本实施例中的数据线可以是存储器中的局部数据线(LIO,local input output,也可以称为本地输入输出线)。
控制电路20用于:当存储器未处于行激活状态时,通过第二预充电单元12控制数据端J15与第二电源端J12之间导通,且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开;当存储器处于行激活状态,且未进行读写操作时,通过第二预充电单元12控制数据端J15与第二电源端J12之间断开,且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开;当存储器处于行激活状态,且读写操作开始后的预设时间内, 通过第二预充电单元12控制数据端J15与第二电源端J12之间断开,且通过第一预充电单元11控制数据端J15与第一电源端J11之间导通;当存储器处于行激活状态,且读写操作开始后的预设时间之后,通过第二预充电单元12控制数据端J15与第二电源端J12之间断开,且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开。
在一些示例中,控制电路20可以具有第一输入端(图1未示出)和第二输入端(图1未示出)。控制电路20的第一输入端可以与存储器的行激活信号线连接,从而获取存储器的行激活信号,控制电路20可以根据存储器的行激活信号判断存储器是否处于行激活状态。控制电路20的第二输入端可以与存储器的读写信号线连接,从而获取存储器的读写信号,控制电路20可以根据存储器的读写信号判断存储器是否开始读写操作。
在其他示例中,控制电路20也可以通过其他方式来判断存储器是否处于行激活状态及是否开始读写操作。
在一些示例中,当控制电路20根据存储器的行激活信号判断存储器是否处于行激活状态,且根据存储器的读写信号判断存储器是否开始读写操作时,请参阅图1和图2,当行激活信号Row active为高电平时存储器处于行激活状态,当行激活信号Row active为低电平时存储器未处于行激活状态;当读写信号Read/Write为高电平时存储器进行读写操作,当读写信号Read/Write为低电平时存储器未进行读写操作。控制电路20根据行激活信号Row active控制向预充电电路10的第一控制端J13(第一预充电单元11的控制端)输出的第一控制信号EqHigh,第一预充电单元11根据第一控制信号EqHigh控制第一电源端J11与数据端J15之间是否导通,从而控制是否向数据端J15输入第一预充电压。控制电路20根据读写信号Read/Write控制向预充电电路10的第二控制端J14(第二预充电单元12的控制端)输出的第二控制信号Eq,第二预充电单元12根据第二控制信号Eq控制第二电源端J12与数据端J15之间是否导通,从而控制是否向数据端J15输入第二预充电压。
在t1时间段内,行激活信号Row active为低电平,存储器未处于行激活状态。控制电路20控制其第二输出端J22输出的第二控制信号Eq为高电平,第二预充电单元12的控制端接收到高电平后控制第二电源端J12与数据端J15之间导通;控制电路20还控制其第一输出端J21输出的第一控制信号EqHigh为高电平,第一预充电单元11的控制端接收到高电平后控制第一电源端J11与数据端J15之间断开;从而当存储器未处于行激活状态时,存储器电路通过数据端J15向数据线输入第二预充电压。
在t2时间段内,行激活信号Row active为高电平,存储器处于行激活状态;且读写 信号Read/Write为低电平,存储器未进行读写操作。控制电路20控制其第二输出端J22输出的第二控制信号Eq为低电平,第二预充电单元12的控制端接收到低电平后控制第二电源端J12与数据端J15之间断开;控制电路20还控制其第一输出端J21输出的第一控制信号EqHigh为高电平,第一预充电单元11的控制端接收到高电平后控制第一电源端J11与数据端J15之间断开;从而当存储器处于行激活状态,且未进行读写操作时,存储器电路没有通过数据端J15向数据线输入第一预充电压,也没有通过数据端J15向数据线输入第二预充电压,此时没有进行预充电操作。
在预设时间t3时间段内,行激活信号Row active为高电平,存储器处于行激活状态;且读写信号Read/Write为高电平,存储器开始进行读写操作。控制电路20控制其第二输出端J22输出的第二控制信号Eq为低电平,第二预充电单元12的控制端接收到低电平后控制第二电源端J12与数据端J15之间断开;控制电路20还控制其第一输出端J21输出的第一控制信号EqHigh为低电平,第一预充电单元11的控制端接收到低电平后控制第一电源端J11与数据端J15之间导通;从而当存储器处于行激活状态,且读写操作开始后的预设时间t3内,存储器电路通过数据端J15向数据线输入第一预充电压,为后续进行数据读写做准备。
在t4时间段内,行激活信号Row active为高电平,存储器处于行激活状态;且在读写操作开始(读写信号Read/Write当上升沿到来时,存储器开始进行读写操作)后的预设时间t3之后。控制电路20控制其第二输出端J22输出的第二控制信号Eq为低电平,第二预充电单元12的控制端接收到低电平后控制第二电源端J12与数据端J15之间断开;控制电路20还控制其第一输出端J21输出的第一控制信号EqHigh为高电平,第一预充电单元11的控制端接收到高电平后控制第一电源端J11与数据端J15之间断开;从而当存储器处于行激活状态,且读写操作开始后的预设时间t3之后,存储器电路没有通过数据端J15向数据线输入第一预充电压,也没有通过数据端J15向数据线输入第二预充电压。此时存储阵列正在进行数据读写,当读操作时,数据线上的电压由存储单元中存储的数据(0或1)决定;当写操作时,数据线上的电压由外部写入的数据决定。
在另一些实施例中,也可以配置为:当行激活信号Row active为高电平时,存储器未处于行激活状态,控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为高电平;控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为高电平。当行激活信号Row active为低电平时,存储器处于行激活状态,且读写信号Read/Write为高电平时,存储器未进行读写操作,控制电路20控制其自身的第一输出端J21输出的 第一控制信号EqHigh为高电平;控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为低电平。当行激活信号Row active为低电平时,存储器处于行激活状态,且读写信号Read/Write为低电平时,存储器进行读写操作,读写操作开始后的预设时间段内,控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为低电平;控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为低电平。当行激活信号Row active为低电平时,存储器处于行激活状态,且读写信号Read/Write为低电平时,存储器进行读写操作,读写操作开始后的预设时间之后,控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为高电平;控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为低电平。
在又一些实施例中,还可以配置为:当行激活信号Row active为低电平时,存储器未处于行激活状态,控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为低电平,第一预充电单元11的控制端接收到低电平时控制第一电源端J11与数据端J15之间断开;控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为低电平,第二预充电单元12的控制端接收到低电平时控制第二电源端J12与数据端J15之间导通。当行激活信号Row active为高电平时,存储器处于行激活状态,且读写信号Read/Write为低电平时,存储器未进行读写操作,控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为低电平,第一预充电单元11的控制端接收到低电平时控制第一电源端J11与数据端J15之间断开;控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为高电平,第二预充电单元12的控制端接收到高电平时控制第二电源端J12与数据端J15之间断开。当行激活信号Row active为高电平时,存储器处于行激活状态,且读写信号Read/Write为高电平时,存储器进行读写操作,读写操作开始后的预设时间段内,控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为高电平,第一预充电单元11的控制端接收到高电平时控制第一电源端J11与数据端J15之间导通;控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为高电平,第二预充电单元12的控制端接收到高电平时控制第二电源端J12与数据端J15之间断开。当行激活信号Row active为高电平时,存储器处于行激活状态,且读写信号Read/Write为高电平时,存储器进行读写操作,读写操作开始后的预设时间之后,控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为低电平,第一预充电单元11的控制端接收到低电平时控制第一电源端J11与数据端J15之间断开;控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为高电平,第二预充电单元12的控制端接收到高电平时 控制第二电源端J12与数据端J15之间断开。
在其他示例中,行激活信号Row active与存储器的行激活状态,读写信号Read/Write与存储器读写状态,控制电路20的输入端与输出端的控制关系以及预充电电路10的控制关系还可以是其他方式,此处不再一一赘述。
上述存储器电路当存储器处于行激活状态,且未进行读写操作时,通过第二预充电单元12控制数据端J15与第二电源端J12之间断开,且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开,此时没有向数据端J15输入第一充电电压,也没有向数据端J15输入第二充电电压,使得不会向数据线进行预充电,从而能够避免在存储器处于行激活状态且未进行读写操作时对电流的浪费。
在一些示例中,第一预充电压为存储器的电源电压VCCA,第二预充电压为存储器的电源电压的一半即1/2VCCA。在其他示例中,也可以根据实际需求设置第一预充电压和第二预充电压的大小。
在一些示例中,存储器在行激活状态的一个周期内进行多次读写,在存储器的行激活状态的一个周期内,每次读写开始时控制电路20通过第一预充电单元11控制数据端J15与第一电源端J11之间导通且预设时间后断开。
仅示例性的,仍然参阅图2,在存储器的行激活状态的一个周期t5内,读写信号Read/Write出现多个高电平即进行多次读写。读写信号Read/Write第一个上升沿到来时,即第一次读写开始,控制电路20的第一输出端J21输出的第一控制信号EqHigh跳变为低电平,并维持低电平预设时间t3后跳变到高电平。直到读写信号Read/Write第二个上升沿到来时,即第二次读写开始,控制电路20的第一输出端J21输出的第一控制信号EqHigh再次跳变到低电平,并维持低电平预设时间t3后跳变到高电平。以此类推,直到存储器未处于行激活状态。本实施例中,当第一控制信号EqHigh为低电平时,第一预充电电路10控制第一电源端J11和数据端J15之间导通,第一电源端J11向数据端J15输入第一预充电压;当第一控制信号EqHigh为高电平时,第一预充电电路10控制第一电源端J11和数据端J15之间断开,第一电源端J11停止向数据端J15输入第一预充电压。
在一些示例中,控制电路20的第一输入端J23输入行激活信号Row active,控制电路20的第二输入端J24输入读写信号Read/Write。当行激活信号Row active为低电平时,存储器未处于行激活状态;当行激活信号Row active为高电平时,存储器处于行激活状态。当读写信号Read/Write为低电平时,存储器未进行读写操作;当读写信号Read/Write为高电平时,存储器进行读写操作。
在一些示例中,请参阅图1至图3,控制电路20包括第一反相单元21、延时单元22、第二反相单元23、或非门24及第三反相单元25。第一反相单元21的输入端为控制电路20的第一输入端J23,即第一反相单元21的输入端输入的信号为行激活信号Row active。第一反相单元21具有第一输出端,且第一反相单元21的第一输出端为控制电路20的第二输出端J22。第一反相单元21的第一输出端用于输出行激活信号Row active反相后的信号,使得控制电路20输出给第二预充电单元12的控制端的第二控制信号Eq为行激活信号Row active反相后的信号。
在t1时间段内,第一反相单元21的输入端输入的行激活信号Row active为低电平,存储器未处于行激活状态,经过第一反相单元21反相后,第一反相单元21的第一输出端输出的第二控制信号Eq为高电平,第二预充电单元12的控制端接收到高电平后控制第二电源端J12与数据端J15之间导通,第二电源端J12向数据端J15输入第二预充电压。
在t5时间段内,第一反相单元21的输入端输入的行激活信号Row active为高电平,存储器处于行激活状态,经过第一反相单元21反相后,第一反相单元21的第一输出端输出的第二控制信号Eq为低电平,第二预充电单元12的控制端接收到低电平后控制第二电源端J12与数据端J15之间断开,第二电源端J12停止向数据端J15输入第二预充电压。
第一反相单元21还具有第二输出端(参阅图3中A点),第一反相单元21的第二输出端用于输出行激活信号Row active反相后的信号。或非门24可以为三输入或非门,第一反相单元21的第二输出端与或非门24的第一输入端连接,或非门24的第一输入端输入的信号为行激活信号Row active反相后的信号。延时单元22的输入端和第二反相单元23的输入端连接并作为控制电路20的第二输入端J24,即延时单元22的输入端和第二反相单元23的输入端输入的信号均为读写信号Read/Write。延时单元22用于将读写信号Read/Write延迟预设时间后输出,或非门24的第二输入端与延时单元22的输出端(参阅图3中B点)连接,即或非门24的第二输入端输入的信号为读写信号Read/Write延迟预设时间后的信号。第二反相单元23用于输出读写信号Read/Write反相后的信号,或非门24的第三输入端与第二反相单元23的输出端(参阅图3中C点)连接,即或非门24的第三输入端输入的信号为读写信号Read/Write反相后的信号。或非门24的输出端(参阅图3中D点)与第三反相单元25的输入端连接。第三反相单元25用于对第三反相单元25的输入端输入的信号进行反相后输出,第三反相单元25的输出端为控制电路20的第一输出端J21。
在t2时间段内,第一反相单元21的输入端输入的行激活信号Row active为高电平, 存储器处于行激活状态,经过第一反相单元21反相后,第一反相单元21的第二输出端输出的信号即A点信号为低电平,即或非门24的第一输入端输入的信号为低电平。延时单元22的输入端和第二反相单元23的输入端输入的读写信号Read/Write为低电平,存储器未进行读写操作,延时单元22向或非门24的第二输入端输出的信号为读写信号Read/Write延时预设时间后的信号,即B点信号,仍然为低电平。读写信号Read/Write经过第二反相单元23反相后,或非门24的第三输入端输入的信号,即C点信号为高电平,从而或非门24输出端输出的信号即D点信号为低电平。经过第三反相单元25的反相后,第三反相单元25的输出端向第一预充电单元11的控制端输入高电平,从而第一预充电单元11控制第一电源端J11和数据端J15之间断开,第一电源端J11停止向数据端J15输入第一预充电压。
在存储器读写操作开始后的预设时间t3内,第一反相单元21的输入端输入的行激活信号Row active为高电平,存储器处于行激活状态,经过第一反相单元21反相后,第一反相单元21的第二输出端输出的信号即A点信号为低电平,即或非门24的第一输入端输入的信号为低电平。延时单元22的输入端和第二反相单元23的输入端输入的读写信号Read/Write为高电平,存储器进行读写操作,延时单元22向或非门24的第二输入端输出的信号为读写信号Read/Write延时预设时间后的信号,即B点信号,仍然为低电平。读写信号Read/Write经过第二反相单元23反相后,或非门24的第三输入端输入的信号,即C点信号为低电平,从而或非门24输出端输出的信号即D点信号为高电平。经过第三反相单元25的反相后,第三反相单元25的输出端向第一预充电单元11的控制端输入低电平,从而第一预充电单元11控制第一电源端J11和数据端J15之间导通,第一电源端J11向数据端J15输入第一预充电压。
在存储器读写操作开始后的预设时间t3之后,例如在t4时间段内,第一反相单元21的输入端输入的行激活信号Row active为高电平,存储器处于行激活状态,经过第一反相单元21反相后,第一反相单元21的第二输出端输出的信号即A点信号为低电平,即或非门24的第一输入端输入的信号为低电平。延时单元22的输入端和第二反相单元23的输入端输入的读写信号Read/Write为高电平,存储器进行读写操作,延时单元22向或非门24的第二输入端输出的信号为读写信号Read/Write延时预设时间t3后的信号,即B点信号,为高电平。读写信号Read/Write经过第二反相单元23反相后,或非门24的第三输入端输入的信号,即C点信号为低电平,从而或非门24输出端输出的信号为低电平。经过第三反相单元25的反相后,第三反相单元25的输出端向第一预充电单元11的控制端输 入高电平,从而第一预充电单元11控制第一电源端J11和数据端J15之间断开,第一电源端J11停止向数据端J15输入第一预充电压。
在存储器读写操作开始后的预设时间t3之后,例如在t6时间段内,第一反相单元21的输入端输入的行激活信号Row active为高电平,存储器处于行激活状态,经过第一反相单元21反相后,第一反相单元21的第二输出端输出的信号即A点信号为低电平,即或非门24的第一输入端输入的信号为低电平。延时单元22的输入端和第二反相单元23的输入端输入的读写信号Read/Write为低电平,存储器未进行读写操作,延时单元22向或非门24的第二输入端输出的信号为读写信号Read/Write延时预设时间t3后的信号,即B点信号,在读写信号Read/Write跳变到低电平之后,还维持高电平预设时间t3之后再跳变到低电平。读写信号Read/Write经过第二反相单元23反相后,或非门24的第三输入端输入的信号,即C点信号为高电平。所以,不管在t6时间段内B点的信号为高电平还是低电平,或非门24输出端输出的信号即D点信号均为低电平。经过第三反相单元25的反相后,第三反相单元25的输出端向第一预充电单元11的控制端输入高电平,从而第一预充电单元11控制第一电源端J11和数据端J15之间断开,第一电源端J11停止向数据端J15输入第一预充电压。
在一些示例中,请参阅图3,第一反相单元21包括N个依次串联的反相器26,第一反相单元21中最后一个反相器26的输出端为第一反相单元21的第一输出端,第一反相单元21中第N x个反相器26的输出端为第一反相单元21的第二输出端。其中,N、N x均为正奇数且N x小于或等于N。图3示例中,N等于3,N x等于1。
在一些示例中,请参阅图3,延时单元22包括M个依次串联的反相器26。其中,M为正偶数。图3示例中,M等于6。在其他示例中,延时单元22也可以采用其他为本领域技术人员所熟知的任意电路结构。
在一些示例中,请参阅图3,第二反相单元23包括Q个依次串联的反相器26。其中,Q为正奇数。图3示例中,Q等于1。
在一些示例中,请参阅图3,第三反相单元25包括P个依次串联的反相器26。其中,P为正奇数。图3示例中,P等于1。
需要说明的是,第一反相单元21中N和N x、延时单元22中M、第二反相单元23中Q以及第三反相单元25中P均不限于图3示例中的数量。
在一些示例中,请参阅图1和图4,数据端J15包括第一数据端J151和第二数据端J152,第一数据端J151和第二数据端J152接收互为相反的数据信号。譬如,第一数据端J151 可以与局部数据线连接,从而接收LIO信号;第二数据端J152可以与互补局部数据线连接,从而接收LIO_信号。第一预充电单元11包括第一开关单元111和第二开关单元112。第一开关单元111的第一电连接端和第二开关单元112的第一电连接端均与第一电源端J11连接,第一电源端J11输入第一预充电压V1。第一开关单元111的控制端和第二开关单元112的控制端均与第一控制端J13连接,从而获取第一控制信号EqHigh。第一开关单元111的第二电连接端与第一数据端J151连接,第二开关单元112的第二电连接端与第二数据端J152连接。
第一开关单元111和第二开关单元112的开关特性可以相同,控制电路20的第一输出端J21输出的第一控制信号EqHigh控制第一开关单元111的第一电连接端和第二电连接端之间导通,同时还控制第二开关单元112的第一电连接端和第二电连接端之间导通,使得第一电源端J11同时向第一数据端J151和第二数据端J152输入第一预充电压V1;或者控制电路20的第一输出端J21输出的第一控制信号EqHigh控制第一开关单元111的第一电连接端和第二电连接端之间断开,同时还控制第二开关单元112的第一电连接端和第二电连接端之间断开,使得第一电源端J11同时停止向第一数据端J151和第二数据端J152输入第一预充电压V1。
第二预充电单元12包括第三开关单元121和第四开关单元122。第三开关单元121的第一电连接端和第四开关单元122的第一电连接端均与第二电源端J12连接,从而输入第二预充电压V2。第三开关单元121的控制端和第四开关单元122的控制端均与第二控制端J14连接,从而获取第二控制信号Eq。第三开关单元121的第二电连接端与第一数据端J151连接,第四开关单元122的第二电连接端与第二数据端J152连接。
第三开关单元121和第四开关单元122的开关特性可以相同,控制电路20的第二输出端J22输出的第二控制信号Eq控制第三开关单元121的第一电连接端和第二电连接端之间导通,同时还控制第四开关单元122的第一电连接端和第二电连接端之间导通,使得第二电源端J12同时向第一数据端J151和第二数据端J152输入第二预充电压V2;或者控制电路20的第二输出端J22输出的第二控制信号Eq控制第三开关单元121的第一电连接端和第二电连接端之间断开,同时还控制第四开关单元122的第一电连接端和第二电连接端之间断开,使得第二电源端J12同时停止向第一数据端J151和第二数据端J152输入第二预充电压V2。
在一些示例中,第一开关单元111和第二开关单元112均包括PMOS管。第一开关单元111的第一电连接端和第二开关单元112的第一电连接端均为PMOS管的源极,第一开 关单元111的第二电连接端和第二开关单元112的第二电连接端均为PMOS管的漏极,第一开关单元111的控制端和第二开关单元112的控制端均为PMOS管的栅极。譬如,可以参阅图4,第一开关单元包括PMOS管P1,第二开关单元包括PMOS管P2。
当第一控制信号EqHigh为高电平时,PMOS管P1的源极和漏极之间断开且PMOS管P2的源极和漏极之间断开,第一电源端J11停止向第一数据端J151和第二数据端J152输入第一预充电压V1;当第一控制信号EqHigh为低电平时,PMOS管P1的源极和漏极之间导通且PMOS管P2的源极和漏极之间导通,第一电源端J11向第一数据端J151和第二数据端J152输入第一预充电压V1。
第三开关单元121和第四开关单元122均包括NMOS管,第三开关单元121的第一电连接端和第四开关单元122的第一电连接端均为NMOS管的源极,第三开关单元121的第二电连接端和第四开关单元122的第二电连接端均为NMOS管的漏极,第三开关单元121的控制端和第四开关单元122的控制端均为NMOS管的栅极。譬如,可以参阅图4,第三开关单元包括NMOS管N1,第四开关单元包括NMOS管N2。
当第二控制信号Eq为高电平时,NMOS管N1的源极和漏极之间导通且NMOS管N2的源极和漏极之间导通,第二电源端J12向第一数据端J151和第二数据端J152输入第二预充电压V2;当第二控制信号Eq为低电平时,NMOS管N1的源极和漏极之间断开且NMOS管N2的源极和漏极之间断开,第二电源端J12停止向第一数据端J151和第二数据端J152输入第二预充电压V2。
本申请还提供一种电子设备。电子设备包括如上述任意一个实施例中的存储器电路。
上述电子设备当存储器处于行激活状态,且未进行读写操作时,通过第二预充电单元控制数据端与所述第二电源端之间断开,且通过第一预充电单元控制数据端与第一电源端之间断开,此时没有向数据端输入第一充电电压,也没有向数据端输入第二充电电压,使得不会向数据线进行预充电,从而能够避免在存储器处于行激活状态且未进行读写操作时对电流的浪费。
在一些示例中,电子设备可以是存储器,进一步的,电子设备可以是动态随机存取内存(DRAM,Dynamic Random Access Memory)等等。在其他示例中,电子设备还可以是包含存储设备的任意设备。
本申请还提供一种存储器预充电的控制方法。存储器预充电的控制方法应用于存储器的预充电电路。预充电电路包括第一预充电单元、第二预充电单元、第一电源端、第二电源端、第一控制端、第二控制端及数据端;第一预充电单元与第一电源端、第一控制端及 数据端连接;第二预充电单元与第二电源端、第二控制端及数据端连接;第一电源端输入第一预充电压,第二电源端输入第二预充电压。如图5所示,存储器预充电的控制方法包括:
步骤S51,判断存储器是否处于行激活状态。
若是,则执行步骤S53;否则,执行步骤S52。
步骤S52,通过第二预充电单元控制数据端与第二电源端之间导通,且通过第一预充电单元控制数据端与第一电源端之间断开。
步骤S53,判断存储器是否进行读写操作。
若是,则执行步骤S55;否则,执行步骤S54。
步骤S54,通过第二预充电单元控制数据端与第二电源端之间断开,且通过第一预充电单元控制数据端与第一电源端之间断开。
步骤S55,读写操作开始后的预设时间内,通过第二预充电单元控制数据端与第二电源端之间断开,且通过第一预充电单元控制数据端与第一电源端之间导通。
步骤S56,读写操作开始后的预设时间之后,通过第二预充电单元控制数据端与第二电源端之间断开,且通过第一预充电单元控制数据端与第一电源端之间断开。
上述存储器预充电的控制方法当存储器处于行激活状态,且未进行读写操作时,通过第二预充电单元控制数据端与所述第二电源端之间断开,且通过第一预充电单元控制数据端与第一电源端之间断开,此时没有向数据端输入第一充电电压,也没有向数据端输入第二充电电压,使得不会向数据线进行预充电,从而能够避免在存储器处于行激活状态且未进行读写操作时对电流的浪费。
在一些示例中,第一预充电压为存储器的电源电压,第二预充电压为存储器的电源电压的一半。
在一些示例中,存储器在行激活状态一个周期内进行多次读写,在存储器的行激活状态的一个周期内,每次读写开始时通过第一预充电单元控制数据端与第一电源端之间导通且预设时间后断开。如此,既保证了在每次数据读写之前对数据线预充电到电源电压,为后续数据读写做准备,又能够避免在存储器处于行激活状态且未进行读写操作时对电流的浪费。
在一些示例中,当行激活信号为低电平时,存储器未处于行激活状态;当行激活信号为高电平时,存储器处于行激活状态;当读写信号为低电平时,存储器未进行读写操作;当读写信号为高电平时,存储器进行读写操作。
应该理解的是,虽然图5的流程图中的各个步骤按照箭头的指示依次显示,但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明,这些步骤的执行并没有严格的顺序限制,这些步骤可以以其它的顺序执行。而且,图5中的至少一部分步骤可以包括多个步骤或者多个阶段,这些步骤或者阶段并不必然是在同一时刻执行完成,而是可以在不同的时刻执行,这些步骤或者阶段的执行顺序也不必然是依次进行,而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
本申请还提供一种计算机设备,包括存储器和处理器,所述存储器存储有计算机程序,所述处理器执行所述计算机程序时实现上述任意一个实施例中控制方法的步骤。
在本说明书的描述中,参考术语“有些实施例”、“其他实施例”、“理想实施例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特征包含于本申请的至少一个实施例或示例中。在本说明书中,对上述术语的示意性描述不一定指的是相同的实施例或示例。
上所述实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对申请专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本申请构思的前提下,还可以做出若干变形和改进,这些都属于本申请的保护范围。因此,本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种存储器电路,包括:
    预充电电路,包括第一预充电单元、第二预充电单元、第一电源端、第二电源端、第一控制端、第二控制端及数据端;所述第一预充电单元与所述第一电源端、所述第一控制端及所述数据端连接;所述第二预充电单元与所述第二电源端、所述第二控制端及所述数据端连接;所述第一电源端输入第一预充电压,所述第二电源端输入第二预充电压;及
    控制电路,所述控制电路的第一输出端与所述第一控制端连接,所述控制电路的第二输出端与所述第二控制端连接;所述控制电路用于:
    当存储器未处于行激活状态时,通过所述第二预充电单元控制所述数据端与第二电源端之间导通,且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开;
    当所述存储器处于行激活状态,且未进行读写操作时,通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开,且通过所述第一预充电单元控制所述数据端与第一电源端之间断开;
    当所述存储器处于行激活状态,且读写操作开始后的预设时间内,通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开,且通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通;
    当所述存储器处于行激活状态,且读写操作开始后的预设时间之后,通过所述第二预充电单元控制所述数据端与第二电源端之间断开,且通过所述第一预充电单元控制所述数据端与第一电源端之间断开。
  2. 根据权利要求1所述的存储器电路,其中,所述第一预充电压为存储器的电源电压,所述第二预充电压为所述存储器的电源电压的一半。
  3. 根据权利要求1所述的存储器电路,其中,所述存储器在行激活状态的一个周期内进行多次读写,在所述存储器的行激活状态的一个周期内,每次读写开始时所述控制电路通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通且所述预设时间后断开。
  4. 根据权利要求1至3任一项所述的存储器电路,其中,所述控制电路的第一输入端输入行激活信号,所述控制电路的第二输入端输入读写信号;当所述行激活信号为低电平时,所述存储器未处于行激活状态;当所述行激活信号为高电平时,所述存储器处于行激活状态;当所述读写信号为低电平时,所述存储器未进行读写操作;当所述读写信号为高电平时,所述存储器进行读写操作。
  5. 根据权利要求4所述的存储器电路,其中,所述控制电路包括第一反相单元、延时单元、第二反相单元、或非门及第三反相单元;
    所述第一反相单元的输入端为所述控制电路的第一输入端,所述第一反相单元的第一输出端和第二输出端均用于输出所述行激活信号反相后的信号;所述第一反相单元的第一输出端为所述控制电路的第二输出端;
    所述延时单元的输入端和所述第二反相单元的输入端连接并作为所述控制电路的第二输入端,所述延时单元用于将所述读写信号延迟所述预设时间后输出,所述第二反相单元用于输出所述读写信号反相后的信号;
    所述或非门的第一输入端与所述第一反相单元的第二输出端连接,所述或非门的第二输入端与所述延时单元的输出端连接,所述或非门的第三输入端与所述第二反相单元的输出端连接,所述或非门的输出端与所述第三反相单元的输入端连接;
    所述第三反相单元用于对所述第三反相单元的输入端输入的信号进行反相后输出,所述第三反相单元的输出端为所述控制电路的第一输出端。
  6. 根据权利要求5所述的存储器电路,其中,所述第一反相单元包括N个依次串联的反相器,所述第一反相单元中最后一个反相器的输出端为所述第一反相单元的第一输出端,所述第一反相单元中第N x个反相器的输出端为所述第一反相单元的第二输出端;
    其中,N、N x均为正奇数且N x小于或等于N。
  7. 根据权利要求5所述的存储器电路,其中,所述延时单元包括M个依次串联的反相器;
    其中,M为正偶数。
  8. 根据权利要求5所述的存储器电路,其中,所述第二反相单元包括Q个依次串联的反相器;
    其中,Q为正奇数。
  9. 根据权利要求5所述的存储器电路,其中,所述第三反相单元包括P个依次串联的反相器;
    其中,P为正奇数。
  10. 根据权利要求1所述的存储器电路,其中,所述数据端包括第一数据端和第二数据端,所述第一数据端和所述第二数据端接收互为相反的数据信号;所述第一预充电单元包括第一开关单元和第二开关单元,所述第一开关单元的第一电连接端和所述第二开关单元的第一电连接端均与所述第一电源端连接,所述第一开关单元的控制端和所述第二开关 单元的控制端均与所述第一控制端连接,所述第一开关单元的第二电连接端与所述第一数据端连接,所述第二开关单元的第二电连接端与所述第二数据端连接;
    所述第二预充电单元包括第三开关单元和第四开关单元,所述第三开关单元的第一电连接端和所述第四开关单元的第一电连接端均与所述第二电源端连接,所述第三开关单元的控制端和所述第四开关单元的控制端均与所述第二控制端连接,所述第三开关单元的第二电连接端与所述第一数据端连接,所述第四开关单元的第二电连接端与所述第二数据端连接。
  11. 根据权利要求10所述的存储器电路,其中,所述第一开关单元和所述第二开关单元均包括PMOS管,所述第一开关单元的第一电连接端和所述第二开关单元的第一电连接端均为所述PMOS管的源极,所述第一开关单元的第二电连接端和所述第二开关单元的第二电连接端均为所述PMOS管的漏极,所述第一开关单元的控制端和所述第二开关单元的控制端均为所述PMOS管的栅极;
    所述第三开关单元和所述第四开关单元均包括NMOS管,所述第三开关单元的第一电连接端和所述第四开关单元的第一电连接端均为所述NMOS管的源极,所述第三开关单元的第二电连接端和所述第四开关单元的第二电连接端均为所述NMOS管的漏极,所述第三开关单元的控制端和所述第四开关单元的控制端均为所述NMOS管的栅极。
  12. 一种电子设备,包括如权利要求1至11任一项所述的存储器电路。
  13. 一种存储器预充电的控制方法,应用于存储器的预充电电路,所述预充电电路包括第一预充电单元、第二预充电单元、第一电源端、第二电源端、第一控制端、第二控制端及数据端;所述第一预充电单元与所述第一电源端、所述第一控制端及所述数据端连接;所述第二预充电单元与所述第二电源端、所述第二控制端及所述数据端连接;所述第一电源端输入第一预充电压,所述第二电源端输入第二预充电压;所述方法包括:
    当所述存储器未处于行激活状态时,通过所述第二预充电单元控制所述数据端与第二电源端之间导通,且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开;
    当所述存储器处于行激活状态,且未进行读写操作时,通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开,且通过所述第一预充电单元控制所述数据端与第一电源端之间断开;
    当所述存储器处于行激活状态,且读写操作开始后的预设时间内,通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开,且通过所述第一预充电单元控制所述 数据端与所述第一电源端之间导通;
    当所述存储器处于行激活状态,且读写操作开始后的预设时间之后,通过所述第二预充电单元控制所述数据端与第二电源端之间断开,且通过所述第一预充电单元控制所述数据端与第一电源端之间断开。
  14. 根据权利要求13所述的存储器预充电的控制方法,其中,所述存储器在行激活状态的一个周期内进行多次读写,在所述存储器的行激活状态的一个周期内,每次读写开始时通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通且所述预设时间后断开。
  15. 一种计算机设备,包括存储器和处理器,所述存储器存储有计算机程序,所述处理器执行所述计算机程序时实现权利要求13或14所述的控制方法的步骤。
PCT/CN2021/106734 2021-03-31 2021-07-16 存储器电路、存储器预充电的控制方法及设备 WO2022205683A1 (zh)

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