WO2022205681A1 - 存储器电路、存储器预充电的控制方法及设备 - Google Patents

存储器电路、存储器预充电的控制方法及设备 Download PDF

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Publication number
WO2022205681A1
WO2022205681A1 PCT/CN2021/106688 CN2021106688W WO2022205681A1 WO 2022205681 A1 WO2022205681 A1 WO 2022205681A1 CN 2021106688 W CN2021106688 W CN 2021106688W WO 2022205681 A1 WO2022205681 A1 WO 2022205681A1
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Prior art keywords
terminal
unit
memory
read
precharging
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PCT/CN2021/106688
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English (en)
French (fr)
Inventor
张良
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长鑫存储技术有限公司
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Priority to US17/446,958 priority Critical patent/US11670349B2/en
Publication of WO2022205681A1 publication Critical patent/WO2022205681A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to a memory circuit, a control method for precharging memory, and a computer device.
  • DRAM Dynamic Random Access Memory
  • Dynamic Random Access Memory is a volatile memory that usually includes multiple read circuits for reading the information in the memory cells in an array. Each read and write operation often requires completed within a time period. During the operation of the memory, the data line needs to be precharged to a predetermined voltage, that is, a precharge (Precharge) operation is performed.
  • Precharge precharge
  • the present application provides a memory circuit, including: a precharge circuit, including a first precharge unit, a second precharge unit, a first power supply terminal, a second power supply terminal, a first control terminal, a second control terminal and a data terminal ;
  • the first pre-charging unit is connected to the first power terminal, the first control terminal and the data terminal;
  • the second pre-charging unit is connected to the second power terminal and the second control terminal is connected to the data terminal;
  • the first power terminal is input with a first precharge voltage
  • the second power terminal is input with a second precharge voltage;
  • control circuit the first output end of the control circuit is connected to the first control end, and the second output end of the control circuit is connected to the second control end; the control circuit is used for:
  • the second precharging unit controls the conduction between the data terminal and the second power terminal, and the first precharging unit controls the data terminal and all The first power supply terminal is disconnected;
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal
  • the first precharging unit controls the disconnection between the data terminal and the second power terminal. controlling the disconnection between the data terminal and the first power terminal
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal, and controls the disconnection between the data terminal and the second power terminal through the second precharging unit.
  • the first precharging unit controls conduction between the data terminal and the first power terminal;
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal, and controls the disconnection between the data terminal and the second power terminal through the second precharging unit.
  • the first precharging unit controls the disconnection between the data terminal and the first power terminal;
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal, and controls the disconnection between the data terminal and the second power terminal through the second precharging unit.
  • the first precharging unit controls the disconnection between the data terminal and the first power terminal;
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal, and controls the disconnection between the data terminal and the second power terminal through the second precharging unit.
  • the first precharging unit controls conduction between the data terminal and the first power terminal.
  • the present application also provides a control method for precharging a memory, which is applied to a precharging circuit of a memory, where the precharging circuit includes a first precharging unit, a second precharging unit, a first power supply terminal, a second power supply terminal, a first control terminal, a second control terminal and a data terminal; the first pre-charging unit is connected to the first power terminal, the first control terminal and the data terminal; the second pre-charging unit is connected to the the second power terminal, the second control terminal and the data terminal are connected; the first power terminal is input with a first precharge voltage, and the second power terminal is input with a second precharge voltage; the method includes:
  • the second precharging unit controls the conduction between the data terminal and the second power terminal, and the first precharging unit controls the data terminal disconnected from the first power terminal;
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal
  • the first precharging unit controls the disconnection between the data terminal and the second power terminal. controlling the disconnection between the data terminal and the first power terminal
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal, and controls the disconnection between the data terminal and the second power terminal through the second precharging unit.
  • the first precharging unit controls conduction between the data terminal and the first power terminal;
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal, and controls the disconnection between the data terminal and the second power terminal through the second precharging unit.
  • the first precharging unit controls the disconnection between the data terminal and the first power terminal;
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal, and controls the disconnection between the data terminal and the second power terminal through the second precharging unit.
  • the first precharging unit controls the disconnection between the data terminal and the first power terminal;
  • the second precharging unit controls the disconnection between the data terminal and the second power terminal, and controls the disconnection between the data terminal and the second power terminal through the second precharging unit.
  • the first precharging unit controls conduction between the data terminal and the first power terminal.
  • the present application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the control method described in any of the above embodiments when the processor executes the computer program.
  • the above-mentioned memory circuit and control method for memory precharging When the memory is in a row active state and no read and write operations are performed, the second precharging unit controls the disconnection between the data terminal and the second power terminal, and the first precharging unit controls the disconnection between the data terminal and the second power terminal.
  • the control data terminal is disconnected from the first power terminal.
  • the memory circuit inputs the first precharge voltage to the data line through the data terminal, so that the memory does not need a separate preset time in subsequent read and write operation cycles. Pre-charging improves the read and write speed of the memory.
  • FIG. 1 is a structural block diagram of a memory circuit provided in an embodiment
  • FIG. 2 is a waveform diagram of each signal in a memory circuit provided in an embodiment
  • FIG. 3 is a circuit diagram of a control circuit provided in an embodiment
  • FIG. 4 is a circuit diagram of a precharge circuit provided in an embodiment
  • FIG. 5 is a flowchart of a method for controlling memory precharging provided in an embodiment.
  • Precharge circuit 11, First precharge unit; 111, First switch unit; 112, Second switch unit; 12, Second precharge unit; 121, Third switch unit; 122, Fourth switch unit; 20, control circuit; 21, first inversion unit; 22, delay unit; 23, second inversion unit; 24, latch unit; 25, three-input NOR gate; 26, third inversion unit; 27 ,inverter.
  • the first precharge unit is referred to as the second precharge unit, and similarly, the second precharge unit may be referred to as the first precharge unit; the first precharge unit and the second precharge unit are different precharge units.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • FIG. 1 is a structural block diagram of a memory circuit in an embodiment.
  • the memory circuit includes a precharge circuit 10 and a control circuit 20 .
  • the precharging circuit 10 includes a first precharging unit 11 , a second precharging unit 12 , a first power terminal J11 , a second power terminal J12 , a first control terminal J13 , a second control terminal J14 and a data terminal J15 .
  • the first precharging unit 11 is connected to the first power terminal J11 , the first control terminal J13 and the data terminal J15 , and the first control terminal J13 is the control terminal of the first precharging unit 11 .
  • the second precharging unit 12 is connected to the second power terminal J12 , the second control terminal J14 and the data terminal J15 , and the second control terminal J14 is the control terminal of the second precharging unit 12 .
  • the first power terminal J11 is input with a first precharge voltage
  • the second power terminal J12 is input with a second precharge voltage.
  • the first output terminal J21 of the control circuit 20 is connected to the first control terminal J13, and the control circuit 20 controls the operation of the first precharging unit 11 by controlling the signal of the first output terminal J21 thereof. Specifically, the first precharging unit 11 controls the first precharging unit 11. A power terminal J11 and the data terminal J15 are turned on, so as to input the first precharge voltage to the data terminal J15, or the first precharge unit 11 controls the disconnection between the first power terminal J11 and the data terminal J15, so as to stop the voltage to the data terminal J15.
  • the data terminal J15 inputs the first precharging voltage; the second output terminal J22 of the control circuit 20 is connected to the second control terminal J14, and the control circuit 20 also controls the second precharging unit 12 to work by controlling the signal of the second output terminal J22 thereof, Specifically, the second precharging unit 12 controls the conduction between the second power terminal J12 and the data terminal J15, so as to input the second precharging voltage to the data terminal J15, or controls the second power terminal J12 through the second precharging unit 12. It is disconnected from the data terminal J15, thereby stopping the input of the second precharge voltage to the data terminal J15.
  • the first precharge voltage and the second precharge voltage can be set according to actual requirements, and the two can be set to be unequal.
  • the data terminal J15 can be connected to the data line in the memory, so that the precharge of the data line can be controlled by the memory circuit.
  • the data line in this embodiment may be a local data line (LIO, local input output, also referred to as a local input output line) in the memory.
  • control circuit 20 is used for:
  • the second precharging unit 12 controls the conduction between the data terminal J15 and the second power terminal J12, and the first precharging unit 11 controls the connection between the data terminal J15 and the first power terminal J11 intermittent;
  • the second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12, and the first precharging unit 11 controls the data terminal J15 and the second power terminal J15 to be disconnected. A disconnect between the power terminals J11;
  • the second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12
  • the first precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12. 11 Control the conduction between the data terminal J15 and the first power terminal J11;
  • the second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12
  • the first precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12.
  • 11 Control the disconnection between the data terminal J15 and the first power terminal J11;
  • the second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12, and the first precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12. 11. Continue to disconnect between the control data terminal J15 and the first power terminal J11;
  • the second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12
  • the first precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12.
  • 11 controls conduction between the data terminal J15 and the first power terminal J11.
  • control circuit 20 may have a first input (not shown in FIG. 1 ) and a second input (not shown in FIG. 1 ).
  • the first input terminal of the control circuit 20 can be connected to the row activation signal line of the memory to obtain the row activation signal of the memory.
  • the control circuit 20 can determine whether the memory is in the row activation state according to the row activation signal of the memory.
  • the second input terminal of the control circuit 20 can be connected to the read and write signal lines of the memory to obtain the read and write signals of the memory.
  • the control circuit 20 can determine whether the memory starts to read and write according to the read and write signals of the memory.
  • control circuit 20 can also determine whether the memory is in a row active state and whether to start a read-write operation by other methods.
  • control circuit 20 determines whether the memory is in the row active state according to the row activation signal of the memory, and determines whether the memory starts to read or write according to the read and write signals of the memory, please refer to FIG. 1 and FIG. 2 , when the row activation signal When Row active is high level, the memory is in the row active state, when the row active signal Row active is low level, the memory is not in the row active state; when the read and write signal Read/Write is high, the memory performs read and write operations, when the read and write signal Read When /Write is low, the memory is not being read or written.
  • the control circuit 20 controls the first control signal EqHigh output to the first control terminal J13 of the precharge circuit 10 (the control terminal of the first precharge unit 11 ) according to the row activation signal Row active, and the first precharge unit 11 according to the first control
  • the signal EqHigh controls whether the connection between the first power terminal J11 and the data terminal J15 is conducted, thereby controlling whether to input the first precharge voltage to the data terminal J15.
  • the control circuit 20 controls the second control signal Eq output to the second control terminal J14 of the precharge circuit 10 (the control terminal of the second precharge unit 12 ) according to the read/write signal Read/Write.
  • the control signal Eq controls whether the connection between the second power terminal J12 and the data terminal J15 is conducted, thereby controlling whether to input the second precharge voltage to the data terminal J15.
  • the row active signal Row active is at a low level, and the memory is not in a row active state.
  • the control circuit 20 controls the second control signal Eq output by the second output terminal J22 to be a high level, and the control terminal of the second pre-charging unit 12 controls the conduction between the second power terminal J12 and the data terminal J15 after receiving the high level.
  • the control circuit 20 also controls the first control signal EqHigh output by the first output terminal J21 to be a high level, and the control terminal of the first pre-charging unit 11 controls the first power terminal J11 and the data terminal J15 after receiving the high level Therefore, when the memory is not in the row active state, the memory circuit inputs the second precharge voltage to the data line through the data terminal J15.
  • the row activation signal Row active is at a high level, and the memory is in a row activation state; and the read/write signal Read/Write is at a low level, and the memory does not perform read and write operations.
  • the control circuit 20 controls the second control signal Eq output by the second output terminal J22 to be a low level, and the control terminal of the second pre-charging unit 12 controls the disconnection between the second power terminal J12 and the data terminal J15 after receiving the low level ;
  • the control circuit 20 also controls the first control signal EqHigh output by its first output terminal J21 to be a high level, and the control terminal of the first pre-charging unit 11 controls the connection between the first power supply terminal J11 and the data terminal J15 after receiving the high level Therefore, when the memory is in the row active state and no read and write operations are performed, the memory circuit does not input the first precharge voltage to the data line through the data terminal J15, nor does it input the second precharge voltage to the data line through the data terminal J15.
  • the row activation signal Row active is high, and the memory is in the row active state; and the read/write signal Read/Write is high, the memory starts to read write operation.
  • the control circuit 20 controls the second control signal Eq output by the second output terminal J22 to be a low level, and the control terminal of the second pre-charging unit 12 controls the disconnection between the second power terminal J12 and the data terminal J15 after receiving the low level
  • the control circuit 20 also controls the first control signal EqHigh output by its first output terminal J21 to be a low level, and the control terminal of the first pre-charging unit 11 controls the first power supply terminal J11 and the data terminal J15 after receiving the low level Therefore, when the memory is in the row active state, and within the preset time period t3 after the first read and write operation starts, the memory circuit inputs the first precharge voltage to the data line through the data terminal J15, which is used for subsequent data processing. Prepare to read and write.
  • the row activation signal Row active is at a high level, and the memory is in a row activation state; and the read/write signal Read/Write is at a high level, the first read/write operation starts (the read/write signal Read/Write rises when the When the edge comes, the memory starts to read and write operations) after the preset time t3, until the first read and write operation ends (when the read/write signal Read/Write comes down, the memory starts to end the read and write operations).
  • the control circuit 20 controls the second control signal Eq output by the second output terminal J22 to be a low level, and the control terminal of the second pre-charging unit 12 controls the disconnection between the second power terminal J12 and the data terminal J15 after receiving the low level ;
  • the control circuit 20 also controls the first control signal EqHigh output by its first output terminal J21 to be a high level, and the control terminal of the first pre-charging unit 11 controls the connection between the first power supply terminal J11 and the data terminal J15 after receiving the high level Therefore, when the memory is in the row active state, and after the preset time t3 after the first read and write operation starts, until the first read and write operation ends, the memory circuit does not input the first preset time to the data line through the data terminal J15.
  • the charging voltage, and the second precharging voltage is not input to the data line through the data terminal J15.
  • the storage array is reading and writing data.
  • the voltage on the data line is determined by the data (0 or 1) stored in the memory cell; during the write operation, the voltage on the data line is determined by the externally written data. Decide.
  • the row activation signal Row active is high, and the memory is in the row active state; and the read and write signal Read/Write is low, and the memory is not read. write operation.
  • the control circuit 20 controls the second control signal Eq output by the second output terminal J22 to be a low level, and the control terminal of the second pre-charging unit 12 controls the disconnection between the second power terminal J12 and the data terminal J15 after receiving the low level ;
  • the control circuit 20 also controls the first control signal EqHigh output by its first output terminal J21 to be a high level, and the control terminal of the first pre-charging unit 11 controls the connection between the first power supply terminal J11 and the data terminal J15 after receiving the high level so that when the memory is in the row active state, and within the preset time period t5 after the first read and write operation is completed, the memory circuit does not input the first precharge voltage to the data line through the data terminal J15, nor does it The second precharge voltage is input to the
  • the control The circuit 20 controls the second control signal Eq output by the second output terminal J22 to be low level, and the control terminal of the second precharging unit 12 controls the disconnection between the second power terminal J12 and the data terminal J15 after receiving the low level;
  • the control circuit 20 also controls the first control signal EqHigh output by the first output terminal J21 to be low level, and the control terminal of the first pre-charging unit 11 controls the connection between the first power terminal J11 and the data terminal J15 after receiving the low level.
  • the memory circuit inputs the first precharge voltage to the data line through the data terminal J15. After the t6 time period ends, the second read and write operation starts.
  • the memory When the row activation signal Row active is at a high level, the memory is not in a row activation state, and the control circuit 20 controls the first control signal EqHigh output by its own first output terminal J21 to be at a high level; the control circuit 20 also controls its own first control signal EqHigh The second control signal Eq output by the two output terminals J22 is at a high level.
  • the memory When the row activation signal Row active is at a low level, the memory is in a row activated state, and when the read/write signal Read/Write is at a high level, the memory does not perform read and write operations, and the control circuit 20 controls the first output terminal J21 of its own to output the first output.
  • a control signal EqHigh is at a high level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be at a low level.
  • the control circuit 20 controls the first control signal EqHigh output by its own first output terminal J21 to be low level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be low level.
  • the memory When the row activation signal Row active is low level, the memory is in the row active state, and when the read/write signal Read/Write is low level, the memory performs the first read and write operation, and after the preset time after the first read and write operation starts , the control circuit 20 controls the first control signal EqHigh output by its own first output terminal J21 to be high level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be low level.
  • the control circuit 20 When the row activation signal Row active is at a low level, the memory is in a row activated state, and when the read/write signal Read/Write is at a high level, the control circuit 20 continues to control itself within a preset time after the first read and write operation of the memory is completed.
  • the first control signal EqHigh output by the first output terminal J21 of the control circuit 20 is high level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be low level.
  • the control circuit 20 controls its own The first control signal EqHigh output by the first output terminal J21 is at a low level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be at a low level.
  • the memory When the row activation signal Row active is at a low level, the memory is not in a row activation state, and the control circuit 20 controls the first control signal EqHigh output by its own first output terminal J21 to be at a low level; the control circuit 20 also controls its own first control signal EqHigh The second control signal Eq output by the two output terminals J22 is at a low level.
  • the memory When the row activation signal Row active is at a high level, the memory is in a row activated state, and when the read/write signal Read/Write is at a low level, the memory does not perform read and write operations, and the control circuit 20 controls the first output terminal J21 of its own to output the first output.
  • a control signal EqHigh is at a low level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be at a high level.
  • the control circuit 20 controls the first control signal EqHigh output by its own first output terminal J21 to be high level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be high level.
  • the memory When the row activation signal Row active is at a high level, the memory is in the row activation state, and when the read/write signal Read/Write is at a high level, the memory performs the first read and write operation, and after the preset time after the first read and write operation starts , the control circuit 20 controls the first control signal EqHigh output by its own first output terminal J21 to be low level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be high level.
  • the control circuit 20 When the row activation signal Row active is at a high level, the memory is in a row activation state, and when the read/write signal Read/Write is at a low level, the control circuit 20 continues to control itself within a preset time after the first read and write operation of the memory is completed.
  • the first control signal EqHigh output by the first output terminal J21 of the circuit 20 is low level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be high level.
  • the control circuit 20 controls its own The first control signal EqHigh output by the first output terminal J21 is at a high level; the control circuit 20 also controls the second control signal Eq output by its own second output terminal J22 to be at a high level.
  • the row activation signal Row active and the row activation state of the memory can also be There are other ways, which will not be repeated here.
  • the second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12, and the first precharging unit 11 controls the data terminal.
  • the connection between J15 and the first power terminal J11 is disconnected.
  • the first charging voltage is not input to the data terminal J15
  • the second charging voltage is not input to the data terminal J15, so that the data line will not be pre-charged, so as to avoid the The waste of current when the memory is row-active and not being read or written.
  • the memory circuit inputs the first precharge voltage to the data line through the data terminal J15 to prepare for the subsequent read and write operations, so that the memory can be used in subsequent read and write operations.
  • the operation cycle there is no need for a separate preset time for precharging, which improves the read and write speed of the memory.
  • the first precharge voltage is the power supply voltage VCCA of the memory
  • the second precharge voltage is half the power supply voltage of the memory, ie, 1/2 VCCA.
  • the magnitudes of the first precharge voltage and the second precharge voltage may also be set according to actual requirements.
  • the memory performs multiple read and write operations in one cycle of the row active state of the memory, and in one cycle of the row active state of the memory, after a preset time after each read and write operation is completed, the control circuit 20
  • the first pre-charging unit 11 controls the conduction between the data terminal J15 and the first power terminal J11, and the memory circuit inputs the first pre-charging voltage to the data line through the data terminal J15 to prepare for the subsequent read and write operations.
  • the read and write speed of the memory and after a preset time after the start of the next read and write operation, the first precharge unit 11 controls the disconnection between the data terminal J15 and the first power terminal J11, at this time, the storage array is reading and writing data. .
  • the read/write signal Read/Write appears multiple high levels, that is, multiple reads and writes are performed.
  • the first control signal EqHigh output by the first output terminal J21 of the control circuit 20 jumps to a low level and remains at a low level Jump to high level after preset time t3.
  • the first control signal EqHigh output by the first output terminal J21 of the control circuit 20 jumps to a low level again, and maintains a low level until the next read and write operation After a preset time after the start, the transition goes high. And so on until the memory is not row active.
  • the row active signal Row active jumps from high level to low level, at the same time, the read/write signal Read/Write remains at low level, and the signal at point A jumps from low level Change to high level, the signal at point B remains at low level, the signal at point C jumps from low level to high level, the signal at point D jumps from high level to low level, the first control signal EqHigh changes from low level The level jumps to a high level, and the second control signal Eq jumps from a low level to a high level.
  • the first precharge circuit 10 when the first control signal EqHigh is at a low level, controls the conduction between the first power terminal J11 and the data terminal J15, and the first power terminal J11 inputs the first precharge to the data terminal J15. charging voltage; when the first control signal EqHigh is at a high level, the first pre-charging circuit 10 controls the disconnection between the first power terminal J11 and the data terminal J15, and the first power terminal J11 stops inputting the first pre-charging voltage to the data terminal J15 .
  • the row activation signal Row active is input to the first input terminal J23 of the control circuit 20, and the read/write signal Read/Write is input to the second input terminal J24 of the control circuit 20; when the row activation signal Row active is at a low level, the memory is not In the row active state; when the row active signal Row active is high, the memory is in the row active state; when the read/write signal Read/Write is low, the memory is not reading and writing; when the read/write signal Read/Write is high Usually, the memory performs read and write operations.
  • control circuit 20 includes a first inversion unit 21 , a delay unit 22 , a second inversion unit 23 , a latch unit 24 , a three-input NOR gate 25 , a third Inverting unit 26; latching unit 24 includes a first input terminal, a second input terminal and an output terminal.
  • the input end of the first inversion unit 21 is connected to the first input end of the latch unit 24 and serves as the first input end J23 of the control circuit 20 , that is, the signal input by the input end of the first inversion unit 21 is the row activation signal Row active; both the first output terminal and the second output terminal (refer to point A in FIG. 3 ) of the first inversion unit 21 are used to output the inverted signal of the row activation signal Row active.
  • the first output terminal of the first inversion unit 21 is the second output terminal J22 of the control circuit 20, so that the second control signal Eq output by the control circuit 20 to the control terminal of the second precharging unit 12 is the row activation signal Row active inversion. signal after.
  • the first input terminal of the three-input NOR gate 25 is connected to the second output terminal of the first inversion unit 21, and the signal input to the first input terminal of the three-input NOR gate 25 is the inverted row activation signal Row active Signal.
  • the input end of the delay unit 22 is connected to the input end of the second inversion unit 23 and serves as the second input end J24 of the control circuit 20.
  • the output end of the delay unit 22 (refer to point B in FIG. 3) is connected to the three-input NOR
  • the second input terminal of the gate 25 is connected, that is, the signal input by the second input terminal of the three-input NOR gate 25 is the signal after the read/write signal Read/write is delayed by a preset time; the delay unit 22 is used for the read/write signal Read /write is output after a delay of a preset time; the second inversion unit 23 is used for outputting the inverted signal of the read/write signal Read/write.
  • the second input end of the latch unit 24 is connected to the output end of the second inversion unit 23, that is, the signal input by the first input end of the latch unit 24 is the row activation signal Row active, and the second input end of the latch unit 24
  • the input signal is the inverted signal of the read/write signal Read/write.
  • the output terminal of the latch unit 24 (see point C in FIG. 3 ) is connected to the third input terminal of the three-input NOR gate 25 .
  • the input terminal of the third inverting unit 26 is connected to the output terminal of the three-input NOR gate 25 (see point D in FIG. 3 ), and the output terminal of the third inverting unit 26 is used as the first output terminal J21 of the control circuit 20;
  • the three-phase inversion unit 26 is used for inverting and outputting the signal input from the input terminal.
  • the output terminal of the third inverting unit 26 is the first output terminal J21 of the control circuit 20 .
  • the row activation signal Row active input to the input terminal of the first inversion unit 21 is at a low level, and the memory is not in the row activation state.
  • the second control signal Eq output by the first output terminal of the first inversion unit 21 is high level, and the control terminal of the second precharging unit 12 controls the second power supply terminal J12 and the data after receiving the high level. Conduction between the terminals J15, the second power terminal J12 inputs the second precharge voltage to the data terminal J15; the row activation signal Row active input by the first input terminal of the latch unit 24 is low level, so that the output signal is Point C signal is high level.
  • the row activation signal Row active input to the input terminal of the first inversion unit 21 is at a high level, and the memory is in a row activation state.
  • the first inversion unit 21 The signal output from the second output terminal of , that is, the signal at point A is low level; that is, the signal input from the first input terminal of the three-input NOR gate 25 is low level; the input terminal of the delay unit 22 and the second inversion
  • the input signal of the input terminal of the unit 23 is the read/write signal Read/Write, which is a low level, the memory does not perform a read/write operation, and the signal input by the delay unit 22 to the second input terminal of the three-input NOR gate 25 is read.
  • the write signal Read/Write is delayed by a preset time, that is, the signal at point B, which is still at a low level.
  • the row activation signal Row active input by the first input terminal of the latch unit 24 is high level, and the read/write signal Read/write inverted signal input by the second input terminal of the latch unit 24 is high level, latching
  • the signal output from the output terminal of the unit 24, namely the signal at point C remains the same as the previous state and is at a high level; thus, the signal output at the output terminal of the three-input NOR gate 25, namely the signal at point D, is at a low level.
  • the output terminal of the third inversion unit 26 inputs a high level to the control terminal of the first precharging unit 11, so that the first precharging unit 11 controls the first power supply terminal J11 and the The data terminals J15 are disconnected, and the first power terminal J11 does not input the first precharge voltage to the data terminal J15.
  • the row activation signal Row active input from the input terminal of the first inversion unit 21 is at a high level, and the memory is in a row activation state.
  • the signal output by the second output terminal of the first inversion unit 21, that is, the signal at point A is low level, that is, the signal input by the first input terminal of the three-input NOR gate 25 is low level;
  • the delay unit The read/write signal Read/Write input by the input end of 22 and the input end of the second inversion unit 23 is a high level, the memory performs read and write operations, and the delay unit 22 inputs the second input end of the three-input NOR gate 25
  • the signal is the signal after the read/write signal Read/Write delays the preset time t3, that is, the B point signal, which is still low level;
  • the row activation signal Row active input by the first input end of the latch unit 24 is high level , the inverted signal of the read/write signal
  • the output terminal of the third inversion unit 26 inputs a low level to the control terminal of the first precharging unit 11, so that the first precharging unit 11 controls the first power supply terminal J11 and the The data terminals J15 are turned on, and the first power terminal J11 inputs a first precharge voltage to the data terminal J15.
  • the row activation signal Row active input by the input terminal of the first inverting unit 21 is at a high level , the memory is in the row active state.
  • the signal output by the second output terminal of the first inversion unit 21, that is, the signal at point A is low level, that is, the three-input NOR gate 25.
  • the signal input by the first input terminal is low level; the read/write signal Read/Write input by the input terminal of the delay unit 22 and the input terminal of the second inversion unit 23 is high level, the memory performs read and write operations, and delays
  • the signal input by the unit 22 to the second input end of the three-input NOR gate 25 is the read/write signal Read/Write delayed by the preset time t3, that is, the signal at point B, which becomes a high level;
  • the row activation signal Row active input by the first input terminal is high level, the read/write signal Read/write inputted by the second input terminal of the latch unit 24 is inverted and the signal is low level, and the output terminal of the latch unit 24
  • the output signal, that is, the signal at point C remains unchanged and is at a low level; thus, the signal output from the output end of the three-input NOR gate 25, that is, the signal at point D is at a low level.
  • the output terminal of the third inversion unit 26 inputs a high level to the control terminal of the first precharging unit 11, so that the first precharging unit 11 controls the first power supply terminal J11 and the The data terminals J15 are disconnected, and the first power terminal J11 stops inputting the first precharge voltage to the data terminal J15.
  • the row activation signal Row active input from the input terminal of the first inversion unit 21 is at a high level, and the memory is in a row activation state.
  • the signal output by the second output terminal of the first inversion unit 21, that is, the signal at point A is low level, that is, the signal input by the first input terminal of the three-input NOR gate 25 is low level; delay time
  • the input terminal of the unit 22 and the input terminal of the second inversion unit 23 input the read/write signal Read/Write as low level, the memory does not perform the read/write operation, and the delay unit 22 sends the second input of the three-input NOR gate 25
  • the signal input by the terminal is the signal after the read/write signal Read/Write is delayed by the preset time t5, that is, the signal at point B is still high; the row activation signal Row active input by the first input terminal of the latch unit 24 is high level, the inverted read/write
  • the output terminal of the third inversion unit 26 inputs a high level to the control terminal of the first precharging unit 11, so that the first precharging unit 11 controls the first power supply terminal J11 and the When the data terminals J15 are disconnected, the first power terminal J11 still stops inputting the first precharge voltage to the data terminal J15.
  • the row activation signal Row active input by the input terminal of the first inversion unit 21 is high level, The memory is in the row active state.
  • the signal output by the second output terminal of the first inversion unit 21, that is, the signal at point A is low level, that is, the third input of the three-input NOR gate 25.
  • the input signal of an input terminal is low level; the read/write signal Read/Write input by the input terminal of the delay unit 22 and the input terminal of the second inversion unit 23 is low level, the memory does not perform read and write operations, and the delay is delayed.
  • the signal input by the unit 22 to the second input terminal of the three-input NOR gate 25 is the signal after the read/write signal Read/Write is delayed by the preset time t5, that is, the signal at point B becomes a low level;
  • the row activation signal Row active input from one input terminal is high level
  • the read/write signal Read/write inverted signal input from the second input terminal of the latch unit 24 is high level
  • the output terminal of the latch unit 24 outputs
  • the signal of point C that is, the signal at point C, remains the same as the previous state, and is at a low level; thus, the signal output from the output terminal of the three-input NOR gate 25, that is, the signal at point D is at a high level.
  • the output terminal of the third inversion unit 26 inputs a low level to the control terminal of the first precharging unit 11, so that the first precharging unit 11 controls the first power supply terminal J11 and the The data terminals J15 are turned on, and the first power terminal J11 inputs a first precharge voltage to the data terminal J15.
  • the row activation signal Row active input to the input terminal of the first inversion unit 21 is at a high level, and the memory is in a row activation state.
  • the first inversion unit The second control signal Eq output by the first output terminal of 21 is a low level, and the control terminal of the second pre-charging unit 12 controls the disconnection between the second power terminal J12 and the data terminal J15 after receiving the low level, and the second power The terminal J12 stops inputting the second precharge voltage to the data terminal J15.
  • the first inverter unit 21 includes N inverters 27 connected in series in sequence, and the output terminal of the last inverter 27 in the first inverter unit 21 is the first inverter
  • the first output terminal of the unit 21 and the output terminal of the Nxth inverter 27 in the first inverting unit 21 are the second output terminal of the first inverting unit 21 .
  • N and Nx are both positive odd numbers and Nx is less than or equal to N. In the example of FIG. 3, N is equal to 3 and Nx is equal to 1.
  • the delay unit 22 includes M inverters 27 connected in series. Among them, M is a positive even number. In the example of Figure 3, M is equal to six. In other examples, the delay unit 22 may also adopt any other circuit structure well known to those skilled in the art.
  • the second inverter unit 23 includes Q inverters 27 connected in series. where Q is a positive odd number. In the example of Figure 3, Q is equal to one.
  • the third inverter unit 26 includes P inverters 27 connected in series. Among them, P is a positive odd number. In the example of Figure 3, P is equal to 1.
  • N and N x in the first inversion unit 21 , M in the delay unit 22 , Q in the second inversion unit 23 and P in the third inversion unit 26 are not limited to the numbers in the example in FIG. 3 .
  • latch unit 24 includes a latch. In other examples, the latch unit 24 may also adopt any circuit structure known to those skilled in the art.
  • the latch unit 24 includes a first NAND gate 28 and a second NAND gate 29 .
  • the first input terminal of the first NAND gate 28 is used as the first input terminal of the latch unit 24, the second input terminal of the first NAND gate 28 is connected to the output terminal of the second NAND gate 29, and the first and The output terminal of the NOT gate 28 is connected to the third input terminal of the three-input NOR gate 25 and the first input terminal of the second NAND gate 29 as the output terminal of the latch unit 24, and the second input terminal of the second NAND gate 29 is connected.
  • the terminal serves as the second input terminal of the latch unit 24 .
  • the data terminal J15 includes a first data terminal J151 and a second data terminal J152 , and the first data terminal J151 and the second data terminal J152 receive mutually opposite data signals.
  • the first data terminal J151 may be connected to the local data line to receive the LIO signal; the second data terminal J152 may be connected to the complementary local data line to receive the LIO_ signal.
  • the first precharge unit 11 includes a first switch unit 111 and a second switch unit 112 , and the first electrical connection terminal of the first switch unit 111 and the first electrical connection terminal of the second switch unit 112 are both connected to the first power terminal J11 , the first power terminal J11 inputs the first precharge voltage V1; the control terminal of the first switch unit 111 and the control terminal of the second switch unit 112 are both connected to the first control terminal J13 to obtain the first control signal EqHigh.
  • the second electrical connection terminal of the first switch unit 111 is connected to the first data terminal J151, and the second electrical connection terminal of the second switch unit 112 is connected to the second data terminal J152;
  • the switching characteristics of the first switch unit 111 and the second switch unit 112 may be the same, and the first control signal EqHigh output by the first output terminal J21 of the control circuit 20 controls the first electrical connection terminal of the first switch unit 111 and the second electrical connection terminal, and also controls the conduction between the first electrical connection terminal and the second electrical connection terminal of the second switch unit 112, so that the first power supply terminal J11 is connected to the first data terminal J151 and the first data terminal J151 at the same time.
  • the second data terminal J152 inputs the first precharge voltage V1; or the first control signal EqHigh output from the first output terminal J21 of the control circuit 20 controls the disconnection between the first electrical connection terminal and the second electrical connection terminal of the first switch unit 111 It also controls the disconnection between the first electrical connection terminal and the second electrical connection terminal of the second switch unit 112, so that the first power supply terminal J11 simultaneously stops inputting the first preset to the first data terminal J151 and the second data terminal J152. charging voltage V1.
  • the second precharge unit 12 includes a third switch unit 121 and a fourth switch unit 122 , and both the first electrical connection terminal of the third switch unit 121 and the first electrical connection terminal of the fourth switch unit 122 are connected to the first electrical connection terminal of the third switch unit 121 and the fourth switch unit 122 .
  • the two power terminals J12 are connected to input the second precharge voltage V2; the control terminal of the third switch unit 121 and the control terminal of the fourth switch unit 122 are both connected to the second control terminal J14 to obtain the second control signal Eq.
  • the second electrical connection terminal of the third switch unit 121 is connected to the first data terminal J151, and the second electrical connection terminal of the fourth switch unit 122 is connected to the second data terminal J152.
  • the switching characteristics of the third switch unit 121 and the fourth switch unit 122 may be the same, and the second control signal Eq output by the second output terminal J22 of the control circuit 20 controls the first electrical connection terminal of the third switch unit 121 and the second electrical connection terminal, and also controls the conduction between the first electrical connection terminal and the second electrical connection terminal of the fourth switch unit 122, so that the second power terminal J12 is connected to the first data terminal J151 and the first data terminal J151 at the same time.
  • the second data terminal J152 inputs the second precharge voltage V2; or the second control signal Eq output from the second output terminal of the control circuit 20 controls the disconnection between the first electrical connection terminal and the second electrical connection terminal of the third switch unit 121 , and also controls the disconnection between the first electrical connection terminal and the second electrical connection terminal of the fourth switch unit 122, so that the second power supply terminal J12 simultaneously stops inputting the second precharge to the first data terminal J151 and the second data terminal J152. Press V2.
  • both the first switch unit 111 and the second switch unit 112 include PMOS transistors
  • the first electrical connection terminal of the first switch unit 111 and the first electrical connection terminal of the second switch unit 112 are both sources of the PMOS transistors pole
  • the second electrical connection terminal of the first switch unit 111 and the second electrical connection terminal of the second switch unit 112 are both the drains of the PMOS transistors
  • the control terminal of the first switch unit 111 and the control terminal of the second switch unit 112 Both are the gates of the PMOS transistors.
  • the first switch unit includes a PMOS transistor P1
  • the second switch unit includes a PMOS transistor P2.
  • the first control signal EqHigh when the first control signal EqHigh is at a high level, the source and drain of the PMOS transistor P1 are disconnected and the source and drain of the PMOS transistor P2 are disconnected, and the first power supply terminal J11 stops supplying the first data
  • the first precharge voltage V1 is input to the terminal J151 and the second data terminal J152; when the first control signal EqHigh is at a low level, the source and drain of the PMOS transistor P1 are turned on and the source and drain of the PMOS transistor P2
  • the first power supply terminal J11 inputs the first precharge voltage V1 to the first data terminal J151 and the second data terminal J152.
  • both the third switch unit 121 and the fourth switch unit 122 include NMOS transistors, and both the first electrical connection terminal of the third switch unit 121 and the first electrical connection terminal of the fourth switch unit 122 are sources of the NMOS transistors pole, the second electrical connection terminal of the third switch unit 121 and the second electrical connection terminal of the fourth switch unit 122 are both the drains of the NMOS transistor, the control terminal of the third switch unit 121 and the control terminal of the fourth switch unit 122 Both are gates of NMOS transistors.
  • the third switch unit includes an NMOS transistor N1
  • the fourth switch unit includes an NMOS transistor N2 .
  • the second control signal Eq when the second control signal Eq is at a high level, the source and the drain of the NMOS transistor N1 are conducting and the source and the drain of the NMOS transistor N2 are conducting, and the second power supply terminal J12 is connected to the first The data terminal J151 and the second data terminal J152 input the second precharge voltage V2; when the second control signal Eq is at a low level, the source and drain of the NMOS transistor N1 are disconnected and the source and drain of the NMOS transistor N2 The second power terminal J12 stops inputting the second precharge voltage V2 to the first data terminal J151 and the second data terminal J152.
  • the present application also provides a control method for memory precharging, which is applied to a precharging circuit of a memory.
  • the precharging circuit includes a first precharging unit 11 , a second precharging unit 12 , a first power terminal J11 , a second power terminal J12 , a first control terminal J13 , a second control terminal J14 and a data terminal J15;
  • the first pre-charging unit 11 is connected to the first power terminal J11, the first control terminal J13 and the data terminal J15;
  • the second pre-charging unit 12 is connected to the second power terminal J12, the second control terminal J14 and the data terminal J15;
  • the first power terminal J11 is input with a first precharge voltage
  • the second power terminal J12 is input with a second precharge voltage.
  • the control method of memory precharge includes:
  • Step S51 Determine whether the memory is in a row active state.
  • step S53 If yes, go to step S53; otherwise, go to step S52.
  • Step S52 The second precharging unit 12 controls the conduction between the data terminal J15 and the second power terminal J12, and the first precharging unit 11 controls the disconnection between the data terminal J15 and the first power terminal J11.
  • Step S53 Determine whether the memory performs read and write operations.
  • step S55 If yes, go to step S55; otherwise, go to step S54.
  • Step S54 The second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12, and the first precharging unit 11 controls the disconnection between the data terminal J15 and the first power terminal J11.
  • Step S55 Determine whether the memory performs the first read/write operation.
  • Step S56 within a preset time after the first read and write operation starts, the second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12, and the first precharging unit 11 controls the data terminal J15 Conducted with the first power terminal J11.
  • Step S57 After a preset time after the first read and write operation starts, the second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12, and the first precharging unit 11 controls the data terminal J15 It is disconnected from the first power terminal J11.
  • Step S58 within a preset time after the completion of the first read and write operation, the second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12, and the first precharging unit 11 controls the data terminal J15 It is disconnected from the first power terminal J11.
  • Step S59 After the preset time after the first read and write operation is completed, the second precharging unit 12 controls the disconnection between the data terminal J15 and the second power terminal J12, and the first precharging unit 11 controls the data terminal J15 Conducted with the first power terminal J11.
  • the second precharging unit 12 is used to control the disconnection between the data terminal J15 and the second power terminal J12, and the first precharging unit 12 is used. 11. Control the disconnection between the data terminal J15 and the first power terminal J11. At this time, the first charging voltage is not input to the data terminal J15, and the second charging voltage is not input to the data terminal J15, so that the data line will not be pre-charged; When the read-write operation command arrives, the data terminal J15 is pulled to the first pre-charge voltage, which can not only reduce power consumption, but also will not affect the normal operation of the memory.
  • the memory circuit inputs the first precharge voltage to the data line through the data terminal J15, so that the memory does not need a separate preset in the subsequent read and write operation cycles. Time to precharge, improve the read and write speed of the memory.
  • steps in the flowchart of FIG. 5 are sequentially displayed according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 5 may include multiple steps or multiple stages, these steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution sequence of these steps or stages is also It does not have to be performed sequentially, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages within the other steps.
  • the memory performs multiple read and write operations in one cycle of the row active state of the memory.
  • the control circuit 20 passes the first A pre-charging unit 11 controls the conduction between the data terminal J15 and the first power terminal J11, and controls the data terminal J15 and the first power terminal through the first pre-charging unit 11 after a preset time after the next read and write operation starts disconnect between J11.
  • the above-mentioned control method for pre-charging the memory not only ensures that the data line is pre-charged to the power supply voltage before each data read and write, to prepare for subsequent data read and write, but also can avoid the memory being in a row-activated state and not yet performing a read and write operation. waste of current.
  • the present application also provides a computer device, including a memory and a processor, the memory stores a computer program, and the processor implements the steps of the control method for precharging the memory provided in any of the foregoing embodiments when the processor executes the computer program.

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Abstract

一种存储器电路、存储器预充电的控制方法及计算机设备，包括：预充电电路（10），包括第一预充电单元（11），第二预充电单元（12），第一电源端（J11），第二电源端（J12），第一控制端（J13），第二控制端（J14）及数据端（J15）；第一预充电单元（11）与第一电源端（J11）、第一控制端（J13）及数据端（J15）连接；第二预充电单元（12）与第二电源端（J12）、第二控制端（J14）及数据端（J15）连接；第一电源端（J11）输入第一预充电压，第二电源端（J12）输入第二预充电压；及控制电路（20），用于当存储器处于行激活状态，且未进行读写操作时，通过第二预充电单元（12）控制数据端（J15）与第二电源端（J12）之间断开，且通过第一预充电单元（11）控制数据端（J15）与第一电源端（J11）之间断开。上述存储器电路能够避免在存储器处于行激活状态且未进行读写操作时对电流的浪费，同时还能够提升读写速度。

Description

存储器电路、存储器预充电的控制方法及设备
本申请要求于2021年3月31日提交中国专利局，申请号为2021103525020，申请名称为“存储器电路、存储器预充电的控制方法及设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种存储器电路、存储器预充电的控制方法及计算机设备。
背景技术
DRAM(Dynamic Random Access Memory，动态随机存取存储器)是一种易失性的存储器，通常包括多个读取电路，用于读取呈阵列的存储单元中的信息，每个读写操作往往需要在一个时间周期内完成。在存储器工作过程中，需要将数据线预充电到预定的电压，即进行预充电(Precharge)操作。
传统的存储器每次进入行激活状态，则存储阵列(array)中的数据线被输入预定的电压，从而为后续的读写操作做准备。如此，会增加激活(active)电流IDD0，若在行激活状态下没有进行后续的读写操作，则这部分电流被浪费掉，导致存储器耗电量大。
发明内容
本申请提供了一种存储器电路，包括：预充电电路，包括第一预充电单元，第二预充电单元，第一电源端，第二电源端，第一控制端，第二控制端及数据端；所述第一预充电单元与所述第一电源端、所述第一控制端及所述数据端连接；所述第二预充电单元与所述第二电源端、所述第二控制端及所述数据端连接；所述第一电源端输入第一预充电压，所述第二电源端输入第二预充电压；及
控制电路，所述控制电路的第一输出端与所述第一控制端连接，所述控制电路的第二输出端与所述第二控制端连接；所述控制电路用于：
当存储器未处于行激活状态时，通过所述第二预充电单元控制所述数据端与所述第二电源端之间导通，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
当所述存储器处于行激活状态，且未进行读写操作时，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
当所述存储器处于行激活状态，且第一次读写操作开始后的预设时间内，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通；
当所述存储器处于行激活状态，且第一次读写操作开始后的预设时间之后，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
当所述存储器处于行激活状态，且第一次读写操作完成后的预设时间内，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
当所述存储器处于行激活状态，且第一次读写操作完成后的预设时间之后，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元 控制所述数据端与所述第一电源端之间导通。
本申请还提供了一种存储器预充电的控制方法，应用于存储器的预充电电路，所述预充电电路包括第一预充电单元，第二预充电单元，第一电源端，第二电源端，第一控制端，第二控制端及数据端；所述第一预充电单元与所述第一电源端、所述第一控制端及所述数据端连接；所述第二预充电单元与所述第二电源端、所述第二控制端及所述数据端连接；所述第一电源端输入第一预充电压，所述第二电源端输入第二预充电压；所述方法包括：
当所述存储器未处于行激活状态时，通过所述第二预充电单元控制所述数据端与所述第二电源端之间导通，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
当所述存储器处于行激活状态，且未进行读写操作时，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
当所述存储器处于行激活状态，且第一次读写操作开始后的预设时间内，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通；
当所述存储器处于行激活状态，且第一次读写操作开始后的预设时间之后，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
当所述存储器处于行激活状态，且第一次读写操作完成后的预设时间内，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
当所述存储器处于行激活状态，且第一次读写操作完成后的预设时间之后，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通。
本申请还提供了一种计算机设备，包括存储器和处理器，所述存储器存储有计算机程序，所述处理器执行所述计算机程序时实现如上任一实施例中所述的控制方法的步骤。
上述存储器电路及存储器预充电的控制方法当存储器处于行激活状态，且未进行读写操作时，通过第二预充电单元控制数据端与第二电源端之间断开，且通过第一预充电单元控制数据端与第一电源端之间断开，此时没有向数据端输入第一预充电压，也没有向数据端输入第二预充电压，使得存储器在未进行读写操作时，即使处于行激活状态也不会向数据线进行预充电，从而能够避免在存储器处于行激活状态且未进行读写操作时对激活电流的浪费；当读写操作的命令到来时，再将数据端拉至第一预充电压，这样既能够减少耗电，又不会影响存储器的正常工作。同时，在第一次读写操作完成后的预设时间之后，存储器电路即通过数据端向数据线输入第一预充电压，使得存储器在后续的读写操作周期中，无需单独的预设时间进行预充电，提升了存储器的读写速度。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例中提供的存储器电路的结构框图；
图2为一实施例中提供的存储器电路中各信号的波形图；
图3为一实施例中提供的控制电路的电路图；
图4为一实施例中提供的预充电电路的电路图；
图5为一实施例中提供的存储器预充电的控制方法的流程图。
附图标记说明：
10、预充电电路；11、第一预充电单元；111、第一开关单元；112、第二开关单元；12、第二预充电单元；121、第三开关单元；122、第四开关单元；20、控制电路；21、第一反相单元；22、延时单元；23、第二反相单元；24、锁存单元；25、三输入或非门；26、第三反相单元；27、反相器。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一预充电单元称为第二预充电单元，且类似地，可以将第二预充电单元称为第一预充电单元；第一预充电单元与第二预充电单元为不同的预充电单元。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
图1为一实施例中的存储器电路的结构框图。如图1所示，存储器电路包括预充电电路10及控制电路20。预充电电路10包括第一预充电单元11，第二预充电单元12，第一电源端J11，第二电源端J12，第一控制端J13，第二控制端J14及数据端J15。第一预充电单元11与第一电源端J11、第一控制端J13及数据端J15连接，第一控制端J13即为第一预充电单元11的控制端。第二预充电单元12与第二电源端J12、第二控制端J14及数据端J15连接，第二控制端J14即为第二预充电单元12的控制端。第一电源端J11输入第一预充电压，第二电源端J12输入第二预充电压。
控制电路20的第一输出端J21与第一控制端J13连接，控制电路20通过控制其第一输出端J21的信号控制第一预充电单元11工作，具体为通过第一预充电单元11控制第一电源端J11与数据端J15之间导通，从而向数据端J15输入第一预充电压，或者通过第一预充电单元11控制第一电源端J11与数据端J15之间断开，从而停止向数据端J15输入第一预充电压；控制电路20的第二输出端J22与第二控制端J14连接，控制电路20还通过控制其第二输出端J22的信号控制第二预充电单元12工作，具体为通过第二预充电单元12控制第二电源端J12与数据端J15之间导通，从而向数据端J15输入第二预充电压，或者通过第二预充电单元12控制第二电源端J12与数据端J15之间断开，从而停止向数据端J15输入第二预充电压。第一预充电压和第二预充电压可以根据实际需求进行设置，两者可以设置为不相等。数据端J15可以连接存储器中的数据线，从而可以通过存储器电路对数据线的预充电进行控制。本实施例中的数据线可以是存储器中的局部数据线(LIO，local input output，也可以称为本地输入输出线)。
具体的，控制电路20用于：
当存储器未处于行激活状态时，通过第二预充电单元12控制数据端J15与第二电源端J12之间导通，且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开；
当存储器处于行激活状态，且未进行读写操作时，通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开；
当存储器处于行激活状态，且第一次读写操作开始后的预设时间内，通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间导通；
当存储器处于行激活状态，且第一次读写操作开始后的预设时间之后，通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开；
当存储器处于行激活状态，且第一次读写操作完成后的预设时间内，通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间继续断开；
当存储器处于行激活状态，且第一次读写操作完成后的预设时间之后，通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间导通。
在一些示例中，控制电路20可以具有第一输入端(图1未示出)和第二输入端(图1未示出)。控制电路20的第一输入端可以与存储器的行激活信号线连接，从而获取存储器的行激活信号，控制电路20可以根据存储器的行激活信号判断存储器是否处于行激活状态。控制电路20的第二输入端可以与存储器的读写信号线连接，从而获取存储器的读写信号，控制电路20可以根据存储器的读写信号判断存储器是否开始读写操作。
在其他示例中，控制电路20也可以通过其他方式来判断存储器是否处于行激活状态及是否开始读写操作。
在一些示例中，当控制电路20根据存储器的行激活信号判断存储器是否处于行激活状态，且根据存储器的读写信号判断存储器是否开始读写操作时，请参阅图1和图2，当行激活信号Row active为高电平时存储器处于行激活状态，当行激活信号Row active为低电平时存储器未处于行激活状态；当读写信号Read/Write为高电平时存储器进行读写操作，当读写信号Read/Write为低电平时存储器未进行读写操作。控制电路20根据行激活信号Row active控制向预充电电路10的第一控制端J13(第一预充电单元11的控制端)输出的第一控制信号EqHigh，第一预充电单元11根据第一控制信号EqHigh控制第一电源端J11与数据端J15之间是否导通，从而控制是否向数据端J15输入第一预充电压。控 制电路20根据读写信号Read/Write控制向预充电电路10的第二控制端J14(第二预充电单元12的控制端)输出的第二控制信号Eq，第二预充电单元12根据第二控制信号Eq控制第二电源端J12与数据端J15之间是否导通，从而控制是否向数据端J15输入第二预充电压。
在t1时间段内，行激活信号Row active为低电平，存储器未处于行激活状态。控制电路20控制其第二输出端J22输出的第二控制信号Eq为高电平，第二预充电单元12的控制端接收到高电平后控制第二电源端J12与数据端J15之间导通；控制电路20还控制其第一输出端J21输出的第一控制信号EqHigh为高电平，第一预充电单元11的控制端接收到高电平后控制第一电源端J11与数据端J15之间断开；从而当存储器未处于行激活状态时，存储器电路通过数据端J15向数据线输入第二预充电压。
在t2时间段内，行激活信号Row active为高电平，存储器处于行激活状态；且读写信号Read/Write为低电平，存储器未进行读写操作。控制电路20控制其第二输出端J22输出的第二控制信号Eq为低电平，第二预充电单元12的控制端接收到低电平后控制第二电源端J12与数据端J15之间断开；控制电路20还控制其第一输出端J21输出的第一控制信号EqHigh为高电平，第一预充电单元11的控制端接收到高电平后控制第一电源端J11与数据端J15之间断开；从而当存储器处于行激活状态，且未进行读写操作时，存储器电路没有通过数据端J15向数据线输入第一预充电压，也没有通过数据端J15向数据线输入第二预充电压，此时虽然存储器已经处于行激活状态，但读写信号Read/Write为低电平，存储器未进行读写操作，也没有进行预充电操作。
在第一次读写操作开始后的预设时间t3时间段内，行激活信号Row active为高电平，存储器处于行激活状态；且读写信号Read/Write为高电平，存储器开始进行读写操作。控制电路20控制其第二输出端J22输出的第二控制信号Eq为低电平，第二预充电单元12的控制端接收到低电平后控制第二电源端J12与数据端J15之间断开；控制电路20还控制其第一输出端J21输出的第一控制信号EqHigh为低电平，第一预充电单元11的控制端接收到低电平后控制第一电源端J11与数据端J15之间导通；从而当存储器处于行激活状态，且第一次读写操作开始后的预设时间t3时间段内，存储器电路通过数据端J15向数据线输入第一预充电压，为后续进行数据读写做准备。
在t4时间段内，行激活信号Row active为高电平，存储器处于行激活状态；且读写信号Read/Write为高电平，第一次读写操作开始(读写信号Read/Write当上升沿到来时，存储器开始进行读写操作)后的预设时间t3之后，直至第一次读写操作结束(读写信号Read/Write当下降沿到来时，存储器开始结束读写操作)。控制电路20控制其第二输出端J22输出的第二控制信号Eq为低电平，第二预充电单元12的控制端接收到低电平后控制第二电源端J12与数据端J15之间断开；控制电路20还控制其第一输出端J21输出的第一控制信号EqHigh为高电平，第一预充电单元11的控制端接收到高电平后控制第一电源端J11与数据端J15之间断开；从而当存储器处于行激活状态，且第一次读写操作开始后的预设时间t3之后，直至第一次读写操作结束，存储器电路没有通过数据端J15向数据线输入第一预充电压，也没有通过数据端J15向数据线输入第二预充电压。此时存储阵列正在进行数据读写，当读操作时，数据线上的电压由存储单元中存储的数据(0或1)决定；当写操作时，数据线上的电压由外部写入的数据决定。
在第一次读写操作完成后的预设时间t5时间段内，行激活信号Row active为高电平，存储器处于行激活状态；且读写信号Read/Write为低电平，存储器未进行读写操作。控制电路20控制其第二输出端J22输出的第二控制信号Eq为低电平，第二预充电单元12的控制端接收到低电平后控制第二电源端J12与数据端J15之间断开；控制电路20还控制其第一输出端J21输出的第一控制信号EqHigh为高电平，第一预充电单元11的控制端接收到高电平后控制第一电源端J11与数据端J15之间继续断开；从而当存储器处于行激活 状态，且第一次读写操作完成后的预设时间t5时间段内，存储器电路没有通过数据端J15向数据线输入第一预充电压，也没有通过数据端J15向数据线输入第二预充电压。
在t6时间段内，行激活信号Row active为高电平，存储器处于行激活状态；且读写信号Read/Write为低电平，第一次读写操作完成后的预设时间t5之后，控制电路20控制其第二输出端J22输出的第二控制信号Eq为低电平，第二预充电单元12的控制端接收到低电平后控制第二电源端J12与数据端J15之间断开；控制电路20还控制其第一输出端J21输出的第一控制信号EqHigh为低电平，第一预充电单元11的控制端接收到低电平后控制第一电源端J11与数据端J15之间导通；从而当存储器处于行激活状态，且第一次读写操作完成后的预设时间t5之后，存储器电路通过数据端J15向数据线输入第一预充电压。t6时间段结束后开始第二次读写操作。
在另一些实施例中，还可以配置为：
当行激活信号Row active为高电平时，存储器未处于行激活状态，控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为高电平；控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为高电平。
当行激活信号Row active为低电平时，存储器处于行激活状态，且读写信号Read/Write为高电平时，存储器未进行读写操作，控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为高电平；控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为低电平。
当行激活信号Row active为低电平时，存储器处于行激活状态，且读写信号Read/Write为低电平时，存储器进行第一次读写操作，第一次读写操作开始后的预设时间内，控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为低电平；控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为低电平。
当行激活信号Row active为低电平时，存储器处于行激活状态，且读写信号Read/Write为低电平时，存储器进行第一次读写操作，第一次读写操作开始后的预设时间之后，控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为高电平；控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为低电平。
当行激活信号Row active为低电平时，存储器处于行激活状态，且读写信号Read/Write为高电平时，存储器第一次读写操作完成后的预设时间内，控制电路20继续控制其自身的第一输出端J21输出的第一控制信号EqHigh为高电平；控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为低电平。
当行激活信号Row active为低电平时，存储器处于行激活状态，且读写信号Read/Write为高电平时，存储器第一次读写操作完成后的预设时间之后，控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为低电平；控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为低电平。
在又一些实施例中，还可以配置为：
当行激活信号Row active为低电平时，存储器未处于行激活状态，控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为低电平；控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为低电平。
当行激活信号Row active为高电平时，存储器处于行激活状态，且读写信号Read/Write为低电平时，存储器未进行读写操作，控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为低电平；控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为高电平。
当行激活信号Row active为高电平时，存储器处于行激活状态，且读写信号Read/Write为高电平时，存储器进行第一次读写操作，第一次读写操作开始后的预设时间内，控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为高电平；控制电路20 还控制其自身的第二输出端J22输出的第二控制信号Eq为高电平。
当行激活信号Row active为高电平时，存储器处于行激活状态，且读写信号Read/Write为高电平时，存储器进行第一次读写操作，第一次读写操作开始后的预设时间之后，控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为低电平；控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为高电平。
当行激活信号Row active为高电平时，存储器处于行激活状态，且读写信号Read/Write为低电平时，存储器第一次读写操作完成后的预设时间内，控制电路20继续控制其自身的第一输出端J21输出的第一控制信号EqHigh为低电平；控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为高电平。
当行激活信号Row active为高电平时，存储器处于行激活状态，且读写信号Read/Write为低电平时，存储器第一次读写操作完成后的预设时间之后，控制电路20控制其自身的第一输出端J21输出的第一控制信号EqHigh为高电平；控制电路20还控制其自身的第二输出端J22输出的第二控制信号Eq为高电平。
在其他示例中，行激活信号Row active与存储器的行激活状态，读写信号Read/Write与存储器读写状态，控制电路20的输入端与输出端的控制关系以及预充电电路10的控制关系还可以是其他方式，此处不再一一赘述。
上述存储器电路当存储器处于行激活状态，且未进行读写操作时，通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开，此时没有向数据端J15输入第一充电电压，也没有向数据端J15输入第二充电电压，使得不会向数据线进行预充电，从而能够避免在存储器处于行激活状态且未进行读写操作时对电流的浪费。同时，在第一次读写操作完成后的预设时间之后，存储器电路即通过数据端J15向数据线输入第一预充电压，为后续的读写操作做准备，使得存储器在后续的读写操作周期中，无需单独的预设时间进行预充电，提升了存储器的读写速度。
在一些示例中，第一预充电压为存储器的电源电压VCCA，第二预充电压为存储器的电源电压的一半即1/2VCCA。在其他示例中，也可以根据实际需求设置第一预充电压和第二预充电压的大小。
在一些示例中，存储器在行激活状态的一个周期内进行多次读写操作，在所述存储器的行激活状态的一个周期内，每次读写操作完成后的预设时间之后，控制电路20通过第一预充电单元11控制数据端J15与第一电源端J11之间导通，存储器电路即通过数据端J15向数据线输入第一预充电压，为后续的读写操作做准备，提升了存储器的读写速度；并在下次读写操作开始后的预设时间之后，通过第一预充电单元11控制数据端J15与第一电源端J11之间断开，此时存储阵列正在进行数据读写。
仅示例性的，仍然参阅图2，在存储器的行激活状态的一个周期t7内，读写信号Read/Write出现多个高电平即进行多次读写。读写信号Read/Write第一个上升沿到来时，即第一次读写开始，控制电路20的第一输出端J21输出的第一控制信号EqHigh跳变为低电平，并维持低电平预设时间t3后跳变到高电平。直到第一次读写操作完成后的预设时间之后，控制电路20的第一输出端J21输出的第一控制信号EqHigh再次跳变到低电平，并维持低电平至下一个读写操作开始后的预设时间后，跳变为高电平。以此类推，直到存储器未处于行激活状态。在存储器的行激活状态的一个周期结束时，行激活信号Row active由高电平跳变至低电平，同时，读写信号Read/Write维持在低电平，A点信号由低电平跳变至高电平，B点信号维持在低电平，C点信号由低电平跳变至高电平，D点信号由高电平跳变至低电平，所述第一控制信号EqHigh由低电平跳变至高电平，第二控制信号Eq由低电平跳变至高电平。
本实施例中，当第一控制信号EqHigh为低电平时，第一预充电电路10控制第一电源 端J11和数据端J15之间导通，第一电源端J11向数据端J15输入第一预充电压；当第一控制信号EqHigh为高电平时，第一预充电电路10控制第一电源端J11和数据端J15之间断开，第一电源端J11停止向数据端J15输入第一预充电压。
在一些示例中，控制电路20的第一输入端J23输入行激活信号Row active，控制电路20的第二输入端J24输入读写信号Read/Write；当行激活信号Row active为低电平时，存储器未处于行激活状态；当行激活信号Row active为高电平时，存储器处于行激活状态；当读写信号Read/Write为低电平时，存储器未进行读写操作；当读写信号Read/Write为高电平时，存储器进行读写操作。
在一些示例中，请参阅图1至图3，控制电路20包括第一反相单元21、延时单元22、第二反相单元23、锁存单元24、三输入或非门25、第三反相单元26；锁存单元24包括第一输入端、第二输入端及输出端。
第一反相单元21的输入端与锁存单元24的第一输入端连接并作为控制电路20的第一输入端J23，即第一反相单元21的输入端输入的信号为行激活信号Row active；第一反相单元21的第一输出端和第二输出端(参阅图3中A点)均用于输出行激活信号Row active反相后的信号。第一反相单元21的第一输出端为控制电路20的第二输出端J22，使得控制电路20输出给第二预充电单元12的控制端的第二控制信号Eq为行激活信号Row active反相后的信号。
三输入或非门25的第一输入端与第一反相单元21的第二输出端连接，三输入或非门25的第一输入端输入的信号即为行激活信号Row active反相后的信号。
延时单元22的输入端与第二反相单元23的输入端连接并作为控制电路20的第二输入端J24，延时单元22的输出端(参阅图3中B点)与三输入或非门25的第二输入端连接，即三输入或非门25的第二输入端输入的信号为读写信号Read/write延迟预设时间后的信号；延时单元22用于将读写信号Read/write延迟预设时间后输出；第二反相单元23用于输出读写信号Read/write反相后的信号。
锁存单元24的第二输入端与第二反相单元23的输出端连接，即锁存单元24的第一输入端输入的信号为行激活信号Row active，锁存单元24的第二输入端输入的信号为读写信号Read/write反相后的信号，锁存单元24的输出端(参阅图3中C点)与三输入或非门25的第三输入端连接。
第三反相单元26的输入端与三输入或非门25的输出端(参阅图3中D点)连接，第三反相单元26的输出端作为控制电路20的第一输出端J21；第三反相单元26用于将输入端输入的信号进行反相后输出，第三反相单元26的输出端为控制电路20的第一输出端J21。
具体的，在t1时间段内，在t1时间段内，第一反相单元21的输入端输入的行激活信号Row active为低电平，存储器未处于行激活状态，经过第一反相单元21反相后，第一反相单元21的第一输出端输出的第二控制信号Eq为高电平，第二预充电单元12的控制端接收到高电平后控制第二电源端J12与数据端J15之间导通，第二电源端J12向数据端J15输入第二预充电压；锁存单元24的第一输入端输入的行激活信号Row active为低电平，从而输出的信号，即C点信号为高电平。
在t2时间段内，第一反相单元21的输入端输入的行激活信号Row active为高电平，存储器处于行激活状态，经过第一反相单元21反相后，第一反相单元21的第二输出端输出的信号，即A点信号为低电平；即三输入或非门25的第一输入端输入的信号为低电平；延时单元22的输入端和第二反相单元23的输入端输入的信号均为读写信号Read/Write，为低电平，存储器未进行读写操作，延时单元22向三输入或非门25的第二输入端输入的信号为读写信号Read/Write延时预设时间后的信号，即B点信号，仍然为低电平。锁存单元24的第一输入端输入的行激活信号Row active为高电平，锁存单元24的第二输入端输 入的读写信号Read/write反相后的信号为高电平，锁存单元24的输出端输出的信号，即C点信号维持上一状态不变，为高电平；从而三输入或非门25输出端输出的信号即D点信号为低电平。经过第三反相单元26的反相后，第三反相单元26的输出端向第一预充电单元11的控制端输入高电平，从而第一预充电单元11控制第一电源端J11和数据端J15之间断开，第一电源端J11未向数据端J15输入第一预充电压。
在第一次读写操作开始后的预设时间t3内，第一反相单元21的输入端输入的行激活信号Row active为高电平，存储器处于行激活状态，经过第一反相单元21反相后，第一反相单元21的第二输出端输出的信号即A点信号为低电平，即三输入或非门25的第一输入端输入的信号为低电平；延时单元22的输入端和第二反相单元23的输入端输入的读写信号Read/Write为高电平，存储器进行读写操作，延时单元22向三输入或非门25的第二输入端输入的信号为读写信号Read/Write延时预设时间t3后的信号，即B点信号，仍然为低电平；锁存单元24的第一输入端输入的行激活信号Row active为高电平，锁存单元24的第二输入端输入的读写信号Read/write反相后的信号为低电平，锁存单元24的输出端输出的信号，即C点信号产生跳变，变为低电平；从而三输入或非门25输出端输出的信号，即D点信号为高电平。经过第三反相单元26的反相后，第三反相单元26的输出端向第一预充电单元11的控制端输入低电平，从而第一预充电单元11控制第一电源端J11和数据端J15之间导通，第一电源端J11向数据端J15输入第一预充电压。
在第一次读写操作开始后的预设时间t3之后，直至第一次读写操作结束的t4时间段内，第一反相单元21的输入端输入的行激活信号Row active为高电平，存储器处于行激活状态，经过第一反相单元21反相后，第一反相单元21的第二输出端输出的信号，即A点信号为低电平，即三输入或非门25的第一输入端输入的信号为低电平；延时单元22的输入端和第二反相单元23的输入端输入的读写信号Read/Write为高电平，存储器进行读写操作，延时单元22向三输入或非门25的第二输入端输入的信号为读写信号Read/Write延时预设时间t3后的信号，即B点信号，变为高电平；锁存单元24的第一输入端输入的行激活信号Row active为高电平，锁存单元24的第二输入端输入的读写信号Read/write反相后的信号为低电平，锁存单元24的输出端输出的信号，即C点信号保持不变，为低电平；从而三输入或非门25输出端输出的信号，即D点信号为低电平。经过第三反相单元26的反相后，第三反相单元26的输出端向第一预充电单元11的控制端输入高电平，从而第一预充电单元11控制第一电源端J11和数据端J15之间断开，第一电源端J11停止向数据端J15输入第一预充电压。
在第一次读写操作完成后的预设时间t5内，第一反相单元21的输入端输入的行激活信号Row active为高电平，存储器处于行激活状态，经过第一反相单元21反相后，第一反相单元21的第二输出端输出的信号，即A点信号为低电平，即三输入或非门25的第一输入端输入的信号为低电平；延时单元22的输入端和第二反相单元23的输入端输入的读写信号Read/Write为低电平，存储器未进行读写操作，延时单元22向三输入或非门25的第二输入端输入的信号为读写信号Read/Write延时预设时间t5后的信号，即B点信号仍为高电平；锁存单元24的第一输入端输入的行激活信号Row active为高电平，锁存单元24的第二输入端输入的读写信号Read/write反相后的信号为高电平，锁存单元24的输出端输出的信号，即C点信号维持上一状态不变，为低电平；从而三输入或非门25输出端输出的信号，即D点信号为低电平。经过第三反相单元26的反相后，第三反相单元26的输出端向第一预充电单元11的控制端输入高电平，从而第一预充电单元11控制第一电源端J11和数据端J15之间断开，第一电源端J11仍然停止向数据端J15输入第一预充电压。
在第一次读写操作完成后的预设时间t5之后，直至下一次读写操作开始的t6时间段内，第一反相单元21的输入端输入的行激活信号Row active为高电平，存储器处于行激 活状态，经过第一反相单元21反相后，第一反相单元21的第二输出端输出的信号，即A点信号为低电平，即三输入或非门25的第一输入端输入的信号为低电平；延时单元22的输入端和第二反相单元23的输入端输入的读写信号Read/Write为低电平，存储器未进行读写操作，延时单元22向三输入或非门25的第二输入端输入的信号为读写信号Read/Write延时预设时间t5后的信号，即B点信号变为低电平；锁存单元24的第一输入端输入的行激活信号Row active为高电平，锁存单元24的第二输入端输入的读写信号Read/write反相后的信号为高电平，锁存单元24的输出端输出的信号，即C点信号维持上一状态不变，为低电平；从而三输入或非门25输出端输出的信号，即D点信号为高电平。经过第三反相单元26的反相后，第三反相单元26的输出端向第一预充电单元11的控制端输入低电平，从而第一预充电单元11控制第一电源端J11和数据端J15之间导通，第一电源端J11向数据端J15输入第一预充电压。
在整个t7时间段内，第一反相单元21的输入端输入的行激活信号Row active为高电平，存储器处于行激活状态，经过第一反相单元21反相后，第一反相单元21的第一输出端输出的第二控制信号Eq为低电平，第二预充电单元12的控制端接收到低电平后控制第二电源端J12与数据端J15之间断开，第二电源端J12停止向数据端J15输入第二预充电压。
在一些示例中，请参阅图3，第一反相单元21包括N个依次串接的反相器27，第一反相单元21中的最后一个反相器27的输出端为第一反相单元21的第一输出端，第一反相单元21中的第N x个反相器27的输出端为第一反相单元21的第二输出端。其中，N、N x均为正奇数且N x小于或等于N。图3示例中，N等于3，N x等于1。
在一些示例中，请参阅图3，延时单元22包括M个依次串联的反相器27。其中，M为正偶数。图3示例中，M等于6。在其他示例中，延时单元22也可以采用其他为本领域技术人员所熟知的任意电路结构。
在一些示例中，请参阅图3，第二反相单元23包括Q个依次串接的反相器27。其中，Q为正奇数。图3示例中，Q等于1。
在一些示例中，请参阅图3，第三反相单元26包括P个依次串接的反相器27。其中，P为正奇数。图3示例中，P等于1。
需要说明的是，第一反相单元21中N和N x、延时单元22中M、第二反相单元23中Q以及第三反相单元26中P均不限于图3示例中的数量。
在一些示例中，请参阅图3，锁存单元24包括锁存器。在其他示例中，锁存单元24也可以采用本领域技术人员所熟知的任意电路结构。
在一些示例中，请参阅图3，锁存单元24包括：第一与非门28及第二与非门29。其中，第一与非门28的第一输入端作为锁存单元24的第一输入端，第一与非门28的第二输入端与第二与非门29的输出端连接，第一与非门28的输出端作为锁存单元24的输出端与三输入或非门25的第三输入端及第二与非门29的第一输入端连接，第二与非门29的第二输入端作为锁存单元24的第二输入端。
在一些示例中，请参阅图1和图4，数据端J15包括第一数据端J151和第二数据端J152，第一数据端J151和第二数据端J152接收互为相反的数据信号。譬如，第一数据端J151可以与局部数据线连接，从而接收LIO信号；第二数据端J152可以与互补局部数据线连接，从而接收LIO_信号。第一预充电单元11包括第一开关单元111和第二开关单元112，第一开关单元111的第一电连接端和第二开关单元112的第一电连接端均与第一电源端J11连接，第一电源端J11输入第一预充电压V1；第一开关单元111的控制端和第二开关单元112的控制端均与第一控制端J13连接，从而获取第一控制信号EqHigh。第一开关单元111的第二电连接端与第一数据端J151连接，第二开关单元112的第二电连接端与第二数据端J152连接；
在一些示例中，第一开关单元111和第二开关单元112的开关特性可以相同，控制电路20的第一输出端J21输出的第一控制信号EqHigh控制第一开关单元111的第一电连接端和第二电连接端之间导通，同时还控制第二开关单元112的第一电连接端和第二电连接端之间导通，使得第一电源端J11同时向第一数据端J151和第二数据端J152输入第一预充电压V1；或者控制电路20的第一输出端J21输出的第一控制信号EqHigh控制第一开关单元111的第一电连接端和第二电连接端之间断开，同时还控制第二开关单元112的第一电连接端和第二电连接端之间断开，使得第一电源端J11同时停止向第一数据端J151和第二数据端J152输入第一预充电压V1。
在一些示例中，第二预充电单元12包括第三开关单元121和第四开关单元122，第三开关单元121的第一电连接端和第四开关单元122的第一电连接端均与第二电源端J12连接，从而输入第二预充电压V2；第三开关单元121的控制端和第四开关单元122的控制端均与第二控制端J14连接，从而获取第二控制信号Eq。第三开关单元121的第二电连接端与第一数据端J151连接，第四开关单元122的第二电连接端与第二数据端J152连接。
在一些示例中，第三开关单元121和第四开关单元122的开关特性可以相同，控制电路20的第二输出端J22输出的第二控制信号Eq控制第三开关单元121的第一电连接端和第二电连接端之间导通，同时还控制第四开关单元122的第一电连接端和第二电连接端之间导通，使得第二电源端J12同时向第一数据端J151和第二数据端J152输入第二预充电压V2；或者控制电路20的第二输出端输出的第二控制信号Eq控制第三开关单元121的第一电连接端和第二电连接端之间断开，同时还控制第四开关单元122的第一电连接端和第二电连接端之间断开，使得第二电源端J12同时停止向第一数据端J151和第二数据端J152输入第二预充电压V2。
在一些示例中，第一开关单元111和第二开关单元112均包括PMOS管，第一开关单元111的第一电连接端和第二开关单元112的第一电连接端均为PMOS管的源极，第一开关单元111的第二电连接端和第二开关单元112的第二电连接端均为PMOS管的漏极，第一开关单元111的控制端和第二开关单元112的控制端均为PMOS管的栅极。譬如，可以参阅图4，第一开关单元包括PMOS管P1，第二开关单元包括PMOS管P2。
具体的，当第一控制信号EqHigh为高电平时，PMOS管P1的源极和漏极之间断开且PMOS管P2的源极和漏极之间断开，第一电源端J11停止向第一数据端J151和第二数据端J152输入第一预充电压V1；当第一控制信号EqHigh为低电平时，PMOS管P1的源极和漏极之间导通且PMOS管P2的源极和漏极之间导通，第一电源端J11向第一数据端J151和第二数据端J152输入第一预充电压V1。
在一些示例中，第三开关单元121和第四开关单元122均包括NMOS管，第三开关单元121的第一电连接端和第四开关单元122的第一电连接端均为NMOS管的源极，第三开关单元121的第二电连接端和第四开关单元122的第二电连接端均为NMOS管的漏极，第三开关单元121的控制端和第四开关单元122的控制端均为NMOS管的栅极。譬如，可以参阅图4，第三开关单元包括NMOS管N1，第四开关单元包括NMOS管N2。
具体的，当第二控制信号Eq为高电平时，NMOS管N1的源极和漏极之间导通且NMOS管N2的源极和漏极之间导通，第二电源端J12向第一数据端J151和第二数据端J152输入第二预充电压V2；当第二控制信号Eq为低电平时，NMOS管N1的源极和漏极之间断开且NMOS管N2的源极和漏极之间断开，第二电源端J12停止向第一数据端J151和第二数据端J152输入第二预充电压V2。
本申请还提供一种存储器预充电的控制方法，存储器预充电的控制方法应用于存储器的预充电电路。请继续参阅图1，预充电电路包括第一预充电单11，第二预充电单元12，第一电源端J11，第二电源端J12，第一控制端J13，第二控制端J14及数据端J15；第一 预充电单元11与第一电源端J11、第一控制端J13及数据端J15连接；第二预充电单元12与第二电源端J12、第二控制端J14及数据端J15连接；第一电源端J11输入第一预充电压，第二电源端J12输入第二预充电压。如图5所示，存储器预充电的控制方法包括：
步骤S51：判断存储器是否处于行激活状态。
若是，则执行步骤S53；否则，执行步骤S52。
步骤S52：通过第二预充电单元12控制数据端J15与第二电源端J12之间导通，且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开。
步骤S53：判断存储器是否进行读写操作。
若是，则执行步骤S55；否则，执行步骤S54。
步骤S54：通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开。
步骤S55：判断存储器是否进行第一次读写操作。
若是，则依次执行步骤S56及S57；否则，依次执行步骤S58及S59。
步骤S56：第一次读写操作开始后的预设时间内，通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间导通。
步骤S57：第一次读写操作开始后的预设时间之后，通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开。
步骤S58：第一次读写操作完成后的预设时间内，通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开。
步骤S59：第一次读写操作完成后的预设时间之后，通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间导通。
上述存储器预充电的控制方法当存储器处于行激活状态，且未进行读写操作时，通过第二预充电单元12控制数据端J15与第二电源端J12之间断开，且通过第一预充电单元11控制数据端J15与第一电源端J11之间断开，此时没有向数据端J15输入第一充电电压，也没有向数据端J15输入第二充电电压，使得不会对数据线进行预充电；当读写操作的命令到来时，再将数据端J15拉至第一预充电压，这样既能够减少耗电，又不会影响存储器的正常工作。同时，在第一次读写操作完成后的预设时间之后，存储器电路即通过数据端J15向数据线输入第一预充电压，使得存储器在后续的读写操作周期中，无需单独的预设时间进行预充电，提升了存储器的读写速度。
应该理解的是，虽然图5的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图5中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
在一些示例中，存储器在行激活状态的一个周期内进行多次读写操作，在存储器的行激活状态的一个周期内，每次读写操作完成后的预设时间之后，控制电路20通过第一预充电单元11控制数据端J15与第一电源端J11之间导通，并在下次读写操作开始后的预设时间之后，通过第一预充电单元11控制数据端J15与第一电源端J11之间断开。
上述存储器预充电的控制方法既保证了在每次数据读写之前对数据线预充电到电源电压，为后续数据读写做准备，又能够避免在存储器处于行激活状态且还未进行读写操作 时对电流的浪费。
本申请还提供一种计算机设备，包括存储器和处理器，存储器存储有计算机程序，处理器执行计算机程序时实现上述任一实施例中提供的存储器预充电的控制方法的步骤。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种存储器电路，包括：
    预充电电路，包括第一预充电单元，第二预充电单元，第一电源端，第二电源端，第一控制端，第二控制端及数据端；所述第一预充电单元与所述第一电源端、所述第一控制端及所述数据端连接；所述第二预充电单元与所述第二电源端、所述第二控制端及所述数据端连接；所述第一电源端输入第一预充电压，所述第二电源端输入第二预充电压；及
    控制电路，所述控制电路的第一输出端与所述第一控制端连接，所述控制电路的第二输出端与所述第二控制端连接；所述控制电路用于：
    当存储器未处于行激活状态时，通过所述第二预充电单元控制所述数据端与所述第二电源端之间导通，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
    当所述存储器处于行激活状态，且未进行读写操作时，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
    当所述存储器处于行激活状态，且第一次读写操作开始后的预设时间内，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通；
    当所述存储器处于行激活状态，且第一次读写操作开始后的预设时间之后，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
    当所述存储器处于行激活状态，且第一次读写操作完成后的预设时间内，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
    当所述存储器处于行激活状态，且第一次读写操作完成后的预设时间之后，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通。
  2. 根据权利要求1所述的存储器电路，其中，所述第一预充电压为所述存储器的电源电压，所述第二预充电压为所述存储器的电源电压的一半。
  3. 根据权利要求1所述的存储器电路，其中，所述存储器在行激活状态的一个周期内进行多次读写操作，在所述存储器的行激活状态的一个周期内，每次读写操作完成后的预设时间之后，所述控制电路通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通，并在下次读写操作开始后的预设时间之后，通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开。
  4. 根据权利要求1至3任一项所述的存储器电路，其中，所述控制电路的第一输入端输入行激活信号，所述控制电路的第二输入端输入读写信号；当所述行激活信号为低电平时，所述存储器未处于行激活状态；当所述行激活信号为高电平时，所述存储器处于行激活状态；当所述读写信号为低电平时，所述存储器未进行读写操作；当所述读写信号为高电平时，所述存储器进行读写操作。
  5. 根据权利要求4所述的存储器电路，其中，所述控制电路包括第一反相单元、延时单元、三输入或非门、第二反相单元、第三反相单元以及锁存单元，所述锁存单元包括第一输入端、第二输入端及输出端；其中，
    所述第一反相单元的输入端与所述锁存单元的第一输入端连接并作为所述控制电路的第一输入端，所述第一反相单元的第一输出端和第二输出端均用于输出所述行激活信号反相后的信号；所述第一反相单元的第一输出端为所述控制电路的第二输出端；
    所述三输入或非门的第一输入端与所述第一反相单元的第二输出端连接；
    所述延时单元的输入端与所述第二反相单元的输入端连接并作为所述控制电路的第二输入端，所述延时单元的输出端与所述三输入或非门的第二输入端连接；所述延时单元用于将所述读写信号延迟所述预设时间后输出；所述第二反相单元用于输出所述读写信号反相后的信号；
    所述锁存单元的第二输入端与所述第二反相单元的输出端连接，所述锁存单元的输出端与所述三输入或非门的第三输入端连接；
    所述第三反相单元的输入端与所述三输入或非门的输出端连接，所述第三反相单元的输出端作为所述控制电路的第一输出端；所述第三反相单元用于将输入端输入的信号进行反相后输出。
  6. 根据权利要求5所述的存储器电路，其中，所述第一反相单元包括N个依次串接的反相器，所述第一反相单元中的最后一个反相器的输出端为所述第一反相单元的第一输出端，所述第一反相单元中的第N x个反相器的输出端为所述第一反相单元的第二输出端；
    其中，N、N x均为正奇数且N x小于或等于N。
  7. 根据权利要求5所述的存储器电路，其中，所述延时单元包括M个依次串联的反相器；
    其中，M为正偶数。
  8. 根据权利要求5所述的存储器电路，其中，所述第二反相单元包括Q个依次串接的反相器；
    其中，Q为正奇数。
  9. 根据权利要求5所述的存储器电路，其中，所述第三反相单元包括P个依次串接的反相器；
    其中，P为正奇数。
  10. 根据权利要求5所述的存储器电路，其中，所述锁存单元包括锁存器。
  11. 根据权利要求10所述的存储器电路，其中，所述锁存单元包括：第一与非门及第二与非门；其中，
    所述第一与非门的第一输入端作为所述锁存单元的第一输入端，所述第一与非门的第二输入端与所述第二与非门的输出端连接，所述第一与非门的输出端作为所述锁存单元的输出端与所述三输入或非门的第三输入端及所述第二与非门的第一输入端连接；
    所述第二与非门的第二输入端作为所述锁存单元的第二输入端。
  12. 根据权利要求1所述的存储器电路，其中，所述数据端包括第一数据端和第二数据端，所述第一数据端和所述第二数据端接收互为相反的数据信号；所述第一预充电单元包括第一开关单元和第二开关单元，所述第一开关单元的第一电连接端和所述第二开关单元的第一电连接端均与所述第一电源端连接，所述第一开关单元的控制端和所述第二开关单元的控制端均与所述第一控制端连接，所述第一开关单元的第二电连接端与所述第一数 据端连接，所述第二开关单元的第二电连接端与所述第二数据端连接；
    所述第二预充电单元包括第三开关单元和第四开关单元，所述第三开关单元的第一电连接端和所述第四开关单元的第一电连接端均与所述第二电源端连接，所述第三开关单元的控制端和所述第四开关单元的控制端均与所述第二控制端连接，所述第三开关单元的第二电连接端与所述第一数据端连接，所述第四开关单元的第二电连接端与所述第二数据端连接。
  13. 根据权利要求12所述的存储器电路，其中，所述第一开关单元和所述第二开关单元均包括PMOS管，所述第一开关单元的第一电连接端和所述第二开关单元的第一电连接端均为所述PMOS管的源极，所述第一开关单元的第二电连接端和所述第二开关单元的第二电连接端均为所述PMOS管的漏极，所述第一开关单元的控制端和所述第二开关单元的控制端均为所述PMOS管的栅极；
    所述第三开关单元和所述第四开关单元均包括NMOS管，所述第三开关单元的第一电连接端和所述第四开关单元的第一电连接端均为所述NMOS管的源极，所述第三开关单元的第二电连接端和所述第四开关单元的第二电连接端均为所述NMOS管的漏极，所述第三开关单元的控制端和所述第四开关单元的控制端均为所述NMOS管的栅极。
  14. 一种存储器预充电的控制方法，应用于存储器的预充电电路，所述预充电电路包括第一预充电单元，第二预充电单元，第一电源端，第二电源端，第一控制端，第二控制端及数据端；所述第一预充电单元与所述第一电源端、所述第一控制端及所述数据端连接；所述第二预充电单元与所述第二电源端、所述第二控制端及所述数据端连接；所述第一电源端输入第一预充电压，所述第二电源端输入第二预充电压；所述方法包括：
    当所述存储器未处于行激活状态时，通过所述第二预充电单元控制所述数据端与所述第二电源端之间导通，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
    当所述存储器处于行激活状态，且未进行读写操作时，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
    当所述存储器处于行激活状态，且第一次读写操作开始后的预设时间内，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通；
    当所述存储器处于行激活状态，且第一次读写操作开始后的预设时间之后，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
    当所述存储器处于行激活状态，且第一次读写操作完成后的预设时间内，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间断开；
    当所述存储器处于行激活状态，且第一次读写操作完成后的预设时间之后，通过所述第二预充电单元控制所述数据端与所述第二电源端之间断开，且通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通。
  15. 根据权利要求14所述的存储器预充电的控制方法，其中，所述存储器在行激活状态的一个周期内进行多次读写操作，在所述存储器的行激活状态的一个周期内，每次读写操作完成后的预设时间之后，所述控制电路通过所述第一预充电单元控制所述数据端与所述第一电源端之间导通，并在下次读写操作开始后的预设时间之后，通过所述第一预充电 单元控制所述数据端与所述第一电源端之间断开。
  16. 一种计算机设备，包括存储器和处理器，所述存储器存储有计算机程序，所述处理器执行所述计算机程序时实现权利要求14或15所述的控制方法的步骤。
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