WO2022193786A1 - 阵列基板、液晶显示面板及液晶显示装置 - Google Patents

阵列基板、液晶显示面板及液晶显示装置 Download PDF

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Publication number
WO2022193786A1
WO2022193786A1 PCT/CN2021/143353 CN2021143353W WO2022193786A1 WO 2022193786 A1 WO2022193786 A1 WO 2022193786A1 CN 2021143353 W CN2021143353 W CN 2021143353W WO 2022193786 A1 WO2022193786 A1 WO 2022193786A1
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WO
WIPO (PCT)
Prior art keywords
metal pattern
array substrate
layer
signal lead
pattern layer
Prior art date
Application number
PCT/CN2021/143353
Other languages
English (en)
French (fr)
Inventor
何静
康报虹
Original Assignee
绵阳惠科光电科技有限公司
惠科股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 绵阳惠科光电科技有限公司, 惠科股份有限公司 filed Critical 绵阳惠科光电科技有限公司
Priority to JP2022542494A priority Critical patent/JP7341352B2/ja
Priority to EP21912345.2A priority patent/EP4310820A1/en
Priority to KR1020227022312A priority patent/KR20220131226A/ko
Priority to US17/907,825 priority patent/US20240192553A1/en
Publication of WO2022193786A1 publication Critical patent/WO2022193786A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133302—Rigid substrates, e.g. inorganic substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads

Definitions

  • the present application belongs to the field of display technology, and in particular, relates to an array substrate, a liquid crystal display panel and a liquid crystal display device.
  • LCDs Liquid crystal display panels
  • LCDs have the advantages of low radiation, small size and low power consumption, and are widely used in various electronic devices such as notebook computers and televisions.
  • the liquid crystal display panel usually includes an array substrate (thin film transistor, TFT), a color filter substrate (color filter, CF), a liquid crystal (liquid crystal, LC) sandwiched between the array substrate and the color filter substrate, and a sealant frame, etc. .
  • TFT thin film transistor
  • CF color filter substrate
  • LC liquid crystal
  • the array substrate includes a display area and a binding area disposed outside the display area. Since the array substrate needs to be bonded with various circuits to realize signal transmission, a bonding area is provided on the array substrate, and a plurality of conductive contacts are arranged in the bonding area of the array substrate, wherein each The conductive contacts are connected to a signal lead on the array substrate. Then, the conductive contacts of the array substrate are bound with the gold fingers of an external flexible printed circuit (FPC), and the external signal can be transmitted to the inside of the array substrate by using this structure to control the display screen.
  • FPC external flexible printed circuit
  • the routing direction of the signal leads in the array substrate and the extending direction of the conductive contacts are usually designed to be perpendicular to each other, so that the signal leads and the conductive contacts are connected to form an L-shape. Bend. If the gold finger has an alignment deviation when binding the conductive contacts and extends beyond the binding area to the top of the signal leads connected to other conductive contacts, when the protective layer covering the signal leads is crushed, the gold finger will This leads to conduction between different signal leads, resulting in a short circuit problem.
  • Embodiments of the present application provide an array substrate, a liquid crystal display panel, and a liquid crystal display device.
  • a second metal pattern layer to the protective layer above the bent signal leads, the signal leads can be protected. , so that the short circuit problem caused by the gold finger when binding the gold finger can be avoided.
  • an array substrate comprising: a base substrate, a first metal pattern layer and a protective layer that are stacked in sequence; the array substrate further includes: a display area and a peripheral area surrounding the display area, the The peripheral area includes a binding area and a non-binding area, and the binding area is located on at least one side outside the display area;
  • the first metal pattern layer includes a plurality of conductive contacts located in the binding area and spaced along a first direction, and a plurality of bent signal leads located in the non-binding area. One end of the conductive contact piece close to the display area is connected to the corresponding signal lead. The conductive contact piece extends along the second direction and is used for binding with the gold finger on the circuit board to be bound.
  • the first direction parallel to the edge of the display area closest to the binding area, the second direction and the first direction are perpendicular to each other;
  • the protective layer includes a first insulating layer and a second metal pattern layer that are stacked and arranged.
  • the first insulating layer is located where the second metal pattern layer is close to the base substrate.
  • a second metal pattern layer is added to the protective layer above the bent signal leads, so that when the gold fingers are bound with the conductive contacts, the second metal pattern of the signal leads is at least partially covered.
  • the metal pattern layer can withstand a certain binding pressure to provide protection for the signal leads, so that the short circuit problem caused by the binding in the prior art can be avoided.
  • the second metal pattern layer can also be prepared in the same layer as the source electrode and the drain electrode in the thin film transistor, so that no additional production cost is required.
  • a third metal pattern located in the binding region is further provided on a side of the protective layer away from the base substrate Floor;
  • the third metal pattern layer is connected to the conductive contact piece through a via hole disposed in the protective layer, and the third metal pattern layer is used for binding the conductive contact piece to the gold finger.
  • the conductive contacts and the gold fingers are turned on. In this implementation manner, the conductive contacts and the gold fingers are conducted through the third metal pattern layer as an intermediate medium.
  • the signal lead includes a first signal lead subsection extending along the second direction and a second signal lead subsection extending along the first direction, and the first signal lead subsection extends along the first direction.
  • the first end of a signal lead sub-section is connected to the conductive contact piece, and the second end is connected to one end of the second signal lead sub-section;
  • the second metal pattern layer includes a plurality of metal protection lines, so The metal protection line is located on the side of the signal lead away from the base substrate.
  • the metal protection line is located on the side of the signal lead away from the base substrate, which can prevent short circuit between the signal leads.
  • the projection of the metal protection line on the base substrate coincides with the projection of the signal lead on the base substrate.
  • the projection of the metal protection line on the base substrate coincides with the projection of the second signal lead subsection on the base substrate.
  • the metal protection line on the side of the second signal lead away from the base substrate includes a plurality of sub-metal protection lines; along the first direction, adjacent sub-metal protection lines The length of the second spacer between the metal protection lines is less than or equal to the length of the first spacer between two adjacent conductive contacts; wherein, the second spacers corresponding to different second signal leads , located between the extension lines of the two edges of the first spacer parallel to the second direction.
  • the metal protection line is configured as a structure of multiple sub-metal protection lines, even if the multiple gold fingers crush the first insulating layer on the same signal lead, due to the gaps between the sub-metal protection lines, Short circuit problems can be avoided.
  • the protective layer further includes: a second insulating layer;
  • the second metal pattern layer is located between the first insulating layer and the second insulating layer.
  • the gold fingers will only be connected to the second metal pattern layer, which can be avoided.
  • the signal lead is shorted to other signal leads.
  • the protective layer further includes: a second insulating layer;
  • the second insulating layer is located between the first insulating layer and the second metal pattern layer.
  • a liquid crystal display panel comprising: an opposite substrate and an array substrate as in the first aspect or any possible implementation manner of the first aspect, and a liquid crystal display panel disposed between the opposite substrate and the array substrate the liquid crystal layer in between.
  • a third aspect provides a liquid crystal display device, comprising: a circuit board to be bound and the liquid crystal display panel described in the second aspect;
  • the to-be-bonded circuit board is provided with a gold finger, the gold finger is adapted to the shape of the conductive contact piece on the array substrate in the liquid crystal display panel, and the gold finger is used for matching with the conductive contact piece. bind.
  • Embodiments of the present application provide an array substrate, a liquid crystal display panel, and a liquid crystal display device.
  • a second metal pattern layer to the protective layer above the bent signal leads, the gold fingers are bound to the conductive contacts. Timing, the second metal pattern layer covering at least part of the signal leads can withstand a certain binding pressure to provide protection for the signal leads, so that the short circuit problem caused by binding in the prior art can be avoided.
  • the second metal pattern layer can also be prepared in the same layer as the source electrode and the drain electrode in the thin film transistor, so that no additional production cost is required.
  • FIG. 1 is a schematic structural diagram of a liquid crystal display device
  • FIG. 2 is a schematic top view of an array substrate in FIG. 1;
  • Fig. 3 is the structural representation of the P region in Fig. 2;
  • FIG. 4 is a schematic structural diagram of the conductive contact piece in FIG. 3 after binding with the gold finger;
  • Fig. 5 is the cross-sectional schematic diagram of Fig. 4 along AA' direction;
  • FIG. 6 is a schematic cross-sectional view along the AA' direction after another conductive contact piece is bound with a gold finger;
  • FIG. 7 is a schematic structural diagram of a P region in an array substrate provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of the conductive contact piece and the gold finger in FIG. 7 after binding;
  • FIG. 9 is a schematic cross-sectional view of FIG. 8 along the BB' direction;
  • FIG. 10 is a schematic structural diagram of a signal lead 22
  • FIG. 11 is a schematic structural diagram of a P region in another array substrate provided by an embodiment of the present application.
  • Figure 12 is a schematic structural diagram of the conductive contact piece and the gold finger after binding in Figure 11;
  • Figure 13 is a schematic cross-sectional view of Figure 12 along the CC' direction;
  • FIG. 14 is a schematic structural diagram of a P region in another array substrate provided by an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a P region in yet another array substrate provided by an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of the first metal pattern layer and the second metal pattern layer in FIG. 15 .
  • liquid crystal display technology has been widely used in various electronic devices.
  • Electronic equipment that utilizes liquid crystal display technology for display includes a liquid crystal display device, and the liquid crystal display device usually includes a liquid crystal display panel and a driving device for driving the liquid crystal display panel, and the liquid crystal display panel in turn includes an array substrate.
  • the embodiment of the present application provides an array substrate, which is applied to a liquid crystal display device in an electronic device.
  • the electronic devices may be various types of electronic devices such as smart phones, tablet computers, electronic readers, in-vehicle computers, navigators, digital cameras, smart TVs, and smart wearable devices.
  • This embodiment of the present application does not impose any limitation on this.
  • FIG. 1 shows a schematic structural diagram of a liquid crystal display device 400 provided by an embodiment of the present application.
  • the main structure of the liquid crystal display device 400 includes a frame 1 , a cover glass 2 , a liquid crystal display panel 3 , a backlight module 4 , a circuit board 5 , and other electronic accessories including a camera.
  • the circuit board 5 is a driving device for driving the liquid crystal display panel 3 , or is a part of the driving device for driving the liquid crystal display panel 3 .
  • the circuit board 5 may be a flexible circuit board.
  • the liquid crystal display panel 3 includes an array substrate 31 , an opposite substrate 32 , a liquid crystal layer 33 disposed between the array substrate 31 and the opposite substrate 32 , and upper and lower polarizing layers.
  • the array substrate 31 and the opposite substrate 32 are assembled together by the frame sealant, so that the liquid crystal layer 33 is limited in the area surrounded by the frame sealant.
  • the opposite substrate 32 is a color filter substrate.
  • the longitudinal section of the frame 1 is U-shaped, the liquid crystal display panel 3, the backlight module 4, the circuit board 5 and other electronic accessories including cameras are arranged in the frame 1, the backlight module 4 is located under the liquid crystal display panel 3, and the circuit board 5 is located between the backlight module 4 and the frame 1 , and the cover plate 2 is located on the side of the liquid crystal display panel 3 away from the backlight module 4 .
  • FIG. 2 shows a schematic top view of an array substrate 31 in FIG. 1 .
  • the array substrate 31 includes a display area 10 and a peripheral area 20 surrounding the display area 10 .
  • the peripheral area 20 includes a binding area 210 and a non-binding area 220 , and the binding area 210 is disposed in the At least one side outside the display area 10 is illustrated in FIG. 2 by taking the binding area 210 located on the lower side outside the display area 10 as an example.
  • FIG. 3 is a schematic structural diagram of the P region in FIG. 2 .
  • FIG. 4 is a schematic structural diagram of the conductive contact piece in FIG. 3 after binding with the gold finger.
  • FIG. 5 is a schematic cross-sectional view of FIG. 4 along the AA' direction.
  • FIG. 6 is a schematic cross-sectional view of another conductive contact piece along the AA' direction after binding with the gold finger.
  • the display area 10 of the array substrate 31 is provided with various signal lines 11 for displaying, and the binding area 210 is provided with a plurality of conductive contacts 21 arranged along the x direction (as shown in FIG. 3 to M1 to M4 shown in FIG. 6 ), a plurality of signal leads 22 (L1 to L4 shown in FIG. 3 to FIG. 6 ) are provided in the non-binding area 220 .
  • the signal lines 11 of the display area 10 and the conductive contacts 21 of the bonding area 210 are connected through the signal leads 22 in the non-bonding area 220 .
  • the signal leads 22 are in a one-to-one correspondence with the conductive contacts 21 .
  • the conductive contacts 21 are bound with the gold fingers 40 of the FPC, that is, the conductive contacts 21 and the gold fingers 40 are in one-to-one correspondence and connected, so that the signals provided by the circuit board 5 can be
  • the sequence of the chip 21 , the signal lead 22 and the signal line 11 is transmitted to the inside of the display area 10 to control the display screen.
  • the four conductive contacts 21 are along the first direction (such as the x direction) are arranged in order.
  • Each of the conductive contacts 21 extends along the second direction (eg, the y direction), and the x direction and the y direction are perpendicular to each other.
  • each conductive contact 21 close to the display area 10 is connected with a signal lead 22 .
  • the signal lead 22 is used to connect with the signal line 11 inside the display area 10 .
  • the shape of the signal lead 22 is generally bent, for example, the shape of the signal lead 22 may be an L-shaped bend, that is, each signal lead 22 may include a first signal lead extending along the second direction y
  • the subsection 221 and the second signal lead subsection 222 connected to one end of the first signal lead subsection 221 and extending along the first direction x.
  • each conductive contact 21 is used for binding with one gold finger 40 of the FPC.
  • the length of the first signal lead sub-portion 221 included in the signal lead 22 extending along the second direction y is usually compressed, and the length along the second The length of the second signal lead sub-portion 222 extending in one direction x.
  • the gold finger 40 when the conductive contact piece 21 is bound to the gold finger 40 of the FPC, if the gold finger 40 has a misalignment due to problems such as limited equipment accuracy or the design of the alignment mark position, It does not accurately cover the top of the conductive contacts 21, but extends to the top of the signal leads 22 connected to other conductive contacts 21. At this time, although a protective layer 320 is also provided above the signal leads 22, the pressure during binding is relatively large. , the gold finger 40 is very likely to crush the protective layer 320 above the signal lead 22 , which will cause the gold finger 40 to connect to different signal leads 22 , resulting in a short circuit problem, and then the array substrate cannot work normally.
  • the protective layer 320 (the Q area shown in FIG. 5 ) above the signal lead 22 connected to the conductive contact piece M2 is crushed, which will make the signal lead L1 connected to the conductive contact piece M1
  • the signal lead L2 connected to the conductive contact piece M2 is conducted through the gold finger 40, thereby causing a short circuit problem.
  • Example 2 originally only the gold finger 40 above the conductive contact piece M1 needs to be covered due to the misalignment, and it also covers the top of the signal lead 22 connected to the conductive contact piece M2, the conductive contact piece M3, and the conductive contact piece M4. , if the gold finger 40 is bound with the conductive contact piece M1, the protective layer 320 on the conductive contact piece M2, the conductive contact piece M3, and the conductive contact piece M4 is crushed (the R area shown in FIG.
  • the signal lead L2, the signal lead L3, the signal lead L4, and the signal lead L1 connected to the conductive contact piece M2, the conductive contact piece M3, and the conductive contact piece M4, respectively, are conducted through the gold finger 40, and all the four signal leads are short-circuited, resulting in The array substrate 31 cannot work normally.
  • an embodiment of the present application provides an array substrate.
  • a second metal pattern layer that at least partially covers the signal leads in the protective layer above the signal leads, so that when the gold fingers are bound with the conductive contacts,
  • the second metal pattern layer can withstand a certain binding pressure to provide protection for the signal leads, so that the short circuit problem caused by the binding in the prior art can be avoided.
  • FIG. 7 is a schematic structural diagram of a P region in an array substrate provided by an embodiment of the present application
  • FIG. 8 is a structural schematic diagram of the conductive contact piece and the gold finger in FIG. 7 after binding
  • FIG. 9 is a schematic cross-sectional view along the direction BB' of FIG. 8 .
  • the array substrate provided by the embodiments of the present application includes a base substrate 300 , a first metal pattern layer 310 , and a protective layer 320 that are stacked in sequence.
  • the protective layer 320 is provided on one side of the base substrate 300 , and the first metal pattern layer 310 is provided between the base substrate 310 and the protective layer 320 .
  • the protective layer 320 may include a multi-layer structure, and the embodiments of the present application do not impose any limitations on the number of layers and the positions between the layers included in the protective layer 30 .
  • the array substrate 31 further includes: a display area 10 and a peripheral area 20 surrounding the display area 10 .
  • the peripheral area 20 includes a binding area 210 and a non-binding area 220 , and the binding area 210 is located at least one part outside the display area 10 . side.
  • the display area 10 refers to the area where the array substrate 31 can display images, and can be arranged in the middle area of the array substrate 31 .
  • the display area 10 that is arranged at the center of the array substrate 31 and has a rectangular shape is example.
  • the peripheral area 20 refers to an area where images cannot be displayed, and is arranged around the display area 10 .
  • the embodiment of the present application takes the peripheral area 20 having the same width around the display area 10 as an example.
  • the peripheral area 20 is used for arranging circuit traces and other electronic components for driving.
  • the binding area 210 refers to the area where the array substrate 31 is used for connecting the gold fingers 40 of the FPC, and is usually disposed on the side outside the display area 10 . In this embodiment of the present application, the binding area 210 is located in the display area 10 . the lower side as an example.
  • the non-binding area 220 refers to all the remaining areas in the peripheral area 20 except the over-binding area 210 .
  • the first metal pattern layer 310 includes a plurality of conductive contacts 21 located in the bonding area 210 and spaced along the first direction, and a plurality of bent signal leads 22 located in the non-binding area 220.
  • the conductive contacts One end of 21 close to the display area 10 is connected to the corresponding signal lead 22 .
  • the conductive contact piece 21 extends along the second direction for binding with the gold finger 40 on the circuit board to be bound.
  • the first direction is parallel to the edge of the display area 10 closest to the binding area 210
  • the second direction is parallel to the edge of the display area 10 closest to the binding area 210
  • the first directions are perpendicular to each other.
  • the display area 10 and the binding area 210 are both rectangles, and the binding area 210 is located on the lower side of the display area 10 as an example, and the first direction is parallel to the display area 10 and away from the binding area.
  • the closest edge of 210 refers to the edge below the display area 10 that is close to the binding area 210 , that is, the first direction is the x-direction.
  • the second direction and the first direction are perpendicular to each other, and the second direction is the y direction.
  • the first metal pattern layer 310 includes a plurality of conductive contacts 21 located in the bonding area 210 and spaced along the x direction, each conductive contact 21 extends along the y direction, and each conductive contact 21 is close to One end (the upper end) of the display area 10 is connected to the corresponding signal lead 22 .
  • the conductive contacts 21 and the signal leads 22 are in one-to-one correspondence, so that the signal leads 22 are connected to the signal lines of the display area 10, so that the conductive contacts 21 are bound to the gold fingers 40 of the circuit board to be bound. If it is determined, the signal can be transmitted from the outside to the display area 10 to control the display screen.
  • the circuit board to be bound may be an FPC.
  • the size of the binding area 210 can be set as required, which is not limited in the embodiment of the present application.
  • the cross-sectional width of the conductive contacts 21 is the same as that of the signal leads 22.
  • the widths of the cross-sections of the conductors can be the same or different, and thus, the interval between the conductive contacts 21 and the interval between the signal leads 22 can be the same or different.
  • the routing direction of the bent signal lead 22 can be set as required, which is not limited in the embodiment of the present application.
  • first metal pattern layer 310 and the gate electrode in the thin film transistor (Thin Film Transistor, TFT) disposed in the display area 10 may be prepared by using the same material and in the same layer.
  • the protective layer 320 includes a first insulating layer 321 and a second metal pattern layer 323 that are stacked and arranged.
  • the first insulating layer 321 is located on the side of the second metal pattern layer 323 close to the base substrate, wherein , the second metal pattern layer 323 is located in the unbonded area 220 , and the second metal pattern layer 323 at least partially covers the signal lead 22 .
  • the protective layer 320 may be laid on the entire layer of the first metal pattern layer 310 on the side of the first metal pattern layer 310 away from the base substrate 300 and the region of the base substrate 300 where the first metal pattern layer 310 is not laid. Having a certain shape, the protective layer 320 laid on the first metal pattern layer 310 will vary with the shape of the first metal pattern layer 310 . For example, part of the protective layer 320 is laid over the conductive contacts 21 , part of the protective layer 320 is laid at the space between the conductive contacts 21 , part of the protective layer 320 is laid over the signal leads 22 , and part of the protective layer 320 is laid on the signal leads 22 . space between the leads 22 .
  • the protective layer 320 may also be laid on the side of the first metal pattern layer 310 away from the base substrate 300 , or the protective layer 320 may be laid only in the non-binding area 220 , which is not performed in this embodiment of the present application. limit.
  • the protective layer 320 is used to protect the conductive contacts 21 and the signal leads 22 .
  • the protective layer 320 includes the first insulating layer 321 and the second metal pattern layer 323 which are arranged in layers, the film layer structure from bottom to top along the thickness direction of the array substrate 31 is, in order, the base substrate 300 , the The first metal pattern layer 310 , the first insulating layer 321 and the second metal pattern layer 323 .
  • the protective layer 320 includes the first insulating layer 321, and the first insulating layer 321 is located between the first metal pattern layer 310 and the second metal pattern layer 323, the second metal pattern layer 323 located in the unbonded region 220 It is not adjacent to the signal leads 22 included in the first metal pattern layer 310 .
  • the protective layer 320 may further include other layers on the side of the first insulating layer 321 close to the second metal pattern layer 323, or between the side close to the first metal pattern layer 310, which can be set as required. The application examples do not impose any restrictions on this.
  • the so-called second metal pattern layer 323 at least partially covering the signal lead 22 means that the second metal pattern layer 323 located in the non-binding area 220 may be laid on the entire layer, or may be laid only on the corresponding top of the signal lead 22 That is, the projection of the second metal pattern layer 323 on the base substrate 300 coincides with the projection of the signal lead 22 on the base substrate 300 , and the second metal pattern layer 323 may also be partially laid on the signal lead 22 .
  • the laying area of the second metal pattern layer 323 may be specifically set as required, which is not limited in this embodiment of the present application.
  • the second metal pattern layer 323 and the source and drain electrodes of the TFT disposed in the display area 10 may be prepared by using the same material and in the same layer.
  • a second metal pattern layer 323 is added to the protective layer 320, it can not only provide protection for the signal leads 22, but also reduce the possibility of short circuit problems when the gold fingers 40 are bound. It is added above the signal lead 22 without compressing the design space of the signal lead 22 in the unbonded area 220 . In addition, it can also be prepared in the same layer as the source electrode and the drain electrode in the TFT, so that no additional production cost is required.
  • An embodiment of the present application provides an array substrate.
  • the second metal pattern layer By adding a second metal pattern layer to the protective layer above the bent signal leads, when the gold fingers are bound with the conductive contacts, the second metal pattern layer It can withstand a certain binding pressure and provide protection for the signal leads, so as to avoid the short circuit problem caused by binding in the prior art.
  • a side of the protective layer 320 away from the base substrate 300 is further provided with a binding area 210 located on the side of the protective layer 320 .
  • the third metal pattern layer 330 is further provided along the thickness direction of the base substrate 300 .
  • the third metal pattern layer 330 is connected to the conductive contact piece 21 through the via hole 340 disposed in the protective layer 320 , and the third metal pattern layer 330 is used to conduct the conductive contact piece when the conductive contact piece 21 is bound with the gold finger 40 . 21 and Goldfinger 40.
  • the entire protective layer 320 is usually laid.
  • a via hole 340 needs to be opened in the protective layer 320 above the conductive contacts 21 and then laid
  • the third metal pattern layer 330 conducts the conductive contacts 21 and the gold fingers 40 through the third metal pattern layer 330 as an intermediate medium.
  • the embodiments of the present application do not impose any restrictions on the number, shape, and specific positions of the via holes 340 .
  • the third metal pattern layer 330 and the pixel electrodes disposed in the display area 10 may be prepared by using the same material and in the same layer.
  • the third metal pattern layer 330 located in the bonding area 210 is not in contact with the second metal pattern layer 323 located in the non-binding area 220 .
  • the protective layer 320 further includes: a second insulating layer 322 .
  • the second metal pattern layer 323 is located between the first insulating layer 321 and the second insulating layer 322 .
  • the base substrate 300 , the first insulating layer 321 , the second metal pattern layer 323 , and the second insulating layer 322 are sequentially arranged from bottom to top;
  • the first insulating layer 321 and the second insulating layer 322 can also be exchanged.
  • the base substrate 300 , the second insulating layer 322 , the second metal pattern layer 323 , and the first insulating layer 321 are sequentially from bottom to top.
  • first insulating layer 321 and the second insulating layer 322 are both laid on the whole layer.
  • the first insulating layer 321 may be the same as that of the TFT provided in the display area 10.
  • the source layer is prepared in the same layer, and the second insulating layer 322 can be prepared in the same layer as the insulating layer laid in the display area 10 . Based on this structure, when the pair of gold fingers 40 is bound to the conductive contact piece 21 , even if the gold fingers 40 crush the second insulating layer 322 above the signal leads 22 , the gold fingers 40 will only bind to the second metal pattern layer 323 . connection, the short circuit between the signal lead 22 and other signal leads 22 can still be avoided.
  • the protective layer 320 further includes: a second insulating layer 322;
  • the second insulating layer 322 is located between the first insulating layer 321 and the second metal pattern layer 323 .
  • the base substrate 300, the first insulating layer 321, the second insulating layer 322, and the second metal pattern layer 323 are sequentially from bottom to top;
  • the two insulating layers 322 can also be exchanged.
  • the base substrate 300 , the second insulating layer 322 , the first insulating layer 321 , and the second metal pattern layer 323 are sequentially from bottom to top.
  • FIG. 10 shows a schematic structural diagram of a signal lead 22 .
  • the signal lead 22 includes a first signal lead subsection 221 extending along the second direction and a second signal lead subsection 222 extending along the first direction.
  • the first end of the first signal lead subsection 221 is connected to the conductive contact 21 , the second end is connected to one end of the second signal lead sub-portion 222 .
  • the signal lead L1 includes a first signal lead subsection L11 extending in the second direction y, and a second signal lead subsection L12 extending in the first direction x, the first signal lead subsection L11
  • the first end (the lower end) of the L1 is connected to the conductive contact piece 21, and the second end (such as the upper end) is connected to one end of the second signal lead sub-section L12, thus, the formed signal lead L1 has an L-bend shape.
  • the other signal leads 22 also have an L-bend shape.
  • the second metal pattern layer 323 includes a plurality of metal protection lines 3230 , and the metal protection lines 3230 are located on the side of the signal lead away from the base substrate 300 .
  • the second metal pattern layer 323 added in the protection layer 320 may include a plurality of metal protection lines 3230, and the metal protection lines 3230 are located on the side of the signal lead 22 away from the base substrate 300, which can prevent the signal leads 22 from interacting with each other. short circuit. That is to say, the metal protection wires 3230 are in one-to-one correspondence with the signal leads 22 , and the metal protection wires 3230 play a protective role for the corresponding signal leads 22 . In this way, compared to laying the second metal pattern layer 323 in the whole non-binding area 220, some materials can be saved.
  • FIG. 11 is a schematic structural diagram of the P region in another array substrate 31 provided by the embodiment of the present application
  • FIG. 12 is the conductive contact piece in FIG. 11 after binding with the gold finger.
  • FIG. 13 is a schematic cross-sectional view of FIG. 12 along the CC' direction.
  • the projection of the metal protection line 3230 on the base substrate 300 coincides with the projection of the signal lead 22 on the base substrate.
  • the metal protection line 3230 on the side of the signal lead 22 away from the base substrate is also bent in an L shape.
  • the metal protection line 3230 is G1 to G4 as shown in FIGS. 11 to 13 .
  • the metal protection wires G1-G4 correspond to the signal leads L1-L4 one-to-one respectively.
  • the cross section of the signal lead 22 may be rectangular or trapezoidal.
  • the cross-sectional width of the metal protection line 3230 is equal to the cross-sectional width of the signal lead 22 .
  • the cross-sectional width of the metal protection line 3230 may correspond to the cross-sectional width of the signal lead 22 (the length parallel to the side length of the base substrate 300 ), that is, the metal protection line
  • the cross-sectional width of the 3230 is equal to the cross-sectional width of the signal lead 22; when the cross-section of the signal lead 22 is a trapezoid, the cross-sectional width of the metal protection line 3230 may correspond to the cross-sectional width of the signal lead 22 (parallel to the bottom of the base substrate 300).
  • the length of the bottom edge), that is, the cross-sectional width of the metal protection line 3230 is equal to the cross-sectional width of the signal lead 22 .
  • FIG. 14 is a schematic structural diagram of the P region in yet another array substrate 31 provided in an embodiment of the present application. As shown in FIG. 14 , the projection of the metal protection line 3230 on the base substrate 300 coincides with the projection of the second signal lead sub-portion 222 on the base substrate 300 .
  • the metal protection line 3230 may be provided only above the second signal lead sub-portion 222 to protect the first The role of the two signal lead sub-sections 222 .
  • FIG. 15 is a schematic structural diagram of the P region in yet another array substrate provided by an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of the first metal pattern layer and the second metal pattern layer in FIG. 15 .
  • the metal protection line 3230 located on the side of the second signal lead sub-portion 222 away from the base substrate 300 includes a plurality of sub-metal protection lines 3231 .
  • each metal protection line 3230 and the length of each sub-metal protection line 3231 can be set as required, which is not limited in this embodiment of the present application.
  • the length of the second spacer between adjacent sub-metal protection lines 3231 is less than or equal to the length of the first spacer between two adjacent conductive contacts.
  • the second spacers corresponding to different second signal lead sub-portions 222 are located between the extension lines of the two edges of the first spacer that are parallel to the second direction.
  • the length of the second spacer region S2 between adjacent sub-metal protection lines 3231 is less than or equal to the length of the first space between the two connected conductive contacts 21 .
  • the length of the spacer S1 (d1 as shown in Figure 16).
  • the extension lines of the two edges parallel to the second direction y are respectively s1 and s2. Therefore, in the extension line A plurality of second spacers are distributed between s1 and s2 , and each second spacer corresponds to a second signal lead sub-section 222 .
  • each second spacer corresponds to a second signal Lead sub-section 222 .
  • the first gold finger 40 and the second gold finger 40 arranged in the first direction break the first insulating layer 321 on the signal lead L2, at this time, the The first gold finger 40 and the second gold finger 40 may be conducted through the signal lead L2, which further leads to the conduction of the signal lead L1 and the signal lead L2. Therefore, as shown in FIG. 15 , when there is a second gap area between the sub-metal protection lines 3231 laid above the signal lead L2, the first gold finger 40 and the second gold finger 40 can be isolated to avoid occurrence of short circuit problem.
  • Embodiments of the present application further provide a liquid crystal display panel, comprising: an opposite substrate and the above-mentioned array substrate, and a liquid crystal layer disposed between the opposite substrate and the array substrate.
  • Embodiments of the present application further provide a liquid crystal display device, comprising: a circuit board to be bound and the liquid crystal display panel described above;
  • a gold finger is arranged on the circuit board to be bound, the gold finger is adapted to the shape of the conductive contact piece on the array substrate in the liquid crystal display panel, and the gold finger is used for binding with the conductive contact piece.

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Abstract

一种阵列基板(31)、液晶显示面板(3)及液晶显示装置(400)，阵列基板(31)包括：依次层叠设置的衬底基板(300)、第一金属图案层(310)和保护层(320)，阵列基板(31)还包括：显示区(10)和环绕显示区(10)的周边区(20)，周边区(20)包括绑定区(210)和非绑定区(220)，绑定区(210)位于显示区(10)外至少一侧；第一金属图案层(310)包括位于绑定区(210)且沿第一方向间隔排布的多个导电触片(21)，以及位于非绑定区(220)的多条呈弯折状的信号引线(22)；保护层(320)包括层叠设置的第一绝缘层(321)和第二金属图案层(323)，沿衬底基板(300)的厚度方向，第一绝缘层(321)位于第二金属图案层(323)靠近衬底基板(300)的一侧。通过在保护层(320)中增设至少部分覆盖信号引线(22)的第二金属图案层(323)，可以起到保护信号引线(22)的作用，避免金手指(40)造成的短路问题。

Description

阵列基板、液晶显示面板及液晶显示装置
本申请要求于2021年03月18日在中华人民共和国国家知识产权局专利局提交的、申请号为202110290698.5、发明名称为“阵列基板、液晶显示面板及液晶显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请属于显示技术领域，尤其涉及一种阵列基板、液晶显示面板及液晶显示装置。
 背景技术
液晶显示面板（liquid crystal display，LCD）具有低辐射、体积小及低耗能等优点，被广泛的应用于笔记本电脑、电视等各种电子设备中。
其中，液晶显示面板通常包括阵列基板（thin film transistor，TFT）、彩膜基板（color filter，CF）、夹在阵列基板和彩膜基板之间的液晶（liquid crystal，LC）以及密封胶框等。
阵列基板包括显示区和设置在显示区外的绑定区。由于阵列基板需要与各种电路进行绑定（bonding）以实现信号传递，因此，阵列基板上设置有绑定区，并在阵列基板的绑定区内设置有多个导电触片，其中，每个导电触片与阵列基板上的一条信号引线相连接。然后，阵列基板的导电触片再与外部的柔性电路板（flexible printed circuit，FPC）的金手指进行绑定，利用该结构可以将外界信号传递到阵列基板内部以控制显示画面。
但是，现有技术中，为了实现窄边框，阵列基板内信号引线的走线方向与导电触片的延伸方向通常设计成相互垂直的，这样，信号引线与导电触片连接起来就形成了L形弯折。若金手指在绑定导电触片时出现对位偏差，超出绑定区后延伸到其他导电触片连接的信号引线的上方时，当信号引线上覆盖的保护层被压破时，金手指会导致不同的信号引线之间导通，从而出现短路问题。
由此，亟待一种能避免上述短路问题的阵列基板。
 技术问题
本申请实施例提供了一种阵列基板、液晶显示面板及液晶显示装置，通过在呈弯折状的信号引线上方的保护层中增设一层第二金属图案层，可以起到保护信号引线的作用，从而可以避免绑定金手指时通过金手指造成的短路问题。
 技术解决方案
第一方面，提供了一种阵列基板，包括：依次层叠设置的衬底基板、第一金属图案层和保护层；所述阵列基板还包括：显示区和环绕所述显示区的周边区，所述周边区包括绑定区和非绑定区，所述绑定区位于显示区外至少一侧；
所述第一金属图案层包括位于所述绑定区且沿第一方向间隔排布的多个导电触片，以及位于所述非绑定区的多条呈弯折状的信号引线，所述导电触片靠近所述显示区的一端与对应的信号引线相连接，所述导电触片沿第二方向延伸，用于与待绑定电路板上的金手指进行绑定，所述第一方向平行于所述显示区距离与所述绑定区最近的边沿，所述第二方向与所述第一方向相互垂直；
所述保护层包括层叠设置的第一绝缘层和第二金属图案层，沿所述衬底基板的厚度方向，所述第一绝缘层位于所述第二金属图案层靠近所述衬底基板的一侧，其中，第二金属图案层位于所述非绑定区，所述第二金属图案层至少部分覆盖所述信号引线。
第一方面提供的阵列基板，通过在呈弯折状的信号引线上方的保护层中增加第二金属图案层，以使得金手指与导电触片进行绑定时，至少部分覆盖信号引线的第二金属图案层能承受一定的绑定压力，为信号引线提供保护，从而可以避免出现现有技术中绑定造成的短路问题。此外，第二金属图案层还可以与薄膜晶体管中的源极和漏极同层制备，由此，也不需要额外增加生产成本。
在第一方面一种可能的实现方式中，沿所述衬底基板的厚度方向，在所述保护层远离所述衬底基板的一侧还设置有位于所述绑定区的第三金属图案层；
所述第三金属图案层通过设置于所述保护层中的过孔与所述导电触片连接，所述第三金属图案层用于在所述导电触片与所述金手指绑定时，导通所述导电触片和所述金手指。在该实现方式中，通过第三金属图案层作为中间介质导通导电触片和金手指。
在第一方面一种可能的实现方式中，所述信号引线包括沿所述第二方向延伸的第一信号引线子部及沿所述第一方向延伸的第二信号引线子部，所述第一信号引线子部的第一端与所述导电触片相连接，第二端与所述第二信号引线子部的一端相连接；所述第二金属图案层包括多条金属保护线，所述金属保护线位于信号引线远离所述衬底基板的一侧。在该实现方式中，金属保护线位于信号引线远离衬底基板的一侧，可以防止信号引线之间互相短路。
在第一方面一种可能的实现方式中，所述金属保护线在所述衬底基板上的投影与所述信号引线在衬底基板上的投影重合。
在第一方面一种可能的实现方式中，所述金属保护线在所述衬底基板上的投影与所述第二信号引线子部在所述衬底基板上的投影重合。
在第一方面一种可能的实现方式中，位于所述第二信号引线远离所述衬底基板一侧的所述金属保护线包括多个子金属保护线；沿所述第一方向，相邻子金属保护线之间的第二间隔区的长度小于或者等于相邻两个所述导电触片之间的第一间隔区的长度；其中，不同的第二信号引线对应的所述第二间隔区，位于所述第一间隔区平行于所述第二方向的两条边沿的延长线之间。在该实现方式中，在金属保护线设置为多个子金属保护线的结构后，即使多个金手指均压破同一信号引线上的第一绝缘层，但是由于子金属保护线之间具有间隙，可以避免出现短路问题。
在第一方面一种可能的实现方式中，所述保护层还包括：第二绝缘层；
沿所述衬底基板的厚度方向，所述第二金属图案层位于所述第一绝缘层和所述第二绝缘层之间。在该实现方式中，当一对金手指与导电触片绑定时，即使金手指压破了信号引线上方的第二绝缘层，金手指也只会和第二金属图案层连接，还是可以避免信号引线与其他信号引线短路。
在第一方面一种可能的实现方式中，所述保护层还包括：第二绝缘层；
沿所述衬底基板的厚度方向，所述第二绝缘层位于所述第一绝缘层和所述第二金属图案层之间。
第二方面，提供一种液晶显示面板，包括：对置基板和如第一方面或第一方面的任意可能的实现方式中的阵列基板，以及设置在所述对置基板和所述阵列基板之间的液晶层。
第三方面，提供一种液晶显示装置，包括：待绑定电路板和第二方面所述的液晶显示面板；
所述待绑定电路板上设置有金手指，所述金手指与所述液晶显示面板中的阵列基板上的导电触片的形状相适应，所述金手指用于与所述导电触片相绑定。
 有益效果
本申请实施例提供了一种阵列基板、液晶显示面板及液晶显示装置，通过在呈弯折状的信号引线上方的保护层中增加第二金属图案层，以使得金手指与导电触片进行绑定时，至少部分覆盖信号引线的第二金属图案层能承受一定的绑定压力，为信号引线提供保护，从而可以避免出现现有技术中绑定造成的短路问题。此外，第二金属图案层还可以与薄膜晶体管中的源极和漏极同层制备，由此，也不需要额外增加生产成本。
 附图说明
为了更清楚地说明本申请实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种液晶显示装置的结构示意图；
图2是图1中的一种阵列基板的俯视示意图；
图3是图2中的P区域的结构示意图；
图4是图3中的导电触片与金手指绑定后的结构示意图；
图5是图4沿AA'方向的截面示意图；
图6是另一种导电触片与金手指绑定后沿AA'方向的截面示意图；
图7是本申请实施例提供的一种阵列基板中P区域的结构示意图；
图8是图7中导电触片与金手指绑定后的结构示意图；
图9是图8沿BB'方向的截面示意图；
图10是一种信号引线22的结构示意图；
图11是本申请实施例提供的另一种阵列基板中P区域的结构示意图；
图12图11中导电触片与金手指绑定后的结构示意图；
图13是图12沿CC'方向的截面示意图；
图14是本申请实施例提供的又一种阵列基板中P区域的结构示意图；
图15是本申请实施例提供的又一种阵列基板中P区域的结构示意图；
图16是图15中的第一金属图案层和第二金属图案层的结构示意图。
附图标记：
1-框架；2-盖板玻璃；3-液晶显示面板；4-背光模组；5-电路板；10-显示区；11-信号线；20-周边区；210-绑定区；220-非绑定区；21-导电触片；22-信号引线；221-第一信号引线子部；222-第二信号引线子部；31-阵列基板；32-对置基板；33-液晶层；40-金手指；300-衬底基板；310-第一金属图案层；320-保护层；321-第一绝缘层；322-第二绝缘层；323-第二金属图案层；3230-金属保护线；3231-子金属保护线；330-第三金属图案层；340-过孔；400-液晶显示装置。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
 本发明的实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
随着显示技术的发展，液晶显示技术已被广泛的应用于各种电子设备中。利用液晶显示技术进行显示的电子设备包括液晶显示装置，而液晶显示装置通常包括液晶显示面板和用于驱动液晶显示面板的驱动装置，液晶显示面板又包括阵列基板。本申请实施例提供了一种阵列基板，应用于电子设备中的液晶显示装置中。
其中，电子设备可以为智能手机、平板电脑、电子阅读器、车载电脑、导航仪、数码相机、智能电视机以及智能可穿戴设备等多种不同类型的电子设备。本申请实施例对此不进行任何限制。
图1示出了本申请实施例提供的一种液晶显示装置400的结构示意图。如图1所示，液晶显示装置400的主要结构包括框架1、盖板玻璃2、液晶显示面板3、背光模组4、电路板5以及包括摄像头等的其他电子配件。其中，电路板5为用于驱动液晶显示面板3的驱动装置，或者为驱动液晶显示面板3的驱动装置的一部分。此外，电路板5可以是柔性电路板。
如图1所示，液晶显示面板3包括阵列基板31、对置基板32、设置于阵列基板31和对置基板32之间的液晶层33、以及上下偏光层等。阵列基板31和对置基板32通过封框胶对合在一起，从而将液晶层33限定在封框胶围成的区域内。其中，当彩色滤光层设置于对置基板32上时，对置基板32为彩膜基板。
框架1的纵截面呈U型，液晶显示面板3、背光模组4、电路板5以及包括摄像头等的其他电子配件设置于框架1内，背光模组4位于液晶显示面板3的下方，电路板5位于背光模组4和框架1之间，盖板2位于液晶显示面板3远离背光模组4的一侧。
图1的液晶显示装置400中的光路传播顺序为：背光模组4射出，依次透过液晶显示面板3中的阵列基板31、液晶层33、对置基板32，再射出盖板2。
其中，在图1的基础上，图2示出了图1中的一种阵列基板31的俯视示意图。如图2所示，在该俯视示意图中，阵列基板31包括显示区10和环绕显示区10的周边区20，周边区20包括绑定区210和非绑定区220，绑定区210设置在显示区10外至少一侧，图2中以绑定区210位于显示区10外的下方一侧为例进行示意。
图3是图2中的P区域的结构示意图。图4是图3中的导电触片与金手指绑定后的结构示意图。图5是图4沿AA'方向的截面示意图。图6是另一种导电触片与金手指绑定后沿AA'方向的截面示意图。
如图2~图6所示，阵列基板31的显示区10中设置有用于进行显示的多种信号线11，绑定区210设置有沿x方向排布的多个导电触片21（如图3~图6中所示的M1~M4），非绑定区220中设置有多条信号引线22（如图3~图6中所示的L1~L4）。
应理解，显示区10的信号线11与绑定区210的导电触片21通过非绑定区220中的信号引线22相连接。信号引线22与导电触片21是一一对应的关系。基于此，导电触片21再与FPC的金手指40进行绑定，即，导电触片21与金手指40一一对应且连接，从而可以将电路板5提供的信号按照金手指40、导电触片21、信号引线22、信号线11的顺序传输至显示区10内部，以控制显示画面。
示例性的，如图3~图6所示，以四个导电触片21（如图3~图5中所示的M1~M4）为例，该四个导电触片21沿第一方向（如x方向）依次排布。每个导电触片21沿第二方向（如y方向）延伸，x方向和y方向相互垂直。
其中，每个导电触片21靠近显示区10的一端连接有一条信号引线22。该信号引线22用于与显示区10内部的信号线11进行连接。在布线时，该信号引线22的形状通常为弯折状，例如，信号引线22的形状可以为L形弯折，即，每条信号引线22可以包括沿第二方向y延伸的第一信号引线子部221和与第一信号引线子部221一端连接的且沿第一方向x延伸的第二信号引线子部222。该四个导电触片21中，每个导电触片21用于与FPC的一个金手指40相绑定。
基于上述结构，在现有技术中，为了尽可能满足窄边框的设计要求，通常会压缩信号引线22所包括的沿第二方向y延伸的第一信号引线子部221的长度，尽量增长沿第一方向x延伸的第二信号引线子部222的长度。
然而，如图4~图6所示，当导电触片21与FPC的金手指40进行绑定时，若由于设备精度有限或者对位标记位置设计等问题，造成金手指40出现对位偏差，没有准确覆盖到导电触片21的正上方，而延伸到了其他导电触片21连接的信号引线22上方，此时，虽然信号引线22上方还设置有保护层320，但是由于绑定时压力较大，金手指40非常有可能压破信号引线22上方的保护层320，从而将会导致金手指40连通不同的信号引线22，导致出现短路问题，进而导致阵列基板不能正常工作。
示例性一，本来只需要覆盖导电触片M1上方的金手指40由于出现对位偏差，还覆盖到了相邻导电触片M2连接的信号引线22的上方，此时，若金手指40在与导电触片M1进行绑定时，压破了与导电触片M2连接的信号引线22上方的保护层320（如图5所示的Q区域），将会使得导电触片M1所连接的信号引线L1和导电触片M2所连接的信号引线L2通过金手指40导通，从而导致出现短路问题。
示例性二，本来只需要覆盖导电触片M1上方的金手指40由于出现对位偏差，还覆盖到了导电触片M2、导电触片M3、导电触片M4连接的信号引线22的上方，此时，若金手指40与导电触片M1进行绑定时，压破了与导电触片M2、导电触片M3、导电触片M4上的保护层320（如图6所示的R区域），将会使得分别与导电触片M2、导电触片M3、导电触片M4连接的信号引线L2、信号引线L3、信号引线L4和信号引线L1通过金手指40导通，四根信号引线全部短路，导致阵列基板31无法正常工作。
有鉴于此，本申请实施例提供了一种阵列基板，通过在信号引线上方的保护层中增加至少部分覆盖信号引线的第二金属图案层，以使得金手指与导电触片进行绑定时，第二金属图案层能承受一定的绑定压力，为信号引线提供保护，从而可以避免出现现有技术中绑定造成的短路问题。
下面结合图2、图7~图16，对本申请实施例提供的阵列基板的结构进行详细说明。图7是本申请实施例提供的一种阵列基板中P区域的结构示意图，图8是图7中导电触片与金手指绑定后的结构示意图。图9是图8沿BB'方向的截面示意图。
如图7~图9所示，本申请实施例提供的阵列基板包括依次层叠设置的衬底基板300、第一金属图案层310、保护层320。
即，在衬底基板300的一侧设置有保护层320，在衬底基板310和保护层320之间设置有第一金属图案层310。
应理解，保护层320可以包括多层结构，本申请实施例对保护层30所包括层数和层间位置不做任何限制。
结合图2，该阵列基板31还包括：显示区10和环绕显示区10的周边区20，周边区20包括绑定区210和非绑定区220，绑定区210位于显示区10外至少一侧。
应理解，显示区10，指的是阵列基板31能够显示图像的区域，可设置在阵列基板31的中部区域，本申请实施例以设置于阵列基板31的中心且形状为矩形的显示区10为例。周边区20，指的是不能显示图像的区域，环绕显示区10设置，本申请实施例以环绕显示区10宽度一致的周边区20为例。周边区20用于布置电路走线及其他驱动的电子元器件。
应理解，绑定区210，指的是阵列基板31用于FPC的金手指40进行连接的区域，通常设置在显示区10外的一侧，本申请实施例以绑定区210位于显示区10的下方一侧为例。非绑定区220，指的是周边区20中除过绑定区210之外剩余的所有区域。
第一金属图案层310包括位于绑定区210且沿第一方向间隔排布的多个导电触片21，以及位于非绑定区220的多条呈弯折状的信号引线22，导电触片21靠近显示区10的一端与对应的信号引线22相连接。
其中，导电触片21沿第二方向延伸，用于与待绑定电路板上的金手指40进行绑定，第一方向平行于显示区10距离绑定区210最近的边沿，第二方向与第一方向相互垂直。
应理解，结合图7~图9，以显示区10、绑定区210均为矩形，绑定区210位于显示区10的下方一侧为例，第一方向平行于显示区10距离绑定区210最近的边沿，指的是显示区10下方靠近绑定区210的边沿，也就是说，第一方向为x方向。第二方向与第一方向相互垂直，则第二方向为y方向。
由此，第一金属图案层310包括位于绑定区210且沿x方向间隔排布的多个导电触片21，每个导电触片21沿y方向延伸，并且，每个导电触片21靠近显示区10的一端（上方的一端）与对应的信号引线22相连接。此处，导电触片21与信号引线22是一一对应的，这样，信号引线22与显示区10的信号线进行连接，这样通过导电触片21与待绑定电路板的金手指40相绑定，就能将信号从外界传输至显示区10，以控制显示画面。其中，待绑定电路板可以为FPC。
应理解，绑定区210的尺寸、导电触片21的尺寸、相邻导电触片21之间的间隔距离，均可以根据需要进行设置，本申请实施例对此不进行任何限制。
应理解，由于导电触片21之间具有一定的间隔，相应的，与导电触片21相连接的信号引线22之间也具有一定的间隔，而导电触片21的横截面宽度与信号引线22的横截面宽度可以相同也可以不同，由此，导电触片21之间的间隔和信号引线22之间的间隔可以相同也可以不同。此外，呈弯折状的信号引线22的走线方向可以根据需要进行设置，本申请实施例对此不进行任何限制。
应理解，第一金属图案层310可以与显示区10设置的薄膜晶体管（Thin Film Transistor ，TFT）中的栅极使用相同材料且同层制备的。
保护层320包括层叠设置的第一绝缘层321和第二金属图案层323，沿衬底基板300的厚度方向，第一绝缘层321位于第二金属图案层323靠近衬底基板的一侧，其中，第二金属图案层323位于非绑定区220，第二金属图案层323至少部分覆盖信号引线22。
应理解，保护层320可以在第一金属图案层310远离衬底基板300的一侧以及衬底基板300未铺设第一金属图案层310的区域整层铺设，其中，由于第一金属图案层310具有一定的形状，在第一金属图案层310上铺设的保护层320将随第一金属图案层310的形状变化该变化。例如，部分保护层320铺设在导电触片21的上方，部分保护层320铺设在导电触片21之间的间隔处，部分保护层320铺设在信号引线22的上方，部分保护层320铺设在信号引线22之间的间隔处。
或者，保护层320也可以在第一金属图案层310远离衬底基板300的一侧铺设，或者，保护层320也可以仅在非绑定区220中铺设，本申请实施例对此不进行任何限制。保护层320用于为导电触片21和信号引线22起到保护作用。
应理解，由于保护层320包括层叠设置的第一绝缘层321和第二金属图案层323，因此，沿阵列基板31的厚度方向，从下到上的膜层结构依次为，衬底基板300、第一金属图案层310、第一绝缘层321和第二金属图案层323。
由于保护层320包括了第一绝缘层321，并且第一绝缘层321位于第一金属图案层310和第二金属图案层323之间，因此，位于非绑定区220的第二金属图案层323与第一金属图案层310所包括的信号引线22不相邻。当然，保护层320在第一绝缘层321靠近第二金属图案层323的一侧，或者，在靠近第一金属图案层310的一侧之间还可以包括其他层，具体可以根据需要设置，本申请实施例对此不进行任何限制。
应理解，所谓的第二金属图案层323至少部分覆盖信号引线22指的是：位于非绑定区220的第二金属图案层323可以整层铺设，也可以仅铺设于信号引线22对应的上方，即，第二金属图案层323在衬底基板300上的投影与信号引线22在衬底基板300上的投影重合，第二金属图案层323还可以在信号引线22上进行局部铺设。
此处，第二金属图案层323的铺设面积，具体可以根据需要进行设置，本申请实施例对此不进行任何限制。
应理解，第二金属图案层323可以与显示区10设置的TFT中的源极和漏极使用相同材料且同层制备的。
可以理解的是，由于在保护层320中增加了一层的第二金属图案层323，不但可以为信号引线22提供保护，降低金手指40绑定时出现短路问题的可能性，而且，由于是在信号引线22的上方增设的，不用压缩非绑定区220中信号引线22的走线设计空间。此外，还可以与TFT中的源极和漏极同层制备，由此，也不需要额外增加生产成本。
本申请实施例提供了一种阵列基板，通过在呈弯折状的信号引线上方的保护层中增加第二金属图案层，以使得金手指与导电触片进行绑定时，第二金属图案层能承受一定的绑定压力，为信号引线提供保护，从而可以避免出现现有技术中绑定造成的短路问题。
可选地，作为一种可能实现的方式，如图7~图9所示，沿衬底基板300的厚度方向，在保护层320远离衬底基板300的一侧还设置有位于绑定区210的第三金属图案层330。
第三金属图案层330通过设置于保护层320中的过孔340与导电触片21连接，第三金属图案层330用于在导电触片21与金手指40绑定时，导通导电触片21和金手指40。
应理解，通常保护层320整层铺设，为了将导电触片21和待绑定电路板的金手指40进行绑定，需要在导电触片21上方的保护层320中开设过孔340，然后铺设第三金属图案层330，通过第三金属图案层330作为中间介质导通导电触片21和金手指40。本申请实施例对过孔340的数量、形状、具体位置均不进行任何限制。
应理解，第三金属图案层330可以与显示区10设置的像素电极使用相同材料且同层制备的。
还应理解，位于绑定区210的第三金属图案层330与位于非绑定区220的第二金属图案层323不接触。
可选地，作为一种可能实现的方式，保护层320还包括：第二绝缘层322。
沿衬底基板300的厚度方向，第二金属图案层323位于第一绝缘层321和第二绝缘层322之间。
例如，如图7~图9所示，沿衬底基板300的厚度方向，从下往上依次为衬底基板300、第一绝缘层321、第二金属图案层323、第二绝缘层322；此外，第一绝缘层321和第二绝缘层322还可以交换，此时，从下往上依次为衬底基板300、第二绝缘层322、第二金属图案层323、第一绝缘层321。
其中，第一绝缘层321和第二绝缘层322均整层铺设。
应理解，以第一绝缘层321位于第二金属图案层323下方，第二绝缘层322位于第二金属图案层323上方为例，第一绝缘层321可以与显示区10中设置的TFT的有源层同层制备，第二绝缘层322可以与显示区10中铺设的绝缘层同层制备。基于此结构，当一对金手指40与导电触片21绑定时，即使金手指40压破了信号引线22上方的第二绝缘层322，金手指40也只会和第二金属图案层323连接，还是可以避免信号引线22与其他信号引线22短路。
可选地，作为一种可能实现的方式，保护层320还包括：第二绝缘层322；
沿衬底基板300的厚度方向，第二绝缘层322位于第一绝缘层321和第二金属图案层323之间。
例如，沿衬底基板300的厚度方向，从下往上依次为衬底基板300、第一绝缘层321、第二绝缘层322、第二金属图案层323；此外，第一绝缘层321和第二绝缘层322还可以交换。此时，从下往上依次为衬底基板300、第二绝缘层322、第一绝缘层321、第二金属图案层323。
可选地，作为一种可能实现的方式，图10示出了一种信号引线22的结构示意图。信号引线22包括沿第二方向延伸的第一信号引线子部221及沿第一方向延伸的第二信号引线子部222，第一信号引线子部221的第一端与导电触片21相连接，第二端与第二信号引线子部222的一端相连接。
如图10所示，例如，信号引线L1包括沿第二方向y延伸的第一信号引线子部L11，以及沿第一方向x延伸的第二信号引线子部L12，第一信号引线子部L11的第一端（如下端）与导电触片21相连接，第二端（如上端）与第二信号引线子部L12的一端相连接，由此，形成的信号引线L1成L弯折形状。
同理，其他信号引线22也成L弯折形状。
基于此，第二金属图案层323包括多条金属保护线3230，金属保护线3230位于信号引线远离衬底基板300的一侧。
应理解，在保护层320中增设的第二金属图案层323可以包括多条金属保护线3230，金属保护线3230位于信号引线22远离衬底基板300的一侧，可以防止信号引线22之间互相短路。也就是说，金属保护线3230与信号引线22一一对应，金属保护线3230对对应的信号引线22起到保护作用。这样，相对于在非绑定区220整层铺设第二金属图案层323，可以节约一些材料。
可选地，作为一种可能实现的方式，图11是本申请实施例提供的另一种阵列基板31中P区域的结构示意图，图12是图11中导电触片与金手指绑定后的结构示意图。图13是图12沿CC'方向的截面示意图。
如图11~图13为例，金属保护线3230在衬底基板300上的投影与信号引线22在衬底基板上的投影重合。
应理解，若信号引线22为L形弯折，则在信号引线22远离衬底基板一侧的金属保护线3230也为L形弯折。例如，金属保护线3230如图11~图13所示的G1~G4。金属保护线G1~G4分别于信号引线L1~L4一一对应。
可选地，信号引线22的横截面可以为矩形或者为梯形。
可选地，金属保护线3230的横截面宽度与信号引线22的横截面宽度相等。
应理解，当信号引线22的横截面为矩形时，金属保护线3230的横截面宽度可以对应信号引线22横截面宽度（平行于衬底基板300的边长的长度），也即，金属保护线3230的横截面宽度与信号引线22横截面宽度相等；当信号引线22的横截面为梯形时，金属保护线3230的横截面宽度可以对应信号引线22横截面宽度（平行于衬底基板300的下底边的长度），也即，金属保护线3230的横截面宽度与信号引线22的横截面宽度相等。
可选地，作为另一种可能实现的方式，图14是本申请实施例提供的又一种阵列基板31中P区域的结构示意图。如图14所示，金属保护线3230在衬底基板300上的投影与第二信号引线子部222在衬底基板300上的投影重合。
应理解，由于金手指40绑定时，偏移的方向为第二方向，所以，为了节省材料，可以为仅在第二信号引线子部222的上方设置金属保护线3230，以起到保护第二信号引线子部222的作用。
可选地，作为另一种可能实现的方式，图15是本申请实施例提供的又一种阵列基板中P区域的结构示意图。图16是图15中第一金属图案层和第二金属图案层的结构示意图。
如图15和图16所示，位于第二信号引线子部222远离衬底基板300一侧的金属保护线3230包括多个子金属保护线3231。
应理解，每条金属保护线3230包括的子金属保护线3231的个数、每条子金属保护线3231的长度均可以根据需要设置，本申请实施例对此不进行任何限制。
沿第一方向，相邻子金属保护线3231之间的第二间隔区的长度小于或者等于相邻两个导电触片之间的第一间隔区的长度。
其中，不同的第二信号引线子部222对应的第二间隔区，位于第一间隔区平行于第二方向的两条边沿的延长线之间。
例如，沿第一方向x，相邻子金属保护线3231之间的第二间隔区S2的长度（如图16中所示的d2）小于或者等于相连两个导电触片21之间的第一间隔区S1的长度（如图16中所示的d1）。
在此基础上，例如，导电触片M1和导电触片M2之间的第一间隔区S1，平行于第二方向y的两条边沿的延长线分别为s1和s2，由此，在延长线s1和s2之间分布有多个第二间隔区，且每个第二间隔区对应一条第二信号引线子部222。
同理，其他两两导电触片之间的第一间隔区平行于第二方向的两条边沿的延长线之间也分布有第二间隔区，且每个第二间隔区对应一条第二信号引线子部222。
应理解，在图11~图13的基础上，多个金手指40分别与对应的导电触片21相绑定后，当多个金手指40均压破了信号引线22上的第一绝缘层，此时，若多个金手指40压破同一根信号引线22上的第一绝缘层321，则会通过不同的金手指导通，导致出现短路问题。因此，在金属保护线3230设置为多个子金属保护线3231的结构后，即使多个金手指40均压破同一信号引线22上的第一绝缘层321，但是由于子金属保护线3231之间具有间隙，可以避免出现短路问题。
示例性的，如图12所示，当沿第一方向排布的第1个金手指40和第2个金手指40均压破了信号引线L2上的第一绝缘层321，此时，第1个金手指40和第2个金手指40则有可能通过信号引线L2导通，进一步导致信号引线L1和信号引线L2导通。由此，如图15所示，当信号引线L2上方铺设的子金属保护线3231之间具有第二间隙区时，则可以隔离开第1个金手指40和第2个金手指40，避免出现短路问题。
本申请实施例还提供一种液晶显示面板，包括：对置基板和如上所述的阵列基板，以及设置在对置基板和所述阵列基板之间的液晶层。
本申请实施例提供的液晶显示面板的有益效果与上阵列基板对应的有益效果相同，在此不再赘述。
本申请实施例还提供一种液晶显示装置，包括：待绑定电路板和上所述的液晶显示面板；
待绑定电路板上设置有金手指，金手指与液晶显示面板中的阵列基板上的导电触片的形状相适应，金手指用于与导电触片相绑定。
本申请实施例提供的液晶显示装置的有益效果与上述阵列基板对应的有益效果相同，在此不再赘述。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (15)

  1. 一种阵列基板（31），其中，包括依次层叠设置的衬底基板（300）、第一金属图案层（310）和保护层（320）；所述阵列基板（31）还包括：显示区（10）和环绕所述显示区（10）的周边区（20），所述周边区（20）包括绑定区（210）和非绑定区（220），所述绑定区（210）位于显示区（10）外至少一侧；
    所述第一金属图案层（310）包括位于所述绑定区（210）且沿第一方向间隔排布的多个导电触片（21），以及位于所述非绑定区（220）的多条呈弯折状的信号引线（22），所述导电触片（21）靠近所述显示区（10）的一端与对应的信号引线（22）相连接，所述导电触片（21）沿第二方向延伸，用于与待绑定电路板（5）上的金手指（40）进行绑定，所述第一方向平行于所述显示区（10）距离与所述绑定区（210）最近的边沿，所述第二方向与所述第一方向相互垂直；
    所述保护层（320）包括层叠设置的第一绝缘层（321）和第二金属图案层（323），沿所述衬底基板（300）的厚度方向，所述第一绝缘层（321）位于所述第二金属图案层（323）靠近所述衬底基板（300）的一侧，其中，所述第二金属图案（323）层位于所述非绑定区（220），所述第二金属图案层（323）至少部分覆盖所述信号引线（22）。
  2. 根据权利要求1所述的阵列基板（31），其中，沿所述衬底基板（300）的厚度方向，在所述保护层（320）远离所述衬底基板（300）的一侧还设置有位于所述绑定区（210）的第三金属图案层（330）；
    所述第三金属图案层（330）通过设置于所述保护层（320）中的过孔（340）与所述导电触片（21）连接，所述第三金属图案层（330）用于在所述导电触片（21）与所述金手指（40）绑定时，导通所述导电触片（21）和所述金手指（40）。
  3. 根据权利要求2所述的阵列基板（31），其中，所述信号引线（22）包括沿所述第二方向延伸的第一信号引线子部（221）及沿所述第一方向延伸的第二信号引线子部（222），所述第一信号引线子部（221）的第一端与所述导电触片（21）相连接，第二端与所述第二信号引线子部（222）的一端相连接；
    所述第二金属图案层（323）包括多条金属保护线（3230），所述金属保护线（3230）位于信号引线（22）远离所述衬底基板（300）的一侧。
  4. 根据权利要求3所述的阵列基板（31），其中，所述金属保护线（3230）在所述衬底基板（300）上的投影与所述信号引线（22）在衬底基板（300）上的投影重合。
  5. 根据权利要求3所述的阵列基板（31），其中，所述金属保护线（3230）在所述衬底基板（300）上的投影与所述第二信号引线子部（222）在所述衬底基板（300）上的投影重合。
  6. 根据权利要求3所述的阵列基板（31），其中，位于所述第二信号引线子部（222）远离所述衬底基板（300）一侧的所述金属保护线（3230）包括多个子金属保护线（3231）；
    沿所述第一方向，相邻子金属保护线（3230）之间的第二间隔区的长度小于或者等于相邻两个所述导电触片（21）之间的第一间隔区的长度；
    其中，不同的第二信号引线子部（222）对应的所述第二间隔区，位于所述第一间隔区平行于所述第二方向的两条边沿的延长线之间。
  7. 根据权利要求1所述的阵列基板（31），其中，所述保护层（320）还包括：第二绝缘层（322）；
    沿所述衬底基板（300）的厚度方向，所述第二金属图案层（323）位于所述第一绝缘层（321）和所述第二绝缘层（322）之间。
  8. 根据权利要求1所述的阵列基板（31），其中，所述保护层（320）还包括：第二绝缘层（322）；
    沿所述衬底基板（300）的厚度方向，所述第二绝缘层（322）位于所述第一绝缘层（321）和所述第二金属图案层（323）之间。
  9. 根据权利要求1所述的阵列基板（31），其中，所述第一金属图案层（310）与所述显示区（10）包括的薄膜晶体管的栅极材料相同且同层制备。
  10. 根据权利要求1所述的阵列基板（31），其中，所述第二金属图案层（323）与所述显示区（10）包括的薄膜晶体管的源极和漏极材料相同且同层制备。
  11. 根据权利要求2所述的阵列基板（31），其中，所述第三金属图案层（330）与所述显示区（10）包括的像素电极材料相同且同层制备。
  12. 根据权利要求1所述的阵列基板（31），其中，所述信号引线（22）的横截面为矩形或为梯形。
  13. 根据权利要求12所述的阵列基板（31），其中，所述金属保护线（3230）的横截面宽度与所述信号引线（22）的横截面宽度相等。
  14. 一种液晶显示面板（3），其中，包括：对置基板（32）和如权利要求1所述的阵列基板（31），以及设置在所述对置基板（32）和所述阵列基板（31）之间的液晶层（33）。
  15. 一种液晶显示装置（400），其中，包括：待绑定电路板和权利要求14所述的液晶显示面板（3）；
    所述待绑定电路板上设置有金手指（40），所述金手指（40）与所述液晶显示面板（3）中的阵列基板（31）上的导电触片（21）的形状相适应，所述金手指（40）用于与所述导电触片（21）相绑定。
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