WO2022193357A1 - 一种肖特基二极管结构及其制造方法 - Google Patents

一种肖特基二极管结构及其制造方法 Download PDF

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WO2022193357A1
WO2022193357A1 PCT/CN2021/083484 CN2021083484W WO2022193357A1 WO 2022193357 A1 WO2022193357 A1 WO 2022193357A1 CN 2021083484 W CN2021083484 W CN 2021083484W WO 2022193357 A1 WO2022193357 A1 WO 2022193357A1
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layer
groove
doped
drift
drift layer
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PCT/CN2021/083484
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English (en)
French (fr)
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侯欣蓝
张清纯
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光华临港工程应用技术研发(上海)有限公司
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Publication of WO2022193357A1 publication Critical patent/WO2022193357A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a Schottky diode structure and a manufacturing method thereof.
  • a Junction Barrier Schottky (JBS) diode is a switching diode.
  • the forward characteristic of the JBS is similar to a Schottky Barrier Diode (SBD)
  • the reverse characteristic of the JBS is similar to a PIN diode (in the A thin layer of low-doped intrinsic (Intrinsic) semiconductor layer is added between the P-type semiconductor material and the N-type semiconductor material, and the diode of this P-I-N structure is a PIN diode)
  • JBS diodes have low reverse leakage current, and improving the performance of JBS diodes is an important research goal in this field.
  • the present application provides a Schottky diode structure and a manufacturing method thereof to reduce the on-resistance while maintaining a small size of the device.
  • the present application provides a Schottky diode structure, comprising: a semiconductor substrate layer; a drift layer located on the semiconductor substrate layer, the drift layer has a plurality of spaced grooves facing away from the semiconductor substrate layer, and the plurality of grooves are along the
  • the doped layers are arranged in the first direction; the doped layers are respectively located in the drift layers of the same single side of the plurality of grooves along the first direction, and the conductivity types of the doped layers are opposite to those of the drift layers;
  • the Schottky contact electrode is located on the side of the drift layer facing away from the semiconductor substrate layer and fills the groove.
  • the lateral dimension of the doped layer in the first direction is 0.5 ⁇ m to 1 ⁇ m.
  • the doping layer extends from the drift layer at one side of the groove to the drift layer at the bottom of a part of the groove.
  • the size of the doped layer in the first direction is smaller than or equal to the size of the bottom surface of the groove in the first direction.
  • the longitudinal dimension of the doped layer is 0.5 ⁇ m to 1 ⁇ m.
  • the Schottky diode structure further includes: a barrier layer; the inner wall of the groove includes a first area and a second area, the first area is the surface of the doped layer facing the groove, and the barrier layer at least covers the inner wall of the groove. The surface of the second region; the Schottky contact electrode covers the barrier layer.
  • the thickness of the barrier layer is 500 angstroms to 2000 angstroms.
  • the blocking layer covers at least the surface of the drift layer facing the groove.
  • the present application also provides a method for manufacturing a Schottky diode structure, comprising the following steps: providing a semiconductor substrate layer; forming a drift layer on one side of the semiconductor substrate layer; forming a plurality of drift layers facing away from the semiconductor substrate layer in the drift layer
  • the grooves are spaced apart, and a plurality of grooves are arranged along the first direction; a doped layer is formed in the drift layer of the same single side part of the groove along the first direction, and the conductivity type of the doped layer is the same as that of the drift layer.
  • the conductivity types are opposite; after the doped layer is formed, a Schottky contact electrode is formed, and the Schottky contact electrode is located on the side of the drift layer facing away from the semiconductor substrate layer and fills the groove.
  • a patterned mask layer is formed on the surface of the drift layer
  • the step of forming a plurality of spaced grooves in the drift layer facing away from the semiconductor substrate layer is as follows: using a patterned mask layer as a mask to etch the drift layer to form a plurality of spaced grooves groove;
  • the step of forming a doped layer in the drift layer on the same single side of the plurality of grooves along the first direction respectively includes: performing oblique ion implantation on the grooves by using the patterned mask layer as a mask;
  • the patterned mask layer is removed prior to forming the Schottky contact electrodes.
  • the inner wall surface of the groove includes a first area and a second area, and the first area is the surface of the doped layer facing the groove; the manufacturing method of the Schottky diode structure further includes: Before forming the Schottky contact electrode, a barrier layer is formed at least on the surface of the second region of the inner wall of the groove.
  • the Schottky diode structure provided by this application includes a drift layer located on the semiconductor substrate layer, and the side of the drift layer facing away from the semiconductor substrate layer has a plurality of spaced grooves arranged in the first direction; also include doping layer, the doped layer is located in the drift layer on the same single side of the groove along the first direction, the conductivity type is opposite to the drift layer, and the Schottky contact electrode is located on the side of the drift layer facing away from the semiconductor substrate layer and fills the groove.
  • the distance between the adjacent doped layers By arranging the doped layer in the drift layer of the same single-sided side of the groove along the first direction, compared with the design in which the side of the groove is completely covered with the doped layer, the distance between the adjacent doped layers When the value increases, the width of the drift layer between adjacent doped layers becomes larger, and accordingly, the contact area between this part of the drift layer and the Schottky contact electrode becomes larger, thereby reducing the on-resistance. At the same time, the size of the device is not increased, the small size of the device is maintained on the basis of reducing the on-resistance, and a balance between the two is achieved.
  • the lateral dimension in the first direction is 0.5 ⁇ m to 1 ⁇ m. If the lateral size is too large, the distance between adjacent doped layers is small, the cross-sectional area of the on-resistance between adjacent doped layers is small, and the corresponding on-resistance is large; if the lateral size is too small , the size of the Schottky contact electrode between adjacent doped layers is large, the electric field strength generated by the Schottky contact electrode and the Schottky contact of the drift layer is large, and the reverse leakage current will increase accordingly.
  • the lateral dimension is in the range of 0.5 ⁇ m to 1 ⁇ m, which can achieve a balance between lower on-resistance and lower reverse leakage current.
  • the doped layer also extends from the drift layer on one side of the groove to the drift layer at the bottom of a part of the groove, so that the doped layer on the side of the groove and
  • the total size of the doped layer at the bottom of the groove is increased in the longitudinal direction.
  • the size of the depletion layer formed by each doped layer and the drift layer in the longitudinal direction increases, and the adjacent doped layers
  • the size of the laterally connected part of the formed depletion layer also increases accordingly, so that the electric field generated at the contact between the Schottky contact electrode and the drift layer is reduced, and the reverse leakage current can be reduced accordingly, and the working performance of the device can be reduced. be promoted.
  • the dimension in the first direction is smaller than or equal to the dimension of the bottom surface of the groove in the first direction.
  • the longitudinal dimension of the doped layer is 0.5 ⁇ m to 1 ⁇ m. If the vertical size is too large, the energy requirements for ion implantation are high, and the process cost is too high; if the vertical size is too small, the electric field generated at the contact between the Schottky contact electrode and the drift layer is too large, and the reverse leakage current will increase accordingly.
  • the longitudinal dimension is in the range of 0.5 ⁇ m to 1 ⁇ m, which can strike a balance between less reverse leakage current and simpler processing difficulty.
  • the Schottky diode structure provided by the present application further comprises a barrier layer located on the inner wall of the groove, and the Schottky contact electrode covers the barrier layer. Even though the surface of the inner wall and bottom surface of the groove is usually rough due to the etching process, the arrangement of the barrier layer prevents the Schottky contact electrode from contacting the drift layer in the groove to avoid rough surfaces. It will reduce the Schottky contact barrier between the Schottky contact electrode and the drift layer, thereby preventing the Schottky contact electrode from generating a large electric field at the position where the side of the groove is in contact with the drift layer, thereby avoiding the generation of a large reverse reaction. to leakage current.
  • the inner wall of the groove includes a first area and a second area
  • the first area is the surface of the doped layer facing the groove
  • the barrier layer covers at least the surface of the second area of the inner wall of the groove
  • the Schottky contact electrode covers the barrier Floor. It can be ensured that the Schottky electrode in the groove cannot be in contact with the drift layer, so that no current can pass through the region covered by the barrier layer, and the possibility of reverse leakage current in this region is greatly reduced.
  • the thickness of the barrier layer is 500 angstroms to 2000 angstroms. If the thickness of the barrier layer is too small, the blocking effect is not good, and breakdown may occur when the applied voltage and current are large; if the thickness of the barrier layer is too large, the device size will be affected.
  • the thickness of the barrier layer is in the range of 500 angstroms to 2000 angstroms to achieve a balance between smaller device size and better barrier effect.
  • the manufacturing method of the Schottky diode structure provided by the present application can manufacture the Schottky diode structure provided by the present application, through the setting of the doped layer in the drift layer of the same single side portion of the groove along the first direction , so that compared with the design that the side of the groove is completely covered with doped layers, the spacing between adjacent doped layers increases, and the width of the drift layer between adjacent doped layers becomes larger. Correspondingly, this part of the drift The contact area of the layer with the Schottky contact electrode becomes larger, thereby reducing the on-resistance. At the same time, the size of the device is not increased, the small size of the device is maintained on the basis of reducing the on-resistance, and a balance between the two is achieved.
  • the method for manufacturing a Schottky diode structure provided by the present application before forming a plurality of spaced grooves, forming a patterned mask layer on the surface of the drift layer; forming a backside in the drift layer
  • the steps of forming a plurality of spaced grooves on one side of the semiconductor substrate layer are as follows: etching the semiconductor substrate layer with a patterned mask layer as a mask to form a plurality of spaced grooves;
  • the step of forming a doped layer in the drift layer on the same single side of the plurality of grooves along the first direction includes: using the patterned mask layer as a mask to tilt the grooves. Implant; removing the patterned masking layer prior to forming the Schottky contact electrodes. In this way, the doped layer is only located in the drift layer at the side and bottom of the groove, and the lateral dimension of the formed doped layer and the area ratio covering the bottom of the groove in the first direction are controllable.
  • a barrier layer is formed at least on the surface of the second region of the inner wall of the groove. Even though the surface of the inner wall and bottom surface of the groove is usually rough due to the etching process, the arrangement of the barrier layer prevents the Schottky contact electrode from contacting the drift layer in the groove to avoid rough surfaces. It will reduce the Schottky contact barrier between the Schottky contact electrode and the drift layer, thereby preventing the Schottky contact electrode from generating a large electric field at the position where the side of the groove is in contact with the drift layer, thereby avoiding the generation of a large reverse reaction. to leakage current.
  • forming a barrier layer at least on the surface of the second area of the inner wall of the groove can ensure that the Schottky electrode in the groove cannot make contact with the drift layer, so that no current will pass through the area covered by the barrier layer. The possibility of reverse leakage current generation is greatly reduced.
  • 1 is a schematic structural diagram of a Schottky diode structure
  • FIGS. 2 to 6 are schematic state diagrams of various steps in a manufacturing process of a Schottky diode structure according to an embodiment of the present application.
  • a Schottky diode structure includes: a semiconductor substrate layer 100 ; a drift layer 200 located on the semiconductor substrate layer 100 , wherein the drift layer 200 has a plurality of spaced grooves facing away from the semiconductor substrate layer 100 , a plurality of grooves are arranged along the first direction X; the doped layer 201 ′, the doped layer 201 ′ is located in the drift layer at the side and bottom of the groove, and the conductivity type of the doped layer 201 ′ is the same as that of the drift layer 200 The conductivity types are opposite; the Schottky contact electrode 300 is located on the side of the drift layer 200 facing away from the semiconductor substrate layer 100 and is filled in the groove.
  • the barrier layer 202 on the surface of the groove and the electrode 400 on the side of the semiconductor substrate layer 100 facing away from the drift layer 200 are also included.
  • Such a Schottky diode structure has lower reverse leakage current; in order to improve its working performance, for example, simply increase the distance between two adjacent doped layers 201 ′, although the adjacent doped layers can be increased.
  • the cross-sectional area of the resistance between 201' reduces the on-resistance, but the corresponding device size is also increased. Therefore, how to reduce the on-resistance and keep the device small is an important research goal in the field.
  • the present application provides a Schottky diode structure, including: a semiconductor substrate layer; a drift layer located on the semiconductor substrate layer, the drift layer has a plurality of spaced grooves facing away from the semiconductor substrate layer, and the plurality of grooves Arranged along the first direction; doped layer, the doped layer is located in the drift layer on the same single side of the groove along the first direction, the conductivity type of the doped layer is opposite to that of the drift layer; Schott The base contact electrode is located on the side of the drift layer facing away from the semiconductor substrate layer and fills the groove. In order to reduce the on-resistance of Schottky diodes without increasing the device size.
  • this embodiment provides a Schottky diode structure, including:
  • the semiconductor substrate layer 100 The semiconductor substrate layer 100 .
  • the drift layer 200 located on the semiconductor substrate layer 100 has a plurality of spaced grooves in the drift layer 200 facing away from the semiconductor substrate layer 100 , and the plurality of spaced grooves are arranged along the first direction X.
  • a plurality of doped layers 201, the doped layers 201 are respectively located in the drift layer 200 on the same single side of the plurality of grooves along the first direction X, and the conductivity type of the doped layers 201 is opposite to that of the drift layer 200 .
  • the Schottky contact electrode 300 is located on the side of the drift layer 200 facing away from the semiconductor substrate layer 100 and fills the groove.
  • the drift layer 200 may be an N-type doped SiC layer; the semiconductor substrate layer 100 may be a heavily doped N-type SiC layer; and the doped layer 201 may be a heavily doped P-type semiconductor layer.
  • the doped layer 201 is located in the drift layer 200 of the same single side of the groove along the first direction X, so that compared with the groove shown in FIG.
  • the distance between the adjacent doped layers 201 increases, and the width of the drift layer 200 between the adjacent doped layers 201 increases.
  • this part of the drift layer The contact area between 200 and the Schottky contact electrode 300 becomes larger, thereby reducing the on-resistance.
  • the size of the device is not increased, the small size of the device is maintained on the basis of reducing the on-resistance, and a balance between the two is achieved.
  • the lateral dimension of the doped layer 201 in the first direction X is 0.5 ⁇ m to 1 ⁇ m.
  • it may be 0.5 ⁇ m, 0.6 ⁇ m, 0.7 ⁇ m, 0.8 ⁇ m, 0.9 ⁇ m, and 1 ⁇ m.
  • the lateral dimension in the first direction X is 0.5 ⁇ m to 1 ⁇ m. If the lateral dimension is too large, the distance between adjacent doped layers 201 is small, the cross-sectional area of the on-resistance between adjacent doped layers is small, and the conduction between corresponding adjacent doped layers 201 is small. The on-resistance is large; if the lateral size is too small, the size of the Schottky contact electrode 300 between the adjacent doped layers 201 is too large, the electric field strength generated by the Schottky contact with the drift layer 200 is large, and the reverse leakage current will increase accordingly.
  • the lateral dimension is in the range of 0.5 ⁇ m to 1 ⁇ m, which can achieve a balance between lower on-resistance and lower reverse leakage current.
  • the doped layer 201 extends from the drift layer 200 on one side of the groove to the drift layer 200 at the bottom of the groove, so that the doped layer 201 on the side of the groove and the doped layer on the bottom of the groove are
  • the total size of the layer 201 in the longitudinal direction is increased.
  • the size of the depletion layer formed by each doped layer 201 and the drift layer 200 in the longitudinal direction increases, and the adjacent doped layers 201 are formed.
  • the size of the part where the depletion layer is connected in the lateral direction also increases accordingly, so that the electric field generated at the contact between the Schottky contact electrode 300 and the drift layer 200 is reduced, and accordingly the reverse leakage current can be reduced, and the working performance of the device can be reduced. be promoted.
  • the dimension X of the doped layer 201 in the first direction is smaller than or equal to the dimension of the bottom surface of the groove in the first direction X.
  • the dimension X of the doped layer 201 in the first direction is equal to the dimension of the bottom surface of the groove in the first direction X
  • the dimension X of the doped layer 201 in the first direction is equal to the dimension of the bottom surface of the groove in the first direction X 1/2 of the dimension in the first direction X.
  • the longitudinal dimension of the doped layer 201 is 0.5 ⁇ m to 1 ⁇ m.
  • it may be 0.5 ⁇ m, 0.6 ⁇ m, 0.7 ⁇ m, 0.8 ⁇ m, 0.9 ⁇ m, and 1 ⁇ m. If the vertical size is too large, the energy requirement for ion implantation is high, and the process cost is too high; if the vertical size is too small, the electric field generated at the contact between the Schottky contact electrode 300 and the drift layer 200 is too large, and the reverse leakage The current will increase accordingly.
  • the longitudinal dimension is in the range of 0.5 ⁇ m to 1 ⁇ m, which can strike a balance between less reverse leakage current and simpler processing difficulty.
  • the Schottky diode structure further includes: a barrier layer 202, and the barrier layer 202 is located on the inner wall of the groove.
  • the Schottky contact electrode 300 covers the barrier layer 202 . Since the surfaces of the inner wall and bottom surface of the groove are generally rough surfaces due to the etching process, the rough surface will reduce the Schottky contact barrier between the Schottky contact electrode 300 and the drift layer 200, so that the Schottky contact The electrode 300 generates a larger electric field at the position where the side of the groove is in contact with the drift layer 200, thereby generating a larger reverse leakage current. By disposing the blocking layer 202, the Schottky contact electrode 300 does not make contact with the drift layer 200 in the groove, thereby greatly reducing the possibility of reverse leakage current.
  • the inner wall of the groove includes a first area and a second area
  • the first area is the surface of the doped layer 201 facing the groove
  • the barrier layer 202 at least covers the surface of the second area of the inner wall of the groove; Schottky contact
  • the electrode 300 covers the barrier layer 202 in the groove. In this way, it can be ensured that the Schottky electrode 300 and the drift layer 200 in the groove cannot make contact, so that no current will pass through the area covered by the barrier layer 202, and the reverse leakage current will be greatly reduced in this area. possibility of occurrence.
  • the thickness of the barrier layer 202 is 500 angstroms to 2000 angstroms.
  • it can be 500 angstroms, 1000 angstroms, 1500 angstroms, 2000 angstroms. If the thickness of the blocking layer 202 is too small, the blocking effect is not good, and breakdown may occur when the applied voltage and current are large; if the thickness of the blocking layer 202 is too large, the device size will be affected.
  • the thickness of the barrier layer is in the range of 500 angstroms to 2000 angstroms to achieve a balance between smaller device size and better barrier effect.
  • the Schottky diode structure of this embodiment further includes an electrode 400 located on the side of the substrate layer 100 facing away from the drift layer 200 .
  • the doped layer also satisfies the above-mentioned characteristics in the first direction (not shown in the figure). That is, in the second direction, a plurality of spaced grooves are also arranged along the second direction, and the doped layer 201 also extends into the drift layer on the same single side portion of the plurality of grooves along the second direction.
  • the width of the drift layer between adjacent doped layers becomes larger, and accordingly, the contact area between this part of the drift layer and the Schottky contact electrode becomes larger, thereby reducing the on-resistance.
  • the size of the device is not increased, the small size of the device is maintained on the basis of reducing the on-resistance, and a balance between the two is achieved.
  • the present embodiment further provides a method for manufacturing a Schottky diode structure, including the following steps:
  • a semiconductor substrate layer 100 is provided.
  • the drift layer 200 is formed on one surface of the semiconductor substrate layer 100 .
  • a plurality of spaced grooves 500 are formed in the drift layer 200 on the side facing away from the semiconductor substrate layer 100 , and the plurality of grooves 500 are arranged along the first direction X.
  • a doped layer 201 is formed in the drift layer 200 on the same single side portion of the groove 500 along the first direction X, and the conductivity type of the doped layer 201 is opposite to that of the drift layer 200 .
  • a Schottky contact electrode 300 is formed.
  • the Schottky contact electrode 300 is located on the side of the drift layer 200 facing away from the semiconductor substrate layer 100 and fills the groove 500 .
  • the manufacturing method of the Schottky diode structure provided in this embodiment can manufacture the Schottky diode structure provided in the above-mentioned Embodiment 1.
  • the doping layer 201 is located on the same single side portion of the groove 500 along the first direction X.
  • the arrangement in the drift layer 200 makes the spacing between adjacent doped layers 201 increased compared to the design in which the side of the groove 500 is completely covered with the doped layer 201 ′ as shown in FIG. 1 , The width of the drift layer 200 between the spaced adjacent doped layers 201 becomes larger, and accordingly, the contact area between this part of the drift layer 200 and the Schottky contact electrode 300 becomes larger, thereby reducing the on-resistance and improving the device performance.
  • a patterned mask layer (not shown in the figure) is formed on the surface of the drift layer 200 .
  • the step of forming a plurality of spaced grooves 500 in the drift layer 200 facing away from the semiconductor substrate layer 100 is as follows: using the patterned mask layer as a mask to etch the drift layer to form a plurality of spaced grooves 500 .
  • the step of forming doped layers respectively in the drift layers of the same single side of the plurality of grooves 500 along the first direction includes: using a patterned mask layer as a mask, and ion implantation to the grooves 500 Oblique implantation is performed; the patterned mask layer is removed before the Schottky contact electrodes are formed.
  • the step of oblique implantation may be to incline the device to be processed and keep the vertical direction of ion implantation unchanged, so as to realize ion implantation on one side and part of the bottom of the groove 500 to form the doped layer 201 . It is also possible to keep the device to be processed still, change the direction of ion implantation, and realize ion implantation at one side and part of the bottom of the groove 500 to form the doped layer 201 .
  • the step of ion implantation may also be to cover part of the surface of the drift layer by means of a mask, so as to realize the ion implantation on one side and part of the bottom of the groove 500 to form the doped layer 201 .
  • a mask By adopting such a method to form the doped layer 201 , it can be realized that the doped layer 201 is only located in the drift layer 200 at the side and bottom of the groove 500 , and the lateral dimensions of the doped layer 201 and the first direction of the doped layer 201 are formed.
  • the area ratio of the bottom of the groove 500 on the X is controllable.
  • the first mask layer may be formed on the surface of the drift layer 200 before the groove 500 is formed, and the first mask layer may be removed after patterning the first mask layer and the drift layer 200 to form the groove. Then, before forming the doped layer 201, a second mask layer is formed on the surface of the drift layer 200, the second mask layer is patterned, and then the oblique implantation of ion implantation is performed, and then the second mask layer is removed.
  • the specific number of times of use of the mask layer and whether to manufacture additionally can be determined according to actual process requirements, and are not limited to the above two methods.
  • the inner wall surface of the groove 500 includes a first area and a second area, and the first area is the surface of the doped layer 201 facing the groove 500 .
  • the method for manufacturing the Schottky diode structure further includes: before forming the Schottky contact electrode, forming a barrier layer 202 at least on the surface of the second region of the inner wall of the groove 500 .
  • the Schottky electrode 300 in the groove 500 is spaced apart from the drift layer 200 . Since the surfaces of the inner wall and bottom surface of the groove 500 are generally rough surfaces due to the etching process, the rough surface will lower the Schottky contact potential barrier between the Schottky contact electrode 300 and the drift layer 200 , so that the Schottky contact potential is reduced.
  • the electric field generated by the contact electrode 300 at the position where the second region is in contact with the drift layer 200 is relatively large, and a relatively large reverse leakage current will be generated.
  • the Schottky contact electrode does not make contact with the drift layer in the groove 500, which greatly reduces the possibility of reverse leakage current. .

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Abstract

提供一种肖特基二极管结构及其制造方法。肖特基二极管结构包括：半导体衬底层（100）；位于半导体衬底层（100）上的漂移层（200），漂移层（200）中具有背向半导体衬底层（100）一侧的多个间隔的凹槽(500)，多个凹槽(500)沿着第一方向排布；掺杂层（201），掺杂层（201）位于凹槽(500)沿着第一方向的同一单侧侧部的漂移层（200）中，掺杂层（201）的导电类型与漂移层（200）的导电类型相反；肖特基接触电极（300），位于漂移层（200）背向半导体衬底层（100）的一侧且填充在凹槽(500)中。提供的肖特基二极管结构导通电阻较低且维持器件较小的尺寸。

Description

一种肖特基二极管结构及其制造方法 技术领域
本申请涉及半导体领域，具体涉及一种肖特基二极管结构及其制造方法。
背景技术
结势垒肖特基(Junction Barrier Schottky，JBS)二极管是一种开关二极管。当JBS二极管正向偏置时，JBS的正向特性类似肖特基势垒二极管(Schottky Barrier Diode，SBD)，当JBS反向偏置时，JBS的反向特性类似PIN二极管(在普通二极管的P型半导体材料和N型半导体材料之间加入一薄层低掺杂的本征(Intrinsic)半导体层，组成的这种P-I-N结构的二极管就是PIN二极管)，因此同时具备PIN二极管和SBD的优点，即低的开启电压、高的击穿电压以及较高开关速度等，在高压和高速等领域具有广阔的应用前景。JBS二极管具有较低的反向漏电流，提高JBS二极管的工作性能是本领域的重要研究目标。
然而，现有技术中无法同时兼顾导通电阻的降低和维持器件较小的尺寸。
发明内容
因此，本申请提供一种肖特基二极管结构及其制造方法，以降低导通电阻同时兼顾维持器件较小的尺寸。
本申请提供一种肖特基二极管结构，包括：半导体衬底层；位于半导体衬底层上的漂移层，漂移层中具有背向半导体衬底层一侧的多个间隔的凹槽，多个凹槽沿着第一方向排布；掺杂层，掺杂层分别位于多个凹槽沿着第一方向的同一单侧侧部的漂移层中，掺杂层的导电类型与漂移层的导电类型相反；肖特基接触电极，位于漂移层背向半导体衬底层的一侧且填充凹槽。
可选的，对于位于凹槽侧部的掺杂层，掺杂层在第一方向上的横向尺寸为0.5μm至1μm。
可选的，掺杂层自凹槽的一侧侧部的漂移层延伸至凹槽的部分底部的漂移层中。
可选的，对于位于凹槽部分底部的漂移层中的掺杂层，掺杂层在第一方向上的尺寸小于或等于凹槽的底面在第一方向上的尺寸。
可选的，对于位于凹槽部分底部的漂移层中的掺杂层，掺杂层的纵向尺寸为0.5μm至1μm。
可选的，肖特基二极管结构还包括：阻挡层；凹槽的内壁包括第一区域和第二区域，第一区域为掺杂层朝向凹槽的表面，阻挡层至少覆盖凹槽的内壁的第二区域的表面；肖特基接触电极覆盖阻挡层。
可选的，阻挡层的厚度为500埃至2000埃。
可选的，阻挡层至少覆盖漂移层朝向凹槽的表面。
本申请还提供一种肖特基二极管结构的制造方法，包括以下步骤：提供半导体衬底层；在半导体衬底层一侧表面形成漂移层；在漂移层中形成背向半导体衬底层一侧的多个间隔的凹槽，多个凹槽沿着第一方向排布；在凹槽沿着第一方向的同一单侧侧部的漂移层中形成掺杂层，掺杂层的导电类型与漂移层的导电类型相反；形成掺杂层之后，形成肖特基接触电极，肖特基接触电极位于漂移层背向半导体衬底层的一侧且填充凹槽。
可选的，在形成多个间隔的所述凹槽之前，在所述漂移层的表面形成图形化的掩膜层；
在所述漂移层中形成背向所述半导体衬底层一侧的多个间隔的所述凹槽的步骤为：以图形化的掩膜层为掩膜刻蚀漂移层以形成多个间隔的凹槽；
在多个凹槽沿着第一方向的同一单侧侧部的漂移层中分别形成掺杂层的步骤包括：以图形化的掩膜层为掩膜对凹槽进行倾斜离子注入；
在形成肖特基接触电极之前，去除图形化的掩膜层。
可选的，所述凹槽的内壁表面包括第一区域和第二区域，所述第一区域为所述掺杂层朝向所述凹槽的表面；肖特基二极管结构的制造方法还包括：在形成肖特基接触电极之前，至少在所述凹槽的的内壁第二区域的表面形成阻挡层。
本申请的有益效果在于：
1.本申请提供的肖特基二极管结构，包括位于半导体衬底层上的漂移层，漂移层背向半导体衬底层一侧具有多个间隔的沿第一方向排布的凹槽；还包括掺杂层，掺杂层位于凹槽沿第一方向的同一单侧侧部的漂移层中，与漂移层导电类型相反，肖特基接触电极位于漂移层背向半导体衬底层一侧且填充凹槽。通过掺杂层位于凹槽沿第一方向的同一单侧侧部的漂移层中的设置，使得相比于凹槽侧部全部包覆掺杂层的设计，相邻掺杂层之间的间距增大，相邻掺杂层之间的漂移层宽度变大，相应的，这部分漂移层与肖特基接触电极的接触面积变大，进而使得导通电阻得到减小。同时，没有增加器件的尺寸，在减小导通电阻的基础上维持了器件较小的尺寸，实现了两者的兼顾。
2.本申请提供的肖特基二极管结构，对于位于凹槽侧部的掺杂层，在第一方向上的横向尺寸为0.5μm至1μm。若横向尺寸过大，则相邻掺杂层之 间的距离较小，相邻掺杂层之间的导通电阻的横截面积较小，相应的导通电阻较大；若横向尺寸过小，则相邻掺杂层之间的肖特基接触电极尺寸大，肖特基接触电极与漂移层肖特基接触产生的电场强度大，反向漏电流会随之增大。横向尺寸在0.5μm至1μm范围内，可以在较小的导通电阻和较小的反向漏电流之间取得平衡。
3.本申请提供的肖特基二极管结构，掺杂层还自凹槽的一侧侧部的漂移层延伸至凹槽的部分底部的漂移层中，这样使得凹槽侧部的掺杂层和凹槽底部的掺杂层在纵向上总的尺寸得到增加，随着总的纵向尺寸增加，各个掺杂层与漂移层形成的耗尽层在纵向上的区域尺寸增加，相邻的掺杂层形成的耗尽层在横向上连通的部分的尺寸也相应增加，从而使得肖特基接触电极与漂移层接触处产生的电场减小，相应的可以使得反向漏电流得到降低，器件的工作性能得到提升。
4.本申请提供的肖特基二极管结构，对于位于凹槽部分底部的漂移层中的掺杂层，在第一方向上的尺寸小于或等于凹槽的底面在第一方向上的尺寸。这样的尺寸范围，可以在较小的导通电阻和较小的电场强度之间取得平衡。
5.本申请提供的肖特基二极管结构，对于位于凹槽部分底部的漂移层中的掺杂层，掺杂层的纵向尺寸为0.5μm至1μm。如纵向尺寸过大，则对离子注入所应用的能量要求高，工艺成本过高；如纵向尺寸过小，则肖特基接触电极与漂移层接触处产生的电场过大，反向漏电流会相应增大。纵向尺寸在0.5μm至1μm的范围内，可在较小的反向漏电流和较简单的加工难度之间取得平衡。
6.本申请提供的肖特基二极管结构，还包括位于凹槽的内壁的阻挡层，肖特基接触电极覆盖阻挡层。即使凹槽的内壁和底面的表面通常由于蚀刻工艺的原因使得表面是粗糙的表面，但是通过阻挡层的设置，使得肖特基接触电极在凹槽内与漂移层不产生接触，避免粗糙的表面会降低肖特基接 触电极与漂移层的肖特基接触势垒，进而避免肖特基接触电极在凹槽侧部与漂移层接触的位置处产生较大的电场，从而避免产生较大的反向漏电流。此外，凹槽的内壁包括第一区域和第二区域，第一区域为掺杂层朝向凹槽的表面，阻挡层至少覆盖凹槽的内壁的第二区域的表面，肖特基接触电极覆盖阻挡层。可以保证凹槽内的肖特基电极与漂移层无法产生接触，从而在阻挡层覆盖的区域不会产生电流通过，在这一区域极大减小了反向漏电流的产生的可能性。
7.本申请提供的肖特基二极管结构，阻挡层的厚度为500埃至2000埃。若阻挡层厚度过小，则阻挡效果不佳，在施加电压电流较大的情况下可能发生击穿；若阻挡层厚度过大则影响器件尺寸。阻挡层的厚度在500埃至2000埃的范围内可在较小的器件尺寸和较佳的阻挡效果之间取得平衡。
8.本申请提供的肖特基二极管结构的制造方法，可制造本申请提供的肖特基二极管结构，通过掺杂层位于凹槽沿第一方向的同一单侧侧部的漂移层中的设置，使得相比于凹槽侧部全部包覆掺杂层的设计，相邻掺杂层之间的间距增大，相邻掺杂层之间的漂移层宽度变大，相应的，这部分漂移层与肖特基接触电极的接触面积变大，进而使得导通电阻得到减小。同时，没有增加器件的尺寸，在减小导通电阻的基础上维持了器件较小的尺寸，实现了两者的兼顾。
9.本申请提供的肖特基二极管结构的制造方法，在形成多个间隔的所述凹槽之前，在所述漂移层的表面形成图形化的掩膜层；在所述漂移层中形成背向所述半导体衬底层一侧的多个间隔的所述凹槽的步骤为：以图形化的掩膜层为掩膜刻蚀所述半导体衬底层以形成多个间隔的所述凹槽；在多个所述凹槽沿着第一方向的同一单侧侧部的漂移层中分别形成掺杂层的步骤包括：以所述图形化的掩膜层为掩膜对所述凹槽进行倾斜离子注入；在形成所述肖特基接触电极之前，去除所述图形化的掩膜层。如此可以实 现掺杂层仅位于凹槽的单侧侧部和底部的漂移层中，并且形成掺杂层的横向尺寸以及在第一方向上覆盖凹槽底部的面积比例可控。
10.本申请提供的肖特基二极管结构的制造方法，在形成肖特基接触电极之前，至少在凹槽的的内壁第二区域的表面形成阻挡层。即使凹槽的内壁和底面的表面通常由于蚀刻工艺的原因使得表面是粗糙的表面，但是通过阻挡层的设置，使得肖特基接触电极在凹槽内与漂移层不产生接触，避免粗糙的表面会降低肖特基接触电极与漂移层的肖特基接触势垒，进而避免肖特基接触电极在凹槽侧部与漂移层接触的位置处产生较大的电场，从而避免产生较大的反向漏电流。此外，至少在凹槽的内壁第二区域的表面形成阻挡层可以保证凹槽内的肖特基电极与漂移层无法产生接触，从而在阻挡层覆盖的区域不会产生电流通过，在这一区域极大减小了反向漏电流的产生的可能性。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种肖特基二极管结构的结构示意图；
图2至图6为本申请一实施例的肖特基二极管结构的制造过程中各个步骤的状态示意图。
具体实施方式
参考图1，一种肖特基二极管结构，包括：半导体衬底层100；位于半导体衬底层100上的漂移层200，漂移层200中具有背向半导体衬底层100 一侧的多个间隔的凹槽，多个凹槽沿着第一方向X排布；掺杂层201’，掺杂层201’位于凹槽侧部和底部的漂移层中，掺杂层201’的导电类型与漂移层200的导电类型相反；肖特基接触电极300，肖特基接触电极300位于漂移层200背向半导体衬底层100的一侧且填充在凹槽中。此外还包括位于凹槽表面的阻挡层202以及半导体衬底层100背向漂移层200一侧的电极400。这样的肖特基二极管结构，具有较低的反向漏电流；为了提高其工作性能，如单纯的增加两个相邻的掺杂层201’之间的距离，虽然可以提高相邻掺杂层201’之间的电阻的横截面积，使得导通电阻降低，但是相应的器件尺寸也被加大，因此如何兼顾导通电阻的降低和维持器件较小是本领域的重要研究目标。
故而本申请提供一种肖特基二极管结构，包括：半导体衬底层；位于半导体衬底层上的漂移层，漂移层中具有背向半导体衬底层一侧的多个间隔的凹槽，多个凹槽沿着第一方向排布；掺杂层，掺杂层位于凹槽沿着第一方向的同一单侧侧部的漂移层中，掺杂层的导电类型与漂移层的导电类型相反；肖特基接触电极，位于漂移层背向半导体衬底层的一侧且填充凹槽。以在不增加器件尺寸的前提下降低肖特基二极管的导通电阻。
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”仅用 于描述目的，而不能理解为指示或暗示相对重要性。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
实施例1
参考图6，本实施例提供一种肖特基二极管结构，包括：
半导体衬底层100。
位于半导体衬底层100上的漂移层200，漂移层200中具有背向半导体衬底层100一侧的多个间隔的凹槽，多个间隔的凹槽沿着第一方向X排布。
多个掺杂层201，掺杂层201分别位于多个凹槽沿着第一方向X的同一单侧侧部的漂移层200中，掺杂层201的导电类型与漂移层200的导电类型相反。
肖特基接触电极300，位于漂移层200背向半导体衬底层100的一侧且填充凹槽。
具体的，漂移层200可以为N型掺杂的SiC层；半导体衬底层100可以为重掺杂的N型SiC层；掺杂层201可以为重掺杂的P型半导体层。
本实施例提供的肖特基二极管结构，通过掺杂层201位于凹槽沿第一方向X的同一单侧侧部的漂移层中200中的设置，使得相比于如图1所示的凹槽侧部全部包覆掺杂层201’的设计，相邻掺杂层201之间的间距增大，相邻掺杂层201之间的漂移层200宽度变大，相应的，这部分漂移层200与肖特基接触电极300的接触面积变大，进而使得导通电阻得到减小。同时，没有增加器件的尺寸，在减小导通电阻的基础上维持了器件较小的尺寸，实现了两者的兼顾。
进一步的，对于位于凹槽侧部的掺杂层201，掺杂层201在第一方向X上的横向尺寸为0.5μm至1μm。例如可以为0.5μm、0.6μm、0.7μm、0.8μm、0.9μm、1μm。
本实施例提供的肖特基二极管结构，对于位于凹槽侧部的掺杂层201，在第一方向X上的横向尺寸为，0.5μm至1μm。若横向尺寸过大，则相邻掺杂层201之间的距离较小，相邻掺杂层之间的导通电阻的横截面积较小，相应的相邻掺杂层201之间的导通电阻较大；若横向尺寸过小，则相邻掺杂层201之间的肖特基接触电极300尺寸过大，其与漂移层200肖特基接触产生的电场强度大，反向漏电流会随之增大。横向尺寸在0.5μm至1μm范围内，可以在较小的导通电阻和较小的反向漏电流之间取得平衡。
进一步的，掺杂层201自凹槽的一侧侧部的漂移层200延伸至凹槽的部分底部的漂移层200中，这样使得凹槽侧部的掺杂层201和凹槽底部的掺杂层201在纵向上总的尺寸得到增加，随着总的纵向尺寸增加，各个掺杂层201与漂移层200形成的耗尽层在纵向上的区域尺寸增加，相邻的掺杂层201形成的耗尽层在横向上连通的部分的尺寸也相应增加，从而使得肖特基接触电极300与漂移层200接触处产生的电场减小，相应的可以使得反向漏电流得到降低，器件的工作性能得到提升。
具体的，对于位于凹槽部分底部的漂移层200中的掺杂层201，掺杂层201在第一方向上X的尺寸小于或等于凹槽的底面在第一方向X上的尺寸。例如可以为，掺杂层201在第一方向上X的尺寸等于凹槽的底面在第一方向X上的尺寸，或是掺杂层201在第一方向上X的尺寸等于凹槽的底面在第一方向X上的尺寸的1/2。这样的尺寸范围，可以在较小的导通电阻和较小的电场强度之间取得平衡。
对于位于凹槽部分底部的漂移层200中的掺杂层201，掺杂层201的纵向尺寸为0.5μm至1μm。例如可以为0.5μm、0.6μm、0.7μm、0.8μm、0.9μm、1μm。如纵向尺寸过大，则对离子注入所应用的能量要求高，工艺成本过高；如纵向尺寸过小，则肖特基接触电极300与漂移层200接触处产生的电场过大，反向漏电流会相应增大。纵向尺寸在0.5μm至1μm的范围内，可在较小的反向漏电流和较简单的加工难度之间取得平衡。
进一步的，肖特基二极管结构还包括：阻挡层202，阻挡层202位于凹槽的内壁。肖特基接触电极300覆盖阻挡层202。由于凹槽的内壁和底面的表面通常由于蚀刻工艺的原因使得表面是粗糙的表面，粗糙的表面会降低肖特基接触电极300与漂移层200的肖特基接触势垒，使得肖特基接触电极300在凹槽侧部与漂移层200接触的位置处产生较大的电场，从而产生较大的反向漏电流。通过阻挡层202的设置，使得肖特基接触电极300在凹槽内与漂移层200不产生接触，从而极大减小反向漏电流产生的可能性。
具体的，凹槽的内壁包括第一区域和第二区域，第一区域为掺杂层201朝向凹槽的表面，阻挡层202至少覆盖凹槽的内壁的第二区域的表面；肖特基接触电极300覆盖凹槽中的阻挡层202。如此设置，可以保证凹槽内的肖特基电极300与漂移层200无法产生接触，从而在阻挡层202覆盖的区域不会产生电流通过，在这一区域极大减小了反向漏电流的产生的可能性。
具体的，阻挡层202的厚度为500埃至2000埃。例如可以为500埃、1000埃、1500埃、2000埃。若阻挡层202厚度过小，则阻挡效果不佳，在施加电压电流较大的情况下可能发生击穿；若阻挡层202厚度过大则影响器件尺寸。阻挡层的厚度在500埃至2000埃的范围内可在较小的器件尺寸和较佳的阻挡效果之间取得平衡。
此外，本实施例的肖特基二极管结构，还包括位于衬底层100背向漂移层200一侧的电极400。
对于在平行于衬底层的平面内垂直第一方向X的第二方向上，掺杂层同样满足上述第一方向上的特征(图中未示出)。即，在第二方向上，沿着第二方向还排布了多个间隔的凹槽，掺杂层201还延伸至多个凹槽沿着第二方向的同一单侧侧部的漂移层中。使得在第二方向上，相邻掺杂层之间的漂移层宽度变大，相应的，这部分漂移层与肖特基接触电极的接触面积变大，进而使得导通电阻得到减小。同时，没有增加器件的尺寸，在减小导通电阻的基础上维持了器件较小的尺寸，实现了两者的兼顾。
实施例2
参考图2至图6，本实施例还提供一种肖特基二极管结构的制造方法，包括以下步骤：
参考图2，提供半导体衬底层100。在半导体衬底层100一侧表面形成漂移层200。
参考图3，在漂移层200中形成背向半导体衬底层100一侧的多个间隔的凹槽500，多个凹槽500沿着第一方向X排布。
参考图4，在凹槽500沿着第一方向X的同一单侧侧部的漂移层200中形成掺杂层201，掺杂层201的导电类型与漂移层200的导电类型相反。
参考图6，形成掺杂层201之后，形成肖特基接触电极300，肖特基接触电极300位于漂移层200背向半导体衬底层100的一侧且填充凹槽500。
本实施例提供的肖特基二极管结构的制造方法，可制造如上述实施例1中提供的肖特基二极管结构，通过掺杂层201位于凹槽500沿第一方向X的同一单侧侧部的漂移层200中的设置，使得相比于如图1所示的凹槽500侧部全部包覆掺杂层201’的设计，间隔的相邻掺杂层201之间的间距被增大，间隔的相邻掺杂层201之间的漂移层200宽度变大，相应的，这部分漂移层200与肖特基接触电极300的接触面积变大，进而使得导通电阻得到减小，从而提高器件的工作性能。
具体的，在形成多个间隔的凹槽500之前，在漂移层200的表面形成图形化的掩膜层(图中未示出)。
在漂移层200中形成背向半导体衬底层100一侧的多个间隔的凹槽500的步骤为：以图形化的掩膜层为掩膜刻蚀漂移层以形成多个间隔的凹槽500。
在多个凹槽500沿着第一方向的同一单侧侧部的漂移层中分别形成掺杂层的步骤包括：以图形化的掩膜层为掩膜，通过离子注入的方法对凹槽 500进行倾斜注入；在形成肖特基接触电极之前，去除图形化的掩膜层。
其中，倾斜注入的步骤，可以是将待加工的器件倾斜，离子注入保持垂直注入的方向不变，实现凹槽500单侧侧部和部分底部的离子注入，形成掺杂层201。也可以是保持待加工的器件不动，改变离子注入的方向，实现凹槽500单侧侧部和部分底部的离子注入，形成掺杂层201。
离子注入的步骤还可以是，通过掩膜的手段，遮盖部分的漂移层表面，实现凹槽500单侧侧部和部分底部的离子注入，形成掺杂层201。采用这样的方法实现掺杂层201的形成，可以实现掺杂层201仅位于凹槽500的单侧侧部和底部的漂移层200中，并且形成掺杂层201的横向尺寸以及在第一方向X上覆盖凹槽500底部的面积比例可控。
此外，在其他一些实施例中，也可以是在形成凹槽500之前先在漂移层200表面形成第一掩膜层，图形化第一掩膜层及漂移层200形成凹槽后去除第一掩膜层，然后在形成掺杂层201之前在漂移层200表面形成第二掩膜层，图形化第二掩膜层后再进行离子注入的倾斜注入，之后再去除第二掩膜层。
因此，掩膜层的具体使用次数和是否额外制造，可根据实际工艺需求确定，并且不仅局限于上述的两种方式。
在本实施例中，凹槽500的内壁表面包括第一区域和第二区域，第一区域为掺杂层201朝向凹槽500的表面。参考图5，肖特基二极管结构的制造方法还包括：在形成肖特基接触电极之前，至少在凹槽500的内壁第二区域的表面形成阻挡层202。
通过形成阻挡层202，使得凹槽500内的肖特基电极300与漂移层200被间隔开。由于凹槽500的内壁和底面的表面通常由于蚀刻工艺的原因使得表面是粗糙的表面，粗糙的表面会降低肖特基接触电极300与漂移层200的肖特基接触势垒，使得肖特基接触电极300在第二区域与漂移层200接触的位置处产生的电场较大，会产生较大的反向漏电流。通过形成阻挡层 202，且至少覆盖凹槽500位于第二区域中的内壁表面，使得肖特基接触电极在凹槽500内与漂移层不产生接触，极大降低反向漏电流产生的可能性。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请的保护范围之中。

Claims (10)

  1. 一种肖特基二极管结构，其特征在于，包括：
    半导体衬底层；
    位于所述半导体衬底层上的漂移层，所述漂移层中具有背向所述半导体衬底层一侧的多个间隔的凹槽，多个间隔的凹槽沿着第一方向排布；
    多个掺杂层，所述掺杂层分别位于多个所述凹槽沿着第一方向的同一单侧侧部的漂移层中，所述掺杂层的导电类型与所述漂移层的导电类型相反；
    肖特基接触电极，位于漂移层背向所述半导体衬底层的一侧且填充所述凹槽。
  2. 根据权利要求1所述的肖特基二极管结构，其特征在于，对于位于所述凹槽侧部的掺杂层，所述掺杂层在第一方向上的横向尺寸为0.5μm至1μm。
  3. 根据权利要求1所述的肖特基二极管结构，其特征在于，所述掺杂层自所述凹槽的一侧侧部的漂移层延伸至凹槽的部分底部的漂移层中。
  4. 根据权利要求3所述的肖特基二极管结构，其特征在于，对于位于所述凹槽部分底部的漂移层中的掺杂层，所述掺杂层在第一方向上的尺寸小于或等于所述凹槽的底面在第一方向上的尺寸。
  5. 根据权利要求3所述的肖特基二极管结构，其特征在于，对于位于所述凹槽部分底部的漂移层中的掺杂层，所述掺杂层的纵向尺寸为0.5μm至1μm。
  6. 根据权利要求1所述的肖特基二极管结构，其特征在于，还包括：阻挡层；所述凹槽的内壁包括第一区域和第二区域，所述第一区域为所述掺 杂层朝向所述凹槽的表面，所述阻挡层至少覆盖所述凹槽的内壁的第二区域的表面；所述肖特基接触电极覆盖所述阻挡层。
  7. 根据权利要求6所述的肖特基二极管结构，其特征在于，所述阻挡层的厚度为500埃至2000埃。
  8. 一种权利要求1至7中任一项的肖特基二极管结构的制造方法，其特征在于，包括以下步骤：
    提供半导体衬底层；
    在所述半导体衬底层一侧表面形成漂移层；
    在所述漂移层中形成背向所述半导体衬底层一侧的多个间隔的凹槽，多个凹槽沿着第一方向排布；
    在多个所述凹槽沿着第一方向的同一单侧侧部的漂移层中分别形成掺杂层，所述掺杂层的导电类型与所述漂移层的导电类型相反；
    形成掺杂层之后，形成肖特基接触电极，所述肖特基接触电极位于漂移层背向所述半导体衬底层的一侧且填充所述凹槽。
  9. 根据权利要求8所述的肖特基二极管结构的制造方法，其特征在于，在形成多个间隔的所述凹槽之前，在所述漂移层的表面形成图形化的掩膜层；
    在所述漂移层中形成背向所述半导体衬底层一侧的多个间隔的所述凹槽的步骤为：以图形化的掩膜层为掩膜刻蚀所述漂移层以形成多个间隔的所述凹槽；
    在多个所述凹槽沿着第一方向的同一单侧侧部的漂移层中分别形成掺杂层的步骤包括：以所述图形化的掩膜层为掩膜通过离子注入的方法对所述凹槽进行倾斜离子注入；
    在形成所述肖特基接触电极之前，去除所述图形化的掩膜层。
  10. 根据权利要求8所述的肖特基二极管结构的制造方法，其特征在于，所述凹槽的内壁表面包括第一区域和第二区域，所述第一区域为所述掺杂层朝向所述凹槽的表面；
    所述肖特基二极管结构的制造方法还包括：在形成肖特基接触电极之前，至少在所述凹槽的的内壁第二区域的表面形成阻挡层。
PCT/CN2021/083484 2021-03-19 2021-03-29 一种肖特基二极管结构及其制造方法 WO2022193357A1 (zh)

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