WO2022188353A1 - 脉冲产生电路和交错脉冲产生电路 - Google Patents

脉冲产生电路和交错脉冲产生电路 Download PDF

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Publication number
WO2022188353A1
WO2022188353A1 PCT/CN2021/112004 CN2021112004W WO2022188353A1 WO 2022188353 A1 WO2022188353 A1 WO 2022188353A1 CN 2021112004 W CN2021112004 W CN 2021112004W WO 2022188353 A1 WO2022188353 A1 WO 2022188353A1
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Prior art keywords
signal
selection
oscillation
pulse
reset
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PCT/CN2021/112004
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English (en)
French (fr)
Inventor
王佳
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21929820.5A priority Critical patent/EP4283871A1/en
Priority to US17/665,734 priority patent/US11817862B2/en
Publication of WO2022188353A1 publication Critical patent/WO2022188353A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching

Definitions

  • the present application relates to, but is not limited to, a pulse generation circuit and an interleaved pulse generation circuit.
  • staggered signals are often used, and staggered signals refer to signals generated by a fixed delay at each interval.
  • the clock signal is usually used to generate equidistant interlaced signals; for asynchronous signals, the required equidistant interlaced signals are generated by inserting delay cells, and the delay between the signals can be based on requirements. Insert the corresponding delay unit implementation.
  • the synchronous signal is used to generate the equidistant staggered signal, the delay between the equidistant staggered signals is an integer multiple of the clock period, and the controllability of the delay between the equidistant staggered signals is poor; the asynchronous signal is used to generate the equidistantly staggered signal. In this way, although the delay between the signals is well controllable, it will significantly increase the area of the circuit layout formed and the power consumption of the circuit.
  • variable pulse signal is a prerequisite for optimizing the generation method of the equidistant interleaved signal.
  • An embodiment of the present application provides a pulse generating circuit, including: an oscillation module, receiving a control signal, and generating a first oscillation signal according to the control signal; a period adjustment module, receiving the first oscillation signal and a magnification selection signal, and outputting a second oscillation signal, the period of the second oscillating signal is the period adjusted by the first oscillating signal based on the magnification selection signal; the pulse conversion module receives the second oscillating signal and outputs a pulse signal whose pulse is based on the rising edge of the second oscillating signal or A falling edge is generated, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.
  • FIG. 1 and FIG. 2 are schematic structural diagrams of a pulse generating circuit provided by an embodiment of the application
  • FIG. 3 is a schematic diagram of a specific circuit of an oscillation module provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a delay unit provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a selection unit provided by an embodiment of the present application.
  • 6 and 7 are schematic circuit diagrams of a period adjustment module provided by an embodiment of the application.
  • FIG. 8 is a schematic timing diagram of signals in a pulse generating circuit provided by an embodiment of the present application.
  • FIGS. 9 and 10 are schematic structural diagrams of an interleaved pulse generating circuit provided by another embodiment of the present application.
  • FIG. 11 is a schematic diagram of a specific circuit of a signal generating module provided by another embodiment of the present application.
  • FIG. 12 is a schematic timing diagram of signals in an interleaved pulse generating circuit according to another embodiment of the present application.
  • the synchronous signal is used to generate the equidistant staggered signal.
  • the delay between the equidistant staggered signals must be an integer multiple of the clock period, and the controllability of the delay between the equidistant staggered signals is poor; the asynchronous signal is used to generate the equidistantly staggered signal. , although the delay between the signals is controllable, it will significantly increase the area of the circuit layout formed and the power consumption of the circuit.
  • an embodiment of the present application provides a pulse generation circuit, including: an oscillation module, which receives a control signal, and generates a first oscillation signal according to the control signal; a period adjustment module, which receives the first oscillation signal and a magnification selection signal , and output the second oscillation signal, the period of the second oscillation signal is the period adjusted by the first oscillation signal based on the ratio selection signal; the pulse conversion module receives the second oscillation signal and outputs the pulse signal, and the pulse of the pulse signal is based on the second oscillation signal.
  • a rising edge or a falling edge of the oscillating signal is generated, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillating signal.
  • FIG. 1 and 2 are schematic structural diagrams of a pulse generating circuit provided in this embodiment
  • FIG. 3 is a specific circuit schematic diagram of an oscillation module provided in this embodiment
  • FIG. 4 is a schematic structural diagram of a delay unit provided in this embodiment
  • FIG. 5 Figure 6 and Figure 7 are schematic circuit diagrams of the period adjustment module provided by this embodiment
  • Figure 8 is a schematic timing diagram of signals in the pulse generating circuit provided by this embodiment; The figure further illustrates the pulse generating circuit provided in this embodiment in detail.
  • the pulse generating circuit 100 includes: an oscillation module 101 that receives a control signal RasEn and generates a first oscillation signal Osc1 according to the control signal RasEn.
  • the control signal RasEn is an externally input instruction, and the oscillation module 101 is used to generate the first oscillation signal Osc1 according to the external instruction; specifically, when the control signal RasEn is at an active level, the oscillation module 101 generates the first oscillation signal Osc1; in this embodiment , it is assumed that the period of the first oscillation signal Osc1 is T.
  • the oscillation module 101 starts to oscillate to generate the first oscillation signal Osc1 .
  • the oscillation module 101 includes an oscillation unit 111 and a trigger unit 121 connected to the oscillation unit 111; the trigger unit 121 is configured to receive the reset signal fnRasEn and the control signal RasEn, and trigger based on the reset signal fnRasEn and the control signal RasEn Oscillation unit 111; after the oscillation unit 111 is triggered, a first oscillation signal Osc1 is generated according to the control signal RasEn.
  • the meaning of “based on” includes but is not limited to: when the reset signal fnRasEn is in a non-reset state, and the control signal RasEn is Active level, the triggering unit 121 triggers the oscillating unit 111 .
  • the reset signal fnRasEn is an externally input reset command, which is used to reset the trigger unit 121; specifically, after the trigger unit 121 is reset, if the control signal RasEn received by the trigger unit 121 is a valid level, the trigger unit 121 triggers the oscillation unit 111 , so that the oscillation unit 111 generates the first oscillation signal Osc1.
  • the oscillation unit 111 includes a ring oscillator formed by A inverters connected in series, A is a positive odd number; A can be 5, 7, 9, 11, etc.
  • A 7, that is, a ring oscillator formed by 7 inverters connected in series is used as an example for illustration, which does not constitute a limitation to this embodiment.
  • the number of inverters in the ring oscillator can be selected according to actual needs.
  • the trigger unit 121 includes a first NAND gate 211 and a second NAND gate 212 , an output end of the first NAND gate 211 is connected to an input end of the second NAND gate 212 , and an input end of the first NAND gate 211 And the output terminal of the second NAND gate 212 is used to access the ring oscillator; among the first NAND gate 211 and the second NAND gate 212, one of them is used to receive the control signal RasEn, and the other is used to receive the reset signal fnRasEn; it should be noted that the given first NAND gate 211 in FIG.
  • the second NAND gate 212 is used to receive the reset signal fnRasEn, which does not constitute a limitation to this embodiment.
  • the second NAND gate may also be used to receive the control signal, and the first NAND gate to receive the reset signal.
  • the first inverter can be selected according to actual needs The number of inverters in group 215.
  • the first selection unit (not shown) is used for receiving the first selection signal fnAdjDly1, and based on the first selection signal fnAdjDly1, the first inverter group 215 is connected in series between adjacent inverters in the ring oscillator .
  • the purpose of B number of inverters in the first inverter group 215 is to ensure that the total number of inverters in the ring oscillator is an odd number; specifically, the first selection unit (not shown) includes a first The selector 214 is used for gating the first branch or the second branch according to the first selection signal fnAdjDly1 and the inverted first selection signal fnAdjDly1N; wherein, the first branch is used as the connection of adjacent inverters in the ring oscillator circuit, the second branch connects the first inverter group 215 in series to the connection circuit of the adjacent inverters of the ring oscillator; the purpose of connecting the first inverter group 215 to the ring oscillator is to increase the ring oscillation The number of inverters in the inverter is increased, thereby increasing the period of the first oscillation signal Osc1 generated by the oscillation unit 111 .
  • the signal Osc1 is 1.2T; since the first inverter group 215 is connected to the ring oscillator through the control of the first selection signal fnAdjDly1, the first oscillation signal Osc1 generated by the oscillation unit 111 can be adjusted by the externally input first selection signal fnAdjDly1 cycle.
  • the second inverter can be selected according to actual needs The number of inverters in group 217.
  • the second selection unit (not shown) is configured to receive the second selection signal fnAdjDly2, and based on the second selection signal fnAdjDly2, connect the second inverter group 217 in series between adjacent inverters in the ring oscillator .
  • the purpose of the number of inverters in the second inverter group 217 is to ensure that the total number of inverters in the ring oscillator is an odd number; specifically, the second selection unit (not shown) includes a second The selector 216 is used for gating the third branch or the fourth branch according to the second selection signal fnAdjDly2 and the inverted second selection signal fnAdjDly2N; wherein, the third branch is used as the connection of adjacent inverters in the ring oscillator Circuit, the fourth way connects the second inverter group 217 to the connection circuit of the adjacent inverters of the ring oscillator; the purpose of connecting the second inverter group 217 to the ring oscillator is to increase the ring oscillation The number of inverters in the inverter is increased, thereby increasing the period of the first oscillation signal Osc1 generated by the oscillation unit 111.
  • the The signal Osc1 is 1.4T; since the access of the second inverter group 217 to the ring oscillator is controlled by the second selection signal fnAdjDly2, the first oscillation signal Osc1 generated by the oscillation unit 111 can be adjusted by the externally input second selection signal fnAdjDly2 cycle.
  • B and C can be set to any positive even numbers, and in specific applications, the values of B and C can be reasonably set according to the required change of the first oscillation signal Osc1 generated by the oscillation unit 111; in addition, in this embodiment, The implementation of the two inverter groups is described, and the implementation scheme of adding the third inverter group and the fourth inverter group on the basis of this embodiment should all belong to the protection scope of the present application.
  • the period of the first oscillation signal Osc1 can be changed with different amplitudes; at this time, according to the first selection signal fnAdjDly1 and the second
  • the periodic table 1 of the first oscillation signal Osc1 generated by the different selection signal fnAdjDly2 is shown in:
  • the pulse generation circuit 100 includes: a period adjustment module 102 , which receives the first oscillation signal Osc1 and the magnification selection signal fnAdjDlyx, and outputs a second oscillation signal Osc2 , the period of which is the first oscillation signal Osc1 based on The period after the adjustment of the magnification selection signal fnAdjDlyx, the magnification selection signal fnAdjDlyx is an externally input selection command, which is used to adjust the period of the second oscillation signal Osc2, that is, the pulse generation circuit can be adjusted by the externally input magnification selection signal fnAdjDlyx
  • the period adjustment module 102 generates The period of the second oscillation signal Osc2.
  • the oscillation adjustment signal OscT may be generated by using the first oscillation signal Osc1, and then the first oscillation signal Osc1 may be selected as the second oscillation signal Osc2 for output according to the magnification selection signal fnAdjDlyx, or the oscillation adjustment signal OscT may be selected as the second oscillation signal Osc2 output. It is also possible to determine whether the oscillation adjustment signal OscT needs to be generated according to the magnification selection signal fnAdjDlyx, that is, the second oscillation signal Osc2 is output in a manner of determining first and then generating.
  • the period adjustment module 102 includes: a delay unit 112 that receives the first oscillation signal Osc1 and generates an oscillation adjustment signal OscT based on the first oscillation signal Osc1 , and the period of the oscillation adjustment signal OscT is different from that of the first oscillation signal Osc1
  • the selection unit 122 receives the magnification selection signal fnAdjDlyx, and selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx.
  • the delay unit 112 includes: a D flip-flop 201, the D flip-flop includes an input terminal D, clock terminals Clk and ClkN, a reset terminal RN and an output terminal Q, and the clock terminals Clk and ClkN are used for receiving The first oscillating signal Osc1 and the inverted first oscillating signal Osc1N, the reset terminal RN is used to receive the reset signal fnRasEn, the output terminal Q is used to trigger the inverter 202 in series and connected to the input terminal D, and is used to output the oscillation adjustment signal OscT .
  • the period of the output oscillation adjustment signal OscT at this time is twice the period of the first oscillation signal Osc1.
  • the selection unit 122 includes a magnification selector 203
  • the magnification selector 203 includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal
  • the first selection input terminal is used for receiving the first oscillation signal Osc1
  • the second selection input terminal is used to receive the oscillation adjustment signal OscT
  • the selection signal terminal is used to receive the magnification selection signal fnAdjDlyx and the inverted magnification selection signal fnAdjDlyxN
  • the selection output terminal is used to output the second oscillation signal Osc2, through the magnification selection signal fnAdjDlyx
  • the period of the oscillating signal can be greatly changed.
  • the delay unit 112 includes E series-connected delay subunits, the oscillation adjustment signal OscT includes E delay signals, and E is a positive integer;
  • the signal Osc1 generates a first delay signal Osc11, and inputs the first delay signal Osc11 into the second-stage delay subunit;
  • the F-th stage delay subunit is used for the F-1th stage delay signal Osc1F- 1 Generates the F-th delay signal Osc1F, where F is a positive integer less than or equal to E and greater than or equal to 2.
  • the F-th stage delay subunit includes: a D flip-flop, the D flip-flop includes an input terminal, a clock terminal, a reset terminal, and an output terminal, and the clock terminal and the clock terminal are used to receive the F-1th delay signal Osc1F-1 and Inverting the F-1th delay signal Osc1F-1N, the reset terminal is used for receiving the reset signal, the output terminal is used for triggering the inverter in series and connected to the input terminal, and is used for outputting the Fth delay signal Osc1F.
  • the period of the output F-th delayed signal Osc1F at this time is twice the period of the F-1-th delayed signal Osc1F-1.
  • the delay unit 112 includes three series-connected delay subunits, which are respectively a first-level delay subunit 221 , a second-level delay subunit 223 and a third-level delay subunit 225 ;
  • the first stage delay subunit 221 is used to generate the first delay signal Osc11 according to the first oscillation signal Osc1, and the period of the first delay signal Osc11 is twice the period of the first oscillation signal Osc1;
  • the second stage delay subunit 223 It is used to generate the second delay signal Osc12 according to the first delay signal Osc11, and the period of the second delay signal Osc12 is twice the period of the first delay signal Osc11;
  • the third-stage delay subunit 225 is used for generating the second delay signal Osc12 according to the second
  • the delay signal Osc12 generates a third delay signal Osc13, and the period of the third delay signal Osc13 is twice the period of the second delay signal Osc12.
  • the selection unit 122 selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx, including: selecting the E-1 th delay signal Osc1E-1 or The E-th delayed signal Osc1E is used as the second oscillation signal Osc2.
  • the selection unit 122 selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx, including: selecting the second delay signal Osc12 or the third delay signal based on the magnification selection signal fnAdjDlyx
  • the time signal Osc13 is used as the second oscillation signal Osc2.
  • the first stage delay unit 221 and the second stage delay sub-unit 223 are used to expand the period of the output second oscillation signal Osc2.
  • the selection unit 122 includes E series-connected selection sub-units, and the magnification selection signal fnAdjDlyx includes a sub-magnification selection signal corresponding to each selection sub-unit;
  • the selection signal selects the first oscillation signal Osc1 or the first delay signal Osc11 and inputs it into the second-stage selection subunit;
  • the F-th stage selection sub-unit is used for selecting the F-1th stage selection signal according to the corresponding sub-magnification selection signal
  • the output signal of the subunit or the Fth delay signal Osc1F is input into the F+1th stage selection subunit;
  • the Eth stage selection subunit is used to select the E-1th stage selection subunit according to the corresponding sub-magnification selection signal.
  • the output signal or the oscillation adjustment signal OscT is used as the second oscillation signal Osc2, and F is a positive integer less than E and greater than or equal to 2.
  • the F-th stage selection subunit includes: a magnification selector, the magnification selector includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal, and the first selection terminal is used for receiving the F-1th
  • the output signal of the stage selection subunit the second selection input terminal is used to receive the Fth delay signal Osc1F
  • the selection signal terminal is used to receive the corresponding submultiplier selection signal
  • the selection output terminal is used to output the F-1th stage selection subunit The output signal or the F-th delay signal Osc1F.
  • the selection unit 122 includes three selection subunits connected in series, which are the first-level selection subunit 227 , the second-level selection subunit 228 and the third-level selection subunit 229 ; wherein, the first-level selection subunit 229 227 is used to select the first oscillation signal Osc1 or the first delay signal Osc11 to be input to the second stage selection subunit 228, and the second stage selection subunit 228 is used to select the output signal of the first stage selection subunit 227 or the second delay.
  • the time signal Osc12 is input to the third stage selection subunit 229, and the third stage selection subunit 229 is used to select the output signal of the second stage selection subunit 228 or the third delay signal Osc13 as the oscillation adjustment signal OscT.
  • the third stage selection subunit 229 is used to select the output signal of the second stage selection subunit 228 or the third delay signal Osc13 as the oscillation adjustment signal OscT.
  • the magnification selection signal fnAdjDlyx, the first selection signal fnAdjDly1 and the second selection signal fnAdjDly2 can be implemented by multi-bit binary numbers, that is, the selection signal is a multi-bit binary number, one of which is used as the multiplier.
  • the selection signal fnAdjDlyx one bit is used as the first selection signal fnAdjDly1, and one bit is used as the second selection signal fnAdjDly2.
  • the pulse generation circuit 100 includes: a pulse conversion module 103 that receives the second oscillation signal Osc2 and outputs a pulse signal OscClk, the pulse of the pulse signal OscClk is generated based on the rising edge or the falling edge of the second oscillation signal, and the pulse signal
  • the pulse period of OscClk is the same as the oscillation period of the second oscillation signal.
  • the pulse conversion module 103 includes a pulse converter 113 for receiving the second oscillating signal Osc2 and generating the pulse signal OscClk based on the second oscillating signal Osc2 .
  • the pulse converter 113 when the pulse converter 113 detects the rising edge of the second oscillating signal Osc2 and outputs an upward narrow pulse, the output end of the pulse converter 113 can also pass through a series inverter to output a downward narrow pulse. pulse. In another example, when the pulse converter 113 detects the rising edge of the second oscillating signal Osc2 and outputs a narrow downward pulse, the output end of the pulse converter 113 can also pass through a series inverter to output an upward pulse. narrow pulse. In addition, in this embodiment, the pulse converter 113 operates based on the rising edge of the second oscillation signal Osc2 . In other embodiments, the pulse converter 113 may also operate based on the falling edge of the second oscillation signal.
  • the meaning of “based on” includes but is not limited to: detecting the rising edge of the second oscillating signal Osc2, or detecting the second oscillating signal Osc2
  • the narrow pulse of the pulse signal OscClk is generated after the oscillation signal Osc2 changes from low level to high level (high level to low level).
  • the pulse signal OscClk is generated based on the rising edge of the second oscillating signal Osc2, and in other embodiments, the pulse signal may also be generated according to the falling edge of the second oscillating signal.
  • the oscillation module 101 when the control signal RasEn is at an active level, the oscillation module 101 generates a first oscillation signal Osc1 with a period T, and the period adjustment module 102 adjusts the period of the second oscillation signal Osc2 (Osc2') according to the magnification selection signal fnAdjDlyx.
  • the second oscillation signal Osc2 generated at this time has a periodic change. Assuming that the period T is changed to the period 2T, the pulse signal OscClk generated at this time has a pulse in the pulse signal OscClk. The period is also changed from period T to period 2T; if the magnification selection signal fnAdjDlyx is changed before the control signal RasEn is at the active level, the second oscillation signal Osc2' generated at this time has no period change, and the pulse period in the generated pulse signal OscClk' There is also no pulse period variation.
  • the first oscillating signal is generated according to the control signal, that is, when the control signal is at an active level, a first oscillating signal with a certain period is generated; That is, based on the magnification selection signal, the period of the first oscillating signal is changed to generate the corresponding second oscillating signal; then the second oscillating signal is used as a signal source to generate a pulse signal, and the pulse period of the generated pulse signal is the same as the oscillation of the second oscillating signal.
  • the cycle is the same; in the process of generating the pulse signal, if the magnification selection signal changes, the amplitude of the cycle of the first oscillating signal is adjusted to change, so that the cycle of the generated second oscillating signal changes, thereby generating a pulse signal with an adjustable cycle.
  • each unit involved in this embodiment is a logical unit.
  • a logical unit may be a physical unit, a part of a physical unit, or multiple physical units.
  • a composite implementation of the unit in order to highlight the innovative part of this application, this embodiment does not introduce units that are not very closely related to solving the technical problem proposed by this application, but this does not mean that there are no other units in this embodiment.
  • an interleaved pulse generating circuit including: a signal generating module for generating a first control signal and a second control signal according to an activation signal, where the first control signal and the second control signal are inverted signals;
  • the first pulse generation unit includes the above-mentioned pulse generation circuit, and the first pulse generation unit is used to generate the first pulse signal according to the first control signal;
  • the second pulse generation unit includes the above-mentioned pulse generation circuit, and the second pulse generation unit uses The second pulse signal is generated according to the second control signal; the first pulse signal and the second pulse signal are interleaved pulse signals.
  • FIG. 9 and FIG. 10 are schematic structural diagrams of the interleaved pulse generating circuit provided by the present embodiment
  • FIG. 11 is a specific circuit schematic diagram of the signal generating module provided by the present embodiment
  • Schematic diagram of timing sequence; the interleaved pulse generating circuit provided in this embodiment will be described in detail below with reference to the accompanying drawings, and the parts that are the same as or corresponding to the above-mentioned embodiment will not be described in detail below.
  • the interleaved pulse generating circuit 300 includes: a signal generating module 303 for generating a first control signal ActEn and a second control signal PreEn according to the activation signal Active, and the first control signal ActEn and the second control signal PreEn are inverted Signal.
  • the activation signal Active is an activation command input from the outside, and the signal generating module 303 is configured to generate the first control signal ActEn and the second control signal PreEn which are mutually inverse signals according to the external activation command.
  • the signal generating module 303 includes:
  • the reset unit 313 receives the first reset signal fnActEn and the activation signal Active, and generates the first control signal ActEn based on the first reset signal fnActEn and the activation signal Active.
  • the first reset signal fnActEn is an externally input reset command, which is used to reset the reset unit 313; specifically, after the reset unit 313 is reset, if the activation signal Active received by the reset unit 313 is an active level, the reset unit 313 generates the first reset signal.
  • the inversion unit 323 receives the first control signal ActEn, and generates the second control signal PreEn based on the first control signal ActEn.
  • the signal generating module 303 further includes: a reset signal generating unit 333 for generating a second reset signal fnPreEn according to the first reset signal fnActEn and the first control signal ActEn, so that when the first reset signal fnActEn is a reset When the second reset signal fnPreEn is in the reset state, when the first reset signal fnActEn is in the non-reset state, the second reset signal fnPreEn generates a reset narrow pulse based on the changing edge of the first control signal ActEn.
  • the signal generation module 303 further includes: a selection signal generation unit 343, configured to receive the selection signal fnAdjDly, and generate a selection signal group based on the selection signal fnAdjDly, the selection signal group includes the selection signal fnAdjDly and the inverted selection signal fnAdjDlyN, The selection signal fnAdjDly and the inversion selection signal fnAdjDlyN are inversion signals.
  • the selection signal fnAdjDly includes the rate selection signal fnAdjDlyx, the first selection signal fnAdjDly1 and the second selection signal fnAdjDly2 for regulating the pulse generating circuit 100 .
  • the reset unit 313 includes a reset NAND gate 403 and a reset inverter 404, the reset inverter 404 is connected to the output terminal of the reset NAND gate 403, and the reset NAND gate 403 is used to receive the first A reset signal fnActEn and an activation signal Active.
  • the inversion unit 323 includes an output inverter 405 connected to the reset unit 313 for generating the second control signal PreEn according to the first control signal ActEn.
  • the reset signal generation unit 333 includes a pulse conversion device 406 for detecting the changing edge (such as a rising edge) of the first control signal ActEn to generate a pulse control signal; an output NAND gate 407 and an output inverter 408 are used to output a NAND gate 407 It is also used to receive the first reset signal fnActEn, and at this time, the output inverter 408 outputs the second reset signal fnPreEn.
  • a pulse conversion device 406 for detecting the changing edge (such as a rising edge) of the first control signal ActEn to generate a pulse control signal
  • an output NAND gate 407 and an output inverter 408 are used to output a NAND gate 407 It is also used to receive the first reset signal fnActEn, and at this time, the output inverter 408 outputs the second reset signal fnPreEn.
  • the selection signal generating unit 343 includes: a first selection inverter 401 and a second selection inverter 402 connected in series, the output end of the first selection inverter 401 is connected to the input end of the second selection inverter 402, and is used for according to The selection signal fnAdjDly generates a selection signal group.
  • the interleaved pulse generation circuit 300 further includes: a first pulse generation unit 301 and a second pulse generation unit 302; the first pulse generation unit 301 includes the above-mentioned pulse generation circuit 100, and the first pulse generation unit 301 is used for
  • the first pulse signal ActClk is generated according to the first control signal ActEn;
  • the second pulse generation unit 302 includes the above-mentioned pulse generation circuit 100, and the second pulse generation unit 302 is configured to generate the second pulse signal PreClk according to the second control signal PreEn;
  • the pulse signal ActClk and the second pulse signal PreClk are interleaved pulse signals, and the interleaved pulse signal is the pulse signal (the first pulse signal ActClk and the second pulse signal) generated according to the inverted signals (the first control signal ActEn and the second control signal PreEn). signal PreClk).
  • the interleaved pulse generating circuit 300 is used for receiving an externally input activation signal Active, and the signal generating module 303 is used for generating a first control signal ActEn and a second control signal PreEn according to the externally input activation signal Active, and the first control signal ActEn and the second control signal PreEn are inverted signals.
  • the first pulse generating unit 301 is configured to generate a first oscillation signal with a period of T according to the first control signal ActEn Osc1 and the second oscillating signal Osc2 with a period of 2T; in this embodiment, the period of the second oscillating signal Osc2 is consistent with the period of the first oscillating signal Osc1, and the first pulse signal ActClk is generated based on the rising edge of the second oscillating signal Osc2.
  • the second pulse generating unit 302 is configured to configure the second control signal PreEn to generate a first oscillation signal Osc1′′ with a period of T and a second oscillation signal Osc2′′ with a period of 2T; in this embodiment, the second oscillation signal Osc2′′ and The cycles of the first oscillating signal Osc1′′ are the same, and the second pulse signal PreClk is generated based on the rising edge of the second oscillating signal Osc2′′.
  • the first pulse signal ActClk and the second pulse signal PreClk generated at this time are interleaved pulse signals.
  • the first control signal and the second control signal are mutually inverse signals; the first pulse signal and the second control signal are generated according to the inverse control signal.
  • the two pulse signals are interleaved pulse signals, that is, the first pulse signal is in the pulse period and the second pulse signal is inactive level; the second pulse signal is in the pulse period, the first pulse signal is inactive level, and the generated first pulse signal and
  • the period of the second pulse signal can be adjusted, that is, a pulse signal with an adjustable period is generated, and the circuit involves fewer devices, the area of the circuit layout is small, and the power consumption of the circuit is low.
  • each unit involved in this embodiment is a logical unit.
  • a logical unit may be a physical unit, a part of a physical unit, or multiple physical units.
  • a composite implementation of the unit in order to highlight the innovative part of the present application, this embodiment does not introduce units that are not closely related to solving the technical problem raised by the present application, but this does not mean that there are no other units in this embodiment.
  • the pulse generating circuit includes: an oscillation module, which receives a control signal, and generates a first oscillation signal according to the control signal; a period adjustment module, which receives the first oscillation signal and the magnification selection signal, and outputs the second oscillation signal, The period of the second oscillating signal is the period adjusted by the first oscillating signal based on the magnification selection signal; the pulse conversion module receives the second oscillating signal and outputs a pulse signal, the pulse of which is based on the rising or falling edge of the second oscillating signal is generated, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.
  • the embodiment of the present application can generate a pulse signal with an adjustable period, and the area of the circuit layout is small, and the power consumption of the circuit is small.

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Abstract

本申请实施例提供一种脉冲产生电路和交错脉冲产生电路，其中，脉冲产生电路，包括：振荡模块，接收控制信号，且根据控制信号生成第一振荡信号；周期调整模块，接收第一振荡信号以及倍率选择信号，并输出第二振荡信号，第二振荡信号的周期为第一振荡信号基于倍率选择信号调整后的周期；脉冲转换模块，接收第二振荡信号，并输出脉冲信号，脉冲信号的脉冲基于第二振荡信号的上升沿或下降沿产生，且脉冲信号的脉冲周期与第二振荡信号的振荡周期相同；本申请实施例以产生周期可调整的脉冲信号，且电路版图的面积小，电路的功耗小。

Description

脉冲产生电路和交错脉冲产生电路
相关申请的交叉引用
本申请要求在2021年03月09日提交中国专利局、申请号为202110256942.6、申请名称为“脉冲产生电路和交错脉冲产生电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及但不限于一种脉冲产生电路和交错脉冲产生电路。
背景技术
在半导体电路设计中，经常会用到等间距交错(Stagger)信号，等间距交错信号指每间隔固定延迟产生的信号。
对于同步信号而言，通常借助时钟信号来产生等间距交错信号；对于异步信号而言，通过插入延时单元(delay cell)来产生所需的等间距交错信号，信号之间的延迟可以根据需求插入相应的延时单元实现。其中，采用同步信号产生等间距交错信号的方式，等间距交错信号之间的延迟是时钟周期的整数倍，等间距交错信号之间延迟大小的可控性差；采用异步信号产生等间距交错信号的方式，虽然信号之间的延迟可控性好，但会明显增大形成的电路版图的面积和电路的功耗。
然而申请人发现，通过脉冲信号的周期来调整等间距交错信号的信号延迟可以减小电路版图的面积和电路的功耗，且信号之间的延迟无需为时钟周期的整数倍，如何产生周期可变的脉冲信号，是优化等间距交错信号产生方式的前提条件。
发明内容
本申请实施例提供了一种脉冲产生电路，包括：振荡模块，接收控制信号，且根据控制信号生成第一振荡信号；周期调整模块，接收第一振荡信号以及倍 率选择信号，并输出第二振荡信号，第二振荡信号的周期为第一振荡信号基于倍率选择信号调整后的周期；脉冲转换模块，接收第二振荡信号，并输出脉冲信号，脉冲信号的脉冲基于第二振荡信号的上升沿或下降沿产生，且脉冲信号的脉冲周期与第二振荡信号的振荡周期相同。
附图说明
图1和图2为本申请一实施例提供的脉冲产生电路的结构示意图；
图3为本申请一实施例提供的振荡模块的具体电路示意图；
图4为本申请一实施例提供的延时单元的结构示意图；
图5为本申请一实施例提供的选择单元的结构示意图；
图6和图7为本申请一实施例提供的周期调整模块的电路示意图；
图8为本申请一实施例提供的脉冲产生电路中信号的时序示意图；
图9和图10为本申请另一实施例提供的交错脉冲产生电路的结构示意图；
图11为本申请另一实施例提供的信号产生模块的具体电路示意图；
图12为本申请另一实施例提供的交错脉冲产生电路中信号的时序示意图。
具体实施方式
采用同步信号产生等间距交错信号的方式，等间距交错信号之间的延迟必须是时钟周期的整数倍，等间距交错信号之间延迟大小的可控性差；采用异步信号产生等间距交错信号的方式，虽然信号之间的延迟可控性好，但会明显增大形成的电路版图的面积和电路的功耗。
为解决上述问题，本申请一实施例提供了一种脉冲产生电路，包括：振荡模块，接收控制信号，且根据控制信号生成第一振荡信号；周期调整模块，接收第一振荡信号以及倍率选择信号，并输出第二振荡信号，第二振荡信号的周期为第一振荡信号基于倍率选择信号调整后的周期；脉冲转换模块，接收第二振荡信号，并输出脉冲信号，脉冲信号的脉冲基于第二振荡信号的上升沿或下降沿产生，且脉冲信号的脉冲周期与第二振荡信号的振荡周期相同。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1和图2为本实施例提供的脉冲产生电路的结构示意图，图3为本实施例提供的振荡模块的具体电路示意图，图4为本实施例提供的延时单元的结构示意图，图5为本实施例提供的选择单元的结构示意图，图6和图7为本实施例提供的周期调整模块的电路示意图，图8为本实施例提供的脉冲产生电路中信号的时序示意图；以下结合附图对本实施例提供的脉冲产生电路作进一步详细说明。
参考图1，脉冲产生电路100包括：振荡模块101，接收控制信号RasEn，且根据控制信号RasEn生成第一振荡信号Osc1。
控制信号RasEn即外部输入的指令，振荡模块101用于根据外部指令生成第一振荡信号Osc1；具体地，当控制信号RasEn处于有效电平时，振荡模块101生成第一振荡信号Osc1；在本实施例中，假设第一振荡信号Osc1的周期为T。
在一个例子中，当接收到控制信号RasEn，且控制信号RasEn为有效电平时，振荡模块101起振以产生第一振荡信号Osc1。
进一步地，参考图2，振荡模块101包括振荡单元111以及连接在振荡单元111中的触发单元121；触发单元121用于接收复位信号fnRasEn以及控制信号RasEn，并基于复位信号fnRasEn和控制信号RasEn触发振荡单元111；振荡单元111触发后，根据控制信号RasEn生成第一振荡信号Osc1。
需要注意的是，此处描述的“基于复位信号fnRasEn和控制信号RasEn触发振荡单元111”中，“基于”的含义包括但不限定于：当复位信号fnRasEn处 于非复位状态，且控制信号RasEn为有效电平，触发单元121触发振荡单元111。
复位信号fnRasEn即外部输入的复位指令，用于对触发单元121进行复位；具体地，当触发单元121复位后，若触发单元121接收的控制信号RasEn为有效电平，触发单元121触发振荡单元111，以使振荡单元111产生第一振荡信号Osc1。
在一个例子中，参考图3，振荡单元111包括A个反相器串联形成的环形振荡器，A为正奇数；A可以为5、7、9、11等，在本实施例中以A＝7，即7个反相器串联形成的环形振荡器为例进行举例说明，并不构成对本实施例的限定，在具体应用中，可以根据实际需求选择环形振荡器中反相器的数量。触发单元121包括第一与非门211和第二与非门212，第一与非门211的输出端连接至第二与非门212的一输入端，第一与非门211的一输入端和第二与非门212的输出端用于接入环形振荡器；第一与非门211与第二与非门212中，其中一者用于接收控制信号RasEn，另一者用于接收复位信号fnRasEn；需要说明的是，图3中给定的第一与非门211用于接收控制信号RasEn，第二与非门212用于接收复位信号fnRasEn并不构成对本实施例的限定，在其他实施例中也可以采用第二与非门接收控制信号，第一与非门接收复位信号。
在本实施例中，振荡模块101还包括：第一反相器组215，包括串联的B个反相器，B为正偶数；B可以为2、4、6等，在本实施例中以B＝2，即2个反相器串联形成的第一反相器组215为例进行举例说明，并不构成对本实施例的限定，在具体应用中，可以根据实际需求选择第一反相器组215中反相器的数量。第一选择单元(未图示)，用于接收第一选择信号fnAdjDly1，并基于第一选择信号fnAdjDly1，将第一反相器组215串接在环形振荡器中的相邻反相器之间。
具体地，第一反相器组215中反相器为B个的目的在于：保证环形振荡器中反相器的总数为奇数个；具体地，第一选择单元(未图示)包括第一选择器214，用于根据第一选择信号fnAdjDly1和反相第一选择信号fnAdjDly1N选通第一支路或第二支路；其中，第一支路作为环形振荡器中相邻反相器的连接电 路，第二支路将第一反相器组215串接至环形振荡器相邻反相器的连接电路中；将第一反相器组215接入环形振荡器的目的是：增加环形振荡器中反相器的个数，从而增大振荡单元111产生的第一振荡信号Osc1的周期，在本实施例中假设增加第一反相器组215的反相器后，生成的第一振荡信号Osc1为1.2T；由于第一反相器组215接入环形振荡器是通过第一选择信号fnAdjDly1控制，即可通过外部输入的第一选择信号fnAdjDly1调整振荡单元111生成的第一振荡信号Osc1的周期。
在本实施例中，振荡模块101还包括：第二反相器组217，包括串联的C个反相器，C为正偶数；C可以为2、4、6等，在本实施例中以C＝4，即4个反相器串联形成的第二反相器组217为例进行举例说明，并不构成对本实施例的限定，在具体应用中，可以根据实际需求选择第二反相器组217中反相器的数量。第二选择单元(未图示)，用于接收第二选择信号fnAdjDly2，并基于第二选择信号fnAdjDly2，将第二反相器组217串接在环形振荡器中的相邻反相器之间。
具体地，第二反相器组217中反相器为C个的目的在于：保证环形振荡器中反相器的总数为奇数个；具体地，第二选择单元(未图示)包括第二选择器216，用于根据第二选择信号fnAdjDly2和反相第二选择信号fnAdjDly2N选通第三支路或第四支路；其中，第三支路作为环形振荡器中相邻反相器的连接电路，第四之路将第二反相器组217串接至环形振荡器相邻反相器的连接电路中；将第二反相器组217接入环形振荡器的目的是：增加环形振荡器中反相器的个数，从而增大振荡单元111产生的第一振荡信号Osc1的周期，在本实施例中假设增加第二反相器组217的反相器后，生成的第一振荡信号Osc1为1.4T；由于第二反相器组217接入环形振荡器是通过第二选择信号fnAdjDly2控制，即可通过外部输入的第二选择信号fnAdjDly2调整振荡单元111生成的第一振荡信号Osc1的周期。
在本实施例中B和C可以设置为任意正偶数，在具体应用于可以根据振荡单元111产生的第一振荡信号Osc1所需的变化，合理设置B和C的值；另外， 本实施例中说明了两个反相器组的实现方式，在本实施例的基础上继续加入第三反相器组、第四反相器组的实现方案，都应该属于本申请的保护范围。
另外，通过第一反相器组215和第二反相器组217同时接入环形振荡器，可以实现不同幅度的改变第一振荡信号Osc1的周期；此时根据第一选择信号fnAdjDly1和第二选择信号fnAdjDly2的不同生成的第一振荡信号Osc1的周期表1所示：
表1 Osc1周期表
fnAdjDly1 fnAdjDly2 Osc1的周期
0 0 T
1 0 1.2T
0 1 1.4T
1 1 1.6T
继续参考图1，脉冲产生电路100包括：周期调整模块102，接收第一振荡信号Osc1以及倍率选择信号fnAdjDlyx，并输出第二振荡信号Osc2，第二振荡信号Osc2的周期为第一振荡信号Osc1基于倍率选择信号fnAdjDlyx调整后的周期，倍率选择信号fnAdjDlyx为外部输入的选择指令，用于调整第二振荡信号Osc2的周期，即脉冲产生电路可通过外部输入的倍率选择信号fnAdjDlyx调整周期调整模块102生成的第二振荡信号Osc2的周期。
在一个例子中，可以利用第一振荡信号Osc1生成振荡调整信号OscT，然后根据倍率选择信号fnAdjDlyx选择第一振荡信号Osc1作为第二振荡信号Osc2输出，或选择振荡调整信号OscT作为第二振荡信号Osc2输出。也可以根据倍率选择信号fnAdjDlyx判断是否需要生成振荡调整信号OscT，即采用先判断再生成的方式，输出第二振荡信号Osc2。
参考图2，周期调整模块102包括：延时单元112，接收第一振荡信号Osc1，并基于第一振荡信号Osc1生成振荡调整信号OscT，振荡调整信号OscT的周期与第一振荡信号Osc1的周期不同；选择单元122，接收倍率选择信号 fnAdjDlyx，并基于倍率选择信号fnAdjDlyx选择第一振荡信号Osc1或振荡调整信号OscT作为第二振荡信号Osc2。
在一个例子中，参考图4，延时单元112包括：D触发器201，D触发器包括输入端D、时钟端Clk和ClkN、复位端RN和输出端Q，时钟端Clk和ClkN用于接收第一振荡信号Osc1和反相第一振荡信号Osc1N，复位端RN用于接收复位信号fnRasEn，输出端Q用于串联触发反相器202并连接至输入端D，且用于输出振荡调整信号OscT。本领域技术人员可知，此时输出的振荡调整信号OscT的周期是第一振荡信号Osc1周期的两倍。
参考图5，选择单元122包括倍率选择器203，倍率选择器203包括第一选择输入端、第二选择输入端、选择信号端和选择输出端，第一选择输入端用于接收第一振荡信号Osc1，第二选择输入端用于接收振荡调整信号OscT，选择信号端用于接收倍率选择信号fnAdjDlyx和反相倍率选择信号fnAdjDlyxN，选择输出端用于输出第二振荡信号Osc2，通过倍率选择信号fnAdjDlyx可以大幅度的改变振荡信号的周期。
此时，根据第一选择信号fnAdjDly1、第二选择信号fnAdjDly2和倍率选择信号fnAdjDlyx的不同生成的第二振荡信号Osc2的周期如表2所示：
表2 Osc2的周期表
fnAdjDlyx fnAdjDly1 fnAdjDly2 Osc2的周期
0 0 0 T
0 1 0 1.2T
0 0 1 1.4T
0 1 1 1.6T
1 0 0 2T
1 1 0 2.4T
1 0 1 2.8T
1 1 1 3.2T
在本实施例中，延时单元112包括E个串联的延时子单元，振荡调整信号OscT包括E个延时信号，E为正整数；第一级延时子单元，用于根据第一振荡信号Osc1生成第一延时信号Osc11，并将第一延时信号Osc11输入到第二级延时子单元中；第F级延时子单元，用于根据第F-1级延时信号Osc1F-1生成第F延时信号Osc1F，所述F为小于等于E，且大于等于2正整数。
具体地，第F级延时子单元包括：D触发器，D触发器包括输入端、时钟端和、复位端和输出端，时钟端和用于接收第F-1延时信号Osc1F-1和反相第F-1延时信号Osc1F-1N，复位端用于接收复位信号，输出端用于串联触发反相器并连接至输入端，且用于输出第F延时信号Osc1F。本领域技术人员可知，此时输出的第F延时信号Osc1F的周期是第F-1延时信号Osc1F-1周期的两倍。
参考图6，延时单元112包括3个串联的延时子单元，分别为第一级延时子单元221、第二级延时子单元223和第三级延时子单元225；其中，第一级延时子单元221用于根据第一振荡信号Osc1生成第一延时信号Osc11，第一延时信号Osc11的周期是第一振荡信号Osc1周期的两倍；第二级延时子单元223用于根据第一延时信号Osc11生成第二延时信号Osc12，第二延时信号Osc12的周期是第一延时信号Osc11周期的两倍；第三级延时子单元225用于根据第二延时信号Osc12生成第三延时信号Osc13，第三延时信号Osc13的周期是第二延时信号Osc12周期的两倍。
在一个例子中，选择单元122基于倍率选择信号fnAdjDlyx选择第一振荡信号Osc1或振荡调整信号OscT作为第二振荡信号Osc2，包括：基于倍率选择信号fnAdjDlyx选择第E-1延时信号Osc1E-1或第E延时信号Osc1E作为第二振荡信号Osc2。
在本实施例中，选择单元122基于倍率选择信号fnAdjDlyx选择第一振荡信号Osc1或振荡调整信号OscT作为第二振荡信号Osc2，包括：基于倍率选择信号fnAdjDlyx选择第二延时信号Osc12或第三延时信号Osc13作为第二振荡 信号Osc2。其中，第一级延时单元221和第二级延时子单元223用于扩大输出的第二振荡信号Osc2的周期。
此时根据第一选择信号fnAdjDly1、第二选择信号fnAdjDly2和倍率选择信号fnAdjDlyx的不同生成的第二振荡信号Osc2的周期如表3所示：
表3 Osc2的周期表
fnAdjDlyx fnAdjDly1 fnAdjDly2 Osc2的周期
0 0 0 4T
0 1 0 4.8T
0 0 1 5.6T
0 1 1 6.4T
1 0 0 8T
1 1 0 9.6T
1 0 1 11.2T
1 1 1 12.8T
在另一个例子中，选择单元122包括E个串联的选择子单元，倍率选择信号fnAdjDlyx包括对应于每个选择子单元的子倍率选择信号；第一级选择子单元，用于根据对应的子倍率选择信号，选择第一振荡信号Osc1或第一延时信号Osc11输入到第二级选择子单元中；第F级选择子单元，用于根据对应的子倍率选择信号，选择第F-1级选择子单元的输出信号或第F延时信号Osc1F输入到第F+1级选择子单元中；第E级选择子单元，用于根据对应的子倍率选择信号，选择第E-1级选择子单元的输出信号或振荡调整信号OscT作为第二振荡信号Osc2，F为小于E，且大于等于2的正整数。
具体地，第F级选择子单元包括：倍率选择器，倍率选择器包括第一选择输入端、第二选择输入端、选择信号端和选择输出端、第一选择端用于接收第F-1级选择子单元的输出信号，第二选择输入端用于接收第F延时信号Osc1F， 选择信号端用于接收对应的子倍率选择信号，选择输出端用于输出第F-1级选择子单元的输出信号或第F延时信号Osc1F。
参考图7，选择单元122包括3个串联的选择子单元，分别为第一级选择子单元227、第二级选择子单元228和第三级选择子单元229；其中，第一级选择子单元227用于选择第一振荡信号Osc1或第一延时信号Osc11输入到第二级选择子单元228，第二级选择子单元228用于选择第一级选择子单元227的输出信号或第二延时信号Osc12输入到第三级选择子单元229，第三级选择子单元229用于选择第二级选择子单元228的输出信号或第三延时信号Osc13作为振荡调整信号OscT。通过多个选择子单元的串联，实现了第二振荡信号Osc2周期更多的变化选择。
需要说明的是，在具体应用过程中，倍率选择信号fnAdjDlyx、第一选择信号fnAdjDly1和第二选择信号fnAdjDly2可以通过多位二进制数实现，即选择信号是一个多位二进制数，其中一位作为倍率选择信号fnAdjDlyx，一位作为第一选择信号fnAdjDly1，一位作为第二选择信号fnAdjDly2。
继续参考图1，脉冲产生电路100包括：脉冲转换模块103，接收第二振荡信号Osc2，并输出脉冲信号OscClk，脉冲信号OscClk的脉冲基于第二振荡信号的上升沿或下降沿产生，且脉冲信号OscClk的脉冲周期与第二振荡信号的振荡周期相同。
具体地，参考图2，脉冲转换模块103包括：脉冲转换器113，用于接收第二振荡信号Osc2，且基于第二振荡信号Osc2生成脉冲信号OscClk。
在一个例子中，当脉冲转换器113检测到第二振荡信号Osc2的上升沿后输出一个向上的窄脉冲，脉冲转换器113的输出端还可以通过串联反相器，以输出一个向下的窄脉冲。在另一个例子中，当脉冲转换器113检测到第二振荡信号Osc2的上升沿后输出一个向下的窄脉冲，脉冲转换器113的输出端还可以通过串联反相器，以输出一个向上的窄脉冲。另外，本实施例中脉冲转换器113是基于第二振荡信号Osc2的上升沿工作，在其他实施例中，脉冲转换器还可以基于第二振荡信号的下降沿工作。
需要注意的是，此处描述的“基于第二振荡信号Osc2生成脉冲信号OscClk”中，“基于”的含义包括但不限定于：检测到第二振荡信号Osc2的上升沿，或者检测到第二振荡信号Osc2由低电平变为高电平(高电平变为低电平)后产生脉冲信号OscClk的窄脉冲。
需要说明的是，在本实施例中，脉冲信号OscClk是基于第二振荡信号Osc2的上升沿产生，在其他实施例中，脉冲信号还可以根据第二振荡信号的下降沿产生。
参考图8，在控制信号RasEn为有效电平期间，振荡模块101产生周期为T的第一振荡信号Osc1，周期调整模块102根据倍率选择信号fnAdjDlyx调整第二振荡信号Osc2(Osc2′)的周期。
具体地，若在控制信号RasEn为有效电平期间改变倍率选择信号fnAdjDlyx，此时产生的第二振荡信号Osc2存在周期变化，假设由周期T变为周期2T，此时产生的脉冲信号OscClk中脉冲周期也由周期T变为周期2T；若在控制信号RasEn为有效电平之前改变倍率选择信号fnAdjDlyx，此时产生的第二振荡信号Osc2′不存在周期变化，产生的脉冲信号OscClk′中脉冲周期也不存在脉冲周期的变化。
相对于相关技术而言，根据控制信号产生第一振荡信号，即控制信号在处于有效电平时，产生周期一定的第一振荡信号；根据倍率选择信号，基于第一振荡信号产生第二振荡信号，即基于倍率选择信号，改变第一振荡信号的周期，以产生相应的第二振荡信号；然后将第二振荡信号作为信号源产生脉冲信号，产生的脉冲信号的脉冲周期与第二振荡信号的振荡周期相同；在产生脉冲信号的过程中，若倍率选择信号改变，调整第一振荡信号的周期的幅度改变，以使产生的第二振荡信号的周期变化，从而产生周期可调整的脉冲信号。
值得一提的是，本实施例中所涉及到的各单元均为逻辑单元，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这 并不表明本实施例中不存在其它的单元。
本申请另一实施例涉及一种交错脉冲产生电路，包括：信号产生模块，用于根据激活信号生成第一控制信号和第二控制信号，第一控制信号与第二控制信号为反相信号；第一脉冲产生单元，包括上述的脉冲产生电路，第一脉冲产生单元用于根据第一控制信号生成第一脉冲信号；第二脉冲产生单元，包括上述的脉冲产生电路，第二脉冲产生单元用于根据第二控制信号生成第二脉冲信号；第一脉冲信号与第二脉冲信号为交错脉冲信号。
图9和图10为本实施例提供的交错脉冲产生电路的结构示意图；图11为本实施例提供的信号产生模块的具体电路示意图；图12为本实施例提供的交错脉冲产生电路中信号的时序示意图；以下将结合附图对本实施例提供的交错脉冲产生电路进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
参考图9，交错脉冲产生电路300，包括：信号产生模块303，用于根据激活信号Active生成第一控制信号ActEn和第二控制信号PreEn，第一控制信号ActEn和第二控制信号PreEn为反相信号。其中，激活信号Active即外部输入的激活指令，信号产生模块303用于根据外部激活指令生成互为反相信号的第一控制信号ActEn和第二控制信号PreEn。
具体地，参考图10，信号产生模块303包括：
复位单元313，接收第一复位信号fnActEn以及激活信号Active，并基于第一复位信号fnActEn和激活信号Active生成第一控制信号ActEn。
第一复位信号fnActEn即外部输入的复位指令，用于对复位单元313进行复位；具体地，当复位单元313复位后，若复位单元313接收的激活信号Active为有效电平，复位单元313产生第一控制信号ActEn。
反向单元323，接收第一控制信号ActEn，并基于第一控制信号ActEn生成第二控制信号PreEn。
在本实施例中，信号产生模块303还包括：复位信号产生单元333，用于根据第一复位信号fnActEn和第一控制信号ActEn生成第二复位信号fnPreEn， 以使当第一复位信号fnActEn为复位状态时，第二复位信号fnPreEn也处于复位状态，当第一复位信号fnActEn为非复位状态时，第二复位信号fnPreEn基于第一控制信号ActEn的变化沿产生复位窄脉冲。
在本实施例中，信号产生模块303还包括：选择信号产生单元343，用于接收选择信号fnAdjDly，并基于选择信号fnAdjDly生成选择信号组，选择信号组包括选择信号fnAdjDly和反相选择信号fnAdjDlyN，选择信号fnAdjDly与反相选择信号fnAdjDlyN为反相信号。
需要说明的是，在本实施例中选择信号fnAdjDly包括用于调控脉冲产生电路100的倍率选择信号fnAdjDlyx、第一选择信号fnAdjDly1和第二选择信号fnAdjDly2。
在一个例子中，参考图11，复位单元313包括复位与非门403和复位反相器404，复位反相器404连接复位与非门403的输出端，复位与非门403用于接接收第一复位信号fnActEn和激活信号Active。
反向单元323包括连接复位单元313的输出反相器405，用于根据第一控制信号ActEn生成第二控制信号PreEn。
复位信号产生单元333包括脉冲转换装置406，用于检测第一控制信号ActEn的变化沿(如上升沿)，产生脉冲控制信号；输出与非门407和输出反相器408，输出与非门407还用于接收第一复位信号fnActEn，此时输出反相器408输出第二复位信号fnPreEn。
选择信号产生单元343包括：串联的第一选择反相器401和第二选择反相器402，第一选择反相器401的输出端连接第二选择反相器402的输入端，用于根据选择信号fnAdjDly生成选择信号组。
继续参考图9，交错脉冲产生电路300，还包括：第一脉冲产生单元301和第二脉冲产生单元302；第一脉冲产生单元301，包括上述脉冲产生电路100，第一脉冲产生单元301用于根据第一控制信号ActEn生成第一脉冲信号ActClk；第二脉冲产生单元302，包括上述脉冲产生电路100，第二脉冲产生单元302用于根据第二控制信号PreEn生成第二脉冲信号PreClk；第一脉冲信号ActClk 与第二脉冲信号PreClk为交错脉冲信号，交错脉冲信号即根据反相的信号(第一控制信号ActEn和第二控制信号PreEn)产生的脉冲信号(第一脉冲信号ActClk和第二脉冲信号PreClk)。
参考图10，交错脉冲产生电路300用于接收外部输入的激活信号Active，信号产生模块303用于根据外部输入的激活信号Active产生第一控制信号ActEn和第二控制信号PreEn，第一控制信号ActEn和第二控制信号PreEn为反相信号。
具体地，参考图12，当激活信号Active为有效电平时，产生的第一控制信号ActEn为有效电平；第一脉冲产生单元301用于根据第一控制信号ActEn产生周期为T第一振荡信号Osc1和周期为2T的第二振荡信号Osc2；在本实施例中，第二振荡信号Osc2与第一振荡信号Osc1的周期一致，第一脉冲信号ActClk基于第二振荡信号Osc2的上升沿产生。第二脉冲产生单元302用于格局第二控制信号PreEn产生周期为T的第一振荡信号Osc1〃和周期为2T的第二振荡信号Osc2〃；在本实施例中，第二振荡信号Osc2〃与第一振荡信号Osc1〃的周期一致，第二脉冲信号PreClk基于第二振荡信号Osc2〃的上升沿产生。此时产生的第一脉冲信号ActClk与第二脉冲信号PreClk为交错脉冲信号。
与相关技术相比，用于根据激活信号产生第一控制信号和第二控制信号，第一控制信号和第二控制信号互为反相信号；根据反相控制信号产生的第一脉冲信号和第二脉冲信号为交错脉冲信号，即第一脉冲信号处于脉冲期间第二脉冲信号为无效电平；第二脉冲信号处于脉冲期间，第一脉冲信号为无效电平，且产生的第一脉冲信号和第二脉冲信号的周期可调整，即产生周期可调整的脉冲信号，且电路涉及的器件较少，电路版图的面积小，电路的功耗低。
值得一提的是，本实施例中所涉及到的各单元均为逻辑单元，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。
工业实用性
本申请实施例中，脉冲产生电路，包括：振荡模块，接收控制信号，且根据控制信号生成第一振荡信号；周期调整模块，接收第一振荡信号以及倍率选择信号，并输出第二振荡信号，第二振荡信号的周期为第一振荡信号基于倍率选择信号调整后的周期；脉冲转换模块，接收第二振荡信号，并输出脉冲信号，脉冲信号的脉冲基于第二振荡信号的上升沿或下降沿产生，且脉冲信号的脉冲周期与第二振荡信号的振荡周期相同。这样，本申请实施例以产生周期可调整的脉冲信号，且电路版图的面积小，电路的功耗小。

Claims (20)

  1. 一种脉冲产生电路，包括：
    振荡模块，接收控制信号，且根据所述控制信号生成第一振荡信号；
    周期调整模块，接收所述第一振荡信号以及倍率选择信号，并输出第二振荡信号，所述第二振荡信号的周期为所述第一振荡信号基于所述倍率选择信号调整后的周期；
    脉冲转换模块，接收所述第二振荡信号，并输出脉冲信号，所述脉冲信号的脉冲基于所述第二振荡信号的上升沿或下降沿产生，且所述脉冲信号的脉冲周期与所述第二振荡信号的振荡周期相同。
  2. 根据权利要求1所述的脉冲产生电路，其中，所述周期调整模块包括：
    延时单元，接收所述第一振荡信号，并基于所述第一振荡信号生成振荡调整信号，所述振荡调整信号的周期与所述第一振荡信号的周期不同；
    选择单元，接收所述倍率选择信号，并基于所述倍率选择信号选择所述第一振荡信号或所述振荡调整信号作为所述第二振荡信号。
  3. 根据权利要求2所述的脉冲产生电路，其中，所述延时单元包括：D触发器，所述D触发器包括输入端、时钟端、复位端和输出端，所述时钟端用于接收所述第一振荡信号，所述复位端用于接收复位信号，所述输出端用于串联触发反相器并连接至所述输入端，且用于输出所述振荡调整信号。
  4. 根据权利要求2所述的脉冲产生电路，其中，所述选择单元包括：倍率选择器，所述倍率选择器包括第一选择输入端、第二选择输入端、选择信号端和选择输出端，所述第一选择输入端用于接收所述第一振荡信号，所述第二选择输入端用于接收所述振荡调整信号，所述选择信号端用于接收所述倍率选择信号，所述选择输出端用于输出所述第二振荡信号。
  5. 根据权利要求2所述的脉冲产生电路，其中，所述延时单元包括E个串联的延时子单元，所述振荡调整信号包括E个延时信号，所述E为正整数；
    第一级延时子单元，用于根据所述第一振荡信号生成第一延时信号，并将 第一延时信号输入到第二级延时子单元中；
    第F级延时子单元，用于根据第F-1延时信号生成第F延时信号，所述F为小于等于所述E，且大于等于2的正整数。
  6. 根据权利要求5所述的脉冲产生电路，其中，所述选择单元基于所述倍率选择信号选择所述第一振荡信号或所述振荡调整信号作为所述第二振荡信号，包括：基于所述倍率选择信号，选择第E-1延时信号或第E延时信号作为所述第二振荡信号。
  7. 根据权利要求5所述的脉冲产生电路，其中，所述第F级延时子单元包括：D触发器，所述D触发器包括输入端、时钟端、复位端和输出端，所述时钟端用于接收所述第F-1延时信号，所述复位端用于接收复位信号，所述输出端用于串联触发反相器并连接至输入端，且用于输出第F级延时信号。
  8. 根据权利要求5所述的脉冲产生电路，其中，所述选择单元包括E个串联的选择子单元，所述倍率选择信号包括对应于每个所述选择子单元的子倍率选择信号；
    第一级选择子单元，用于根据对应的子倍率选择信号，选择第一振荡信号或第一延时信号输入到第二级选择子单元中；
    第F级选择子单元，用于根据对应的子倍率选择信号，选择第F-1级选择子单元的输出信号或所述第F延时信号输入到第F+1级选择子单元中；
    第E级选择子单元，用于根据对应的子倍率选择信号，选择第E-1级选择子单元的输出信号或所述振荡调整信号作为所述第二振荡信号，所述F为小于所述E，且大于等于2的正整数。
  9. 根据权利要求8所述的脉冲产生电路，其中，所述第F级选择子单元包括：倍率选择器，所述倍率选择器包括第一选择输入端、第二选择输入端、选择信号端和选择输出端，所述第一选择输入端用于接收所述第F-1级选择子单元的输出信号，所述第二选择输入端用于接收所述第F延时信号，所述选择信号端用于接收对应的子倍率选择信号，所述选择输出端用于输出所述第F-1级选择子单元的输出信号或所述第F延时信号。
  10. 根据权利要求1所述的脉冲产生电路，其中，所述振荡模块包括：
    振荡单元以及连接在所述振荡单元中的触发单元；
    所述触发单元，用于接收复位信号以及所述控制信号，并基于所述复位信号和所述控制信号触发所述振荡单元；
    所述振荡单元触发后，根据所述控制信号生成所述第一振荡信号。
  11. 根据权利要求10所述的脉冲产生电路，其中，所述振荡单元包括：A个反相器串联形成的环形振荡器，所述A为正奇数。
  12. 根据权利要求11所述的脉冲产生电路，其中，所述触发单元包括：
    第一与非门和第二与非门，所述第一与非门的输出端连接至所述第二与非门的一输入端；
    所述第一与非门的一输入端和所述第二与非门的输出端用于接入所述环形振荡器；
    所述第一与非门与所述第二与非门中，其中一者用于接收所述控制信号，另一者用于接收复位信号。
  13. 根据权利要求12所述的脉冲产生电路，其中，所述振荡模块还包括：
    第一反相器组，包括串联的B个反相器，所述B为正偶数；
    第一选择单元，用于接收第一选择信号，并基于所述第一选择信号，将所述第一反相器组串接在所述环形振荡器中的相邻反相器之间。
  14. 根据权利要求13所述的脉冲产生电路，其中，所述振荡模块还包括：
    第二反相器组，包括串联的C个反相器，所述C为正偶数；
    第二选择单元，用于接收第二选择信号，并基于所述第二选择信号，将所述第二反相器组串接在所述环形振荡器中的相邻反相器之间。
  15. 根据权利要求1所述的脉冲产生电路，其中，所述脉冲转换模块包括：脉冲转换器，用于接收所述第二振荡信号，且基于所述第二振荡信号生成所述脉冲信号。
  16. 一种交错脉冲产生电路，包括：
    信号产生模块，用于根据激活信号生成第一控制信号和第二控制信号，所 述第一控制信号与所述第二控制信号为反相信号；
    第一脉冲产生单元，包括权利要求1～15任一项所述的脉冲产生电路，所述第一脉冲产生单元用于根据所述第一控制信号生成第一脉冲信号；
    第二脉冲产生单元，包括权利要求1～15任一项所述的脉冲产生电路，所述第二脉冲产生单元用于根据所述第二控制信号生成第二脉冲信号；
    所述第一脉冲信号与所述第二脉冲信号为交错脉冲信号。
  17. 根据权利要求16所述的交错脉冲产生电路，其中，所述信号产生模块包括：
    复位单元，接收第一复位信号以及所述激活信号，并基于所述第一复位信号和所述激活信号生成所述第一控制信号；
    反向单元，接收所述第一控制信号，并基于所述第一控制信号生成所述第二控制信号。
  18. 根据权利要求17所述的交错脉冲产生电路，其中，所述复位单元包括：复位与非门和复位反相器，所述复位反相器连接所述复位与非门的输出端，所述复位与非门用于接收所述第一复位信号和所述激活信号。
  19. 根据权利要求17所述的交错脉冲产生电路，其中，所述信号产生模块还包括：复位信号产生单元，用于根据所述第一复位信号和所述第一控制信号生成第二复位信号，以使当所述第一复位信号为复位状态时，所述第二复位信号也处于复位状态，当所述第一复位信号为非复位状态时，所述第二复位信号基于第一控制信号的变化沿产生复位窄脉冲。
  20. 根据权利要求16所述的交错脉冲产生电路，其中，所述信号产生模块还包括：选择信号产生单元，用于接收选择信号，并基于所述选择信号生成选择信号组；
    所述选择信号组包括所述选择信号和反相选择信号，所述选择信号与所述反相选择信号为反相信号。
PCT/CN2021/112004 2021-03-09 2021-08-11 脉冲产生电路和交错脉冲产生电路 WO2022188353A1 (zh)

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CN102148614A (zh) * 2010-02-10 2011-08-10 上海宏力半导体制造有限公司 脉冲产生电路及方法、基准电压产生及其推动电路及方法
CN207475510U (zh) * 2016-02-25 2018-06-08 深圳市华盛昌科技实业股份有限公司 一种脉冲产生装置
CN110995207A (zh) * 2019-12-05 2020-04-10 北京东方计量测试研究所 一种高斯脉冲信号发生器及信号发生方法
CN111277252A (zh) * 2018-12-04 2020-06-12 德克萨斯仪器股份有限公司 脉宽调制(pwm)脉冲的产生
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CN102148614A (zh) * 2010-02-10 2011-08-10 上海宏力半导体制造有限公司 脉冲产生电路及方法、基准电压产生及其推动电路及方法
CN207475510U (zh) * 2016-02-25 2018-06-08 深圳市华盛昌科技实业股份有限公司 一种脉冲产生装置
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