WO2022188354A1 - 交错信号产生电路 - Google Patents

交错信号产生电路 Download PDF

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Publication number
WO2022188354A1
WO2022188354A1 PCT/CN2021/112026 CN2021112026W WO2022188354A1 WO 2022188354 A1 WO2022188354 A1 WO 2022188354A1 CN 2021112026 W CN2021112026 W CN 2021112026W WO 2022188354 A1 WO2022188354 A1 WO 2022188354A1
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Prior art keywords
signal
pulse
delay
oscillation
output
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PCT/CN2021/112026
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English (en)
French (fr)
Inventor
王佳
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21929821.3A priority Critical patent/EP4203319A1/en
Priority to US17/666,750 priority patent/US11569803B2/en
Publication of WO2022188354A1 publication Critical patent/WO2022188354A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation

Definitions

  • the embodiments of the present application relate to, but are not limited to, an interleaved signal generating circuit.
  • staggered signals are often used, and staggered signals refer to signals generated by a fixed delay at each interval.
  • the clock signal is usually used to generate equidistant interlaced signals; for asynchronous signals, the required equidistant interlaced signals are generated by inserting delay cells, and the delay between the signals can be based on requirements. Insert the corresponding delay unit implementation.
  • An embodiment of the present application provides an interleaved signal generation circuit, including: an interleaved pulse generation circuit, configured to generate a first pulse signal according to a first control signal, and generate a second pulse signal according to the second control signal, the first control signal and the The second control signal is an inverted signal, and the first pulse signal and the second pulse signal are interleaved pulse signals;
  • the delay signal output circuit includes G signal output circuits, where G is an integer greater than or equal to 2, and the signal output circuit is used for receiving The input signal, the first pulse signal and the second pulse signal, and output the delayed output signal; wherein, the non-first-stage signal output circuits all receive the delayed output signal output by the previous-stage signal output circuit as the input of the current-stage signal output circuit signal, the first-stage signal output circuit receives the initial input signal as the input signal of the first-stage signal output circuit; the rising edge of the delayed output signal generated by the signal output circuit and the received delayed output output by the previous-stage signal output circuit The rising edge of the signal or the initial input
  • FIG. 1 and FIG. 2 are schematic structural diagrams of an interleaved pulse generating circuit provided by an embodiment of the application;
  • FIG. 3 is a schematic diagram of a specific circuit of a signal generating module provided by an embodiment of the present application.
  • FIG. 4 and FIG. 5 are schematic structural diagrams of a pulse generating circuit provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a specific circuit of an oscillation module provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a delay unit provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a selection unit provided by an embodiment of the present application.
  • 9 and 10 are schematic circuit diagrams of a period adjustment module provided by an embodiment of the application.
  • FIG. 11 is a schematic time sequence diagram of signals in a pulse generating circuit provided by an embodiment of the present application.
  • FIG. 12 is a schematic timing diagram of signals in an interleaved pulse generating circuit provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a signal output circuit provided by an embodiment of the application.
  • FIG. 14 is a schematic diagram of a specific circuit of a first control module provided by an embodiment of the present application.
  • 15 is a schematic diagram of a specific circuit of a second control module provided by an embodiment of the present application.
  • 16 is a schematic structural diagram of a signal output module provided by an embodiment of the application.
  • 17 and 18 are specific circuit schematic diagrams of a signal output module provided by an embodiment of the application.
  • 19 is a schematic time sequence diagram of a signal in a signal output circuit provided by an embodiment of the application.
  • 20 and 21 are schematic structural diagrams of a delay signal output circuit provided by an embodiment of the application.
  • 22 is a schematic diagram of a specific circuit of a delay signal output circuit provided by an embodiment of the present application.
  • 23 is a schematic diagram of a specific circuit of a signal output circuit in a delayed signal output circuit provided by an embodiment of the present application.
  • FIG. 24 is a schematic time sequence diagram of signals in the delayed signal output circuit provided by the embodiment of the present application.
  • the synchronous signal is used to generate the equidistant staggered signal.
  • the delay between the equidistant staggered signals must be an integer multiple of the clock period, and the controllability of the delay between the equidistant staggered signals is poor; the asynchronous signal is used to generate the equidistantly staggered signal. , although the delay between the signals is controllable, it will significantly increase the area of the circuit layout formed and the power consumption of the circuit.
  • an embodiment of the present application provides an interleaved signal generation circuit, including: an interleaved pulse generation circuit configured to generate a first pulse signal according to a first control signal, and generate a second pulse signal according to the second control signal, The first control signal and the second control signal are inverted signals, and the first pulse signal and the second pulse signal are interleaved pulse signals;
  • the delay signal output circuit includes G signal output circuits, where G is an integer greater than or equal to 2, the signal The output circuit is used to receive the input signal, the first pulse signal and the second pulse signal, and output the delayed output signal; wherein, the non-first stage signal output circuits all receive the delayed output signal output by the previous stage signal output circuit as the current stage
  • the input signal of the signal output circuit, the first-stage signal output circuit receives the initial input signal as the input signal of the first-stage signal output circuit; the rising edge of the delayed output signal generated by the signal output circuit is different from the received signal output circuit of the previous stage.
  • the output delay output signal or the rising edge of the initial input signal has a first delay; the falling edge of the delay output signal generated by the signal output circuit is the same as the received delay output signal output by the previous stage signal output circuit or The falling edge of the initial input signal has a second delay.
  • FIG. 1 and FIG. 2 are schematic structural diagrams of an interleaved pulse generating circuit provided by an embodiment of the present application
  • FIG. 3 is a specific circuit schematic diagram of a signal generating module provided by an embodiment of the present application
  • FIG. 4 and FIG. A schematic diagram of the structure of the generation circuit
  • FIG. 6 is a schematic diagram of a specific circuit of an oscillation module provided by an embodiment of the present application
  • FIG. 7 is a schematic structural diagram of a delay unit provided by an embodiment of the present application
  • FIG. 8 is a schematic diagram of a selection unit provided by an embodiment of the present application. Schematic diagram of the structure.
  • Figure 13 is a schematic structural diagram of a signal output circuit provided by an embodiment of the present application
  • Figure 14 is a schematic schematic diagram of a specific circuit of a first control module provided by an embodiment of the present application
  • Figure 15 is an embodiment of the present application.
  • the specific circuit schematic diagram of the second control module provided FIG. 16 is a schematic structural diagram of the signal output module provided by the embodiment of the application
  • FIG. 17 and FIG. 18 are the specific circuit schematic diagrams of the signal output module provided by the embodiment of the application
  • FIG. 19 is 20 and 21 are schematic structural diagrams of the delayed signal output circuit provided by the embodiment of the present application
  • FIG. 22 is the delayed signal output circuit provided by the embodiment of the present application.
  • FIG. 23 is a schematic diagram of a specific circuit of a signal output circuit in the delay signal output circuit provided by this embodiment
  • FIG. 24 is a schematic diagram of a timing sequence of a signal in the delayed signal output circuit provided by the embodiment of the present application. The figure further illustrates the interleaved signal generating circuit provided in this embodiment in detail.
  • Interleaved signal generation circuit including:
  • the interleaved pulse generating circuit is configured to generate the first pulse signal ActClk according to the first control signal ActEn, and generate the second pulse signal PreClk according to the second control signal PreEn, the first control signal ActEn and the second control signal PreEn are inverted signals,
  • the first pulse signal ActClk and the second pulse signal PreClk are interleaved pulse signals.
  • the interleaved pulse signal in this embodiment refers to the pulse signal (the first pulse signal ActClk and the second pulse signal PreClk) generated according to the inverted signals (the first control signal ActEn and the second control signal PreEn).
  • the pulse signal is valid respectively during the period.
  • the delay signal output circuit includes G signal output circuits, G is an integer greater than or equal to 2, the signal output circuit is used to receive the input signal, the first pulse signal ActClk and the second pulse signal PreClk, and output the delay output signal.
  • the non-first-stage signal output circuits all receive the delayed output signal output by the previous-stage signal output circuit as the input signal of the current-stage signal output circuit, and the first-stage signal output circuit receives the initial input signal as the first-stage signal output circuit.
  • the rising edge of the delayed output signal generated by the signal output circuit has a first delay with the rising edge of the delayed output signal output by the received signal output circuit of the previous stage; the delayed output signal generated by the signal output circuit
  • the falling edge of , and the falling edge of the received delayed output signal output by the previous stage signal output circuit have a second delay.
  • the pulse period of the first pulse signal ActClk is t1
  • the pulse period of the second pulse signal PreClk is t2
  • the pulse period of the first pulse signal ActClk is equal to the pulse period of the second pulse signal PreClk; in other implementations
  • the pulse periods of the first pulse signal and the second pulse signal may be different.
  • the interleaved pulse generating circuit 300 includes: a signal generating module 303 for generating a first control signal ActEn and a second control signal PreEn according to the activation signal Active, the first control signal ActEn and the second control signal PreEn for the inverted signal.
  • the activation signal Active is an activation command input from the outside, and the signal generating module 303 is configured to generate the first control signal ActEn and the second control signal PreEn which are mutually inverse signals according to the external activation command.
  • the signal generating module 303 includes:
  • the reset unit 313 receives the first reset signal fnActEn and the activation signal Active, and generates the first control signal ActEn based on the first reset signal fnActEn and the activation signal Active.
  • the first reset signal fnActEn is an externally input reset command, which is used to reset the reset unit 313; specifically, after the reset unit 313 is reset, if the activation signal Active received by the reset unit 313 is an active level, the reset unit 313 generates the first reset signal.
  • the inversion unit 323 receives the first control signal ActEn, and generates the second control signal PreEn based on the first control signal ActEn.
  • the signal generating module 303 further includes: a reset signal generating unit 333 for generating the second reset signal fnPreEn according to the first reset signal fnActEn and the first control signal ActEn, so that when the first reset signal fnActEn is reset When the second reset signal fnPreEn is in the reset state, when the first reset signal fnActEn is in the non-reset state, the second reset signal fnPreEn generates a reset narrow pulse based on the changing edge of the first control signal ActEn.
  • the signal generation module 303 further includes: a selection signal generation unit 343, configured to receive the selection signal fnAdjDly, and generate a selection signal group based on the selection signal fnAdjDly, the selection signal group includes the selection signal fnAdjDly and the inverted selection signal fnAdjDlyN, The selection signal fnAdjDly and the inversion selection signal fnAdjDlyN are inversion signals.
  • the selection signal fnAdjDly includes the rate selection signal fnAdjDlyx, the first selection signal fnAdjDly1 and the second selection signal fnAdjDly2 for regulating the pulse generating circuit 100 .
  • the reset unit 313 includes a reset NAND gate 403 and a reset inverter 404, the reset inverter 404 is connected to the output terminal of the reset NAND gate 403, and the reset NAND gate 403 is used to receive the first The reset signal fnActEn and the activation signal Active.
  • the inversion unit 323 includes an output inverter 405 connected to the reset unit 313 for generating the second control signal PreEn according to the first control signal ActEn.
  • the reset signal generation unit 333 includes a pulse conversion device 406 for detecting the changing edge (such as a rising edge) of the first control signal ActEn to generate a pulse control signal; an output NAND gate 407 and an output inverter 408 are used to output a NAND gate 407 It is also used to receive the first reset signal fnActEn, and at this time, the output inverter 408 outputs the second reset signal fnPreEn.
  • a pulse conversion device 406 for detecting the changing edge (such as a rising edge) of the first control signal ActEn to generate a pulse control signal
  • an output NAND gate 407 and an output inverter 408 are used to output a NAND gate 407 It is also used to receive the first reset signal fnActEn, and at this time, the output inverter 408 outputs the second reset signal fnPreEn.
  • the selection signal generating unit 343 includes: a first selection inverter 401 and a second selection inverter 402 connected in series, the output end of the first selection inverter 401 is connected to the input end of the second selection inverter 402, and is used for according to The selection signal fnAdjDly generates a selection signal group.
  • the interleaved pulse generation circuit 300 further includes: a first pulse generation unit 301 and a second pulse generation unit 302; the first pulse generation unit 301 specifically includes a pulse generation circuit for generating the first pulse according to the first control signal ActEn.
  • the second pulse generating unit 302 and the first pulse generating unit 301 have the same circuit structure.
  • This embodiment is introduced by the pulse generating circuit 100 of the first pulse generating unit 301, wherein the first control signal ActEn and the second control signal PreEn belong to the control signal RasEn; the first reset signal fnActEn and the second reset signal fnPreEn belong to the reset signal fnRasEn.
  • the first pulse generating unit 301 includes a pulse unit circuit 100, including: an oscillation module 101, receiving the control signal RasEn, and generating the first oscillation signal Osc1 according to the control signal RasEn; specifically, when the control signal RasEn is at an active level , the oscillation module 101 generates the first oscillation signal Osc1 ; in this embodiment, it is assumed that the period of the first oscillation signal Osc1 is T.
  • the oscillation module 101 starts to oscillate to generate the first oscillation signal Osc1 .
  • the oscillation module 101 includes an oscillation unit 111 and a trigger unit 121 connected to the oscillation unit 111; the trigger unit 121 is configured to receive the reset signal fnRasEn and the control signal RasEn, and trigger based on the reset signal fnRasEn and the control signal RasEn Oscillation unit 111; after the oscillation unit 111 is triggered, a first oscillation signal Osc1 is generated according to the control signal RasEn.
  • the meaning of “based on” includes but is not limited to: when the reset signal fnRasEn is in a non-reset state, and the control signal RasEn is Active level, the triggering unit 121 triggers the oscillating unit 111 .
  • the reset signal fnRasEn is an externally input reset command, which is used to reset the trigger unit 121; specifically, after the trigger unit 121 is reset, if the control signal RasEn received by the trigger unit 121 is a valid level, the trigger unit 121 triggers the oscillation unit 111 , so that the oscillation unit 111 generates the first oscillation signal Osc1.
  • the oscillation unit 111 includes a ring oscillator formed by A inverters connected in series, A is a positive odd number; A can be 5, 7, 9, 11, etc.
  • A 7, that is, a ring oscillator formed by 7 inverters connected in series is used as an example for illustration, which does not constitute a limitation to this embodiment.
  • the number of inverters in the ring oscillator can be selected according to actual needs.
  • the trigger unit 121 includes a first NAND gate 211 and a second NAND gate 212 , an output end of the first NAND gate 211 is connected to an input end of the second NAND gate 212 , and an input end of the first NAND gate 211 And the output terminal of the second NAND gate 212 is used to access the ring oscillator; among the first NAND gate 211 and the second NAND gate 212, one of them is used to receive the control signal RasEn, and the other is used to receive the reset signal fnRasEn; it should be noted that the given first NAND gate 211 in FIG.
  • the second NAND gate 212 is used to receive the reset signal fnRasEn, which does not constitute a limitation to this embodiment.
  • the second NAND gate may also be used to receive the control signal, and the first NAND gate to receive the reset signal.
  • the first inverter can be selected according to actual needs The number of inverters in group 215.
  • the first selection unit (not shown) is used for receiving the first selection signal fnAdjDly1, and based on the first selection signal fnAdjDly1, the first inverter group 215 is connected in series between adjacent inverters in the ring oscillator .
  • the purpose of B number of inverters in the first inverter group 215 is to ensure that the total number of inverters in the ring oscillator is an odd number; specifically, the first selection unit (not shown) includes a first The selector 214 is used for gating the first branch or the second branch according to the first selection signal fnAdjDly1 and the inverted first selection signal fnAdjDly1N; wherein, the first branch is used as the connection of adjacent inverters in the ring oscillator circuit, the second branch connects the first inverter group 215 in series to the connection circuit of the adjacent inverters of the ring oscillator; the purpose of connecting the first inverter group 215 to the ring oscillator is to increase the ring oscillation The number of inverters in the inverter is increased, thereby increasing the period of the first oscillation signal Osc1 generated by the oscillation unit 111 .
  • the signal Osc1 is 1.2T; since the first inverter group 215 is connected to the ring oscillator through the control of the first selection signal fnAdjDly1, the first oscillation signal Osc1 generated by the oscillation unit 111 can be adjusted by the externally input first selection signal fnAdjDly1 cycle.
  • the second inverter can be selected according to actual needs The number of inverters in group 217.
  • the second selection unit (not shown) is configured to receive the second selection signal fnAdjDly2, and based on the second selection signal fnAdjDly2, connect the second inverter group 217 in series between adjacent inverters in the ring oscillator .
  • the purpose of the number of inverters in the second inverter group 217 is to ensure that the total number of inverters in the ring oscillator is an odd number; specifically, the second selection unit (not shown) includes a second The selector 216 is used for gating the third branch or the fourth branch according to the second selection signal fnAdjDly2 and the inverted second selection signal fnAdjDly2N; wherein, the third branch is used as the connection of adjacent inverters in the ring oscillator circuit, the fourth branch connects the second inverter group 217 in series to the connection circuit of the adjacent inverters of the ring oscillator; the purpose of connecting the second inverter group 217 to the ring oscillator is to increase the ring oscillation The number of inverters in the inverter is increased, thereby increasing the period of the first oscillation signal Osc1 generated by the oscillation unit 111.
  • the The signal Osc1 is 1.4T; since the access of the second inverter group 217 to the ring oscillator is controlled by the second selection signal fnAdjDly2, the first oscillation signal Osc1 generated by the oscillation unit 111 can be adjusted by the externally input second selection signal fnAdjDly2 cycle.
  • B and C can be set to any positive even numbers, and in specific applications, the values of B and C can be reasonably set according to the required change of the first oscillation signal Osc1 generated by the oscillation unit 111 ; in addition, in this embodiment, The implementation of the two inverter groups is described, and the implementation scheme of adding the third inverter group and the fourth inverter group on the basis of this embodiment should all belong to the protection scope of the present application.
  • the period of the first oscillation signal Osc1 can be changed with different amplitudes; at this time, according to the first selection signal fnAdjDly1 and the second
  • the periodic table 1 of the first oscillation signal Osc1 generated by the different selection signal fnAdjDly2 is shown in:
  • the pulse generation circuit 100 includes: a period adjustment module 102 that receives the first oscillation signal Osc1 and the magnification selection signal fnAdjDlyx, and outputs a second oscillation signal Osc2 whose period is based on the first oscillation signal Osc1
  • the period after the adjustment of the magnification selection signal fnAdjDlyx, the magnification selection signal fnAdjDlyx is an externally input selection command, which is used to adjust the period of the second oscillation signal Osc2, that is, the pulse generation circuit can be adjusted by the externally input magnification selection signal fnAdjDlyx
  • the period adjustment module 102 generates The period of the second oscillation signal Osc2.
  • the oscillation adjustment signal OscT may be generated by using the first oscillation signal Osc1, and then the first oscillation signal Osc1 may be selected as the second oscillation signal Osc2 for output according to the magnification selection signal fnAdjDlyx, or the oscillation adjustment signal OscT may be selected as the second oscillation signal Osc2 output. It is also possible to determine whether the oscillation adjustment signal OscT needs to be generated according to the magnification selection signal fnAdjDlyx, that is, the second oscillation signal Osc2 is output in a manner of determining first and then generating.
  • the period adjustment module 102 includes: a delay unit 112 that receives the first oscillation signal Osc1 and generates an oscillation adjustment signal OscT based on the first oscillation signal Osc1 , and the period of the oscillation adjustment signal OscT is different from that of the first oscillation signal Osc1
  • the selection unit 122 receives the magnification selection signal fnAdjDlyx, and selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx.
  • the delay unit 112 includes: a D flip-flop 201, the D flip-flop includes an input terminal D, clock terminals Clk and ClkN, a reset terminal RN and an output terminal Q, and the clock terminals Clk and ClkN are used for receiving The first oscillating signal Osc1 and the inverted first oscillating signal Osc1N, the reset terminal RN is used to receive the reset signal fnRasEn, the output terminal Q is used to trigger the inverter 202 in series and connected to the input terminal D, and is used to output the oscillation adjustment signal OscT .
  • the period of the output oscillation adjustment signal OscT at this time is twice the period of the first oscillation signal Osc1.
  • the selection unit 122 includes a magnification selector 203, the magnification selector 203 includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal, the first selection input terminal and the second selection input terminal respectively It is used to receive the first oscillation signal Osc1 and the oscillation adjustment signal OscT, the selection signal terminal is used to receive the magnification selection signal fnAdjDlyx and the inverted magnification selection signal fnAdjDlyxN, and the selection output terminal is used to output the second oscillation signal Osc2, through the magnification selection signal fnAdjDlyx can be The period of the oscillation signal is greatly changed; in this embodiment, the first selection input terminal is used to receive the first oscillation signal Osc1, and the second selection input terminal is used to receive the oscillation adjustment signal OscT; The selection input terminal receives the oscillation adjustment signal OscT, and the second selection input terminal receives the first oscillation signal Osc1.
  • the delay unit 112 includes E series-connected delay subunits, the oscillation adjustment signal OscT includes E delay signals, and E is a positive integer;
  • the signal Osc1 generates a first delay signal Osc11, and inputs the first delay signal Osc11 into the second-stage delay subunit;
  • the F-th stage delay subunit is used for the F-1th stage delay signal Osc1F- 1 generates the F-th delay signal Osc1F, where F is a positive integer less than or equal to E and greater than or equal to 2.
  • the F-th stage delay subunit includes: a D flip-flop, the D flip-flop includes an input terminal, a clock terminal, a reset terminal, and an output terminal, and the clock terminal and the clock terminal are used to receive the F-1th delay signal Osc1F-1 and Inverting the F-1th delay signal Osc1F-1N, the reset terminal is used for receiving the reset signal, the output terminal is used for triggering the inverter in series and connected to the input terminal, and is used for outputting the Fth delay signal Osc1F.
  • the period of the output F-th delayed signal Osc1F at this time is twice the period of the F-1-th delayed signal Osc1F-1.
  • the delay unit 112 includes three series-connected delay subunits, which are the first-level delay subunit 221 , the second-level delay subunit 223 and the third-level delay subunit 225 ;
  • the first stage delay subunit 221 is used to generate the first delay signal Osc11 according to the first oscillation signal Osc1, and the period of the first delay signal Osc11 is twice the period of the first oscillation signal Osc1;
  • the second stage delay subunit 223 It is used to generate the second delay signal Osc12 according to the first delay signal Osc11, and the period of the second delay signal Osc12 is twice the period of the first delay signal Osc11;
  • the third-stage delay subunit 225 is used for generating the second delay signal Osc12 according to the second
  • the delay signal Osc12 generates a third delay signal Osc13, and the period of the third delay signal Osc13 is twice the period of the second delay signal Osc12.
  • the selection unit 122 selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx, including: selecting the E-1 th delay signal Osc1E-1 or The E-th delayed signal Osc1E is used as the second oscillation signal Osc2.
  • the selection unit 122 selects the first oscillation signal Osc1 or the oscillation adjustment signal OscT as the second oscillation signal Osc2 based on the magnification selection signal fnAdjDlyx, including: selecting the second delay signal Osc12 or the third delay signal based on the magnification selection signal fnAdjDlyx
  • the time signal Osc13 is used as the second oscillation signal Osc2.
  • the first stage delay unit 221 and the second stage delay sub-unit 223 are used to expand the period of the output second oscillation signal Osc2.
  • the selection unit 122 includes E series-connected selection sub-units, and the magnification selection signal fnAdjDlyx includes a sub-magnification selection signal corresponding to each selection sub-unit;
  • the selection signal selects the first oscillation signal Osc1 or the first delay signal Osc11 and inputs it into the second-stage selection subunit;
  • the F-th stage selection sub-unit is used for selecting the F-1th stage selection signal according to the corresponding sub-magnification selection signal
  • the output signal of the subunit or the Fth delay signal Osc1F is input into the F+1th stage selection subunit;
  • the Eth stage selection subunit is used to select the E-1th stage selection subunit according to the corresponding sub-magnification selection signal.
  • the output signal or the oscillation adjustment signal OscT is used as the second oscillation signal Osc2, and F is a positive integer less than E and greater than or equal to 2, that is, the first selection input terminal and the second selection input terminal of the selection unit 122 are respectively used to receive the oscillation adjustment One of the signals (the first delay signal Osc11, the second delay signal Osc12...the F-th delay signal Osc1F) or the first oscillation signal Osc1, and the oscillation adjustment signal (the first delay signal) is selected according to the magnification selection signal One of the signals of Osc11, the second delayed signal Osc12...the F-th delayed signal Osc1F) or one of the first oscillating signals Osc1 is used as the second oscillating signal Osc2.
  • the F-th stage selection subunit includes: a magnification selector, and the magnification selector includes a first selection input terminal, a second selection input terminal, a selection signal terminal and a selection output terminal, a first selection input terminal and a second selection input terminal They are respectively used to receive the output signal of the F-1st stage selection subunit and the Fth delay signal Osc1F.
  • the selection signal terminal is used to receive the corresponding sub-multiplier selection signal
  • the selection output terminal is used to output the F-1st stage selection subunit.
  • the output signal or the Fth delay signal Osc1F in this embodiment, the first selection input terminal is used to receive the output signal of the F-1th stage selection subunit, and the second selection input terminal receives the Fth delay signal Osc1F; In other embodiments, the first selection input terminal may also receive the Fth delay signal Osc1F, and the second selection input terminal may receive the output signal of the F-1th stage selection subunit.
  • the selection unit 122 includes three selection subunits connected in series, which are the first-level selection subunit 227 , the second-level selection subunit 228 and the third-level selection subunit 229 ; wherein, the first-level selection subunit 229 227 is used to select the first oscillation signal Osc1 or the first delay signal Osc11 to be input to the second stage selection subunit 228, and the second stage selection subunit 228 is used to select the output signal of the first stage selection subunit 227 or the second delay.
  • the time signal Osc12 is input to the third stage selection subunit 229, and the third stage selection subunit 229 is used to select the output signal of the second stage selection subunit 228 or the third delay signal Osc13 as the oscillation adjustment signal OscT.
  • the third stage selection subunit 229 is used to select the output signal of the second stage selection subunit 228 or the third delay signal Osc13 as the oscillation adjustment signal OscT.
  • the magnification selection signal fnAdjDlyx, the first selection signal fnAdjDly1 and the second selection signal fnAdjDly2 can be implemented by multi-bit binary numbers, that is, the selection signal is a multi-bit binary number, one of which is used as the multiplier.
  • the selection signal fnAdjDlyx one bit is used as the first selection signal fnAdjDly1, and one bit is used as the second selection signal fnAdjDly2.
  • the pulse generation circuit 100 includes: a pulse conversion module 103 that receives the second oscillation signal Osc2 and outputs a pulse signal OscClk, the pulse of the pulse signal OscClk is generated based on the rising edge or the falling edge of the second oscillation signal, and the pulse signal
  • the pulse period of OscClk is the same as the oscillation period of the second oscillation signal.
  • the pulse conversion module 103 includes: a pulse converter 113 for receiving the second oscillating signal Osc2 and generating the pulse signal OscClk based on the second oscillating signal Osc2 .
  • the pulse converter 113 when the pulse converter 113 detects the rising edge of the second oscillating signal Osc2 and outputs an upward narrow pulse, the output end of the pulse converter 113 can also pass through a series inverter to output a downward narrow pulse. pulse. In another example, when the pulse converter 113 detects the rising edge of the second oscillating signal Osc2 and outputs a narrow downward pulse, the output end of the pulse converter 113 can also pass through a series inverter to output an upward pulse. narrow pulse. In addition, in this embodiment, the pulse converter 113 operates based on the rising edge of the second oscillation signal Osc2 . In other embodiments, the pulse converter 113 may also operate based on the falling edge of the second oscillation signal.
  • the meaning of “based on” includes but is not limited to: detecting the rising edge of the second oscillating signal Osc2, or detecting the second oscillating signal Osc2
  • the narrow pulse of the pulse signal OscClk is generated after the oscillation signal Osc2 changes from low level to high level (high level to low level).
  • the pulse signal OscClk is generated based on the rising edge of the second oscillating signal Osc2, and in other embodiments, the pulse signal may also be generated according to the falling edge of the second oscillating signal.
  • the oscillation module 101 when the control signal RasEn is at an active level, the oscillation module 101 generates a first oscillation signal Osc1 with a period T, and the period adjustment module 102 adjusts the period of the second oscillation signal Osc2 (Osc2') according to the magnification selection signal fnAdjDlyx.
  • the second oscillation signal Osc2 generated at this time has a periodic change. Assuming that the period T is changed to the period 2T, the pulse signal OscClk generated at this time has a pulse in the pulse signal OscClk. The period is also changed from period T to period 2T; if the magnification selection signal fnAdjDlyx is changed before the control signal RasEn is at the active level, the second oscillation signal Osc2' generated at this time has no period change, and the pulse period in the generated pulse signal OscClk' There is also no pulse period variation.
  • the first control signal ActEn generated is at an active level; the first pulse generating unit 301 is used to generate a first oscillation signal Osc1 and a cycle with a period T according to the first control signal ActEn is the second oscillating signal Osc2 of 2T; in this embodiment, the period of the second oscillating signal Osc2 is consistent with the period of the first oscillating signal Osc1 , and the first pulse signal ActClk is generated based on the rising edge of the second oscillating signal Osc2 .
  • the second pulse generating unit 302 is configured to generate a first oscillation signal Osc1′′ with a period of T and a second oscillation signal Osc2′′ with a period of 2T according to the second control signal PreEn; in this embodiment, the second oscillation signal Osc2′′ and The cycles of the first oscillating signal Osc1′′ are the same, and the second pulse signal PreClk is generated based on the rising edge of the second oscillating signal Osc2′′.
  • the first pulse signal ActClk and the second pulse signal PreClk generated at this time are interleaved pulse signals.
  • the delay signal output circuit includes: G signal output circuits 500, where G is an integer greater than or equal to 2, the signal output circuit is used to receive the input signal, the first pulse signal ActClk and the second pulse signal PreClk, and output the delay output signal; wherein, the non-first-stage signal output circuits all receive the delayed output signal output by the previous-stage signal output circuit as the input signal of the current-stage signal output circuit, and the first-stage signal output circuit receives the initial input signal as the first-stage signal output circuit
  • the input signal of the signal output circuit; the rising edge of the delayed output signal generated by the signal output circuit has a first delay with the received delayed output signal output by the previous stage signal output circuit or the rising edge of the initial input signal;
  • the falling edge of the delayed output signal generated by the signal output circuit has a second delay with the received delayed output signal output by the previous stage signal output circuit or the falling edge of the initial input signal.
  • the signal output circuit 500 includes: a first control module 501 that receives a first pulse signal ActClk and an input signal ActBnk0 and outputs a first adjustment signal ActLat, the first preset edge of the first adjustment signal ActLat is relatively The rising delay of the input signal ActBnk0 has a first delay, and the first delay is the pulse period of the first pulse signal ActClk.
  • the input signal ActBnk0 may be sampled by the rising or falling edge of the first pulse signal ActClk, and then the first adjustment signal ActLat may be output; or the output input may be delayed after the rising or falling edge of the first pulse signal ActClk is detected. signal ActBnk0, thereby obtaining the first adjustment signal ActLat.
  • the first preset edge is the rising edge as an example for illustration; specifically, the input signal ActBnk0 is an external input signal (compared to the signal output circuit 500 ), and the signal output circuit 500 is used to The signal ActBnk0 generates the delayed output signal ActBnk1; wherein, the rising edge of the delayed output signal ActBnk1 is generated based on the rising edge of the first adjustment signal ActLat, and the rising edge of the first adjustment signal ActLat and the input signal ActBnk0
  • the rising edge has a first delay; That is, the rising edge of the delayed output signal ActBnk1 and the rising edge of the input signal ActBnk0 have a first delay, and the first delay is the pulse period of the first pulse signal ActClk. It can be seen that the externally input first pulse signal ActClk is used to adjust the delay.
  • the first preset edge may also be a falling edge.
  • the meaning of “based on” includes but is not limited to: the detection of the first adjustment
  • the first preset edge of the signal ActLat generates the rising edge of the delay output signal ActBnk1, or a delay is generated after detecting that the first adjustment signal ActLat changes from low level to high level (high level to low level).
  • the first control module 501 includes a first D flip-flop 511 , the clock terminal is used to receive the first pulse signal ActClk, the reset terminal is used to receive the first reset signal fnActEn, and the input terminal is used to receive the input The signal ActBnk0, the output terminal is used for outputting the first adjustment signal ActLat.
  • the signal output circuit 500 further includes: a second control module 502, receiving the second pulse signal PreClk and the input signal ActBnk0, and outputting the second adjustment signal PreLat, the second preset edge of the second adjustment signal PreLat is relative to The falling edge of the input signal ActBnk0 has a second delay, and the second delay is the pulse period of the second pulse signal PreClk.
  • the second preset edge is taken as an example for illustration; specifically, the falling edge of the delayed output signal ActBnk1 is generated based on the rising edge of the second adjustment signal PreLat, There is a second delay between the edge and the falling edge of the input signal ActBnk0; that is, the falling edge of the delayed output signal ActBnk1 and the falling edge of the input signal ActBnk0 have a second delay, and the second delay is the pulse period of the second pulse signal PreClk, which shows that , the externally input second pulse signal PreClk is used to adjust the delay of the falling edge of the delayed output signal ActBnk1 . It should be noted that, in other embodiments, the second preset edge may also be a falling edge.
  • the meaning of “based on” includes but is not limited to: the second adjustment is detected
  • the second preset edge of the signal PreLat generates the falling edge of the delayed output signal ActBnk1, or a delay is generated after detecting that the second adjustment signal PreLat changes from low level to high level (high level to low level).
  • the second control module 502 includes a second D flip-flop 512 , the clock terminal is used to receive the second pulse signal PreClk, the reset terminal is used to receive the second reset signal fnPreEn, and the input terminal is used to receive the input
  • the signal ActBnk0 outputs the second adjustment signal PreLat after the inverter is connected in series with the output end.
  • one of the pulses of the first pulse signal ActClk is aligned with the rising edge of the input signal ActBnk0
  • one of the pulses of the second pulse signal PreClk is aligned with the falling edge of the input signal ActBnk0.
  • One of the pulses of the first pulse signal ActClk is aligned with the rising edge of the input signal ActBnk0 to ensure the accuracy of the first delay between the first signal edge of the first adjustment signal ActLat and the rising edge of the input signal ActBnk0;
  • One of the pulses of the pulse signal PreClk is aligned with the falling edge of the input signal ActBnk0 to ensure the accuracy of the second delay between the second signal edge of the second adjustment signal PreLat and the falling edge of the input signal ActBnk0 .
  • the signal output circuit 500 further includes: a signal output module 503, receiving the first adjustment signal ActLat and the second adjustment signal PreLat, and outputting the delay output signal ActBnk1, the rising edge of the delay output signal ActBnk1 is based on the first adjustment The first preset edge of the signal ActLat is generated, and the falling edge of the delayed output signal ActBnk1 is generated based on the second preset edge of the second adjustment signal PreLat.
  • the signal output module 503 includes: a first receiving unit 513 that receives the first pulse signal ActClk and the first adjustment signal ActLat, and generates the first pulse control signal during the period when the first adjustment signal ActLat is at an active level
  • the pulse phase of the first pulse control signal ActN is the same as the pulse phase of the first pulse signal ActClk.
  • the second receiving unit 523 receives the second pulse signal PreClk and the second adjustment signal PreLat, and generates a second pulse control signal PreN when the second adjustment signal PreLat is at an active level.
  • the pulse phase of the second pulse control signal PreN is the same as that of the second adjustment signal PreLat.
  • the pulse phases of the second pulse signal PreClk are the same.
  • the latch unit 533 receives the first pulse control signal ActN and the second pulse control signal PreN, and delays the output signal ActBnk1.
  • the inverter when it is detected that the first adjustment signal ActLat is at an active level, the inverter generates the first pulse control signal ActN through the first pulse signal ActClk; when it is detected that the second adjustment signal PreLat is at an active level, based on The inverter generates the second pulse control signal PreN through the second pulse signal PreClk.
  • the first receiving unit 513 includes a first receiving NAND gate 601
  • the first receiving NAND gate 601 includes a first input terminal, a second input terminal and a first output terminal, the first input terminal It is used for receiving the first adjustment signal ActLat
  • the second input terminal is used for receiving the first pulse signal ActClk
  • the first output terminal is used for outputting the first pulse control signal ActN.
  • the second receiving unit 523 includes a second receiving NAND gate 602, the second receiving NAND gate 602 includes a third input terminal, a fourth input terminal and a second output terminal, the third input terminal is used for receiving the second adjustment signal PreLat, The fourth input terminal is used for receiving the second pulse signal PreClk, and the second output terminal is used for outputting the second pulse control signal PreN.
  • the latch unit 533 includes a latch 603, the latch 603 includes a fifth input terminal, a sixth input terminal and a third output terminal, the fifth input terminal is used for receiving the first pulse control signal ActN, and the sixth input terminal is used for After receiving the second pulse control signal PreN, the third output terminal is used for outputting the delay output signal ActBnk1.
  • the latch unit 603 is configured such that: when the first pulse control signal ActN and the second pulse control signal PreN are at different levels, the delay output signal ActBnk1 and the second pulse control signal PreN are at the same level; the first pulse control signal ActN and the second pulse control signal PreN are at the same level; When the second pulse control signal PreN is at a high level, the latch unit 603 maintains the state.
  • the latch unit 603 keeps the state; when the first pulse control signal ActN is at a high level and the second pulse signal control signal PreN is at a low level , the latch unit 603 is at a low level; when the first pulse control signal ActN is at a low level and the second pulse signal control signal PreN is at a high level, the latch unit 603 is at a high level.
  • the first receiving unit 513 is further configured to receive the first control signal ActEn, and the first receiving unit 513 is configured to, during the period when the first adjustment signal ActLat and the first control signal ActEn are active levels, according to the first pulse
  • the signal ActClk generates the first pulse control signal ActN.
  • the second receiving unit 523 is further configured to receive the second control signal PreEn, and the second receiving unit 523 is configured to generate a second pulse according to the second pulse signal PreClk during the period when the second adjustment signal PreLat and the second control signal PreEn are at active levels Control signal PreN.
  • the first receiving NAND gate 601 is further configured to receive the first control signal ActEn, and the first receiving NAND gate 601 generates the first pulse according to the first clock signal ActClk, the first control signal ActEn and the first adjustment signal ActLat Control signal ActN.
  • the second receiving NAND gate 602 is further configured to receive the second control signal PreEn, and the second receiving NAND gate 602 generates the second pulse control signal PreN according to the second clock signal PreClk, the second control signal PreEn and the second adjustment signal PreLat.
  • the first control signal ActEn and the second control signal PreEn are inverted signals
  • the first pulse signal ActClk exists when the first control signal ActEn is at an active level
  • the second pulse signal PreClk is active when the second control signal PreEn is at an active level Exist during peacetime.
  • the first receiving NAND gate 601 and the second receiving NAND gate 601 receive the first control signal ActEn and the second control signal PreEn respectively to ensure the stability of the outputs of the first receiving NAND gate 601 and the second receiving NAND gate 602 .
  • first pulse signal ActClk and the second pulse signal PreClk are interleaved pulse signals, and the interleaved pulse signal is a pulse signal generated according to an inverted signal; in this embodiment, the first pulse signal ActClk is in the first control signal ActEn It exists during the active level period, and the start pulse of the first pulse signal ActClk is aligned with the rising edge of the first control signal ActEn; the second pulse signal PreClk exists during the active level period of the second control signal PreEn, and the second pulse signal The start pulse of the signal PreClk is aligned with the rising edge of the second control signal PreEn; it should be noted that the "alignment" described here is not necessarily a perfect alignment under ideal conditions, and may include a rise due to factors such as circuit delays There is a slight difference in edge/falling edge.
  • the input signal ActBnk0, the first pulse signal ActClk and the second pulse signal PreClk are external input signals; it is assumed that the period of the first pulse signal ActClk is t1 and the period of the second pulse signal PreClk is t2. 15, the first adjustment signal ActLat is generated based on the input signal ActBnk0 and the first pulse signal ActClk.
  • the state of the first adjustment signal ActLat is the current state of the input signal ActBnk0, resulting in the first
  • the first delay is the period of the first pulse signal ActClk, that is, the delay between the rising edge of the first adjustment signal ActLat and the rising edge of the input signal ActBnk0 is t1 .
  • the second adjustment signal PreLat is generated based on the input signal ActBnk0 and the second pulse signal PreClk.
  • the state of the second adjustment signal PreLat is the current state of the input signal ActBnk0, resulting in the second
  • the second delay is the period of the second pulse signal PreClk, that is, the delay between the rising edge of the second adjustment signal PreLat and the falling edge of the input signal ActBnk0 is t2 .
  • the first receiving NAND gate 601 is also used to receive the first control signal ActEn, and the second receiving NAND gate 602 It is also used for receiving the second control signal PreEn, and the first control signal ActEn and the second control signal PreEn are inverted signals.
  • the first receiving NAND gate 601 and the second receiving NAND gate 602 generate the first pulse control signal ActN and the second pulse control signal PreN respectively.
  • the latch unit 603 generates the delayed output signal ActBnk1 according to the first pulse control signal ActN and the second pulse control signal PreN, the rising edge of the delayed output signal ActBnk1 and the rising edge of the input signal ActBnk0 have a first delay, and the first delay is the first delay.
  • a pulse period t1 of the pulse signal ActClk; the falling edge of the delayed output signal ActBnk1 and the falling edge of the input signal ActBnk0 have a second delay, the second delay being the pulse period t2 of the second pulse signal PreClk.
  • the pulse periods of the first pulse signal ActClk and the second pulse signal PreClk are equal, that is, the signal change edge of the delayed output signal ActBnk1 is delayed by an equal time relative to the signal change edge of the input signal ActBnk0.
  • each signal given in FIG. 7 is only used to interpret the circuit function of the signal output circuit 500 provided in this embodiment, and does not constitute a limitation on this embodiment; A corresponding delayed input signal is generated according to other input signals; in addition, the input signal may also be inconsistent with the first control signal.
  • the signal output circuit further includes an even number of inverters, and the inverters are connected in series with the output end of the signal output module to enhance the driving capability of the signal output circuit.
  • the delay signal output circuit 700 includes seven signal output circuits 500 as an example for specific description, which does not constitute a limitation to this embodiment. Specifically, the first stage signal output circuit 701, The second stage signal output circuit 702 , the third stage signal output circuit 703 , the fourth stage signal output circuit 704 , the fifth stage signal output circuit 705 , the sixth stage signal output circuit 706 and the seventh stage signal output circuit 707 . In other embodiments, the delay signal output circuit may include two or more signal output circuits.
  • the first-stage signal output circuit 701 generates the first-stage delayed output signal ActBnk1 according to the initial input signal ActBnk0, the first pulse signal ActClk and the second pulse signal PreClk, and the rising edge of the first-stage delayed output signal ActBnk1 is relative to the rising edge of the first-stage delayed output signal ActBnk1.
  • the rising edge of the initial input signal ActBnk0 has a first delay, and the first delay is the pulse period t1 of the first pulse signal ActClk; the falling edge of the first-stage delayed output signal ActBnk1 has a second delay relative to the falling edge of the initial input signal ActBnk0 , the second delay is the pulse period t2 of the second pulse signal PreClk.
  • the second-stage signal output circuit 702 generates the second-stage delayed output signal ActBnk2 according to the first-stage delayed output signal ActBnk1 , the first pulse signal ActClk and the second pulse signal PreClk, and the rising edge of the second-stage delayed output signal ActBnk2 is relatively
  • the first stage delay output signal ActBnk1 has a first delay; the falling edge of the second stage delay output signal ActBnk2 has a second delay relative to the first stage delay output signal ActBnk1.
  • the third-stage signal output circuit 703 generates the third-stage delayed output signal ActBnk3 according to the second-stage delayed output signal ActBnk2, the first pulse signal ActClk and the second pulse signal PreClk, and the rising edge of the third-stage delayed output signal ActBnk3 is relatively
  • the second-stage delayed output signal ActBnk2 has a first delay; the falling edge of the third-stage delayed output signal ActBnk3 has a second delay relative to the second-stage delayed output signal ActBnk2.
  • the fourth-stage signal output circuit 704 generates the fourth-stage delayed output signal ActBnk4 according to the third-stage delayed output signal ActBnk3, the first pulse signal ActClk and the second pulse signal PreClk, and the rising edge of the fourth-stage delayed output signal ActBnk4 is relatively
  • the third-stage delayed output signal ActBnk3 has a first delay; the falling edge of the fourth-stage delayed output signal ActBnk4 has a second delay relative to the third-stage delayed output signal ActBnk3.
  • the fifth-stage signal output circuit 705 generates the fifth-stage delayed output signal ActBnk5 according to the fourth-stage delayed output signal ActBnk4, the first pulse signal ActClk and the second pulse signal PreClk, and the rising edge of the fifth-stage delayed output signal ActBnk5 is relatively
  • the fourth stage delay output signal ActBnk4 has a first delay; the falling edge of the fifth stage delay output signal ActBnk5 has a second delay relative to the fourth stage delay output signal ActBnk4.
  • the sixth-stage signal output circuit 706 generates the sixth-stage delayed output signal ActBnk6 according to the fifth-stage delayed output signal ActBnk5, the first pulse signal ActClk and the second pulse signal PreClk, and the rising edge of the sixth-stage delayed output signal ActBnk6 is relatively A first delay exists in the fifth-stage delayed output signal ActBnk5; a falling edge of the sixth-stage delayed output signal ActBnk6 has a second delay relative to the fifth-stage delayed output signal ActBnk5.
  • the seventh-stage signal output circuit 707 generates the seventh-stage delayed output signal ActBnk7 according to the sixth-stage delayed output signal ActBnk6, the first pulse signal ActClk and the second pulse signal PreClk, and the rising edge of the seventh-stage delayed output signal ActBnk7 is relatively A first delay exists in the sixth-stage delayed output signal ActBnk6; a falling edge of the seventh-stage delayed output signal ActBnk7 has a second delay relative to the sixth-stage delayed output signal ActBnk6.
  • the first control module of the signal output circuit is further configured to receive the first control signal ActEn
  • the second control module of the signal output circuit is further configured to receive the second control signal PreEn
  • the first pulse signal ActClk and the second pulse signal PreClk are inverted signals; each stage of the signal output circuit is used for the first control signal ActEn, the second control signal PreEn, the first pulse signal ActClk, the second pulse signal PreClk
  • the delay output signal of the current stage is generated with the delay output signal output by the signal output circuit of the previous stage, and the stability of the output of the signal output circuit is ensured by receiving the first control signal ActEn and the second control signal PreEn.
  • the delay signal output circuit 700 further includes: an initial signal output circuit 710, including a first control module, a second control module and a signal output module; the first control module is used for receiving the first control module.
  • the pulse signal ActClk and the first power supply signal Vdd, and the first adjustment signal (not shown) is generated according to the first pulse signal ActClk and the first power supply signal Vdd;
  • the second control module of the output signal output circuit is used to receive the second pulse
  • the signal PreClk and the second power supply signal Vss generate a second adjustment signal (not shown) according to the second pulse signal PreClk and the second power supply signal Vss;
  • the signal output module is used for according to the first adjustment signal (not shown) and the first adjustment signal (not shown).
  • Two adjustment signals (not shown) generate the initial input signal.
  • the delayed output signal of the initial signal output circuit generated according to the first power signal Vdd and the second power signal Vss that is, the initial input signal ActBnk0 output by the initial output circuit 710 according to the initial signal can be avoided compared with the input signal ActBnk0 directly input from the outside Delay caused by circuit elements of a signal output circuit.
  • the circuit of the initial signal output circuit 710 here may be the same as the signal output circuit described above, which will not be repeated here, but this embodiment is not limited thereto.
  • FIG. 22 and FIG. 23 which take the delayed signal output circuit 700 composed of four signal output circuits as an example for introduction.
  • the first clock terminal ActClk of the signal output circuit is used for receiving the first pulse signal ActClk; the second clock terminal PreClk of the signal output circuit is used for receiving the second pulse signal PreClk; the first control terminal ActEn of the signal output circuit is used for receiving the first pulse signal PreClk Control signal ActEn; the second control terminal PreEn of the signal output circuit is used to receive the second control signal PreEn; the signal output terminal ActBnk of the signal output circuit is used to output the delay output signal of the current stage; the signal output circuit also includes a first signal terminal ActEnPre and the second signal terminal PreEnPre (signal input terminal of the signal output circuit), with reference to FIG.
  • the first signal terminal ActEnPre of the initial signal output circuit is used to receive the first power signal Vdd, and the second signal terminal PreEnPre of the initial signal output circuit It is used to receive the second power supply signal Vss; the first signal terminal ActEnPre and the second signal terminal PreEnPre of other signal output circuits are used to receive the delayed output signal output by the previous stage signal output circuit.
  • the first stage signal output circuit 701 generates the first stage delay output signal ActBnk1 according to the initial input signal ActBnk0
  • the second stage signal output circuit 702 generates the second stage delay output signal ActBnk1 according to the first stage delay output signal.
  • the third-stage signal output circuit 703 generates the third-stage delay output signal ActBnk3 according to the second-stage delay output signal ActBnk2
  • the fourth-stage signal output circuit 704 generates the fourth-stage delay output signal ActBnk3 according to the third-stage delay output signal ActBnk3.
  • Stage delay output signal ActBnk4 (not shown)
  • fifth stage signal output circuit 705 generates fifth stage delay output signal ActBnk5 (not shown) according to fourth stage delay output signal ActBnk4, sixth stage signal output circuit 706
  • the sixth-stage delayed output signal ActBnk6 (not shown) is generated according to the fifth-stage delayed output signal ActBnk5
  • the seventh-stage signal output circuit 707 is generated according to the sixth-stage delayed output signal ActBnk6.
  • the seventh-stage delayed output signal ActBnk7 (not shown).
  • the first oscillating signal is generated according to the control signal, that is, when the control signal is at an active level, a first oscillating signal with a certain period is generated; That is, based on the magnification selection signal, the period of the first oscillating signal is changed to generate the corresponding second oscillating signal; then the second oscillating signal is used as a signal source to generate a pulse signal, and the pulse period of the generated pulse signal is the same as the oscillation of the second oscillating signal.
  • the cycle is the same; in the process of generating the pulse signal, if the magnification selection signal changes, the amplitude of the cycle of the first oscillating signal is adjusted to change, so that the cycle of the generated second oscillating signal changes, thereby generating a first pulse signal with an adjustable cycle. and a second pulse signal; and a delay signal with a controllable delay is generated according to the first pulse signal and the second pulse signal.
  • the delay signal has a first delay on the rising edge and a second delay on the falling edge.
  • the first delay is the pulse period of the first pulse signal
  • the second delay is the pulse period of the second pulse signal
  • each unit involved in this embodiment is a logical unit.
  • a logical unit may be a physical unit, a part of a physical unit, or multiple physical units.
  • a composite implementation of the unit in order to highlight the innovative part of the present application, this embodiment does not introduce units that are not very closely related to solving the technical problem proposed by the present application, but this does not mean that there are no other units in this embodiment.
  • the interleaving signal generating circuit may include: an interleaving pulse generating circuit, configured to generate a first pulse signal according to the first control signal, and generate a second pulse signal according to the second control signal, the first control signal and the The second control signal is an inverted signal, and the first pulse signal and the second pulse signal are interleaved pulse signals;
  • the delay signal output circuit includes G signal output circuits, where G is an integer greater than or equal to 2; non-first-level signal output The circuits all receive the delayed output signal output by the previous-stage signal output circuit as the input signal of the current-stage signal output circuit, and the first-stage signal output circuit receives the initial input signal as the input signal of the first-stage signal output circuit; the embodiment of the present application
  • the first pulse signal and the second pulse signal with adjustable period are generated, and the delay signal with controllable delay is generated according to the first pulse signal and the second pulse signal, and the circuit layout area is small, and the power consumption of the circuit is small.

Abstract

提供一种交错信号产生电路，包括：交错脉冲产生电路（300），用于根据第一控制信号（ActEn）生成第一脉冲信号（ActClk），并根据第二控制信号（PreEn）生成第二脉冲信号（PreClk），第一控制信号（ActEn）与第二控制信号（PreEn）为反相信号，第一脉冲信号（ActClk）与第二脉冲信号（PreClk）为交错脉冲信号；延时信号输出电路，包括G个信号输出电路（500），G为大于等于2的整数；非第一级信号输出电路均接收前一级信号输出电路输出的延时输出信号作为当前级信号输出电路的输入信号，第一级信号输出电路接收初始输入信号作为第一级信号输出电路的输入信号，以产生周期可调整的第一脉冲信号（ActClk）和第二脉冲信号（PreClk），并根据第一脉冲信号（ActClk）和第二脉冲信号（PreClk）产生延时可控的延时信号，且电路版图的面积小，电路的功耗小。

Description

交错信号产生电路
相关申请的交叉引用
本申请要求在2021年03月09日提交中国专利局、申请号为202110256944.5、申请名称为“交错信号产生电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及但不限于一种交错信号产生电路。
背景技术
在半导体电路设计中，经常会用到等间距交错(Stagger)信号，等间距交错信号指每间隔固定延迟产生的信号。
对于同步信号而言，通常借助时钟信号来产生等间距交错信号；对于异步信号而言，通过插入延时单元(delay cell)来产生所需的等间距交错信号，信号之间的延迟可以根据需求插入相应的延时单元实现。
然而研究发现，采用同步信号产生等间距交错信号的方式，等间距交错信号之间的延迟必须是时钟周期的整数倍，等间距交错信号之间延迟大小的可控性差；采用异步信号产生等间距交错信号的方式，虽然信号之间的延迟可控性好，但会明显增大形成的电路版图的面积和电路的功耗。
发明内容
本申请实施例提供了一种交错信号产生电路，包括：交错脉冲产生电路，用于根据第一控制信号生成第一脉冲信号，并根据第二控制信号生成第二脉冲信号，第一控制信号与第二控制信号为反相信号，第一脉冲信号与第二脉冲信号为交错脉冲信号；延时信号输出电路，包括G个信号输出电路，G为大于等于2的整数，信号输出电路用于接收输入信号、第一脉冲信号和第二脉冲信号，输出延时输出信号；其中，非第一级信号输出电路均接收前一级信号输出电路 输出的延时输出信号作为当前级信号输出电路的输入信号，第一级信号输出电路接收初始输入信号作为第一级信号输出电路的输入信号；信号输出电路生成的延时输出信号的上升沿，与接收的前一级信号输出电路输出的延时输出信号或所述初始输入信号的上升沿，具有第一延迟；信号输出电路生成的延时输出信号的下降沿，与接收的前一级信号输出电路输出的延时输出信号或所述初始输入信号的下降沿，具有第二延迟。
附图说明
图1和图2为本申请实施例提供的交错脉冲产生电路的结构示意图；
图3为本申请实施例提供的信号产生模块的具体电路示意图；
图4和图5为本申请实施例提供的脉冲产生电路的结构示意图；
图6为本申请实施例提供的振荡模块的具体电路示意图；
图7为本申请实施例提供的延时单元的结构示意图；
图8为本申请实施例提供的选择单元的结构示意图；
图9和图10为本申请实施例提供的周期调整模块的电路示意图；
图11为本申请实施例提供的脉冲产生电路中信号的时序示意图；
图12为本申请实施例提供的交错脉冲产生电路中信号的时序示意图；
图13为本申请实施例提供的信号输出电路的结构示意图；
图14为本申请实施例提供的第一控制模块的具体电路示意图；
图15为本申请实施例提供的第二控制模块的具体电路示意图；
图16为本申请实施例提供的信号输出模块的结构示意图；
图17和图18为本申请实施例提供的信号输出模块的具体电路示意图；
图19为本申请实施例提供的信号输出电路中信号的时序示意图；
图20和图21为本申请实施例提供的延时信号输出电路的结构示意图；
图22为本申请实施例提供的延时信号输出电路的具体电路示意图；
图23为本申请实施例提供的延时信号输出电路中信号输出电路的具体电路示意图；
图24为本申请实施例提供的延时信号输出电路中信号的时序示意图。
具体实施方式
采用同步信号产生等间距交错信号的方式，等间距交错信号之间的延迟必须是时钟周期的整数倍，等间距交错信号之间延迟大小的可控性差；采用异步信号产生等间距交错信号的方式，虽然信号之间的延迟可控性好，但会明显增大形成的电路版图的面积和电路的功耗。
为解决上述问题，本申请实施例提供了一种交错信号产生电路，包括：交错脉冲产生电路，用于根据第一控制信号生成第一脉冲信号，并根据第二控制信号生成第二脉冲信号，第一控制信号与第二控制信号为反相信号，第一脉冲信号与第二脉冲信号为交错脉冲信号；延时信号输出电路，包括G个信号输出电路，G为大于等于2的整数，信号输出电路用于接收输入信号、第一脉冲信号和第二脉冲信号，输出延时输出信号；其中，非第一级信号输出电路均接收前一级信号输出电路输出的延时输出信号作为当前级信号输出电路的输入信号，第一级信号输出电路接收初始输入信号作为第一级信号输出电路的输入信号；信号输出电路生成的延时输出信号的上升沿，与接收的前一级信号输出电路输出的延时输出信号或所述初始输入信号的上升沿，具有第一延迟；信号输出电路生成的延时输出信号的下降沿，与接收的前一级信号输出电路输出的延时输出信号或所述初始输入信号的下降沿，具有第二延迟。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1和图2为本申请实施例提供的交错脉冲产生电路的结构示意图，图3 为本申请实施例提供的信号产生模块的具体电路示意图，图4和图5为本申请实施例提供的脉冲产生电路的结构示意图，图6为本申请实施例提供的振荡模块的具体电路示意图，图7为本申请实施例提供的延时单元的结构示意图，图8为本申请实施例提供的选择单元的结构示意图，图9和图10为本申请实施例提供的周期调整模块的电路示意图，图11为本申请实施例提供的脉冲产生电路中信号的时序示意图，图12为本申请实施例提供的交错脉冲产生电路中信号的时序示意图，图13为本申请实施例提供的信号输出电路的结构示意图，图14为本申请实施例提供的第一控制模块的具体电路示意图，图15为本申请实施例提供的第二控制模块的具体电路示意图，图16为本申请实施例提供的信号输出模块的结构示意图，图17和图18为本申请实施例提供的信号输出模块的具体电路示意图，图19为本申请实施例提供的信号输出电路中信号的时序示意图，图20和图21为本申请实施例提供的延时信号输出电路的结构示意图，图22为本申请实施例提供的延时信号输出电路的具体电路示意图，图23为本实施例提供的延时信号输出电路中信号输出电路的具体电路示意图，图24为本申请实施例提供的延时信号输出电路中信号的时序示意图，以下结合附图对本实施例提供的交错信号产生电路作进一步详细说明。
交错信号产生电路，包括：
交错脉冲产生电路，用于根据第一控制信号ActEn生成第一脉冲信号ActClk，并根据第二控制信号PreEn生成第二脉冲信号PreClk，第一控制信号ActEn和第二控制信号PreEn为反相信号，第一脉冲信号ActClk和第二脉冲信号PreClk为交错脉冲信号。本实施例所称交错脉冲信号表示根据反相的信号(第一控制信号ActEn和第二控制信号PreEn)产生的脉冲信号(第一脉冲信号ActClk和第二脉冲信号PreClk)，也可以为在不同期间分别有效的脉冲信号。
延时信号输出电路，包括G个信号输出电路，G为大于等于2的整数，信号输出电路用于接收输入信号、第一脉冲信号ActClk和第二脉冲信号PreClk，输出延时输出信号。
其中，非第一级信号输出电路均接收前一级信号输出电路输出的延时输出 信号作为当前级信号输出电路的输入信号，第一级信号输出电路接收初始输入信号作为第一级信号输出电路的输入信号；信号输出电路生成的延时输出信号的上升沿，与接收的前一级信号输出电路输出的延时输出信号的上升沿，具有第一延迟；信号输出电路生成的延时输出信号的下降沿，与接收的前一级信号输出电路输出的延时输出信号的下降沿，具有第二延迟。
在本实施例中，第一脉冲信号ActClk的脉冲周期为t1，第二脉冲信号PreClk的脉冲周期为t2，第一脉冲信号ActClk的脉冲周期和第二脉冲信号PreClk的脉冲周期相等；在其他实施例中，第一脉冲信号和第二脉冲信号的脉冲周期可以不同。
具体地，参考图1，交错脉冲产生电路300，包括：信号产生模块303，用于根据激活信号Active生成第一控制信号ActEn和第二控制信号PreEn，第一控制信号ActEn和第二控制信号PreEn为反相信号。其中，激活信号Active即外部输入的激活指令，信号产生模块303用于根据外部激活指令生成互为反相信号的第一控制信号ActEn和第二控制信号PreEn。
更具体地，参考图2，信号产生模块303包括：
复位单元313，接收第一复位信号fnActEn以及激活信号Active，并基于第一复位信号fnActEn和激活信号Active生成第一控制信号ActEn。
第一复位信号fnActEn即外部输入的复位指令，用于对复位单元313进行复位；具体地，当复位单元313复位后，若复位单元313接收的激活信号Active为有效电平，复位单元313产生第一控制信号ActEn。
反向单元323，接收第一控制信号ActEn，并基于第一控制信号ActEn生成第二控制信号PreEn。
在本实施例中，信号产生模块303还包括：复位信号产生单元333，用于根据第一复位信号fnActEn和第一控制信号ActEn生成第二复位信号fnPreEn，以使当第一复位信号fnActEn为复位状态时，第二复位信号fnPreEn也处于复位状态，当第一复位信号fnActEn为非复位状态时，第二复位信号fnPreEn基于第一控制信号ActEn的变化沿产生复位窄脉冲。
在本实施例中，信号产生模块303还包括：选择信号产生单元343，用于接收选择信号fnAdjDly，并基于选择信号fnAdjDly生成选择信号组，选择信号组包括选择信号fnAdjDly和反相选择信号fnAdjDlyN，选择信号fnAdjDly与反相选择信号fnAdjDlyN为反相信号。
需要说明的是，在本实施例中选择信号fnAdjDly包括用于调控脉冲产生电路100的倍率选择信号fnAdjDlyx、第一选择信号fnAdjDly1和第二选择信号fnAdjDly2。
在一个例子中，参考图3，复位单元313包括复位与非门403和复位反相器404，复位反相器404连接复位与非门403的输出端，复位与非门403用于接收第一复位信号fnActEn和激活信号Active。
反向单元323包括连接复位单元313的输出反相器405，用于根据第一控制信号ActEn生成第二控制信号PreEn。
复位信号产生单元333包括脉冲转换装置406，用于检测第一控制信号ActEn的变化沿(如上升沿)，产生脉冲控制信号；输出与非门407和输出反相器408，输出与非门407还用于接收第一复位信号fnActEn，此时输出反相器408输出第二复位信号fnPreEn。
选择信号产生单元343包括：串联的第一选择反相器401和第二选择反相器402，第一选择反相器401的输出端连接第二选择反相器402的输入端，用于根据选择信号fnAdjDly生成选择信号组。
继续参考图2，交错脉冲产生电路300，还包括：第一脉冲产生单元301和第二脉冲产生单元302；第一脉冲产生单元301具体包括脉冲产生电路，用于根据第一控制信号ActEn生成第一脉冲信号ActClk；第二脉冲产生单元302具体包括脉冲产生电路，用于根据第二控制信号PreEn生成第二脉冲信号PreClk；第一脉冲信号ActClk与第二脉冲信号PreClk为交错脉冲信号。
在本实施例中，第二脉冲产生单元302与第一脉冲产生单元301具有相同的电路结构。本实施例以第一脉冲产生单元301的脉冲产生电路100进行介绍，其中，第一控制信号ActEn和第二控制信号PreEn属于控制信号RasEn；第一 复位信号fnActEn和第二复位信号fnPreEn属于复位信号fnRasEn。
参考图4，第一脉冲产生单元301包括脉冲单元电路100，包括：振荡模块101，接收控制信号RasEn，且根据控制信号RasEn生成第一振荡信号Osc1；具体地，当控制信号RasEn处于有效电平时，振荡模块101生成第一振荡信号Osc1；在本实施例中，假设第一振荡信号Osc1的周期为T。
在一个例子中，当接收到控制信号RasEn，且控制信号RasEn为有效电平时，振荡模块101起振以产生第一振荡信号Osc1。
进一步地，参考图5，振荡模块101包括振荡单元111以及连接在振荡单元111中的触发单元121；触发单元121用于接收复位信号fnRasEn以及控制信号RasEn，并基于复位信号fnRasEn和控制信号RasEn触发振荡单元111；振荡单元111触发后，根据控制信号RasEn生成第一振荡信号Osc1。
需要注意的是，此处描述的“基于复位信号fnRasEn和控制信号RasEn触发振荡单元111”中，“基于”的含义包括但不限定于：当复位信号fnRasEn处于非复位状态，且控制信号RasEn为有效电平，触发单元121触发振荡单元111。
复位信号fnRasEn即外部输入的复位指令，用于对触发单元121进行复位；具体地，当触发单元121复位后，若触发单元121接收的控制信号RasEn为有效电平，触发单元121触发振荡单元111，以使振荡单元111产生第一振荡信号Osc1。
在一个例子中，参考图6，振荡单元111包括A个反相器串联形成的环形振荡器，A为正奇数；A可以为5、7、9、11等，在本实施例中以A＝7，即7个反相器串联形成的环形振荡器为例进行举例说明，并不构成对本实施例的限定，在具体应用中，可以根据实际需求选择环形振荡器中反相器的数量。触发单元121包括第一与非门211和第二与非门212，第一与非门211的输出端连接至第二与非门212的一输入端，第一与非门211的一输入端和第二与非门212的输出端用于接入环形振荡器；第一与非门211与第二与非门212中，其中一者用于接收控制信号RasEn，另一者用于接收复位信号fnRasEn；需要说明的是，图3中给定的第一与非门211用于接收控制信号RasEn，第二与非门212用于 接收复位信号fnRasEn并不构成对本实施例的限定，在其他实施例中也可以采用第二与非门接收控制信号，第一与非门接收复位信号。
在本实施例中，振荡模块101还包括：第一反相器组215，包括串联的B个反相器，B为正偶数；B可以为2、4、6等，在本实施例中以B＝2，即2个反相器串联形成的第一反相器组215为例进行举例说明，并不构成对本实施例的限定，在具体应用中，可以根据实际需求选择第一反相器组215中反相器的数量。第一选择单元(未图示)，用于接收第一选择信号fnAdjDly1，并基于第一选择信号fnAdjDly1，将第一反相器组215串接在环形振荡器中的相邻反相器之间。
具体地，第一反相器组215中反相器为B个的目的在于：保证环形振荡器中反相器的总数为奇数个；具体地，第一选择单元(未图示)包括第一选择器214，用于根据第一选择信号fnAdjDly1和反相第一选择信号fnAdjDly1N选通第一支路或第二支路；其中，第一支路作为环形振荡器中相邻反相器的连接电路，第二支路将第一反相器组215串接至环形振荡器相邻反相器的连接电路中；将第一反相器组215接入环形振荡器的目的是：增加环形振荡器中反相器的个数，从而增大振荡单元111产生的第一振荡信号Osc1的周期，在本实施例中假设增加第一反相器组215的反相器后，生成的第一振荡信号Osc1为1.2T；由于第一反相器组215接入环形振荡器是通过第一选择信号fnAdjDly1控制，即可通过外部输入的第一选择信号fnAdjDly1调整振荡单元111生成的第一振荡信号Osc1的周期。
在本实施例中，振荡模块101还包括：第二反相器组217，包括串联的C个反相器，C为正偶数；C可以为2、4、6等，在本实施例中以C＝4，即4个反相器串联形成的第二反相器组217为例进行举例说明，并不构成对本实施例的限定，在具体应用中，可以根据实际需求选择第二反相器组217中反相器的数量。第二选择单元(未图示)，用于接收第二选择信号fnAdjDly2，并基于第二选择信号fnAdjDly2，将第二反相器组217串接在环形振荡器中的相邻反相器之间。
具体地，第二反相器组217中反相器为C个的目的在于：保证环形振荡器中反相器的总数为奇数个；具体地，第二选择单元(未图示)包括第二选择器216，用于根据第二选择信号fnAdjDly2和反相第二选择信号fnAdjDly2N选通第三支路或第四支路；其中，第三支路作为环形振荡器中相邻反相器的连接电路，第四支路将第二反相器组217串接至环形振荡器相邻反相器的连接电路中；将第二反相器组217接入环形振荡器的目的是：增加环形振荡器中反相器的个数，从而增大振荡单元111产生的第一振荡信号Osc1的周期，在本实施例中假设增加第二反相器组217的反相器后，生成的第一振荡信号Osc1为1.4T；由于第二反相器组217接入环形振荡器是通过第二选择信号fnAdjDly2控制，即可通过外部输入的第二选择信号fnAdjDly2调整振荡单元111生成的第一振荡信号Osc1的周期。
在本实施例中B和C可以设置为任意正偶数，在具体应用于可以根据振荡单元111产生的第一振荡信号Osc1所需的变化，合理设置B和C的值；另外，本实施例中说明了两个反相器组的实现方式，在本实施例的基础上继续加入第三反相器组、第四反相器组的实现方案，都应该属于本申请的保护范围。
另外，通过第一反相器组215和第二反相器组217同时接入环形振荡器，可以实现不同幅度的改变第一振荡信号Osc1的周期；此时根据第一选择信号fnAdjDly1和第二选择信号fnAdjDly2的不同生成的第一振荡信号Osc1的周期表1所示：
表1 Osc1周期表
fnAdjDly1 fnAdjDly2 Osc1的周期
0 0 T
1 0 1.2T
0 1 1.4T
1 1 1.6T
继续参考图4，脉冲产生电路100包括：周期调整模块102，接收第一振荡 信号Osc1以及倍率选择信号fnAdjDlyx，并输出第二振荡信号Osc2，第二振荡信号Osc2的周期为第一振荡信号Osc1基于倍率选择信号fnAdjDlyx调整后的周期，倍率选择信号fnAdjDlyx为外部输入的选择指令，用于调整第二振荡信号Osc2的周期，即脉冲产生电路可通过外部输入的倍率选择信号fnAdjDlyx调整周期调整模块102生成的第二振荡信号Osc2的周期。
在一个例子中，可以利用第一振荡信号Osc1生成振荡调整信号OscT，然后根据倍率选择信号fnAdjDlyx选择第一振荡信号Osc1作为第二振荡信号Osc2输出，或选择振荡调整信号OscT作为第二振荡信号Osc2输出。也可以根据倍率选择信号fnAdjDlyx判断是否需要生成振荡调整信号OscT，即采用先判断再生成的方式，输出第二振荡信号Osc2。
参考图5，周期调整模块102包括：延时单元112，接收第一振荡信号Osc1，并基于第一振荡信号Osc1生成振荡调整信号OscT，振荡调整信号OscT的周期与第一振荡信号Osc1的周期不同；选择单元122，接收倍率选择信号fnAdjDlyx，并基于倍率选择信号fnAdjDlyx选择第一振荡信号Osc1或振荡调整信号OscT作为第二振荡信号Osc2。
在一个例子中，参考图7，延时单元112包括：D触发器201，D触发器包括输入端D、时钟端Clk和ClkN、复位端RN和输出端Q，时钟端Clk和ClkN用于接收第一振荡信号Osc1和反相第一振荡信号Osc1N，复位端RN用于接收复位信号fnRasEn，输出端Q用于串联触发反相器202并连接至输入端D，且用于输出振荡调整信号OscT。本领域技术人员可知，此时输出的振荡调整信号OscT的周期是第一振荡信号Osc1周期的两倍。
参考图8，选择单元122包括倍率选择器203，倍率选择器203包括第一选择输入端、第二选择输入端、选择信号端和选择输出端，第一选择输入端和第二选择输入端分别用于接收第一振荡信号Osc1和振荡调整信号OscT，选择信号端用于接收倍率选择信号fnAdjDlyx和反相倍率选择信号fnAdjDlyxN，选择输出端用于输出第二振荡信号Osc2，通过倍率选择信号fnAdjDlyx可以大幅度的改变振荡信号的周期；在本实施例中，采用第一选择输入端接收第一振荡信 号Osc1，第二选择输入端接收振荡调整信号OscT；在其他实施例中，也可以是第一选择输入端接收振荡调整信号OscT，第二选择输入端接收第一振荡信号Osc1。
此时，根据第一选择信号fnAdjDly1、第二选择信号fnAdjDly2和倍率选择信号fnAdjDlyx的不同生成的第二振荡信号Osc2的周期如表2所示：
表2 Osc2的周期表
fnAdjDlyx fnAdjDly1 fnAdjDly2 Osc2的周期
0 0 0 T
0 1 0 1.2T
0 0 1 1.4T
0 1 1 1.6T
1 0 0 2T
1 1 0 2.4T
1 0 1 2.8T
1 1 1 3.2T
在本实施例中，延时单元112包括E个串联的延时子单元，振荡调整信号OscT包括E个延时信号，E为正整数；第一级延时子单元，用于根据第一振荡信号Osc1生成第一延时信号Osc11，并将第一延时信号Osc11输入到第二级延时子单元中；第F级延时子单元，用于根据第F-1级延时信号Osc1F-1生成第F延时信号Osc1F，F为小于等于E，且大于等于2正整数。
具体地，第F级延时子单元包括：D触发器，D触发器包括输入端、时钟端和、复位端和输出端，时钟端和用于接收第F-1延时信号Osc1F-1和反相第F-1延时信号Osc1F-1N，复位端用于接收复位信号，输出端用于串联触发反相器并连接至输入端，且用于输出第F延时信号Osc1F。本领域技术人员可知，此时输出的第F延时信号Osc1F的周期是第F-1延时信号Osc1F-1周期的两倍。
参考图9，延时单元112包括3个串联的延时子单元，分别为第一级延时子单元221、第二级延时子单元223和第三级延时子单元225；其中，第一级延时子单元221用于根据第一振荡信号Osc1生成第一延时信号Osc11，第一延时信号Osc11的周期是第一振荡信号Osc1周期的两倍；第二级延时子单元223用于根据第一延时信号Osc11生成第二延时信号Osc12，第二延时信号Osc12的周期是第一延时信号Osc11周期的两倍；第三级延时子单元225用于根据第二延时信号Osc12生成第三延时信号Osc13，第三延时信号Osc13的周期是第二延时信号Osc12周期的两倍。
在一个例子中，选择单元122基于倍率选择信号fnAdjDlyx选择第一振荡信号Osc1或振荡调整信号OscT作为第二振荡信号Osc2，包括：基于倍率选择信号fnAdjDlyx选择第E-1延时信号Osc1E-1或第E延时信号Osc1E作为第二振荡信号Osc2。
在本实施例中，选择单元122基于倍率选择信号fnAdjDlyx选择第一振荡信号Osc1或振荡调整信号OscT作为第二振荡信号Osc2，包括：基于倍率选择信号fnAdjDlyx选择第二延时信号Osc12或第三延时信号Osc13作为第二振荡信号Osc2。其中，第一级延时单元221和第二级延时子单元223用于扩大输出的第二振荡信号Osc2的周期。
此时根据第一选择信号fnAdjDly1、第二选择信号fnAdjDly2和倍率选择信号fnAdjDlyx的不同生成的第二振荡信号Osc2的周期如表3所示：
表3 Osc2的周期表
fnAdjDlyx fnAdjDly1 fnAdjDly2 Osc2的周期
0 0 0 4T
0 1 0 4.8T
0 0 1 5.6T
0 1 1 6.4T
1 0 0 8T
1 1 0 9.6T
1 0 1 11.2T
1 1 1 12.8T
在另一个例子中，选择单元122包括E个串联的选择子单元，倍率选择信号fnAdjDlyx包括对应于每个选择子单元的子倍率选择信号；第一级选择子单元，用于根据对应的子倍率选择信号，选择第一振荡信号Osc1或第一延时信号Osc11输入到第二级选择子单元中；第F级选择子单元，用于根据对应的子倍率选择信号，选择第F-1级选择子单元的输出信号或第F延时信号Osc1F输入到第F+1级选择子单元中；第E级选择子单元，用于根据对应的子倍率选择信号，选择第E-1级选择子单元的输出信号或振荡调整信号OscT作为第二振荡信号Osc2，F为小于E，且大于等于2的正整数，即选择单元122的第一选择输入端和第二选择输入端分别用于接收振荡调整信号(第1延时信号Osc11、第2延时信号Osc12……第F延时信号Osc1F)中的一个信号或第一振荡信号Osc1，并根据倍率选择信号选择振荡调整信号(第1延时信号Osc11、第2延时信号Osc12……第F延时信号Osc1F)中的一个信号或第一振荡信号Osc1中的一个信号作为第二振荡信号Osc2。
具体地，第F级选择子单元包括：倍率选择器，倍率选择器包括第一选择输入端、第二选择输入端、选择信号端和选择输出端、第一选择输入端和第二选择输入端分别用于接收第F-1级选择子单元的输出信号和第F延时信号Osc1F，选择信号端用于接收对应的子倍率选择信号，选择输出端用于输出第F-1级选择子单元的输出信号或第F延时信号Osc1F；在本实施例中，采用第一选择输入端接收第F-1级选择子单元的输出信号，第二选择输入端接收第F延时信号Osc1F；在其他实施例中，也可以是第一选择输入端接收第F延时信号Osc1F，第二选择输入端接收第F-1级选择子单元的输出信号。
参考图10，选择单元122包括3个串联的选择子单元，分别为第一级选择子单元227、第二级选择子单元228和第三级选择子单元229；其中，第一级选 择子单元227用于选择第一振荡信号Osc1或第一延时信号Osc11输入到第二级选择子单元228，第二级选择子单元228用于选择第一级选择子单元227的输出信号或第二延时信号Osc12输入到第三级选择子单元229，第三级选择子单元229用于选择第二级选择子单元228的输出信号或第三延时信号Osc13作为振荡调整信号OscT。通过多个选择子单元的串联，实现了第二振荡信号Osc2周期更多的变化选择。
需要说明的是，在具体应用过程中，倍率选择信号fnAdjDlyx、第一选择信号fnAdjDly1和第二选择信号fnAdjDly2可以通过多位二进制数实现，即选择信号是一个多位二进制数，其中一位作为倍率选择信号fnAdjDlyx，一位作为第一选择信号fnAdjDly1，一位作为第二选择信号fnAdjDly2。
继续参考图4，脉冲产生电路100包括：脉冲转换模块103，接收第二振荡信号Osc2，并输出脉冲信号OscClk，脉冲信号OscClk的脉冲基于第二振荡信号的上升沿或下降沿产生，且脉冲信号OscClk的脉冲周期与第二振荡信号的振荡周期相同。
具体地，参考图5，脉冲转换模块103包括：脉冲转换器113，用于接收第二振荡信号Osc2，且基于第二振荡信号Osc2生成脉冲信号OscClk。
在一个例子中，当脉冲转换器113检测到第二振荡信号Osc2的上升沿后输出一个向上的窄脉冲，脉冲转换器113的输出端还可以通过串联反相器，以输出一个向下的窄脉冲。在另一个例子中，当脉冲转换器113检测到第二振荡信号Osc2的上升沿后输出一个向下的窄脉冲，脉冲转换器113的输出端还可以通过串联反相器，以输出一个向上的窄脉冲。另外，本实施例中脉冲转换器113是基于第二振荡信号Osc2的上升沿工作，在其他实施例中，脉冲转换器还可以基于第二振荡信号的下降沿工作。
需要注意的是，此处描述的“基于第二振荡信号Osc2生成脉冲信号OscClk”中，“基于”的含义包括但不限定于：检测到第二振荡信号Osc2的上升沿，或者检测到第二振荡信号Osc2由低电平变为高电平(高电平变为低电平)后产生脉冲信号OscClk的窄脉冲。
需要说明的是，在本实施例中，脉冲信号OscClk是基于第二振荡信号Osc2的上升沿产生，在其他实施例中，脉冲信号还可以根据第二振荡信号的下降沿产生。
参考图11，在控制信号RasEn为有效电平期间，振荡模块101产生周期为T的第一振荡信号Osc1，周期调整模块102根据倍率选择信号fnAdjDlyx调整第二振荡信号Osc2(Osc2′)的周期。
具体地，若在控制信号RasEn为有效电平期间改变倍率选择信号fnAdjDlyx，此时产生的第二振荡信号Osc2存在周期变化，假设由周期T变为周期2T，此时产生的脉冲信号OscClk中脉冲周期也由周期T变为周期2T；若在控制信号RasEn为有效电平之前改变倍率选择信号fnAdjDlyx，此时产生的第二振荡信号Osc2′不存在周期变化，产生的脉冲信号OscClk′中脉冲周期也不存在脉冲周期的变化。
参考图12，当激活信号Active为有效电平时，产生的第一控制信号ActEn为有效电平；第一脉冲产生单元301用于根据第一控制信号ActEn产生周期为T第一振荡信号Osc1和周期为2T的第二振荡信号Osc2；在本实施例中，第二振荡信号Osc2与第一振荡信号Osc1的周期一致，第一脉冲信号ActClk基于第二振荡信号Osc2的上升沿产生。第二脉冲产生单元302用于根据第二控制信号PreEn产生周期为T的第一振荡信号Osc1〃和周期为2T的第二振荡信号Osc2〃；在本实施例中，第二振荡信号Osc2〃与第一振荡信号Osc1〃的周期一致，第二脉冲信号PreClk基于第二振荡信号Osc2〃的上升沿产生。此时产生的第一脉冲信号ActClk与第二脉冲信号PreClk为交错脉冲信号。
具体地，延时信号输出电路，包括：G个信号输出电路500，G为大于等于2的整数，信号输出电路用于接收输入信号、第一脉冲信号ActClk和第二脉冲信号PreClk，输出延时输出信号；其中，非第一级信号输出电路均接收前一级信号输出电路输出的延时输出信号作为当前级信号输出电路的输入信号，第一级信号输出电路接收初始输入信号作为第一级信号输出电路的输入信号；信号输出电路生成的延时输出信号的上升沿，与接收的前一级信号输出电路输出 的延时输出信号或所述初始输入信号的上升沿，具有第一延迟；信号输出电路生成的延时输出信号的下降沿，与接收的前一级信号输出电路输出的延时输出信号或所述初始输入信号的下降沿，具有第二延迟。
具体地，参考图13，信号输出电路500包括：第一控制模块501，接收第一脉冲信号ActClk和输入信号ActBnk0，并输出第一调整信号ActLat，第一调整信号ActLat的第一预设沿相对于输入信号ActBnk0的上升延具有第一延迟，第一延迟为第一脉冲信号ActClk的脉冲周期。
在一个例子中，可以利用第一脉冲信号ActClk的上升沿或下降沿去采样输入信号ActBnk0，然后输出第一调整信号ActLat；或检测到第一脉冲信号ActClk的上升沿或下降沿后延迟输出输入信号ActBnk0，从而获取第一调整信号ActLat。
在本实施例中，以第一预设沿为上升沿为例进行举例说明；具体地，输入信号ActBnk0为外部输入信号(相比信号输出电路500来说)，信号输出电路500用于根据输入信号ActBnk0产生延时输出信号ActBnk1；其中，延时输出信号ActBnk1的上升沿基于第一调整信号ActLat的上升沿产生，第一调整信号ActLat的上升沿与输入信号ActBnk0的上升沿具有第一延迟；即延时输出信号ActBnk1的上升沿与输入信号ActBnk0的上升沿具有第一延迟，第一延迟为第一脉冲信号ActClk的脉冲周期，由此可知，外部输入的第一脉冲信号ActClk用于调整延时输出信号ActBnk1的上升沿的延迟。需要说明的是，在其他实施例中，第一预设沿还可以为下降沿。
需要注意的是，此处描述的“延时输出信号ActBnk1的上升沿基于第一调整信号ActLat的第一预设沿产生”中，“基于”的含义包括但不限定于：检测到第一调整信号ActLat的第一预设沿即产生延时输出信号ActBnk1的上升沿，或者检测到第一调整信号ActLat由低电平变为高电平(高电平变为低电平)后产生延时输出信号ActBnk1的上升沿。
在一个例子中，参考图14，第一控制模块501包括第一D触发器511，时钟端用于接收第一脉冲信号ActClk，复位端用于接收第一复位信号fnActEn， 输入端用于接收输入信号ActBnk0，输出端用于输出第一调整信号ActLat。
继续参考图13，信号输出电路500还包括：第二控制模块502，接收第二脉冲信号PreClk和输入信号ActBnk0，并输出第二调整信号PreLat，第二调整信号PreLat的第二预设沿相对于输入信号ActBnk0的下降沿具有第二延迟，第二延迟为第二脉冲信号PreClk的脉冲周期。
在本实施例中，以第二预设沿为上升沿为例进行举例说明；具体地，延时输出信号ActBnk1的下降沿基于第二调整信号PreLat的上升沿产生，第二调整信号PreLat的上升沿与输入信号ActBnk0的下降沿具有第二延迟；即延时输出信号ActBnk1的下降沿与输入信号ActBnk0的下降沿具有第二延迟，第二延迟为第二脉冲信号PreClk的脉冲周期，由此可知，外部输入的第二脉冲信号PreClk用于调整延时输出信号ActBnk1的下降沿的延迟。需要说明的是，在其他实施例中，第二预设沿还可以为下降沿。
需要注意的是，此处描述的“延时输出信号ActBnk1的下降沿基于第二调整信号PreLat的第二预设沿产生”中，“基于”的含义包括但不限定于：检测到第二调整信号PreLat的第二预设沿即产生延时输出信号ActBnk1的下降沿，或者检测到第二调整信号PreLat由低电平变为高电平(高电平变为低电平)后产生延时输出信号ActBnk1的下降沿。
在一个例子中，参考图15，第二控制模块502包括第二D触发器512，时钟端用于接收第二脉冲信号PreClk，复位端用于接收第二复位信号fnPreEn，输入端用于接收输入信号ActBnk0，输出端串联反相器后输出第二调整信号PreLat。
另外，在本实施例中，第一脉冲信号ActClk的其中一个脉冲与输入信号ActBnk0的上升沿对齐，第二脉冲信号PreClk的其中一个脉冲与输入信号ActBnk0的下降沿对齐。需要说明的是，此处描述的“对齐”并不一定是理想情况下的完全对齐，可以包括由于电路延迟等因素导致的上升沿/下降沿存在细微差别。通过第一脉冲信号ActClk的其中一个脉冲与输入信号ActBnk0的上升沿对齐，以保证对第一调整信号ActLat的第一信号沿与输入信号ActBnk0的上 升沿的第一延迟的准确性；通过第二脉冲信号PreClk的其中一个脉冲与输入信号ActBnk0的下降沿对齐，以保证对第二调整信号PreLat的第二信号沿与输入信号ActBnk0的下降沿的第二延迟的准确性。
继续参考图13，信号输出电路500还包括：信号输出模块503，接收第一调整信号ActLat和第二调整信号PreLat，并输出延时输出信号ActBnk1，延时输出信号ActBnk1的上升沿基于第一调整信号ActLat的第一预设沿产生，延时输出信号ActBnk1的下降沿基于第二调整信号PreLat的第二预设沿产生。
具体地，参考图16，信号输出模块503包括：第一接收单元513，接收第一脉冲信号ActClk和第一调整信号ActLat，并在第一调整信号ActLat为有效电平期间，生成第一脉冲控制信号ActN，第一脉冲控制信号ActN的脉冲相位与第一脉冲信号ActClk的脉冲相位相同。第二接收单元523，接收第二脉冲信号PreClk和第二调整信号PreLat，并在第二调整信号PreLat为有效电平期间，生成第二脉冲控制信号PreN，第二脉冲控制信号PreN的脉冲相位与第二脉冲信号PreClk的脉冲相位相同。锁存单元533，接收第一脉冲控制信号ActN和第二脉冲控制信号PreN，并延时输出信号ActBnk1。
在一个例子中，当检测到第一调整信号ActLat为有效电平，基于反相器通过第一脉冲信号ActClk生成第一脉冲控制信号ActN；当检测到第二调整信号PreLat为有效电平，基于反相器通过第二脉冲信号PreClk生成第二脉冲控制信号PreN。
在一个例子中，参考图17，第一接收单元513包括第一接收与非门601，第一接收与非门601包括第一输入端、第二输入端和第一输出端，第一输入端用于接收第一调整信号ActLat，第二输入端用于接收第一脉冲信号ActClk，第一输出端用于输出第一脉冲控制信号ActN。第二接收单元523包括第二接收与非门602，第二接收与非门602包括第三输入端、第四输入端和第二输出端，第三输入端用于接收第二调整信号PreLat，第四输入端用于接收第二脉冲信号PreClk，第二输出端用于输出第二脉冲控制信号PreN。锁存单元533包括锁存器603，锁存器603包括第五输入端、第六输入端和第三输出端，第五输入端 用于接收第一脉冲控制信号ActN，第六输入端用于接收第二脉冲控制信号PreN，第三输出端用于输出延时输出信号ActBnk1。
锁存单元603被配置为：第一脉冲控制信号ActN和第二脉冲控制信号PreN为不同电平时，延时输出信号ActBnk1与第二脉冲控制信号PreN为相同电平；第一脉冲控制信号ActN和第二脉冲控制信号PreN为高电平时，锁存单元603保持状态。
具体地，第一脉冲信号ActN和第二脉冲控制信号PreN为高电平时，锁存单元603保持状态；当第一脉冲控制信号ActN为高电平，第二脉冲信号控制信号PreN为低电平时，锁存单元603为低电平；当第一脉冲控制信号ActN为低电平，第二脉冲信号控制信号PreN为高电平时，锁存单元603为高电平。
在另一例子中，第一接收单元513还用于接收第一控制信号ActEn，第一接收单元513用于在第一调整信号ActLat和第一控制信号ActEn为有效电平期间，根据第一脉冲信号ActClk生成第一脉冲控制信号ActN。第二接收单元523还用于接收第二控制信号PreEn，第二接收单元523用于在第二调整信号PreLat和第二控制信号PreEn为有效电平期间，根据第二脉冲信号PreClk生成第二脉冲控制信号PreN。
参考图18，第一接收与非门601还用于接收第一控制信号ActEn，第一接收与非门601根据第一时钟信号ActClk、第一控制信号ActEn和第一调整信号ActLat生成第一脉冲控制信号ActN。第二接收与非门602还用于接收第二控制信号PreEn，第二接收与非门602根据第二时钟信号PreClk、第二控制信号PreEn和第二调整信号PreLat生成第二脉冲控制信号PreN。其中，第一控制信号ActEn和第二控制信号PreEn为反相信号，第一脉冲信号ActClk在第一控制信号ActEn为有效电平期间存在，第二脉冲信号PreClk在第二控制信号PreEn为有效电平期间存在。通过第一接收与非门601和第二接收与非门分别接收第一控制信号ActEn和第二控制信号PreEn，保证第一接收与非门601和第二接收与非门602输出的稳定性。
进一步地，第一脉冲信号ActClk和第二脉冲信号PreClk为交错脉冲信号， 交错脉冲信号即根据反相的信号产生的脉冲信号；在本实施例中，第一脉冲信号ActClk在第一控制信号ActEn为有效电平期间存在，且第一脉冲信号ActClk的起始脉冲与第一控制信号ActEn的上升沿对齐；第二脉冲信号PreClk在第二控制信号PreEn为有效电平期间存在，且第二脉冲信号PreClk的起始脉冲与第二控制信号PreEn的上升沿对齐；需要说明的是，此处描述的“对齐”并不一定是理想情况下的完全对齐，可以包括由于电路延迟等因素导致的上升沿/下降沿存在细微差别。
在一个例子中，参考图19，输入信号ActBnk0、第一脉冲信号ActClk和第二脉冲信号PreClk为外部输入信号；假设第一脉冲信号ActClk的周期为t1，第二脉冲信号PreClk的周期为t2。结合图15，第一调整信号ActLat基于输入信号ActBnk0和第一脉冲信号ActClk产生，当第一脉冲信号ActClk为高电平时，第一调整信号ActLat的状态为输入信号ActBnk0的当前状态，造成第一调整信号ActLat的上升沿与输入信号ActBnk0的上升沿存在第一延迟，第一延迟为第一脉冲信号ActClk的周期，即第一调整信号ActLat的上升沿与输入信号ActBnk0的上升沿的延迟为t1。结合图16，第二调整信号PreLat基于输入信号ActBnk0和第二脉冲信号PreClk产生，当第二脉冲信号PreClk为高电平时，第二调整信号PreLat的状态为输入信号ActBnk0的当前状态，造成第二调整信号PreLat的上升沿与输入信号ActBnk0的下降沿存在第二延迟，第二延迟为第二脉冲信号PreClk的周期，即第二调整信号PreLat的上升沿与输入信号ActBnk0的下降沿的延迟为t2。结合图18，为了保证第一接收与非门601和第二接收与非门602输出的稳定性，第一接收与非门601还用于接收第一控制信号ActEn，第二接收与非门602还用于接收第二控制信号PreEn，第一控制信号ActEn和第二控制信号PreEn为反相信号。此时第一接收与非门601和第二接收与非门602分别产生的第一脉冲控制信号ActN和第二脉冲控制信号PreN。锁存单元603根据第一脉冲控制信号ActN和第二脉冲控制信号PreN产生延时输出信号ActBnk1，延时输出信号ActBnk1的上升沿与输入信号ActBnk0的上升沿具有第一延迟，第一延迟为第一脉冲信号ActClk的脉冲周期t1；延时输出信号 ActBnk1的下降沿与输入信号ActBnk0的下降沿具有第二延迟，第二延迟为第二脉冲信号PreClk的脉冲周期t2。在本实施例中，第一脉冲信号ActClk和第二脉冲信号PreClk的脉冲周期相等，即延时输出信号ActBnk1信号变化沿相对于输入信号ActBnk0的信号变化沿存在相等时间的延迟。
需要说明的是，图7给出的各信号的时序图，仅用于对本实施例提供的信号输出电路500的电路功能进行解读，并不构成对本实施例的限定；在其他实施例中，可以根据其他输入信号生成对应的延时输入信号；另外，输入信号也可能和第一控制信号不一致。
需要说明的是，在其他实施例中，信号输出电路还包括偶数个反相器，反相器与信号输出模块的输出端串联，以增强信号输出电路的驱动能力。
参考图20，在本实施例中，以延时信号输出电路700包括7个上述信号输出电路500为例进行具体说明，并不构成对本实施例的限定，具体为第一级信号输出电路701、第二级信号输出电路702、第三级信号输出电路703、第四级信号输出电路704、第五级信号输出电路705、第六级信号输出电路706和第七级信号输出电路707。在其他实施例中，延时信号输出电路包括大于等于2个信号输出电路即可。
具体地，第一级信号输出电路701根据初始输入信号ActBnk0、第一脉冲信号ActClk和第二脉冲信号PreClk生成第一级延时输出信号ActBnk1，第一级延时输出信号ActBnk1的上升沿相对于初始输入信号ActBnk0的上升沿存在第一延迟，第一延迟为第一脉冲信号ActClk的脉冲周期t1；第一级延时输出信号ActBnk1的下降沿相对于初始输入信号ActBnk0的下降沿存在第二延迟，第二延迟为第二脉冲信号PreClk的脉冲周期t2。
第二级信号输出电路702根据第一级延时输出信号ActBnk1、第一脉冲信号ActClk和第二脉冲信号PreClk生成第二级延时输出信号ActBnk2，第二级延时输出信号ActBnk2的上升沿相对于第一级延时输出信号ActBnk1存在第一延迟；第二级延时输出信号ActBnk2的下降沿相对于第一级延时输出信号ActBnk1存在第二延时。
第三级信号输出电路703根据第二级延时输出信号ActBnk2、第一脉冲信号ActClk和第二脉冲信号PreClk生成第三级延时输出信号ActBnk3，第三级延时输出信号ActBnk3的上升沿相对于第二级延时输出信号ActBnk2存在第一延迟；第三级延时输出信号ActBnk3的下降沿相对于第二级延时输出信号ActBnk2存在第二延时。
第四级信号输出电路704根据第三级延时输出信号ActBnk3、第一脉冲信号ActClk和第二脉冲信号PreClk生成第四级延时输出信号ActBnk4，第四级延时输出信号ActBnk4的上升沿相对于第三级延时输出信号ActBnk3存在第一延迟；第四级延时输出信号ActBnk4的下降沿相对于第三级延时输出信号ActBnk3存在第二延时。
第五级信号输出电路705根据第四级延时输出信号ActBnk4、第一脉冲信号ActClk和第二脉冲信号PreClk生成第五级延时输出信号ActBnk5，第五级延时输出信号ActBnk5的上升沿相对于第四级延时输出信号ActBnk4存在第一延迟；第五级延时输出信号ActBnk5的下降沿相对于第四级延时输出信号ActBnk4存在第二延时。
第六级信号输出电路706根据第五级延时输出信号ActBnk5、第一脉冲信号ActClk和第二脉冲信号PreClk生成第六级延时输出信号ActBnk6，第六级延时输出信号ActBnk6的上升沿相对于第五级延时输出信号ActBnk5存在第一延迟；第六级延时输出信号ActBnk6的下降沿相对于第五级延时输出信号ActBnk5存在第二延时。
第七级信号输出电路707根据第六级延时输出信号ActBnk6、第一脉冲信号ActClk和第二脉冲信号PreClk生成第七级延时输出信号ActBnk7，第七级延时输出信号ActBnk7的上升沿相对于第六级延时输出信号ActBnk6存在第一延迟；第七级延时输出信号ActBnk7的下降沿相对于第六级延时输出信号ActBnk6存在第二延时。
参考图21，更具体地，在本实施例中，信号输出电路的第一控制模块还用于接收第一控制信号ActEn，信号输出电路的第二控制模块还用于接收第二控 制信号PreEn，其中，第一脉冲信号ActClk和第二脉冲信号PreClk为反相信号；每一级信号输出电路用于根据第一控制信号ActEn、第二控制信号PreEn、第一脉冲信号ActClk、第二脉冲信号PreClk和前一级信号输出电路输出的延时输出信号生成当前级的延时输出信号，通过接收第一控制信号ActEn和第二控制信号PreEn，保证信号输出电路输出的稳定性。
继续参考图21，本实施例中，延时信号输出电路700还包括：初始信号输出电路710，包括第一控制模块、第二控制模块和信号输出模块；第一控制模块，用于接收第一脉冲信号ActClk和第一电源信号Vdd，并根据第一脉冲信号ActClk和第一电源信号Vdd生成第一调整信号(未图示)；输出信号输出电路的第二控制模块，用于接收第二脉冲信号PreClk和第二电源信号Vss并根据第二脉冲信号PreClk和第二电源信号Vss生成第二调整信号(未图示)；信号输出模块，用于根据第一调整信号(未图示)和第二调整信号(未图示)生成初始输入信号。根据第一电源信号Vdd和第二电源信号Vss生成的初始信号输出电路的延时输出信号，即根据初始信号初始输出电路710输出的初始输入信号ActBnk0相比于外部直接输入的输入信号ActBnk0可以避免信号输出电路的电路元件造成的延迟。这里的初始信号输出电路710的电路可以与前文描述的信号输出电路一致，在此不再赘述，但本实施例也不限于此。
在一个例子中，参考图22和图23，该图以4个信号输出电路构成的延时信号输出电路700为例进行介绍。信号输出电路的第一时钟端ActClk用于接收第一脉冲信号ActClk；信号输出电路的第二时钟端PreClk用于接收第二脉冲信号PreClk；信号输出电路的第一控制端ActEn用于接收第一控制信号ActEn；信号输出电路的第二控制端PreEn用于接收第二控制信号PreEn；信号输出电路的信号输出端ActBnk用于输出当前级的延时输出信号；信号输出电路还包括第一信号端ActEnPre和第二信号端PreEnPre(信号输出电路的信号输入端)，结合图23，初始信号输出电路的第一信号端ActEnPre用于接收第一电源信号Vdd，初始信号输出电路的第二信号端PreEnPre用于接收第二电源信号Vss；其他信号输出电路的第一信号端ActEnPre和第二信号端PreEnPre，用于接收前 一级信号输出电路输出的延时输出信号。
参考图21和图24，第一级信号输出电路701根据初始输入信号ActBnk0生成第一级延时输出信号ActBnk1，第二级信号输出电路702根据第一级延时输出信号ActBnk1生成第二级延时输出信号ActBnk2，第三级信号输出电路703根据第二级延时输出信号ActBnk2生成第三级延时输出信号ActBnk3，第四级信号输出电路704根据第三级延时输出信号ActBnk3生成第四级延时输出信号ActBnk4(未图示)，第五级信号输出电路705根据第四级延时输出信号ActBnk4生成第五级延时输出信号ActBnk5(未图示)，第六级信号输出电路706根据第五级延时输出信号ActBnk5生成第六级延时输出信号ActBnk6(未图示)，第七级信号输出电路707根据第六级延时输出信号ActBnk6生成第七级延时输出信号ActBnk7(未图示)。
相对于相关技术而言，根据控制信号产生第一振荡信号，即控制信号在处于有效电平时，产生周期一定的第一振荡信号；根据倍率选择信号，基于第一振荡信号产生第二振荡信号，即基于倍率选择信号，改变第一振荡信号的周期，以产生相应的第二振荡信号；然后将第二振荡信号作为信号源产生脉冲信号，产生的脉冲信号的脉冲周期与第二振荡信号的振荡周期相同；在产生脉冲信号的过程中，若倍率选择信号改变，调整第一振荡信号的周期的幅度改变，以使产生的第二振荡信号的周期变化，从而产生周期可调整的第一脉冲信号和第二脉冲信号；并且根据第一脉冲信号和第二脉冲信号产生延时可控的延时信号，延时信号相对于输入信号而言，上升沿存在第一延时，下降沿存在第二延时；第一延时为第一脉冲信号的脉冲周期，第二延时为第二脉冲信号的脉冲周期，因此可以通过调整第一脉冲信号和第二脉冲信号脉冲周期的方式，调整延时信号的延时时间；同时，调整延时信号的延时时间无需接入更多延时单元，从而简化电路结构，使得电路版图的面积小，电路的功耗小。
值得一提的是，本实施例中所涉及到的各单元均为逻辑单元，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本申请的创新部分，本实施 例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。
工业实用性
在本申请实施例中，该交错信号产生电路可以包括：交错脉冲产生电路，用于根据第一控制信号生成第一脉冲信号，并根据第二控制信号生成第二脉冲信号，第一控制信号与第二控制信号为反相信号，第一脉冲信号与第二脉冲信号为交错脉冲信号；延时信号输出电路，包括G个信号输出电路，G为大于等于2的整数；非第一级信号输出电路均接收前一级信号输出电路输出的延时输出信号作为当前级信号输出电路的输入信号，第一级信号输出电路接收初始输入信号作为第一级信号输出电路的输入信号；本申请实施例以产生周期可调整的第一脉冲信号和第二脉冲信号，并根据第一脉冲信号和第二脉冲信号产生延时可控的延时信号，且电路版图的面积小，电路的功耗小。

Claims (19)

  1. 一种交错信号产生电路，包括：
    交错脉冲产生电路，用于根据第一控制信号生成第一脉冲信号，并根据第二控制信号生成第二脉冲信号，所述第一控制信号与所述第二控制信号为反相信号，所述第一脉冲信号与所述第二脉冲信号为交错脉冲信号；
    延时信号输出电路，包括G个信号输出电路，所述G为大于等于2的整数，所述信号输出电路用于接收输入信号、所述第一脉冲信号和所述第二脉冲信号，输出延时输出信号；
    其中，非第一级信号输出电路均接收前一级信号输出电路输出的延时输出信号作为当前级信号输出电路的输入信号，第一级信号输出电路接收初始输入信号作为第一级信号输出电路的输入信号；
    信号输出电路生成的延时输出信号的上升沿，与接收的前一级信号输出电路输出的延时输出信号或所述初始输入信号的上升沿，具有第一延迟；信号输出电路生成的延时输出信号的下降沿，与接收的前一级信号输出电路输出的延时输出信号或所述初始输入信号的下降沿，具有第二延迟。
  2. 根据权利要求1所述的交错信号产生电路，其中，所述第一脉冲信号和所述第二脉冲信号的脉冲周期相等。
  3. 根据权利要求1所述的交错信号产生电路，其中，所述交错脉冲产生电路包括：
    信号产生模块，用于根据激活信号生成所述第一控制信号和所述第二控制信号；
    第一脉冲产生单元，用于根据所述第一控制信号生成所述第一脉冲信号；
    第二脉冲产生单元，用于根据所述第二控制信号生成所述第二脉冲信号。
  4. 根据权利要求3所述的交错信号产生电路，其中，所述信号产生模块包括：
    复位单元，接收第一复位信号以及所述激活信号，并基于所述第一复位信 号和所述激活信号生成所述第一控制信号；
    反向单元，接收所述第一控制信号，并基于所述第一控制信号生成所述第二控制信号。
  5. 根据权利要求4所述的交错信号产生电路，其中，所述信号产生模块还包括：复位信号产生单元，用于根据所述第一复位信号和所述第一控制信号生成第二复位信号，以使当所述第一复位信号为复位状态时，所述第二复位信号也处于复位状态，当所述第一复位信号为非复位状态时，所述第二复位信号基于第一控制信号的变化沿产生复位窄脉冲。
  6. 根据权利要求3所述的交错信号产生电路，其中，所述第一脉冲产生单元，包括：
    振荡模块，接收第一控制信号，且根据所述第一控制信号生成第一振荡信号；
    周期调整模块，接收所述第一振荡信号以及倍率选择信号，并输出第二振荡信号，且所述第二振荡信号的周期为基于所述倍率选择信号调整所述第一振荡信号后的周期；
    脉冲转换模块，接收所述第二振荡信号，并输出脉冲信号，所述第一脉冲信号的脉冲基于所述第二振荡信号的信号变化沿产生，且所述第一脉冲信号的脉冲周期与所述第二振荡信号的振荡周期相同。
  7. 根据权利要求6所述的交错信号产生电路，其中，所述第二脉冲产生单元与所述第一脉冲产生单元具有相同的电路结构。
  8. 根据权利要求6所述的交错信号产生电路，其中，所述周期调整模块包括：
    延时单元，接收所述第一振荡信号，并基于所述第一振荡信号生成振荡调整信号，所述振荡调整信号的周期与所述第一振荡信号周期的不同；
    选择单元，接收所述倍率选择信号，并基于所述倍率选择信号选择所述第一振荡信号或所述振荡调整信号作为所述第二振荡信号。
  9. 根据权利要求8所述的交错信号产生电路，其中，所述延时单元包括E 个串联的延时子单元，所述振荡调整信号包括E个延时信号，所述E为正整数；
    第一级延时子单元，用于根据所述第一振荡信号生成第一延时信号，并将第一延时信号输入到第二级延时子单元中；
    第F级延时子单元，用于根据第F-1延时信号生成第F延时信号，所述F小于等于所述E，且大于等于2的正整数。
  10. 根据权利要求9所述的交错信号产生电路，其中，所述选择单元包括：倍率选择器，所述倍率选择器包括第一选择输入端、第二选择输入端、选择信号端和选择输出端，所述第一选择输入端和所述第二选择输入端分别用于接收所述振荡调整信号中的一个信号或所述第一振荡信号，所述选择信号端用于接收所述倍率选择信号，所述选择输出端用于输出所述第二振荡信号。
  11. 根据权利要求6所述的交错信号产生电路，其中，所述振荡模块包括：
    振荡单元以及连接在所述振荡单元中的触发单元；
    所述触发单元，用于接收复位信号以及所述第一控制信号，并基于所述复位信号和所述第一控制信号触发所述振荡单元；
    所述振荡单元触发后，用于根据所述第一控制信号生成所述第一振荡信号。
  12. 根据权利要求11所述的交错信号产生电路，其中，所述振荡单元包括：A个反相器串联形成的环形振荡器，所述A为正奇数。
  13. 根据权利要求12所述的交错信号产生电路，其中，所述振荡模块还包括：
    第一反相器组，包括串联的B个反相器，所述B为正偶数；
    第一选择单元，用于接收第一选择信号，并基于所述第一选择信号，将所述第一反相器组串接在所述环形振荡器中的相邻反相器之间。
  14. 根据权利要求6所述的交错信号产生电路，其中，所述脉冲转换模块包括：脉冲转换器，用于接收所述第二振荡信号，且基于所述第二振荡信号生成所述第一脉冲信号。
  15. 根据权利要求1所述的交错信号产生电路，其中，所述信号输出电路包括：
    第一控制模块，接收所述第一脉冲信号和所述输入信号，并输出第一调整信号，所述第一调整信号的第一预设沿相对于所述输入信号的上升沿具有第一延时，所述第一延时为所述第一脉冲信号的脉冲周期；
    第二控制模块，接收所述第二脉冲信号和所述输入信号，并输出第二调整信号，所述第二调整信号的第二预设沿相对于所述输入信号的下降沿具有第二延时，所述第二延时为所述第二脉冲信号的脉冲周期；
    信号输出模块，接收所述第一调整信号和所述第二调整信号，并输出延时输出信号，所述延时输出信号的上升沿基于所述第一调整信号的第一预设沿产生，所述延时输出信号的下降沿基于所述第二调整信号的第二预设沿产生。
  16. 根据权利要求15所述的交错信号产生电路，其中，所述信号输出模块包括：
    第一接收单元，接收所述第一脉冲信号和所述第一调整信号，并在所述第一调整信号为有效电平期间，生成第一脉冲控制信号，所述第一脉冲控制信号的脉冲相位与所述第一脉冲信号的脉冲相位相同；
    第二接收单元，接收所述第二脉冲信号和所述第二调整信号，并在所述第二调整信号为有效电平期间，生成第二脉冲控制信号，所述第二脉冲控制信号的脉冲相位与所述第二脉冲信号的脉冲相位相同；
    锁存单元，接收所述第一脉冲控制信号和所述第二脉冲控制信号，并生成所述延时输出信号。
  17. 根据权利要求16所述的交错信号产生电路，其中，所述第一接收单元还用于接收第一控制信号，所述第一接收单元用于在所述第一调整信号和所述第一控制信号为有效电平期间，根据所述第一脉冲信号生成所述第一脉冲控制信号。
  18. 根据权利要求16所述的交错信号产生电路，其中，所述第二接收单元还用于接收第二控制信号，所述第二接收单元用于在所述第二调整信号和所述第二控制信号为有效电平期间，根据所述第二脉冲信号生成所述第二脉冲控制信号。
  19. 根据权利要求1所述的交错信号产生电路，其中，所述延时信号输出电路还包括：
    初始信号输出电路，包括第一控制模块、第二控制模块和信号输出模块；
    所述第一控制模块，用于接收第一脉冲信号和第一电源信号，并根据所述第一脉冲信号和所述第一电源信号，生成第一调整信号；
    所述第二控制模块，用于接收第二脉冲信号和第二电源信号，并根据所述第二脉冲信号和所述第二电源信号，生成第二调整信号；
    所述信号输出模块，用于根据所述第一调整信号和所述第二调整信号，生成所述初始输入信号。
PCT/CN2021/112026 2021-03-09 2021-08-11 交错信号产生电路 WO2022188354A1 (zh)

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